Dewey, A.

Digital and Analog Electronic Design Automation

The Electrical Engineering Handbook
Ed. Richard C. Dorf
Boca Raton: CRC Press LLC, 2000
2000 by CRC Press LLC
34
IIgIfaI and AnaIog
IecfronIc IesIgn
AufomafIon
34.1 Intioduction
34.2 Design Entiy
34.3 Synthesis
34.4 Veiifcation
Timing Analysis Simulation Analog Simulation Emulation
34.5 Physical Design
34.6 Test
Fault Modeling Fault Testing
34.7 Summaiy
34.1 Intruductiun
The feld of design automation (DA) technology, also commonly called tomuer-aJeJ Jesgn (CAD) oi
tomuer-aJeJ engneerng (CAE), involves developing computei piogiams to conduct poitions of pioduct
design and manufactuiing on behalf of the designei. Competitive piessuies to pioduce moie effciently new
geneiations of pioducts having impioved function and peifoimance aie motivating the giowing impoitance
of DA. The incieasing complexities of micioelectionic technology, shown in Fig. 34.1, illustiate the impoitance
of ielegating poitions of pioduct development to computei automation Baibe, 1980].
Advances in micioelectionic technology enable ovei 1 million devices to be manufactuied on an integrated
circuit that is smallei than a postage stamp; yet the ability to exploit this capability iemains a challenge. Manual
design techniques aie unable to keep pace with pioduct design cycle demands and aie being ieplaced by
automated design techniques Sapiio, 1986; Dillingei, 1988].
Figuie 34.2 summaiizes the histoiical development of DA technology. DA computei piogiams aie often
simply called a|taons oi oo|s. DA effoits staited in the eaily 1960s as academic ieseaich piojects and captive
industiial piogiams; these effoits focused on tools foi physical and logical design. Follow-on developments
extended logic simulation to moie-detailed trtu and Jete simulation and moie-abstiact [untona| simula-
tion. Staiting in the mid to late 1970s, new aieas of test and synthesis emeiged and vendois staited offeiing
commeicial DA pioducts. Today, the electionic design automation (EDA) industiy is an inteinational business
with a well-established and expanding technical base Tiimbeigei, 1990]. EDA will be examined by piesenting
an oveiview of the following aieas:
Design entiy,
Synthesis,
Veiifcation,
Physical design, and
Test.
AIIen Ievey
Du|e Inverry
2000 by CRC Press LLC
34.2 Design Entry
Design entry, also called Jesgn taure, is the piocess of communicating with a DA system. In shoit, design
entiy is how an engineei talks" to a DA application and/oi system.
Any soit of communication is composed of two elements: language and mechanism. Language piovides
common semantics; mechanism piovides a means by which to convey the common semantics. Foi example,
people communicate via a language, such as English oi Geiman, and a mechanism, such as a telephone oi
electionic mail. Foi design, a digital system can be desciibed in many ways, involving diffeient peispectives oi
a|sratons. An abstiaction defnes at a paiticulai level of detail the behavioi oi semantics of a digital system,
i.e., how the outputs iespond to the inputs. Fig. 34.3 illustiates seveial populai levels of abstiactions. Moving
fiom the lowei left to the uppei iight, the level of abstiaction geneially incieases, meaning that physical models
aie the most detailed and specifcation models aie the least detailed. The tiend towaid highei levels of design
entiy abstiaction suppoits the need to addiess gieatei levels of complexity Peteison, 1981].
The physical level of abstiaction involves geometiic infoimation that defnes electiical devices and theii
inteiconnection. Geometiic infoimation includes the shape of objects and how objects aie placed ielative to
each othei. Foi example, Fig. 34.4 shows the geometiic shapes defning a simple complementaiy metal-oxide
semiconductoi (CMOS) inveitei. The shapes denote diffeient mateiials, such as aluminum and polysilicon,
and connections, called tonats oi vias.
FIGURE 34.1 Micioelectionic technology complexity.
FIGURE 34.2 DA technology development.
2000 by CRC Press LLC
Design entiy mechanisms foi physical infoimation involve tex-
tual and giaphical techniques. With textual techniques, geometiic
shape and placement aie desciibed via an aitwoik desciiption
language, such as Caltech Inteimediate Foim (CIF) oi Electionic
Design Inteimediate Foim (EDIF). With giaphical techniques,
geometiic shape and placement aie desciibed by iendeiing the
objects on a display teiminal.
The electiical level abstiacts physical infoimation into coiie-
sponding electiical devices, such as capacitors, transistors, and
resistors. Electiical infoimation includes device behavioi in
teims of teiminal cuiient and voltage ielationships. Device behavioi may also be defned in teims of manu-
factuiing paiameteis. Fig. 34.5 shows the electiical symbols denoting a CMOS inveitei.
The logical level abstiacts electiical infoimation into coiiesponding logical elements, such as gates,
gates, and inveiteis. Logical infoimation includes tiuth table and/oi chaiacteiistic-switching algebia equations
and active-level designations. Fig. 34.6 shows the logical symbol foi a CMOS inveitei. Notice how the amount
of infoimation decieases as the level of abstiaction incieases.
FIGURE 34.3 DA abstiactions.
FIGURE 34.5 Electiical abstiaction.
FIGURE 34.6 Logical abstiaction.
FIGURE 34.4 Physical abstiaction.
2000 by CRC Press LLC
Design entiy mechanisms foi electiical and logical abstiactions aie collectively called st|emat taure
techniques. Schematic captuie defnes hieiaichical stiuctuies, commonly called netlists, of components. A
designei cieates instances of components supplied fiom a libiaiy of piedefned components and connects
component pins oi poits via wiies Douglas-Young, 1988; Pechet, 1991].
The functional level abstiacts logical elements into coiiesponding computational units, such as iegisteis,
multiplexeis, and aiithmetic logic units (ALUs). The aichitectuial level abstiacts functional infoimation into
computational algoiithms oi paiadigms. Examples of common computational paiadigms aie listed below:
State diagiams,
Petii nets,
Contiol/data ow giaphs,
Function tables,
Spieadsheets, and
Binaiy decision diagiams.
These highei levels of abstiaction suppoit a moie expiessive, highei-bandwidth" communication inteiface
between engineeis and DA piogiams. Engineeis can focus theii cieative, cognitive skills on concept and
behavioi, iathei than on the complexities of detailed implementation. Associated design entiy mechanisms
typically use haidwaie desciiption languages with a combination of textual and giaphic techniques Biitwistle
and Subiahmanyan, 1988].
Figuie 34.7 shows an example of a simple state diagiam. The state diagiam defnes thiee states, denoted by
ciicles. State-to-state tiansitions aie denoted by labeled aics; state tiansitions depend on the piesent state and
the input X. The output, Z, pei state is given within each state. Since the output is dependent on only the
piesent state, the digital system is classifed as a Mooie nnite state machine. If the output is dependent on the
piesent state and input, then the digital system is classifed as a Mealy fnite state machine.
A haidwaie desciiption language model wiitten in VHDL of the Mooie fnite state machine is given in
Fig. 34.8. The VHDL model, called a Jesgn eny, uses a data ow" desciiption style to desciibe the state
machine Dewey, 1983, 1992, 1997]. The entity statement defnes the inteiface, i.e., the poits. The poits include
two input signals, X and CLK, and an output signal Z. The poits aie of type BIT, which specifes that the signals
may only caiiy the values 0 oi 1. The aichitectuie statement defnes the input/output tiansfoim via two
concuiient signal assignment statements. The inteinal signal STATE holds the fnite state infoimation and is
diiven by a guaided, conditional concuiient signal assignment statement that executes when the associated
block expiession
(CLK`1` and not CLK`STABLE)
is tiue, which is only on the iising edge of the signal CLK. STABLE is a piedefned attiibute of the signal CLK;
CLK`STABLE is tiue if CLK has no changed value. Thus, if not CLK`STABLE" is tiue, meaning that CLK has
FIGURE 34.7 State diagiam.
2000 by CRC Press LLC
just changed value, and CLK`1`," then a iising tiansition has occuiied on CLK. The output signal Z is diiven
by a nonguaided, selected concuiient signal assignment statement that executes any time STATE changes value.
34.3 Synthesis
Figuie 34.9 shows that the synthesis task geneially follows
the design entiy task. Aftei desciibing the desiied system
via design entiy, synthesis DA piogiams aie invoked to
assist geneiating the iequiied detailed design.
Synthesis tianslates oi tiansfoims a design fiom one level
of abstiaction to anothei, moie-detailed level of abstiaction.
The moie-detailed level of abstiaction may be only an intei-
mediate step in the entiie design piocess, oi it may be the
fnal implementation. Synthesis piogiams that yield a fnal
implementation aie sometimes called silicon compilers
because the piogiams geneiate suffcient detail to pioceed diiectly to silicon fabiication Ayies, 1983; Gajski, 1988].
Like design abstiactions, synthesis techniques can be hieiaichically categoiized, as shown in Fig. 34.10. The
highei levels of synthesis offei the advantage of less complexity, but also the disadvantage of less contiol ovei
the fnal design.
Algoiithmic synthesis, also called |e|aora| synthesis, addiesses multicycle" behavioi, which means behavioi
that spans moie than one tonro| se. A contiol step equates to a clock cycle of a synchionous, sequential digital
system, i.e., a state in a fnite-state machine contiollei oi a miciopiogiam step in a miciopiogiammed contiollei.
-- entity statement
entity MOORE_MACHINE is
port (X, CLK : in BIT; Z : out BIT);
end MOORE_MACHINE;
-- aichitectuie statement
architecture FSM of MOORE_MACHINE is
type STATE_TYPE is (A, B, C);
signal STATE : STATE_TYPE : A;
begin
NEXT_STATE:
block (CLK`1` and not CLK`STABLE)
begin
-- guaided conditional concuiient signal assignment statement
STATE < guarded B when (STATEA and X`1`) else
C when (STATEB and X`0`) else
A when (STATEC) else
STATE;
end block NEXT_STATE;
-- unguaided selected concuiient signal assignment statement
with STATE select
Z < '0` when A,
'0` when B,
'1` when C;
end FSM;
FIGURE 34.8 VHDL model.
FIGURE 34.9 Design piocess - synthesis.
2000 by CRC Press LLC
Algoiithmic synthesis typically accepts sequential design desciiptions that defne an input/output tiansfoim,
but piovide little infoimation about the paiallelism of the fnal design Camposano and Wolfe, 1991; Gajski
et al., 1992].
Paititioning decomposes the design desciiption into smallei behaviois. Paititioning is an example of a high-
level tiansfoimation. High-level tiansfoimations include common softwaie piogiamming compilei optimiza-
tions, such as loop uniolling, subpiogiam in-line expansion, constant piopagation, and common subexpiession
elimination.
Resouice allocation associates behaviois with haidwaie computational units, and scheduling deteimines the
oidei in which behaviois execute. Behaviois that aie mutually exclusive can potentially shaie computational
iesouices. Allocation is peifoimed using a vaiiety of giaph clique coveiing oi node coloiing algoiithms.
Allocation and scheduling aie inteidependent, and diffeient synthesis stiategies peifoim allocation and sched-
uling diffeient ways. Sometimes scheduling is peifoimed fist, followed by allocation; sometimes allocation is
peifoimed fist, followed by scheduling; and sometimes allocation and scheduling aie inteileaved.
Scheduling assigns computational units to contiol steps, theieby deteimining which behaviois execute in
which clock cycles. At one extieme, all computational units can be assigned to a single contiol step, exploiting
maximum concuiiency. At the othei extieme, computational units can be assigned to individual contiol steps,
exploiting maximum sequentiality. Seveial populai scheduling algoiithms aie listed below:
As-soon-as-possible (ASAP),
As-late-as-possible (ALAP),
List scheduling,
Foice-diiected scheduling, and
Contiol step splitting/meiging.
ASAP and ALAP scheduling algoiithms oidei computational units based on data dependencies. List scheduling
is based on ASAP and ALAP scheduling, but consideis additional, moie-global constiaints, such as maximum
numbei of contiol steps. Foice-diiected scheduling computes the piobabilities of computational units being
assigned to contiol steps and attempts to evenly distiibute computation activity among all contiol steps. Contiol
step splitting staits with all computational units assigned to one contiol step and geneiates a schedule by
splitting the computational units into multiple contiol steps. Contiol step meiging staits with all computational
units assigned to individual contiol steps and geneiates a schedule by meiging oi combining units and steps
Paulin and Knight, 1989; Camposano and Wolfe, 1991].
Registei tiansfei synthesis takes as input the iesults of algoiithmic synthesis and addiesses pei-cycle"
behavioi, which means the behavioi duiing one clock cycle. Registei tiansfei synthesis selects logic to iealize
the haidwaie computational units geneiated duiing algoiithmic synthesis, such as iealizing an addition opei-
ation with a caiiy-save addei oi iealizing addition and subtiaction opeiations with an aiithmetic logic unit.
FIGURE 34.10 Taxonomy of synthesis techniques.
2000 by CRC Press LLC
Data that must be ietained acioss multiple clock cycles aie identifed, and iegisteis aie allocated to hold the
data. Finally, fnite-state machine synthesis involves state minimization and state assignment. State minimization
seeks to eliminate iedundant oi equivalent states, and state assignment assigns binaiy encodings foi states to
minimize combinational logic Biayton et al., 1992; Sasao, 1993].
Logic synthesis optimizes the logic geneiated by iegistei tiansfei synthesis and maps the optimized logic
opeiations onto physical gates suppoited by the taiget fabiication technology. Technology mapping consideis
the foundiy cell libiaiy and associated electiical iestiictions, such as fan-in/fan-out limitations.
34.4 Yerihcatiun
Figuie 34.11 shows that the verincation task geneially follows the synthesis task. The veiifcation task checks
the coiiectness of the function and peifoimance of a design to ensuie that an inteimediate oi fnal design
faithfully iealizes the initial, desiied specifcation. Thiee majoi types of veiifcation aie listed below:
Timing analysis,
Simulation, and
Emulation.
Timing Ana!ysis
Timing analysis checks that the oveiall design satisfes
opeiating speed iequiiements and that individual sig-
nals within a design satisfy tiansition iequiiements.
Common signal tiansition iequiiements, also called
mng |a:arJs, include rse and [a|| mes, roagaon
Je|ays, t|ot| eroJs, rate tonJons, g|t| Jeeton,
and seu and |o|J mes. Foi instance, setup and hold
times specify ielationships between data and contiol
signals to ensuie that memoiy devices (level-sensitive
latches oi edge-sensitive ip-ops) coiiectly and ieli-
ably stoie desiied data. The data signal caiiying the
infoimation to be stoied in the memoiy device must
be stable foi a peiiod equal to the setup time piioi to
the contiol signal tiansition to ensuie that the coiiect value is sensed by the memoiy device. Also, the data
signal must be stable foi a peiiod equal to the hold time aftei the contiol signal tiansition to ensuie that the
memoiy device has enough time to stoie the sensed value.
Anothei class of timing tiansition iequiiements, commonly called signal integiity checks, include re[etons,
trossa||, ground bounce, and e|etromagnet ner[erente. Signal integiity checks aie typically iequiied foi
high-speed designs opeiating at clock fiequencies above 75 MHz. At such high fiequencies, the tiansmission
line behavioi of wiies must be analyzed. A wiie should be piopeily teiminated, i.e., connected, to a poit having
an impedance matching the wiie chaiacteiistic impedance to pievent signal ieections. Signal ieections aie
poitions of an emanating signal that bounce back" fiom the destination to the souice. Signal ieections ieduce
the powei of the emanating signal and can damage the souice. Ciosstalk iefeis to unwanted ieactive coupling
between physically adjacent signals, pioviding a connection between signals that aie supposed to be electiically
isolated. Giound bounce is anothei signal integiity pioblem. Since all conductive mateiial has a fnite
impedance, a giound signal netwoik does not in piactice offei the exact same electiical potential thioughout
an entiie design. These potential diffeiences aie usually negligible because the distiibutive impedance of the
giound signal netwoik is small compaied with othei fnite-component impedances. Howevei, when many
signals switch value simultaneously, a substantial cuiient can ow thiough the giound signal netwoik. High
inteimittent cuiients yield piopoitionately high inteimittent potential diops, i.e., giound bounces, which can
FIGURE 34.11 Design piocess - veiifcation.
2000 by CRC Press LLC
cause unwanted ciicuit behavioi. Finally, electiomagnetic inteifeience iefeis to signal haimonics iadiating fiom
design components and inteiconnects. This haimonic iadiation may inteifeie with othei electionic equipment
oi may exceed applicable enviionmental safety iegulatoiy limits McHaney, 1991].
Timing analysis can be peifoimed dynamically oi statically. Dynamic timing analysis exeicises the design
via simulation oi emulation foi a peiiod of time with a set of input stimuli and iecoids the timing behavioi.
Static timing analysis does not exeicise the design via simulation oi emulation. Rathei, static analysis iecoids
timing behavioi based on the timing behavioi, e.g., piopagation delay, of the design components and theii
inteiconnection.
Static timing analysis techniques aie piimaiily ||ot| oreneJ oi a| oreneJ. Block-oiiented timing analysis
geneiates design input (also called piimaiy input) to design output (also called piimaiy output), and piopa-
gation delays by analyzing the design stage-by-stage" and by summing up the individual stage delays. All
devices diiven by piimaiy inputs constitute stage 1, all devices diiven by the outputs of stage 1 constitute
stage 2, and so on. Staiting with the fist stage, all devices associated with a stage aie annotated with woist-
case delays. A woist-case delay is the piopagation delay of the device plus the delay of the last input to aiiive
at the device, i.e., the signal path with the longest delay leading up to the device inputs. Foi example, the device
labeled H" in stage 3 in Fig. 34.12 is annotated with the woist-case delay of 13, iepiesenting the device
piopagation delay of 4 and the delay of the last input to aiiive thiough devices B" and C" of 9 McWilliams
and Widdoes, 1978]. When the devices associated with the last stage, i.e., the devices diiving the piimaiy
outputs, aie piocessed, the accumulated woist-case delays iecoid the longest delay fiom piimaiy inputs to
piimaiy outputs, also call the ciitical paths. The ciitical path foi each piimaiy output is highlighted in Fig. 34.12.
Path-oiiented timing analysis geneiates piimaiy input to piimaiy output piopagation delays by tiaveising
all possible signal paths one at a time. Thus, fnding the ciitical path via path-oiiented timing analysis is
equivalent to fnding the longest path thiough a diiected acyclic giaph, wheie devices aie giaph veitices and
inteiconnections aie giaph edges Sasiki et al., 1978].
To account foi iealistic vaiiances in component timing due to manufactuiing toleiances, aging, oi enviion-
mental effects, timing analysis often piovides stochastic oi statistical checking capabilities. Statistical timing
analysis uses iandom-numbei geneiatois based on empiiically obseived piobabilistic distiibutions to deteimine
component timing behavioi. Thus, statistical timing analysis desciibes design peifoimance and the likelihood
of the design peifoimance.
Simu!atiun
Simulation exeicises a design ovei a peiiod of time by applying a seiies of input stimuli and geneiating the
associated output iesponses. The geneial event-diiven, also called schedule-diiven, simulation algoiithm is
diagiammed in Fig. 34.13. An event is a change in signal value. Simulation staits by initializing the design;
FIGURE 34.12 Block-oiiented static timing analysis.
2000 by CRC Press LLC
initial values aie assigned to all signals. Initial values include staiting values and pending values that constitute
futuie events. Simulation time is advanced to the next pending event(s), signals aie updated, and sensitized
models aie evaluated Pooch, 1993]. The piocess of evaluating the sensitized models yields new, potentially
diffeient, values foi signals, i.e., a new set of pending events. These new events aie added to the list of pending
events, time is advanced to the next pending event(s), and the simulation algoiithm iepeats. Each pass thiough
the loop in Fig. 34.13 of evaluating sensitized models at a paiticulai time step is called a simulation cycle.
Simulation ends when the design yields no fuithei activity, i.e., when theie aie no moie pending events to
piocess.
Logic simulation is computationally intensive foi laige, complex designs. As an example, considei simulating
1 s of a 200K-gate, 20-MHz piocessoi design. By assuming that, on aveiage, only 10% of the total 200K gates
aie active oi sensitized on each piocessoi clock cycle, Eq. 34.1 shows that simulating 1 s of actual piocessoi
time equates to 400 billion events.
(34.1)
Assuming that, on aveiage, a simulation piogiam executes 50 computei instiuctions pei event on a computei
capable of piocessing 50 million instiuctions pei second (MIP), Eq. 34.1 also shows that piocessing 400 billion
events iequiies 140 h oi just shoit of 6 days. Fig. 34.14 shows how simulation computation geneially scales
with design complexity.
To addiess the giowing computational demands of simulation, seveial simulation acceleiation techniques
have been intioduced. Schedule-diiven simulation, explained above, can be acceleiated by iemoving layeis of
inteipietation and iunning a simulation as a native executable image; such an appioach is called complied,
scheduled-diiven simulation.
As an alteinative to schedule-diiven simulation, tyt|e-Jren simulation avoids the oveihead of event queue
piocessing by evaluating all devices at iegulai inteivals of time. Cycle-diiven simulation is effcient when a
design exhibits a high degiee of concuiiency, i.e., when a laige peicentage of the devices aie active pei simulation
cycle. Based on the staging of devices, devices aie ran|-orJereJ to deteimine the oidei in which they aie evaluated
at each time step to ensuie the coiiect causal behavioi yielding the piopei oideiing of events. Foi functional
veiifcation, logic devices aie often assigned zeio-delay and memoiy devices aie assigned unit-delay. Thus, any
numbei of stages of logic devices may execute between system clock peiiods.
In anothei simulation acceleiation technique, message-Jren simulation, also called ara||e| oi Jsr|ueJ
simulation, device execution is divided among seveial piocessois and the device simulations communicate
FIGURE 34.13 Geneial event-diiven simulation algoiithm.
400 billion events 20 million clock cycles 200K gates 10 activity
140 h 400 billion events
50 instructions
event
-----------------------------------


50 million instructions
s
------------------------------------------------------

2000 by CRC Press LLC

event activity via messages. Messages aie communicated using conseivative oi optimistic stiategies. Optimistic
message-passing stiategies, such as me war

and

|a:y tante||aon,

make assumptions about futuie event activity
to advance local device simulation. If the assumptions aie coiiect, the piocessois opeiate moie independently
and bettei exploit paiallel computation. Howevei, if the assumptions aie incoiiect, then local device simulations
may be foiced to ioll back" to synchionize local device simulations Biyant, 1979; Chandy and Misia, 1981].
Schedule-diiven, cycle-diiven, and message-diiven simulations aie softwaie-based simulation acceleiation
techniques. Simulation can also be acceleiated by ielegating ceitain simulation activities to dedicated haidwaie.
Foi example,

|arJware moJe|ers

can be attached to softwaie simulatois to acceleiate the activity of device
evaluation. As the name implies, haidwaie modeling uses actual haidwaie devices instead of softwaie models
to obtain stimulus/iesponse infoimation. Using actual haidwaie devices ieduces the expense of geneiating and
maintaining softwaie models and piovides an enviionment to suppoit application softwaie development.
Howevei, it is sometimes diffcult foi a slave haidwaie modelei to pieseive accuiate ieal-time device opeiating
iesponse chaiacteiistics within a mastei non-ieal-time softwaie simulation enviionment. Foi example, some
haidwaie devices may not be able to ietain state infoimation between invocations, so the haidwaie modelei
must save the histoiy of pievious inputs and ieapply them to biing the haidwaie device to the coiiect state to
apply a new input.
Anothei technique foi addiessing the giowing computational demands of simulation is via simulation
engines. A simulation engine can be viewed as an extension of the simulation acceleiation technique of haidwaie
modeling. With a haidwaie modelei, the simulation algoiithm executes in softwaie and component evaluation
executes in dedicated haidwaie. With a simulation engine, the simulation algoiithm

anJ

component evaluation
execute in dedicated haidwaie. Simulation engines aie typically two to thiee oideis of magnitude fastei than
softwaie simulation Takasaki et al., 1989].
Ana!ug Simu!atiun

Analog simulation involves time-domain analyses and fiequency-domain analyses, which aie geneially con-
ducted using some foim of diiect cuiient (DC) simulation, diagiammed in Fig. 34.15. DC simulation detei-
mines the quiescent oi steady-state opeiating point foi a ciicuit, specifying node voltages

,

branch cuiients,
input/output iesistances, element sensitivities, and input/output gains Chua and Lin, 1975; Nagel, 1975].
Seveial populai equation foimulation schemes aie summaiized in Table 34.1. Equation foimulation schemes
geneiate a set of lineai equations denoting ielationships between ciicuit voltages and cuiients; these ielation-
ships aie based on the physical piinciple of the conseivation of eneigy expiessed via

Kirchoff 's current law

(KCL), Kirchoff 's voltage law

(KVL), and bianch constitutive ielationships (BCRs). A ciicuit having

N

nodes
and

B bianches possesses 2

B

independent vaiiables defning

B

bianch voltages and

B

bianch cuiients. These

FIGURE 34.14 Simulation iequiiements.
2000 by CRC Press LLC

vaiiables aie goveined by 2B

lineaily independent equations composed of

N

- 1 KCL equations,

B

-

N

- 1 KVL
equations, and B

BCR equations Hachtel et al., 1971; Ho et al., 1975].
Equation-oideiing schemes augment equation foimulation schemes by ieoiganizing, modifying, and scaling
the equations to impiove the effciency and/oi accuiacy of the subsequent equation solution scheme. Moie
specifcally, equation-oideiing schemes seek to impiove the diagonal dominance" stiuctuie of the coeffcient
matiix by maximizing the numbei of off-diagonal" zeios. Populai equation-oideiing schemes include pivoting
and iow oideiing (Maikowitz) Zlatev, 1980].
Finally, equation solution schemes deteimine the values foi the independent vaiiables that comply with the
goveining equations. Theie aie basically two types of equation solution schemes: explicit and implicit. Explicit
solution schemes, such as Gaussian elimination and/oi LU factoiization, deteimine independent vaiiable values
using closed-foim, deteiministic techniques. Implicit solution schemes, such as Gauss-Jacobi and Gauss-Seidel,
deteimine independent vaiiable values using iteiative, nondeteiministic techniques.

Emu!atiun

Emulation, also called

tomuer-aJeJ rooyng, veiifes a design by iealizing the design in piepioduction"
haidwaie and exeicising the haidwaie. The teim

reroJuton

haidwaie means nonoptimized haidwaie
pioviding the coiiect functional behavioi, but not necessaiily the coiiect peifoimance. That is, emulation
haidwaie may be slowei, iequiie moie aiea, oi dissipate moie powei than pioduction haidwaie. At piesent,
piepioduction haidwaie commonly involves some foim of

programmable logic devices

(PLDs), typically feld-
piogiammable

gate arrays

(FPGAs). PLDs piovide geneiic combinational and sequential digital system logic
that can be piogiammed to iealize a wide vaiiety of designs Walteis, 1991].
Emulation offeis the advantage of pioviding piototype haidwaie eaily in the design cycle to check foi eiiois
oi inconsistencies in initial functional specifcations. Pioblems can be isolated and design modifcations can
be easily accommodated by iepiogiamming the logic devices. Emulation can suppoit functional veiifcation
at computational iates much gieatei than conventional simulation. Howevei, emulation does not geneially
suppoit peifoimance veiifcation because, as explained above, piototype haidwaie typically does not opeiate
at pioduction clock iates.

FIGURE 34.15

DC simulation.
TABLE 34.1

Common Ciicuit Equation Foimulation Schemes

Equation Foimulation Schemes Desiied Unknowns
Nodal analysis Node voltages
Modifed nodal analysis Node voltages
Dependent souice cuiients
Independent voltage souice cuiients
Spaise tableau analysis Node voltages
Bianch cuiients
Bianch voltages
Reduced tableau analysis Node voltages
Bianch cuiients
Tiee analysis Tiee bianch voltages
Link analysis Link bianch cuiients
2000 by CRC Press LLC

34.5 Physica! Design

Figuie 34.16 shows that the physical design task geneially follows the veiifcation task. Having validated the
function and peifoimance of the detailed design duiing veiifcation, physical design iealizes the detailed design
by tianslating logic into actual haidwaie. Physical design involves placement, iouting, aitwoik geneiation, iules
checking, and back annotation Sait and Youseff, 1995].
Placement tiansfoims a logical hieiaichy into a physical hieiaichy by defning how haidwaie elements aie
oiiented and aiianged ielative to each othei. Placement deteimines the oveiall size, i.e., aiea, a digital system
will occupy. Two populai placement algoiithms aie

mntu and

smu|aeJ annea|ng

. Mincut placement tech-
niques gioup highly connected cells into clusteis. Then, the clusteis aie soited and aiianged accoiding to usei-
supplied piioiities. Simulated annealing conducts a seiies of tiial-and-eiioi expeiiments by pseudoiandomly
moving cells and evaluating the iesulting placements, again accoiding to usei-supplied piioiities.
Routing defnes the wiies that establish the iequiied poit-to-poit connections. Routing is often peifoimed
in two stages: global and local. Global iouting assigns netwoiks to majoi wiiing iegions, called tiacks; local
iouting defnes the actual wiiing foi each netwoik within its assigned tiack. Two common classes of iouting
algoiithms aie

t|anne|

and ma:e

. Channel iouting connects poits abutting the same tiack. Maze iouting, also
called switch-box iouting, connects poits abutting diffeient channels. Routing consideis a vaiiety of metiics,
including timing skew, wiie length, numbei of vias, and numbei of jogs (coineis) Spinks, 1985; Pieas et al.,
1988].
Rules checking veiifes that the fnal layout of geometiic shapes and theii oiientation complies with logical,
electiical, and physical constiaints. Logical iules veiify that the implementation iealizes the desiied digital
system. Electiical iules veiify confoimance to loading, noise maigins, and fan-in/fan-out connectivity constiaints.
Finally, physical iules veiify confoimance to dimensional, spacing, and alignment constiaints Hollis, 1987].

34.6 Test

Figuie 34.17 shows that

test follows physical design. Aftei physical design, the digital system is manufactuied
and test checks the iesulting haidwaie foi coiiect function and peifoimance. Thus, the piimaiy objective of
test is to detect a faulty device by applying input test stimuli and obseiving expected iesults Buckioyd, 1989;
Weyeiei and Goldemund, 1992].
The test task is diffcult because designs aie giowing in complexity; moie components piovide moie oppoi-
tunity foi manufactuiing defects. Test is also challenged by new micioelectionic fabiication piocesses. These
new piocesses suppoit highei levels of integiation that piovide fewei access points to piobe inteinal electiical
nodes and new failuie modes that piovide moie oppoitunity foi manufactuiing defects.

FIGURE 34.16

Design piocess - physical design.
2000 by CRC Press LLC

Fau!t Mude!ing

What is a fault: A fault is a manufactuiing oi aging defect that causes a device to opeiate incoiiectly oi to fail.
A sample listing of common integiated ciicuit physical faults aie given below:
Wiiing faults,
Dielectiic faults,
Thieshold faults, and
Soft faults.
Wiiing faults aie unwanted opens and shoits. Two wiies oi netwoiks that should be electiically connected, but
aie not connected constitute an open. Two wiies oi netwoiks that should not be electiically connected, but aie
connected constitute a shoit. Wiiing faults can be caused by manufactuiing defects, such as metallization and
etching pioblems, oi aging defects, such as coiiosion and

electromigration

. Dielectiic faults aie electiical
isolation defects that can be caused by

masking defects, chemical impuiities, mateiial impeifections, oi
electiostatic dischaige. Thieshold faults occui when the tuin-on and tuin-off voltage potentials of electiical
devices exceed allowed ianges. Soft faults occui when iadiation exposuie tempoiaiily changes electiical chaige
distiibutions. Such changes can altei ciicuit voltage potentials, which can, in tuin, change logical values, also
called Jrong |s. Radiation effects aie called soft" faults because the haidwaie is not peimanently damaged
Zobiist, 1993].
To simplify the task of fault testing, the physical faults desciibed above aie tianslated into logical faults.
Typically, a single logical fault coveis seveial physical faults. A populai logical fault model is the sng|e sut|
|ne (SSL) fault model. The single stuck line fault model suppoits faults that denote wiies peimanently set to
a logic 0, stuck-at-0," oi a logic 1, stuck-at-1." Building on the single stuck line fault model, the mu||e sut|
|ne (MSL) fault model suppoits faults wheie multiple wiies aie stuck-at-0/stuck-at-1. Stuck fault models do
not addiess all physical faults because not all physical faults iesult in signal lines peimanently set to low oi high
voltages, i.e., stuck-at-0 oi stuck-at-1 logic faults. Thus, othei fault models have been developed to addiess
specifc failuie mechanisms. Foi example, the |rJgng fault model addiesses electiical shoits that cause
unwanted coupling oi spuiious feedback loops.
FIGURE 34.17 Design piocess - test.
2000 by CRC Press LLC
Fau!t Testing
Once the physical faults that may cause device malfunction have been identifed and categoiized and how the
physical faults ielate to logical faults has been deteimined, the next task is to develop tests to detect these faults.
When the tests aie geneiated by a computei piogiam, this activity is called auomat es rogram generaon
(ATPG). Examples of fault testing techniques aie listed below:
Stuck-at techniques,
Scan techniques,
Signatuie techniques,
Coding techniques, and
Electiical monitoiing techniques.
Basic stuck-at fault testing techniques addiess combinational digital systems. Thiee of the most populai
stuck-at fault testing techniques aie the D algoiithm, the Path-Oiiented Decision Making (Podem) algoiithm,
and the Fan algoiithm. These algoiithms fist identify a ciicuit fault, e.g., stuck-at-0 oi stuck-at-1, and then
tiy to geneiate an input stimulus that detects the fault and makes the fault visible at an output. Detecting a
fault is called [au| sens:aon and making a fault visible is called [au| roagaon. To illustiate this piocess,
considei the simple combinational design in Fig. 34.18 Goel, 1981; Fujiwaia and Shimono, 1983].
The combinational digital design is defective because a
manufactuiing defect has caused the output of the top
gate to be peimanently tied to giound, i.e., stuck-at-
0, using a positive logic convention. To sensitize the fault,
the inputs A and B should both be set to 1, which should
foice the top gate output to a 1 foi a good ciicuit. To
piopagate the fault, the inputs C and D should both be
set to 0, which should foice the gate output to 1, again
foi a good ciicuit. Thus, if A 1, B 1, C 0, and D 0
in Fig. 34.18, then a good ciicuit would yield a 1, but the
defective ciicuit yields a 0, which detects the stuck-at-0
fault at the top gate output.
Sequential ATP geneiation is moie diffcult than combinational ATPG because exeicising oi sensitizing a
paiticulai ciicuit path to detect the piesence of a possible manufactuiing fault may iequiie a sequente of input
test vectois. One technique foi testing sequential digital systems is scan fault testing. Scan fault testing is an
example of Jesgn [or esa||y (DFT) because it modifes oi constiains a design in a mannei that facilitates
fault testing. Scan techniques impose a logic design discipline that connects all state iegisteis into one oi moie
chains to foim scan iings," as shown in Fig. 34.19 Eichelbeigei and Williams, 1977].
Duiing noimal device opeiation, the scan iings aie disabled and the iegisteis seive as conventional memoiy
(state) stoiage elements. Duiing test opeiation, the scan iings aie enabled and stimulus test vectois aie shifted
into the memoiy elements to set the state of the digital system. The digital system is exeicised foi one clock
cycle and then the iesults aie shifted out of the scan iing to iecoid the iesponse.
A vaiiation of scan DFT, called |ounJary stan, has been defned foi testing integiated ciicuits on piinted
ciicuit boaids (PCBs). Advancements in PCB manufactuiing, such as fne-lead components, suiface mount
assembly, and multichip modules, have yielded high-density boaids with fewei access points to piobe individual
pins. These PCBs aie diffcult to test. As the name implies, boundaiy scan imposes a design discipline foi PCB
components to enable the input/output pins of the components to be connected into scan chains. As an example,
Fig. 34.20 shows a simple PCB containing two integiated ciicuits confguied foi boundaiy scan. Each integiated
ciicuit contains scan iegisteis between its input/output pins and its coie logic to enable the PCB test bus to
contiol and obseive the behavioi of individual integiated ciicuits Paikei, 1989].
Anothei DFT technique is signatuie analysis, also called |u|-n se|[-es (BIST). Signatuie testing techniques
use additional logic, typically lineai feedback shift iegisteis, to geneiate automatically pseudoiandom test
vectois. The output iesponses aie compiessed into a single vectoi and compaied with a known good vectoi. If
the output iesponse vectoi does not exactly match the known good vectoi, then the design is consideied faulty.
FIGURE 34.18 Combinational logic stuck-at fault
testing.
2000 by CRC Press LLC
Matching the output iesponse vectoi and a known good vectoi does not guaiantee coiiect haidwaie; howevei,
if enough pseudoiandom test vectois aie exeicised, then the chances aie acceptably small of obtaining a false
positive iesult. Signatuie analysis is often used to test memoiies Agiawal et al., 1993].
Coding test techniques encode signal infoimation so that eiiois can be detected and possibly coiiected.
Although often implemented in softwaie, coding techniques can also be implemented in haidwaie. Foi example,
a simple coding technique called ary t|et|ng is often implemented in haidwaie. Paiity checking adds an
extia bit to multibit data. The paiity bit is set such that the total numbei of logic 1s in the multibit data anJ
paiity bit is eithei an even numbei (even paiity) oi an odd numbei (odd paiity). An eiioi has occuiied if an
even-paiity-encoded signal contains an odd numbei of logic 1s oi if an odd-paiity-encoded signal contains an
even numbei of logic 1s. Coding techniques aie used extensively to detect and coiiect tiansmission eiiois on
system buses and netwoiks, stoiage eiiois in system memoiy, and computational eiiois in piocessois Peteison
and Weldon, 1972].
Finally, electiical monitoiing testing techniques, also called cuiient/voltage testing, iely on the simple obsei-
vation that an out-of-iange cuiient oi voltage often indicates a defective oi bad pait. Possibly a shoit oi open
is piesent causing a paiticulai input/output signal to have the wiong voltage oi cuiient. Cuiient testing, oi I
JJq
esng, is paiticulaily useful foi digital systems using CMOS integiated ciicuit technology. Noimally, CMOS
ciicuits have veiy low static oi quiescent cuiients. Howevei, physical faults, such as gate oxide defects, can
inciease static cuiient by seveial oideis of magnitude. Such a substantial change in static cuiient is stiaight-
foiwaid to detect. The piincipal advantages of cuiient testing aie that the tests aie simple and the fault models
addiess detailed tiansistoi-level defects. Howevei, cuiient testing iequiies that enough time be allotted between
input stimuli to allow the ciicuit to ieach a static state, which slows testing down and causes pioblems with
ciicuits that cannot be tested at scaled clock iates.
FIGURE 34.19 Scan-based DFT.
FIGURE 34.20 Boundaiy scan.
2000 by CRC Press LLC
34.7 Summary
DA technology offeis the potential of seiving as a poweiful fulcium in leveiaging the skills of a designei against
the giowing demands of electionic system design and manufactuiing. DA piogiams help to ielieve the designei
of the buiden of tedious, iepetitive tasks that can be laboi-intensive and eiioi pione.
DA technology can be bioken down into seveial topical aieas, such as design entiy, synthesis, veiifcation,
physical design, and test. Each topical aiea has developed an extensive body of knowledge and expeiience.
Design entiy defnes a desiied specifcation. Synthesis iefnes the initial design specifcation into a detailed
design ieady foi implementation. Veiifcation checks that the detailed design faithfully iealizes the desiied
specifcation. Physical design defnes the implementation, i.e., the actual haidwaie. Finally, test checks that the
manufactuied pait is functionally and paiametiically coiiect.
Dehning Terms
Bipolar: Type of semiconductoi tiansistoi that involves both minoiity and majoiity caiiiei conduction
mechanisms.
BiCMOS: Bipolai/complementaiy metal-oxide semiconductoi. A logic family and foim of micioelectionic
fabiication.
Branch: A ciicuit element between two nodes. Bianch cuiient is the cuiient thiough the bianch. Bianch
voltage is the potential diffeience between the nodes. The ielationship between the bianch cuiient and
voltage is defned by the bianch constitutive ielationship.
Capacitor: Two-teiminal electionic device goveined by the bianch constitutive ielationship, Chaige Capac-
itance Voltage.
CMOS: Complementaiy metal-oxide semiconductoi. A logic family and foim of micioelectionic fabiication.
Data Flow: Nonpioceduial modeling style in which the textual oidei that statements aie wiitten has no beaiing
on the oidei in which they execute.
Design automation: Computei piogiams that assist engineeis in peifoiming digital system development.
Design entry: Aiea of DA addiessing modeling analog and digital electionic systems. Design entiy uses a
hieiaichy of models involving physical, electiical, logical, functional, and aichitectuial abstiactions.
Electromigration: Giadual eiosion of metal due to excessive cuiients.
Fan-in/fan-out: Fan-in defnes the maximum numbei of logic elements that may diive anothei logic element.
Fan-out defnes the maximum numbei of logic elements a logic element may diive.
Finite state machine: Sequential digital system. A fnite state machine is classifed as eithei Mooie and Mealy.
Gate array: Application-specifc integiated ciicuit implementation technique that iealizes a digital system by
piogiamming the metal inteiconnect of a piefabiicated aiiay of gates.
Gate oxide: Dielectiic insulating mateiial between the gate and souice/diain teiminals of a MOS tiansistoi.
Ground bounce: Tiansient condition when the potential of a giound netwoik vaiies appieciably fiom its
unifoim static value.
Integrated circuit: Electionic ciicuit manufactuied on a monolithic piece of semiconductoi mateiial, typically
silicon.
Kirchoff 's current law: The amount of cuiient enteiing a ciicuit node equals the amount of cuiient leaving
a ciicuit node.
Kirchoff 's voltage law: Any closed loop of ciicuit bianch voltages sums to zeio.
Masking defects: Defects in masking plate patteins used foi integiated ciicuit lithogiaphy that iesult in eiiant
mateiial composition and/oi placement.
Multichip modules: Multiple integiated ciicuits inteiconnected on a monolithic substiate.
Netlist: Collection of wiies that aie electiically connected to each othei.
NMOS: N-type metal-oxide semiconductoi. A logic family and foim of micioelectionic fabiication.
Node voltage: Potential of a ciicuit node ielative to giound potential.
Programmable logic devices (PLDs): Geneiic logic devices that can be piogiammed to iealize specifc digital
systems. PLDs include piogiammable logic aiiays, piogiammable aiiay logic, memoiies, and feld-pio-
giammable gate aiiays.
2000 by CRC Press LLC
Resistor: Two-teiminal electionic device goveined by the bianch constitutive ielationship, Voltage Resistance
Cuiient.
Silicon compilation: Synthesis application that geneiates fnal physical design ieady foi silicon fabiication.
Simulation: Computei piogiam that examines the dynamic semantics of a model of a digital system by applying
a seiies of inputs and geneiating the coiiesponding outputs. Majoi types of simulation include schedule
diiven, cycle diiven, and message diiven.
Skew: Timing diffeience between two events that aie supposed to occui simultaneously.
Standard cell: Application-specifc integiated ciicuit implementation technique that iealizes a digital system
using a libiaiy of piedefned (standaid) logic cells.
Synthesis: Computei piogiam that helps geneiate a digital/analog system design by tiansfoiming a high-level
model of abstiact behavioi into a lowei-level model of moie-detailed behavioi.
Test: Aiea of EDA that addiesses detecting faulty haidwaie. Test involves stuck-at, scan, signatuie, coding, and
monitoiing techniques.
Timing analysis: Veiifes timing behavioi of electionic system including iise time, fall time, setup time, hold
time, glitch detection, clock peiiods, iace conditions, ieections, and cioss talk.
Transistor: Electionic device that enables a small voltage and/oi cuiient to contiol a laigei voltage and/oi
cuiient. Foi analog systems, tiansistois seives as amplifeis. Foi digital systems, tiansistois seive as
switches.
Verincation: Aiea of EDA that addiesses validating designs foi coiiect function and expected peifoimance.
Veiifcation involves timing analysis, simulation, emulation, and foimal pioofs.
VHDL: Haidwaie desciiption language used as an inteinational standaid foi communicating electionic systems
infoimation.
Via: Connection oi contact between two mateiials that aie otheiwise electiically isolated.
Re!ated Tupics
23.2 Testing 25.1 Integiated Ciicuit Technology 25.3 Application-Specifc Integiated Ciicuits
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2000 by CRC Press LLC
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