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# Dept of Avionics Even Semester Jan 2014 Digital Electronics and VLSI Design Assignment I Logic Families TTL

CMOS BICMOS ECL Course Co-coordinator Dr. J. Sheeba Rani 1. A CMOS inverter has VOH=0.8V, VOL=0.1V, VIH=0.6V, VIL=0.4V. Calculate the noise margins for this circuit. What would happen to the output if the input to this circuit was at 0.5V? 2. Complete the complex CMOS gate below by adding the require NMOS transistors. Write the logic equation for the completed circuit (i.eZ= ?)

3. For this problem, consider the convention that a logical one corresponds to a high voltage level and a logical zero corresponds to a low voltage level. Thus, when the voltage vA associated with the Boolean variable A is high(3V), A =1. When vA is l ow ( 0V ),A =0. The same relation holds with vB and B, vC and C. Assume also the following: i. ii. The high voltage level is much greater than the threshold voltage. The on resistance of the MOSFET is 100.

iii. The off resistance of the MOSFET is 100M. Then, for each circuit in Fig.2: a. Generate a truth table which shows how the variable C (associated with vC) depends on the inputs A(associated with vA)and B (associated with vB). b. For each particular entry of C in the corresponding truth table of part a., find the value of the output voltage vC .

4. The data sheet of a quad two-input NAND gate specifies the following parameters: IOH(max.)=0.4mA, VOH(min.)=2.7 V, VIH (min.)=2V, VIL(max.)=0.8 V, VOL(max.)=0.4 V, IOL(max.)=8 mA,IIL(max.)=0.4 mA, IIH (max.)=20_A, ICCH(max.)=1.6 mA, ICCL(max.)=4.4 mA, tpLH =tpHL=15 ns and a supply voltage range of 5 V. Determine (a) the average power dissipation of a single NAND gate, (b) the maximum average propagation delay of a single gate, (c) the HIGH-state noise margin and (d) the LOW-state noise margin How many NAND gate inputs can be driven from the output of a NAND gate of this type?

5. Explain the following circuit Operation and find what type of gate operation it is doing

6. Determine the current being sourced by gate 1 when its output is HIGH and sunk by it when its output is LOW. All gates are from the standard TTL family, given that IIH = 40_A and IIL= 1.6 mA.

7. The data sheet of a quad two-input AND gate (type 74S08) specifies the propagation delay and power supply parameters as VCC=5.0V (typical), ICCH (for all four gates)=18 mA, ICCL (for all four gates)=32 mA, tpLH= 4.5 ns and tpHL=5.0 ns. Determine the speedpower product specification. 8. Draw the logic diagram using CMOS Y = AB+AB 9. Give the salient features of ECL Logic 10. For the given circuit draw the input verses output voltage characteristics (Transfer Characteristics) The specifications are