2012 IEEE 21st Asian Test Symposium

A Test Screening Method for 28nm HK/MG Single-port and Dual-port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues
Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara and Kazuyoshi Okamoto
Renesas Electronics Corporation, Kodaira, Tokyo, Japan {koji.nii.uj, yasumasa.tsukamoto.gx, yuichiro.ishii.ud, makoto.yabuuchi.ub, hidehiro.fujiwara.vj, kazuyoshi.okamoto.vf}@renesas.com
Abstract We discuss dynamic read and write stabilities of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. Test chips which include 1-Mbit single-port SRAM and 512-kbit dual-port SRAM macros are designed and fabricated. A Good correlation for minimum operating voltage (Vmin) between simulation and measurement is observed. We also introduce the test screening circuitry which takes the dynamic stability into consideration. We obtain the appropriate screening results from the evaluations of the testchip. It is also confirmed assured screening with 2.0% dynamic stability fault detection for an SoC product. Keywords-SRAM, 6T, 8T, single-port, dual-port, 28nm, Dynamic stability,Read/Write disturb, test screening, fault ditect
(a)
WL

(b)
BLB

WLB /BLB PUR SN1 SN2 PDL PDR PGRB PGRA /BLA
SN1 SN2

PUL SN1

PUR /BL SN2 PGR PDR

PUL PGLB PGLA BLA

BL

PGL PDL

WLA Pull-up PMOS Pull-down NMOS Pass-gate NMOS Wordline Bitline : : : : : PUL, PUR PDL, PDR PGL, PGR, PGLA, PGLB, PGRA, PGRB WL, WLA, WLB BL, /BL, BLA, /BLA, BLB, /BLB

Figure 1. Schematics of SRAM bitcells: (a) 6T single-port (SP) SRAM, (b) 8T dual-port (DP) SRAM.
(a)
SN1 SN2

(b)

I.

INTRODUCTION
SNML SN2

For system-on-chip (SoC) applications in deep submicron era, the robust design against process variations becomes essential. Typical embedded SRAM bitcells of 6T single-port (SP) SRAM and 8T dual-port (DP) SRAM (shown in Fig. 1) are especially facing both the voltage and area scaling limitations because of increasing Vth variation of transistors. To overcome such limitations, many SRAM assist circuitries have been reported [1-4] to improve the minimum operating voltage (Vmin). These reports are discussed using conventional DC characteristics such as static noise margin (SNM) [5] and write noise margin (WNM) as shown in Fig. 2. However, some assist circuits made use of benefits of dynamic characteristic which is not assessed by DC analysis [6, 7], and thus, the analysis of dynamic stability has attracted much attention of SRAM researchers [8-12]. Meanwhile, the operating speed is about to exceed 1 GHz frequency in 28-nm nodes thanks to the high-k and metal gate (HK/MG) transistors, which have good Ion-Ioff characteristics and small local Vth variation compared to previous poly-Si gate. This means that the dynamic stability, which depends on the wordline (WL) pulse width, bitline (BL) swing, voltage noise and the other AC parameters, should be considered for robust design and manufacturing. In this paper, we discuss the dynamic stability considering with local Vth variation not only for SP SRAM but also for DP SRAM [13] in section II. Next, the comparison with simulation results and measured Vmins are shown. In section IV, a screening circuitry of dynamic stability faults is presented and screening results of a test chip and an SoC product are shown.
1081-7735/12 $26.00 2012 IEEE DOI 10.1109/ATS.2012.59 246

SN2

SNMR

WNM

SN1

SN1

Figure 2. Conventional DC stability: (a) Static noise margin (SNM) [5], (b) Write noise margin (WNM).

II.

DYNAMIC STABILITY FOR SRAM

A. Dynamic Stability for Single-port (SP) SRAM Figure 3 shows the concepts of dynamic stability against the WL pulse width (TWL) for read and write operations, respectively. In read operation, the internal nodes SN1 and SN2 of the bitcell are not flipped for the short TWL while SN1 and SN2 may flip unlikely for long TWL, resulting in readfailure. In contrast, the short TWL induces the write-failure while the long TWL ensures the data flip for writing the correct data.
Long TWL Short TWL

Read operation

SN1 SN2

Tflip

Fail

Tflip

Pass

Long TWL

Short TWL

Write operation

SN1 Tflip SN2

Pass

Tflip

Fail

Figure 3. Dynamic stability against wordline pulse width (TWL) for read and write operations.

Reproducing the fail bit rate for various TWL is obtained by estimating the most probable failure point (MPFP) for read and write operations [8]. The MPFP is characterized by the norm (failure rate) as well as the combination of Vth variation (6-dimensional worst-vector (WV) [14] denoted by coefficients a1 ~ a6 in Fig. 4 (a)). Note that those coefficients are normalized as a12 + a22 + a32 + a42 + a52 + a62 = 1. PU, PD and PG are the standard deviations due to local Vth variation described by the Pelgrom law [15]. Figures 4 (b) and (c) depict failure patterns induced by the MPFP in single WL pulse operation for read and write, respectively.
(a) WL (b) BLT, BLB SN1 PUL PGL PDL BLT SN1 SN2 PUR PGR PDR BLB (c) WL SN2 BLB SN1 PUL a1PU PUR a2PU PDL a3PD PDR a4PD PGL a5PG PGR a6PG WL BLT SN2

-2

-3 -4 -5 -6

SF SS TT FF FS

Normalized component

(a)

(b)

Sigma Write Write @0.8V Sigma at 0.8V

-7 0.0 0.2 0.4 0.6 0.8 1.0 Twl T [a.u.]

WL

PUR

PDR

Figure 6. (a) TWL dependence of Sigma Write for 5 process corners at 0.8V and -40 C. (b) The worst vectors for 6 TWL conditions at SF corner. Square plots are the worst vector that makes the DC write margin zero.

Figure 4. (a) SP SRAM and 6-D vector determining MPFP. Simulated failure pattern in one pulse operation for read (b) and write (c).
-4

Figure 6 (a) shows the Write-MPFP (Sigma Write) dependence on TWL (solid lines) and compares those with the results for DC calculation (dotted lines). Measuring from DC results, the (absolute) sigma value decreases with decreasing TWL. Also, there is no significant difference between the WV for DC and those for shorter TWL, meaning that the WV is maintained in simulated TWL region. On top, the same WV with decreasing sigma means that the write dynamic stability is attributed to non-zero positive value of write DC margin. B. Disturb Issues in Dual-port (DP) SRAM Next, we consider the dynamic stability for DP SRAM. The schematic of an 8T DP SRAM bitcell is shown in Fig. 1 (b). DP SRAM allows for asynchronous clock operation between Port-A and Port-B due to its independent two ports. It brings a specific problem that does not appear in SP SRAM operations. As discussed in [13], when both WLA and WLB in a common row are accessed simultaneously, the write stability is disturbed by the half-select due to the other port activation as shown in Fig. 7 (a). In case of the different row access, there is no disturb by the other port since either WLA or WLB is only activated in a target bitcell. The read stability is also disturbed in common row access, not discussing here but showing screening results in section IV Fig. 7 (b) shows the waveforms for the write-disturb failure in a common row access with clock skew, where three stages exist: (I) single write operation, (II) write with SNM disturb due to WLB and pre-charged BLB and /BLB, and (III) single SNM disturb without BL discharging power for writing a data. Here, the skew is defined as the rise time of WLB measured from that of WLA.
(a)
BLB WLB (disturb) /BLB

1
FS FF TT SS

-5 -6 -7 -8

Normalized component

(b)

Sigma Readat @0.8V Sigma SNM 0.8V

SF

(a)
-9 0.0 0.2 0.4 0.6 0.8 TwlT [a.u.] WL 1.0

PUR

PDR

Figure 5. (a) TWL dependence of Sigma Read for 5 process corners at 0.8V and 125 C. (b) The worst vectors for simulated 6 TWL condition at FS corner. Square plots are the worst vector that makes SNM zero [14].

Next, we show simulation results obtained by the importance sampling Monte Carlo (ISMC) method [16-18], which improves the computational time significantly. Fig. 5 (a) shows the dependence of the norm of Read-MPFP (Sigma Read) on TWL for all process corners. Solid lines are the results by ISMC while the dotted lines are the DC results using [14]. It is found that DC results are independent to TWL while the sigma value increases with decreasing TWL. There is no cross-point where a sigma value for one process corner exceeds that for the others, which means that the FS corner is also the worst condition for shorter TWL. Fig. 5 (b) compares the WV components for 6 TWL conditions (lines) with those derived by [14] (square). This result indicates that the WV for dynamic stability is the same as that for DC condition, i.e., the WV which makes the SNM zero keeps providing the worst condition even in short TWL. This also implies that the dynamic stability for shorter TWL is determined by non-zero negative value of SNM since sigma is increased without changing WV.

PGR

PDL

PUL

PGL

-1

a1 a2

a3

a4

a5

a6

(b) (b)

H BLA

SN1
SN1 SN2 H H /BLA

Pass
SN2 SN1 SN2

Fail

WLA (write)
I II III

Figure 7. (a) DP SRAM in write-disturb mode (BLA=L, /BLA=H for writing and BLB=/BLB=H for disturbing). (b) Waveforms for WLs with skew and internal nodes in case of Pass and Fail.

247

PGR
WLA (write) WLB (disturb)

PDL

PUL

PGL

-1

a1 a2

a3

a4

a5

a6

In those successive events, the internal nodes of a bitcell with some Vth variations are eventually flipped back, resulting in a write failure as shown in the third row of Fig. 7 (b). It is, in fact, impossible to identify the corresponding MPFP for write-disturb by conventional DC analysis, and hence it should be treated by the metric of dynamic stability. Fig. 8 (a) shows the Sigma Write dependence on clock skew for three VDD conditions. Those three curves show linear dependence against VDD, which allows us to convert the vertical sigma-axis into Vmin-axis. Fig. 8 (b) is Shmoo plot (skew vs. Vmin) calculated from Fig. 8 (a), assuming that the DP SRAM cell-array is equivalent to 5.5 . As shown in Fig. 8 (b), the worst Vmin appears at a positive clock skew.
-4.0 -5.0 -5.5 -6.0 -7.0 -8.0 -9.0 -2.0
(a)

macros for SP SRAM and each of sixteen 32-kbit macros for DP SRAM were implemented in a same test chip. Both SRAM modules we designed have an optional test mode so that the outer memory tester can directly control the TWL without using internal WL pulse generator. This enables us to estimate Vmin dependence on TWL, simply and effectively.
1-Mbit Single Port SRAM

512-kbit Dual Port SRAM

0.84

Figure 10. Microphotographs of fabricated 1-Mbit SP SRAM macro and 512-kbit DP SRAM macro using 28nm HK/MG bulk CMOS technology.

(b)

(V) Vmin Vmin [V, 5.5sigma]

0.82 0.80 0.78

0.80V 0.85V 0.90V

@5.5sigma
0.76 -2.0 -1.0 0.0 1.0 2.0

-1.0

0.0

1.0

2.0

Clock Clocc skew skew [ns] (ns)

Clock Clocc skew skew [ns] (ns)

Figure 8. (a) Simulated clock-skew dependence of Sigma Write for different VDD and (b) interpolated Shmoo result at -5.5 sigma in (a).

Fig. 9 (a) is the process-corner dependence, indicating that for the common row access mode, SS provides the worst condition and the Sigma-Write is improved by lowering PMOS |Vth|. Fig. 9 (b) compares the WVs for SS and SF conditions. The worst Vmin in SS is caused by a bitcell having higher variations in PUR and PGLB while the Vmins in the tail (0.5 ns) are determined by those having higher variation only in PUR. Regarding SF corner which provides the write worst condition for different row access mode [13], the WV for the peak Vmin is the same as that for SS, but the tail is determined by the conventional one that makes the write DC margin zero.
-6.5 -7.0
Sigma Write

B. Measurement Results and Comparison with Simulation Fig. 11 (a) and (b) show measured fail bit rate of SP SRAM against supply voltage VDD for read and write operation, respectively. Since the unit module consists of a 1 Mbit cell-array per chip, then the data plotted are statistically processed by summing up results for eight chips, which corresponds to a total 8 Mbit evaluation (1 fail per 8 Mbit is equivalent to the fail bit rate of -5.17 ). In Fig. 11, we also plotted DC simulation results based on [14]. Those results are derived so that the static DC margin such as SNM for each VDD becomes zero due to local Vth variations, clarifying that the measured data for TWL = 250 ns is long enough to be considered as a static operation. Fig. 11 (a) shows that Vmin gets lowered by making the pulse width shorter; e.g., 0.8 improvement is achieved at 0.8 V by decreasing TWL from 250 ns to 3 ns. Thus, read Vmin is enhanced by dynamic stability. In contrast, the dynamic stability in write operation degrades the write Vmin (Fig. 11 (b)). At 0.8 V, we observe 0.8 degradation by changing TWL from 250 ns to 5 ns. Note that in this study, we examine Vmin improvement or degradation by estimating the difference in fail bit rate or sigma value at fixed VDD.
-3.5
Fail Fail BitBit Rate Rate [unit (sigma) of sigma]

Sigma Write

Component

(a) SS

(b) Peak Tail

SS Corner

Fail Bit Rate (sigma) Fail Bit Rate [unit of sigma]

-4.0

Twl=3ns Twl=5ns Twl=15ns Twl=250ns DC-sim [14]

-3.5

Twl=5ns Twl=250ns DC-sim [14]

-4.0

(c) (b) Dynamic

-7.5 -8.0 -8.5 -9.0 -1.0 -0.5

FS SF FF

(b) (a)

-1 1

Component

SF Corner Peak

-4.5

Static

-4.5

-5.0
Dynamic

-5.0
Static

Tail

DC PGRB

PUR

PDR

PGRA

PGLA

PGLB

PUL

PDL

0.0

0.5

1.0

-1

-5.5 0.5 0.6 0.7 0.8 0.9 1 VDD (V) [V] VDD

-5.5 0.5 0.6 0.7 0.8 0.9 1 VDD (V) [V] VDD

Clock skew [ns] Clocc (ns)

Figure 9. (a) Process dependence of simulated Shmoo plot at 0.9 V and (b) the worst vector for SS and SF corners.

Figure 11. Measured VDD dependence of fail bit rate for read at 125 C (a) and write at -40 C (b) using outer WL pulse generated by the tester.

III.

MEASREMENT RESUTLS OF DYNAMIC STABILITIES

A. Test chip implementation We designed a 1-Mbit SP SRAM macro and a 512-kbit DP SRAM macro using 28-nm HK/MG bulk CMOS technology as shown in Fig. 10. Each of thirty-two 32-kbit
248

The result that the WV is independent of TWL both for read and write can be verified by measurement. In measuring Fig. 11 (a) and (b), we monitored several fail-bit addresses that appear around Vmin for all TWL conditions and compared them with each other. As a result, the worst address observed for TWL = 250 ns appears for shorter TWL with a few exceptions. Those exceptions are considered to be

responsible for measurement accuracy of the memory tester or the other fluctuation sources such as random telegraph signal (RTS). Figure 12 compares simulated results with measured data at 0.8 V shown in Fig. 11. In this simulation, we modified Vth and Ids of original SPICE model so that they correspond to the measured data for SRAM transistors. As a result, our simulation shows a good accordance with measurement. A slight discrepancy in the Sigma Write is considered to be attributed to a significant distortion of the WL pulse width for low temperature (-40 C).
Sigma Read, Sigma Write
-4.0 -4.5 -5.0
@ 0.8V, 125C (Read), -40C (Write)

Shmoo 1bit (at peak) 1bit (at tail)

(a)

-6.8 -7.0 Sigma Write -7.2 -7.4 -7.6 -7.8 -8.0

ISMC WV at peak WV at tail

(b)

VDD VDD [a.u.]

-3

-2

-1 0 1 2 Clock skew Clock skew[a.u.] (a.u.)

-0.5

Clock skew Clock skew[ns] (ns)

0.5

Figure 14. (a) Measured bit-by-bit Shmoo plot. The deviation at the peak is due to measurement accuracy. (b) Simulated results based on ISMC and those for WV-by-WV separation.

Write (Meas.) Read (Sim.) Read (Meas.)

IV.

TEST SCREENING METHOD

-5.5 -6.0 0 5 10 15

Write (Sim.)
20

TWL (ns)

Figure 12. Comparison between measured sigma and simulation at 0.8 V. Dashed lines are expected TWL distortion due to temperature effect in memory tester.

In 512-kbit DP SRAM macro, the write-disturb is observed by measuring Shmoo plot shown in Fig. 13. Note that the x-axis represents the clock skew (~WL pulse skew) between ports and that the worst Vmin due to write-disturb appears at a finite positive-skew. Here the WL pulse widths for both ports are designed to be the same and measured by skewing the clock phase of port-B as shown in Fig. 13.
Curtain Shmoo
WLA (Fixed pulse) /BLB /BLA BLA BLB

A. Test Screeing Circuity for DP SRAM macro To detect the disturb failures for DP SRAM with asynchronous clock frequencies increases test time and cost. Now we propose expanding a WL pulse of the disturb port to fully cover a WL pulse of the test port in the screening operation. The operation in the test port is being affected constantly by the disturbance from the disturb port when a WL is activated, or we can generate the worst write/read disturb condition at the same clock access phase. This screening technique with synchronous clock frequencies is efficient for all failure modes with small overheads of test time and cost. Fig. 15 shows the concept of proposed screening technique. Fig. 15 (a) shows read-failure screening, Fig. 15 (b) shows current-failure screening, and Fig. 15 (c) shows write-failure screening.
CLKA, CLKB CLKA, CLKB CLKA, CLKB

Test Port

WLA BLB

WLA BLB WLB BLA

WLA BLB WLB BLA

VDD

Pass LH Vmin degradation due to clock skew Fail 0ns WLB (Shift pulse) HH

Disturb Port

WLB BLA

Disturb
MB MT

Worstmargin
MB MT

Disturb
MT MB

Disturb

WL skew

Figure 13. Measured Shmoo plot for the write-disturb condition. Note that the boundary represents Vmin for each clock skew.

Data flipped

Simulation results are compared with measured data. Fig. 14 (a) represents the same Shmoo plot shown in Fig. 13 as well as the ones measured in bit-by-bit manner. The bit-bybit data are obtained by monitoring the fail-bit addresses in measuring Fig. 13. After extracting the fail-bit address for the peak Vmin and that for the tail at a negative clock skew, we measured Vmin for each address by changing the clock skew. It is shown that the fail-bit for the worst Vmin only appears around the peak, and the tails in both sides (negative and positive skews) are determined by the other fail address. This observation is well explained by estimating the simulated norm of MPFP and corresponding WV for each clock skew. The WV generating the worst Vmin only appears at the peak, while the tail Vmin is determined by the other WV (see Fig. 14 (b)).

(a)

Pulled up by PortB

(b)

(c)

Data not flipped

Figure 15. Concept of proposed screening technique. (a) Read-failure screening, (b) Current-failure screening, (c) Write-failure screening.

Fig. 16 portrays the proposed screening circuitry. Note that clock generators are implemented to both ports. This circuitry detects the rising edge of the clock signal, and generates a WL pulse necessitated by the write/read operation. The screeing circuitry consists of complex gate and delay elements, and delays the rising edge or falling edge of WL pulse depending on the test/disturb ports. TME is a test signal to switch the operation into the test port, while TAE identifies which port produces disturbing expanded WL pulse with negative/positive clock skews. The test port is set to TME=H and TAE=L, while the disurb port is set to TME=TAE=H. The WLB pulse in the disturb

249

port is expanded by both Delay 1 and Delay 2 elements, so that it fully covers WLA pulse in the test-port. This is how the disturb test condition is generated.
Waveform
CLKA CLKB WLA, WLB (Normal)
CLKB TMEB TAEB

Port-B

S.A. & W.D. MUX

Clock Generator

WLA (Test)

(Delay1)

(Delay1)
WLA

Pre Decoder

WLB (Disturb)

(Delay1)+(Delay2)

MC

MC

Screening circuitry
TMEA TAEA Delay2 Pre Decoder MUX Delay S.A. & W.D. Complex gate MC MC WLB

the same-row accesses in both cases are higher than those in the different-row accesses, meaning that the same-row accesses are critical because of the influence of readwrite disturbs. Furthermore, the clock skew degrades Vmin more than the synchronous clock accesses: tests using asynchronous clock frequencies between ports are generally necessary to sort out failures. Screening test results are presented in Figs. 20 (a) and 20 (b). Actually, Vmin with the proposed test circuitry is always higher than or equal to the worst case Vmin of the same row access. The proposed test circuitry enables sorting of write and read disturbs without asynchronous clock frequencies.
900 Pass 800 820mV@0.9ns 50mV

900 800mV@0.2ns VDD (mV) 800 Pass 700 670mV 0.0 5.0 clock skew (ns) 10.0 130mV

Delay1 CLKA Delay

Clock Generator

Port-A

VDD (mV)

700

770mV@0.0ns Fail 0.0 5.0 clock skew (ns) 10.0

Figure 16. Proposed screening circuitry for DP SRAM macro and its waveforms. For SP SRAM macro, remove the Port-B peripheral and replace to 6T SRAM cell-array from 8T SRAM cell-array.

600 5.0

600 5.0

Fail

Fig. 17 shows simulated waveforms of the proposed screening technique. Each simulation was performed in the worst process/temperature condition. As explained in Fig. 16, the pulse width of WLB covers that of WLA, showing that the bitcell accessed by WLA is being disturbed by WLB. All the worst-case disturb conditions are realized: positive clock skew for the write margin, zero skew for the read margin, and negative skew for the cell current. It should be noticed that our circuitry can reproduce those worst cases without using asynchronous clock frequencies.
Voltage
CLKA, CLKB BLA WLB MB MT BLA WLB MB MT WLA Disturb WLA

Figure 18. Measured shmoo plot: (a) write disturb and (b) read disturb.
Synchronous clock Worst case clock skew Synchronous clock Worst case clock skew

Normalized Vmin @ same-row access

# of test chips = 20 Temp. = 25 C (a) Normalized Vmin @ different-row access

Normalized V min @ same-row access

# of test chips = 20 Temp. = 25 C (b) Normalized Vmin @ different-row access

Voltage

Figure 19. Measurement results of comparisons between different-row and same-row accesses: (a) write operation and (b) read operation.
# of test chips = 20 Temp. = 25 C # of test chips = 20 Temp. = 25 C

CLKA, CLKB BLA WLB MT MB WLA Disturb

Voltage

Voltage

Normalized Vmin

(a)
Data flipped

(c)
Data not flipped

FS Corner, 125 C

Voltage

Time

(b)
SS Corner, 125 C

Voltage

Pulled up by PortB

Vmin (proposed test) Vmin (worst) (a) #5 #10 Samples #15 #19

Normalized Vmin

Disturb

FS Corner, 40 C

Voltage

Voltage

Vmin (proposed test) Vmin (worst) (b) #5 #10 Samples #15 #19

#0

#0

Figure 17. Simulated waveforms of the screening: (a) read margin failure screening, (b) current failure screening, and (c) write failure screening.

Figure 20. Measurement results of the proposed screening test: (a) write operation and (b) read operation.

B. Measurement Results of DP SRAM Figs. 18 (a) and 18 (b) depict measured typical shmoo plots of a 32-kbit macro in the write and read disturbs at 25C, respectively. The worst Vmin in the write disturb is 820 mV when clock skew is 0.9 ns. This Vmin value is 50 mV higher than that of a synchronous clock. In contrast, the worst Vmin in the read disturb, 800 mV at -0.2 ns clock skew point, is degraded 130 mV compared with the best Vmin in the read operation. Therefore, the worst Vmin in the read disturb is determined by the cell current failure in the test chip. Figs. 19 (a) and 19 (b) portray Vmin measurement results of comparisons between different-row and same-row accesses in read and write operations. The values of Vmin in

C. A Test flow and Screening Results for SoC Product We introduce the proposed screening method with considering dynamic stability for our 28-nm SoC product, which contains a lot of SP- and DP-SRAM macros with over 100-Mbit totally. Fig. 21 (a) shows a screening test flow for whole embedded SRAM in a chip. The additional SP and DP dummy-read tests and DP read/write-disturb test contribute to detect the failure caused by less dynamic stability. In the dummy-read test, the WL pulse width is expanded to produce the worst condition for read stability. Fig. 21 (b) shows the screening test results of the SoC product for two wafers. It is observed that failure chips are detected additionally by 0.24% and 2.01% with the proposed

250

screening method. But note that the detected failure chips may contain less dynamic margin SRAMs not only by local Vth variations but also by abnormal process issues due to the early production phase. The test flow will be changed in a mass production phase to add/remove some sequences depending on the tradeoff between test coverage and its cost.
(a)
Start

[4]

(b) Detected by 0.24% # of Pass Chips 2.01%

[5]

Normal read/write function test Change temperature Dummy read test w/ expanded TWL Read/write disturb test for DP-SRAM Pass? Yes No All temp.? Yes End: Pass End: Fail No

[6]

Screening dynamic stability faults

[7]
w/o w/ Wafer A w/o w/ Wafer B

Figure 21. (a) Proposed screening test flow considering dynamic stability, (b) Screening test results of our 28-nm SoC product.

[8]

V.

CONCLUSION

[9]

The dynamic stabilities for SP- and DP-SRAM have been discussed by comparing with measurement data obtained for 28-nm SRAM modules [19]. Measured Vmin improvement and degradation for SP SRAM were reproduced, and the WV that specifies the MPFP has been identified. In addition, specific Shmoo plot observed in DP SRAM has been systematically explained by the dynamic stability [19]. Furthermore, we proposed the test screening circuitry considering with the dynamic read and write stabilities including DP SRAM disturb issues [13]. The appropriate test screening results of fabricated test-chips were obtained, and confirmed assured dynamic stability fault detection for our 28-nm SoC product. ACKNOWLEDGMENT The authors would like to acknowledge all the hard work and dedications of our SRAM design and test members. We also thank Y. Shimazaki, T. Sato, K. Mori, K. Yanagisawa and T. Takeda for their technical management and support. REFERENCES
[1] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa and T. Kawahara, 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique, IEEE J. of Solid-State Circuits, Vol. 41, No. 3, pp. 705711, March 2006. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits, IEEE J. of Solid-State Circuits, Vol. 42, no. 4, pp. 820-829, April 2007. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. lshikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations, in

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[2]

[17]

[18]

[3]

[19]

Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 326327,606, Feb. 2007. Azeez Bhavnagarwala, Stephen Kosonocky, Yuen Chant, Kevin Stawiasz, Uma Srinivasant, Steve Kowalczyk, and Matt Ziegler, A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing, in Symp. VLSI Circuits Dig. Tech. Papers, pp. 78-79, June 2007. E. Seevinck, F. J. List and J. Lohstroh, Static Noise Margin Analysis of MOS SRAM Cells, IEEE J. of Solid-State Circuits, Vol.SC-22, No. 5, 748-754, 1987. Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler, An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage, IEEE J. of Solid-State Circuits, Vol. 42, no. 4, pp. 813-819, April 2007. M. Khellah, Y. Ye, N. Kim, D. Somasekhar, G.. Pandya, A. Farhang, K. Zhang, C. Webb, V. De, Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs, in Symp. VLSI Circuits Dig. Tech. Papers, pp. 9-10, June 2006. D. Khalil, M. Khellah, N. Kim, Y. Ismail, T. Karnik, and V. K. De, Accurate Estimation of SRAM Dynamic Stability, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1639-1647, Dec. 2008. M. Khellah, D. Khalil, D. Somasekhar, Y. Ismail, T. Karnik, V. De, Effect of Power Supply Noise on SRAM Dynamic Stability, in Symp. Symp. VLSI Circuits Dig. Tech. Papers, pp. 76-77, June 2007. M. Sharifkhani, S. M. Jahinuzzaman, M. Sachdev, Dynamic Data Stability in Low-power SRAM Design, in Proc. Custom Integrated Circuits Conf. (CICC), pp. 237-240, 2007. Masanao Yamaoka, Kenichi Osada, and Takayuki Kawahara, A Cell-activation-time Controlled SRAM for Low-voltage Operation in DVFS SoCs Using Dynamic Stability Analysis, in Proc. European Solid-State Circuits Conf. (ESSCIRC), pp. 286-289, 2008. Seng Oon Toh, Zheng Guo, and Borivoje Nikoli, Dynamic SRAM Stability Characterization in 45nm CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, pp. 35-36, June 2010. Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, and Kazumasa Yanagisawa, A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against WriteRead Disturb Failure Issues, IEEE J. of Solid-State Circuits, Vol. 46, No. 11, Nov. 2011. Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, S. Ohbayashi, T. Yoshizawa, H. Makino, K. Ishibashi, and H. Shinohara, Worst-case analysis to obtain stable read/write DC margin of high density 6TSRAM-array with local Vth variability, in Proc. Int. Conf. on Computer-Aided Design (ICCAD), pp. 398-405, Nov. 2005. M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, Matching Properties of MOS Transistors, IEEE J. of Solid-State Circuits, Vol. 24, No. 5, 1433-1440, 1989. Rouwaida Kanj, Rajiv Joshi, and Sani Nassif, Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure Events, in Proc. Int. Design Automation Conf. (DAC), pp. 69-72, 2006. Lara Dolecek, Masood Qazi, Devavrat Shah, and Anantha Chandrakasan, Breaking the Simulation Barrier: SRAM Evaluation Through Norm Minimization, in Proc. Int. Conf. on Computer-Aided Design (ICCAD), Nov. 2008. Takanori Date, Shiho Hagiwara, Kazuya Masu, and Takashi Sato, Robust Importance Sampling for Efficient SRAM Yield Analysis, in Proc. Int. Symposium on Quality Electronic Design (ISQED), pp. 15-21, 2010. Y. Tsukamoto, T. Kida, T. Yamaki, Y. Ishii, K. Nii, K. Tanaka, S. Tanaka, and Y. Kihara, Dynamic Stability in Minimum Operating Voltage Vmin for Single-port and Dual-port SRAMs, in Proc. Custom Integrated Circuits Conf. (CICC), Sep. 2011.

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