Problem 2 tb

--------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 18:35:37 04/17/2014 -- Design Name: -- Module Name: H:/spring 2014/lab12/problem2tb.vhd -- Project Name: lab12 -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: problem2 --

-- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY problem2tb IS

END problem2tb;

ARCHITECTURE behavior OF problem2tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT problem2

PORT(

clk : IN std_logic;

rst : IN std_logic;

tc : OUT std_logic;

B : INOUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal rst : std_logic := '0';

--BiDirs

signal B : std_logic_vector(3 downto 0);

--Outputs

signal tc : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: problem2 PORT MAP (

clk => clk,

rst => rst,

tc => tc,

B => B

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

rst <= '1';

wait for 10 ns;

rst <= '0';

-- insert stimulus here

wait;

end process;

END;

Problem 2 vhd

----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 18:34:42 04/17/2014 -- Design Name: -- Module Name: problem2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description:

--- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity problem2 is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

tc : out STD_LOGIC;

B : inout STD_LOGIC_VECTOR (3 downto 0));

end problem2;

architecture Behavioral of problem2 is

begin

process (clk, rst)

begin

if rst = '1' then B <= "0000";

elsif (clk'event and clk='1') then

B <= B + 1;

if (B = "1110") then tc<='1';

else tc<='0';

end if;

end if;

end process;

end Behavioral;

----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 19:02:44 04/17/2014 -- Design Name: -- Module Name: problem1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments:

----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity problem1 is Port ( cen : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; b: inout STD_lOGIC_VECTOR (3 downto 0)); end problem1;

architecture Behavioral of problem1 is

begin

process (clk,rst) begin if rst='1' then b<="0000"; elsif (cen = '1') then if(clk 'event and clk='1') then

b(3)<= ((b(3) and not b(1)) or (b(3) and not b(2)) or (b(3) and b(1) and not b(0)) or (not b(3) and b(2) and b(1) and b(0))) ; b(2)<= ((b(2) and not b(0)) or (b(2) and not b(1)) or (b(0) and b(1) and not b(2))) ; b(1)<= (b(1) xor b(0)) ; b(0)<= not b(0) ; end if; end if; end process;

end Behavioral;

vhdl tb --------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 19:34:13 04/17/2014 -- Design Name: -- Module Name: H:/spring 2014/lab12/tb1-2.vhd -- Project Name: lab12

-- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: problem1 --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL;

ENTITY tb1 IS END tb1;

ARCHITECTURE behavior OF tb1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT problem1 PORT( cen : IN std_logic; clk : IN std_logic; rst : IN std_logic; b : INOUT std_logic_vector(3 downto 0) ); END COMPONENT;

--Inputs signal cen : std_logic := '1'; signal clk : std_logic := '0'; signal rst : std_logic := '0';

--BiDirs signal b : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT) uut: problem1 PORT MAP ( cen => cen, clk => clk, rst => rst, b => b );

-- Stimulus process stim_proc: process begin rst<='1';

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; rst<='0'; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

clk<='0'; wait for 10 ns; clk<='1'; wait for 10 ns;

wait; end process;

END;