DEPARTMENT OF ELECTRICAL & ELECTRONIC ENGINEERING BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY COURSE NO.

: EEE 210 EXPERIMENT NO. 02

Name ! "#e E$%e&'me(": STUDY OF CHARACTERISTICS OF BIPOLAR )UNCTION TRANSISTOR *B)T+.

OB)ECTIVE
The objective of this experiment is to simulate DC characteristics of BJT in Common Emitter (CE) and Common Base (CB) configuration. Biasing of BJT. mall signal !nal"sis using BJT.

THEORY
Transistor has t#o p$n junctions (see figure belo#). %ne junction is called emitter junction and other is called collector junction. &hen transistor is used as an amplifier' it is operated in active mode. (n active mode' emitter junction is for#ard biased and collector junction is reverse biased. JnE JpE iE E n p JnC nE p nC iC n C iB C

B
B Emitter current is given b" (E ) (nE * (pE #e can also #rite (E ) (C * (B ) +(, * )-.(C &here ) (C -(B is called common emitter current gain. (n good transistor (C//(B i.e. //,. (C can also be expressed as (C ) (E . #here ) -(,*) . is called common base current gain. 0or good transistor' is close to unit". 1roper dc biasing of a transistor is a prere2uisite for proper operation as an amplifier. The purpose of the biasing is to fix the (C (dc) and 3CE (dc) . But (C is a function of temperature' 3BE and . (t is al#a"s desirable to design a biasing circuit #here (C is insensitive to change in . &hen E$B junction is for#ard biased and C$B junction is reverse biased' the transistor operates in active mode. 0or saturation mode of operation' both junction are for#ard$biased. Cut$off region operation re2uires that both E$B and C$B junctions be reverse biased. The inverted active operation occurs #hen E$b is reverse$biased and C$B is for#ard biased.

O,"%," C#a&a-"e&'."'-. & L a/ L'(e

tatic %4T14T C5!6!CTE6( T(C define stead" state conditions famil" of curves of (C vs 3CE for increasing (B 7raphical design procedure gives performance under non$linear conditions start 8 finish points in anal"tical procedure

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0or 3i ) :' (B ) :

IC (mA) 10 mA

Saturation !"ion
LOAD LINE 50 A 40 A Q-point 30 A 25 A 20 A IB

5 mA

10 A 0 A 0 5V 10 V V CE (V)

so 3 ) 3CE(max) 0or 3i // 3BE' (sa" 3i ) 3s)' (B is high and (C is at maximum nearl" all volts dropped across 6 3CE ) : 8 (C(max) ) 3 -6; Transistor is said to be !T46!TED ! ;%!D ;(<E dra#n from (C(max) to 3CE(max) lope of load line is $(,-6;)

no current flo#s through 6; thus (C ) :

Cut-o## r!"ion

B'a.'(0 ! B)T
(n order to characteri=e the operation of a particular transistor' a complete set of characteristic e2uations is needed. T"picall"' these curves loo> li>e those in 0igure. These curves sho# that in the active region of operation' the collector current is constant and depends on the base current.

0igure? Characteristic curves for the BJT transistor. These curves can be used to calculate the large signal current gain' DC (or h0E) and the small signal current gain' !C (or hfe). These values are in general calculated for a given bias point ( C@' 3CE@ using the follo#ing e2uations?

0rom this' one can see that the large signal gain depends onl" on the @ point and the small signal gain depends onl" on small deviations around the @ point. (n order to use a transistor in an amplif"ing circuit it has to be biased. (n other #ords' a @ point has to be set in order to place the device in the active region of operation. There are several methods #hich can be used bias a transistor. 0igures a and b demonstrate t#o possibilities. The first scheme (0igure a) is called a fixed bias scheme. (n a fixed biasing the base current is set through a base resistor and the emitter of the transistor is grounded. This scheme is not used in practice since the @ point depends ver" strongl" on .

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0igure (a)? 0ixed bias circuit ! second possibilit"' #hich is commonl" used' is the self biasing scheme. 5ere the base voltage is set through a voltage divider and the emitter is tied to ground through a resistor. (f designed correctl"' this scheme is relativel" independent of .

0igure b? elf bias circuit

Sma11 .'0(a1 a(a12.'.:

Dan" electronic components T3 can be represented b" a t#o port E41a-5 4 $F P &" S2."em.

Ii * Vi
-

Io T#o$1ort "stem * Vo
-

&ithin the Eblac> boxF a mathematical representation of the behaviour can be constructed. (mportant characteristics of interested to electronic designers are?

7ain in dB)A:log,:(vout-vin) !t cut$off (vout-vin)),-BA o' at cut$off gain in dB is $C.

Gi Go !v !i

) ) ) )

(nput (mpedance ) Vi-Ii %utput (mpedance ) Vo-Io 3oltage 7ain ) Vo-Vi Current 7ain ) Io-Ii

PROCEDURE

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DC C#a&a-"e&'."'-. ! B)T 62N2222

Output Characteristics

Q1 0V%$ 0A%$ I& Q2N2222

V$!

F'0.1.

C'&-,'" ! & DC a(a12.'. ! B)T '( CE - (!'0,&a"' (

,.,.

Dra# the circuit sho#n in 0ig. , in 1 pice schematics.

,.A. 5ere' for determining the output characteristics a nested DC #eep of 3 CE and (B is re2uired. 0or achieving this' elect Se",% A(a12.'. and then DC S3ee% from the pop$up #indo#. #eep first 3CE from : to ,:3 in :.,3 increments. Then clic> on the Ne."e/ S3ee% button for s#eeping (B from :! to , m! in :.Am! increments. Dar> the E(a41e Ne."e/ S3ee% box. ,.C. !fter placing a current mar>er in the collector of the BJT (as sho#n in 0ig. ,)' run the simulation. ,.H. %utput characteristic of the BJT #ill appear in the probe. ,.I. +5ome #or>. Dra# a circuit for obtaining output characteristics of @A<AAAA in CB configuration and simulate it using appropriate sources and nested s#eeps. Plot of DC Current Gain vs. collector current (IC) and vs. base current (IB) a) Circuit for this anal"sis is sho#n in 0ig. ,. Se" 3CE) I3. b) #eep (B from ,:! to , m! in DECADES #ith A: points per decade. c) Determine the DC current gain ((C-(B) vs. (B curve. d) Determine the DC current gain ((C-(B) vs. (C curve (normall" given in data sheets of (C supplied b" the manufacturer). e) 0ind' from second plot' the maximum DC current gain. 0ind the corresponding ( C. Determine Common Emitter (CE) current gain () at calculated (C. DC Current gain vs. Temperature f) Circuit for this anal"sis is sho#n in 0ig. ,. Consider 3CE ) I3. g) #eep for (B from ,::! to , m! in DECADES #ith A: points per decade. Clic> on the Ne."e/ S3ee% button and set values JAI' AI' ,AI Celsius. Dar> in the E(a41e Ne."e/ S3ee% box.

h) 6un the simulation. 7enerate a plot of DC current gain versus collector current. <%TE? (f "ou find difficult" in identif"ing the curves' "ou should run each case separatel" and verif" the identit" of each curve.

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B'a.'(0 ! B)T

F'0.2.

B'a.'(0 ! B)T

A.,. Dra# the circuit of 0ig. C ( elf Bias Circuit). B" choosing Se",% a(a12.'.' mar> B'a. P '(" De"a'1 and Tem%e&a",&e. et Temperature to AK: C. A.A. 6un the simulation and clic> on the E(a41e B'a. V 1"a0e D'.%1a2 and E(a41e B'a. C,&&e(" D'.%1a2 icons. A.C. 3CC 0ill up the follo#ing table. 3B 3E 3C 3CE (B (E (C

A.H. A.I.

Change 6, to around IKL' so that 3CE ) :.I 3CC. Change temperature to I:: C and note the change in 3CE.

A.9. Change transistor model (replace @A<CM:H #ith @A<AAAA) and set temperature bac> to AK: C. !gain' note the change in 3CE. A.K. <o#' for circuit in 0ig. C' remove 6E and short Emitter to ground (0ixed Bias Circuit). 6epeat steps A to 9. 6, #ill needed to be set around AANL to achieve 3CE ) :.I 3CC. A.N. Comment on the stabilit" of the biasing circuits (fixed and self) #ith change in temperature and device model (current gain' etc.).

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Sma11 S'0(a1 A(a12.'. ! B)T

F'0.7.

C'&-,'" ! & Sma11 .'0(a1 a(a12.'. ,.'(0 B)T

C.,.

Dra# the circuit sho#n in 0ig. H in 1 pice schematics.

C.A. 5ere' 3(< is variable fre2uenc" !C source (5aving Pa&" Name of VAC). et its amplitude to , m3' >eeping other parameters (e.g. 3dc) to =ero value. C.C. elect !C #eep from Se",% A(a12.'.. elect s#eep from ,: 5= to ,: D5= (or higher or lo#er' ensure that "ou observe both the cut$off fre2uencies) in Decade mode' #ith A: 1ts-decade. C.H. 6un the simulation. C.I. %bserve the voltage gain (!3)vo-vin) and phase shift bet#een vo and vi at different fre2uencies. +0or obtaining phase difference clic> on the A// "&a-e icon' obtain the plotting of P(vo)$P(vin).. C.9. C.K. <ormali=e the voltage gain !3<)!3-!3max 1lot the voltage gain (in dB) vs. fre2uenc" (f) +!3dB)A:log,:(!3<).

C.N. Determine the $CdB (cut$off) fre2uencies from the plot. !lso note the phase difference bet#een vo and vi at JCdB fre2uencies. C.M. +5ome #or>. !t mid$band fre2uenc"' note the voltage gain (! 3)' current gain (!()' input resistance (6i) and output resistance (6o) of the configuration. 0or output resistance use the >no#ledge obtained from theveninOs e2uivalence. Preserve these values for further use in later experiments. C.,:. +5ome#or>. 0ind the h$ parameters of the given CE configuration using the data ta>en in step M. Consult references for proper e2uations.

Prepared by : Yeasir Arafat, Ahmad Ehteshamul Islam, Shaikh Asif Mahmood

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