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The p89v51RD2 is an 8051 microcontroller which is having a 64KB flash memory and 1KB of data RAM.A type characteristics of the p89v51RD2 is its X2 mode option. Actually the engineers designed to run the application with the predictable clock rate or select the X2mode to attain two times the throughput at the similar clock frequency. To meet the performance of this feature reduce the clock frequency to half this radically reduces the EMI. In system programming the flash program memory supports both parallel and serial programming. AT high speed this parallel programming modes offer gang programming which reduces programming cost and market time. By using software control the ISP allows a device to reprogrammed the end product. The application firmware has the capability to field in the wide range of application possible. In application programmable the p89v51RD2 allows the flash program memory to be rearranged while the application is running. 3.1.1: Features: The 8051 microcontroller has 80C51 central processing unit. Which operated at 5V operating voltage from 0 to 40 MHZ. 64 kB of on-chip Flash program memory with ISP (In-System Programming) and IAP (In-Application Programming). Supports 12-clock (default) or 6-clock mode selection via software or ISP. SPI (Serial Peripheral Interface) and enhanced UART. PCA (Programmable Counter Array) with PWM and Capture/Compare functions. Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each). Three 16-bit timers/counters. Programmable Watchdog timer (WDT). Eight interrupt sources with four priority levels. Second DPTR register. Low EMI mode (ALE inhibit). TTL- and CMOS-compatible logic levels.

3.2Block diagram of P89V51RD2:

High performance 80C51 microcontroller

64KB code flash 1KB Data Internal Bus RAM Port3



Port2 TIMER 2 Port1 PCA programmable counter array Watchdog Timer


Crystal ( Or)Resonator


FIG 3.1: Block Diagram of P89V51RD2

3.3 Pin diagram of P89V51RD2:

FIG 3.2 :Pin Diagram of P89V51RD2.

Table 3.1: Description of P89V51RD2








Port 2: Port 2 is a 8-bit bidirectional P2.0 to p2.7 21-28 18-25 24-31 I/O internal pull-up I/O port with

with internal pull-ups. Port 2 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can be used as inputs in this states. As inputs, port2 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 2 sends highorder address byte during

fetches from external program memory and accesses s external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to 1s. Port 2 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification.

P3.0 to p3.7





with Port 3: Port 3 is a 8-bit internal pull-ups. When 1s are written to port 3 then its pins are pulled HIGH by the internel pull-ups and can be used as inputs in this states. As inputs, port2 pins will source current (IIL) because of the internal pullups only when port 2 pins are externally pulled LOW. During the external host mode

internal pull- bidirectional I/O port and it has up

programming and verification Port 3 pins receives control

signals and a partial of high order address bits. P3.0 P3.1 10 11 5 7 11 13 I O RXD:RXD is a serial input port. TXD: TXD is a serial output port




INT 0: External interrupt 0 taken as a input..







taken as a input.





T0: T0 is a External count input to Timer/Counter 0.





T1: T1 is a External count input to Timer/Counter 1. WR: WR is a External data memory write strobe.









RD: RD is a External data memory read strobe. Program Store Enable: For the









PSEN is act as a read strobe. PSEN get inactive When device is executed from internal PSEN is



activated by twice each machine cycle, only When device is

executing code from external program memory, except that two PSEN activations are

skipped during each access to external data memory. The

device enter into the external host mode programming only when forced HIGH-to-LOW

input transition on the PSEN pin while the RST input is

continually HIGH for more than 10 machine cycles.

Reset: Whenever the oscillator RST 9 4 10 I is running, the device will reset by having the HIGH logic state on Reset pin for two machine cycles. If the PSEN pin driven by HIGH-to-LOW input transition if the RST input pin held HIGH, the device will enter the external host mode, else the device will enter into the normal operation mode. External Access Enable: To EA 31 29 35 I fetch Code from external program memory EA must be connected to VSS. For internal program execution EA must be strapped to VDD. Security lock level 4 disable EA, and program execution is possible only from internal program memory. It can tolerate upto 12 V. Address Latch Enable: ALE is ALE/PROG 30 27 33 I/O act as a output signal when latching the low byte of the address during an access to external memory. ALE is also the programming pulse input (PROG) to the flash programming. Normally the ALE can be used for external timing and clocking. One ALE

pulse is skipped only when each access to external data memory happened. ALE is disabled only when AO is set as 1.


6, 17, 28, 39

1, 12, 23, 34


NC means No Connect

Crystal 1:XTAL1 is a Input for XTAL1 19 15 21 I inverting oscillator amplifier as well as to the internal clock

generator circuits. Crystal 2:XTAL2 is a Output XTAL2 18 14 20 O from the inverting oscillator amplifier.





VDD indicates Power supply.





VSS indicates Ground.

ALE loading issue: When ALE pin experiences higher load (>30 pF) while reset, the microcontroller may enter into other modes rather than normal working mode. This can be avoided by adding a pull-up resistor of 3 khz to 50 Khz to VDD. e.g., for ALE pin.

For 6-clock mode, ALE is emitted at 1/3 of crystal frequency.

3.4 Special function registers:

Special Function Registers (SFRs) are restricted in accessing in the following ways:

In Undefined SFR locations User must not attempt to access. Accesses to any defined SFR locations must be strict for the functions for the SFRs.

SFR bits labelled as follows: 1. - It must written 0 Unless otherwise specified, but can return any value when read. It is a reserved bit and may be used in future derivatives. 2. 0 must be written with 0, and will return a 0 when read. 3. 1 must be written with 1, and will return a 1 when read.

3.5 Timers and Counters:

The quartz crystal is used by the microcontroller oscillator for its operation. This oscillator generates pulses those are of same width then these are ideal for time measurement since the frequency of this oscillator is accurately defined and very stable. Those types of crystals are also used in quartz watches. To know the time taken between two events if we calculate pulses coming from oscillator then it is sufficient. The timer functioning is also same as above described. Per each machine cycle, the value in the timer register get incremented or decremented only when the timer get properly functioned. If we combine both quartz and oscillator frequency of 12 MHZ the number in the register changes per microsecond, because a single machine-cycle instruction lasts for 12 quartz oscillator periods. The 8051 microcontroller has 2 timers/counters called T0 and T1.T0 and T1 are used to measure time and count external events. These timers/counters also generate clock pulses to be used in serial communication, so called Baud Rate. Timers/Counters can be accessed by user with special function registers. T0 and T1 share two SFRs those are TMOD and TCON. Each timer has two registers dedicated to itself those are TH0/TL0 and TH1/TL1.

TMOD (Timer Mode Register): It is a non-bit-addressable, 8-bit register. 7 6 5 4 3 2 1 0

Timer/counter 1 Gate# C/T# M1 M0

Timer/counter 0 Gate# C/T# M1 M0

Lower 4 bits are used to indicate Timer0 and Upper 4 bits are used to indicateTimer1. GATE bit is used for either internal or external control. GATE=0 then it indicates internal control, start and stop are controlled by software and GATE=1 then it indicates external control, start and stop are controlled by software and and external source. C/T specify either timer or counter. M0 and M1 bits are used to set timer mode (the same for Timer0 and Timer1) Table 3.2 : 8051 delivers 4 timer modes M1 0 0 1 1 M0 0 1 0 1 Mode Mode 0 Mode 1 Mode 2 Mode 3 Description 13 bit timer 16 bit timer 8 bit auto reload Split timer mode

TCON (Timer Control Register):

It is a 8 bit- addressable register in which 4 upper bits are used to indicate timers/counters shown below.









If TR set then timer turn on otherwise it turn off. TR=0 turn off, TR=1 turn on.TF0 and TF1 are Timer Flags informing about overflow, If TF=1 then interrupt could be activate, and it should be cleaned.

Equivalent instructions for TCON: Timer0: SETB TR0 CLR TR0 = = = = SETB TCON.4 CLR TCON.4



Timer1: SETB TR1 CLR TR1 = = = = SETB TCON.6 CLR TCON.6



TH0 and TL0 are upper and lower registers of Timer0, TH1 and TL1 are upper and lower registers of Timer1. They help to set initial value of timer/counter.

3.5.1Timer mode 0:
In this mode Timer 0 is a 13-bit timer, which consists all 8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 bits out of 16 bits.

3.5.2 Timer mode 1:

The timer is a 16 bit timer in the mode1 Timer0, which consists all the bits of TH0 and TL0.For that reason only it is most preferred one. Timer in mode1 operates similarly as in mode 0, only difference is that the registers count up to 65 536 because of the 16 bits. The mode bits are set to 0lb in TMOD . Mode 1 is similar to mode 0 except TLX is contained all 8bits.

3.5.3 Timer mode 2:

In this mode2 Timer 0 is a 8-bit timer. Here one 8-bit register is used for counting and it actually never count from 0, but from an arbitrary value (0-255) and that value is stored in another register (TH0).

3.5.4 Timer mode 3:

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two independent 8-bit timers. This mode is provided for applications requiring an additional

8-bit timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1.


3.6 UART (Universal Asynchronous Receiver and Transmitter)

Integrated UART is one of the microcontroller feature to make it so powerful and it is a serial port.UART is a full-duplex port, so it can be able to transmit and receive the data simultaneously and at different baud rates. Except UART it is very complicated to send and receive serial data, at which the pin state is regularly changed. When using UART,it is simple

to select the serial port and baud rate.Because of its simple understandings serial data transmit is nothing but writing to the SBUF register, while data receive represents reading the same register. The microcontroller will take care of not making any error while data transmission.

3.6.1 Serial port control(SCON) register:

SM0 bit7

SM1 bit6 bit5

SM2 bit4

REN bit3

TB8 bit2

RB8 bit1


RI bit0

SM0 - Serial port mode bit 0 is used for serial port mode selection. SM1 - Serial port mode bit 1. SM2 - Serial port mode 2 bit, It is also known as multiprocessor communication enable bit. When SM2 set, it activates multiprocessor communication in mode 2 ,mode 3 and mode 1. It should be cleared in mode 0.

REN When Reception Enable bit is 1 then it activates serial reception. When it is reset, serial reception is deactivate. TB8 TB8 is a Transmitter bit 8. Because all registers are 8-bit length, this bit gives solution to the problem of transmitting the 9th bit in modes 2 and 3. In the 9th bit TB8 is set to transmit logic 1.

RB8 RB8 is a Receiver bit 8 or the 9th bit received in modes 2 and 3.If the 9th bit received is a logic 1 then RB8 is set by software,. If the 9th bit received is a logic 0 then RB8 is cleared by hardware.

TI TI is a Transmit Interrupt flag it is set automatically when the last bit of a sent byte occurs. TI is a signal to the processor that the line is available for a new byte transmit. It must be cleared from the software.

RI RI is a Receive Interrupt flag, which is set automatically when one byte received. It signals that byte which is to be received should be read quickly before being replaced by a new data. This bit is also cleared from the software.

As seen, serial port mode is selected by combining the SM0 and SM2 bits. SM0 0 SM1 0 MODE 0 DESCRIPTION 8bit shift register BAUD RATE 1/12th of the

quartz frequency 0 1 1 8bit UART Determined timer 1 1 0 2 9bit UART 1/32th of the by

quartz frequency 1 1 3 9bit UART Determined timer 1 by

3.7 Reset:
A system reset is a function which is to be used to initializes the MCU and starts the program execution from memory location 0000H. The reset input for device is the RST pin. To reset the device a logic level high is to be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. While reset ALE, PSEN are weakly pulled high. During reset, ALE and PSEN output a high level for perform a proper reset. External element cant going to affect this level. While the system is running a system reset will not affect the 1 Kbyte of on-chip RAM memory, however, the contents of the on-chip RAM during power up are indeterminate.

3.8 Microcontroller Interrupts:

Five interrupt sources observed for the 8051, which means when the normal program execution is happening they recognize different events which are going to interrupt. If in case dont want any interrupt disturbances during normal program execution clear the EA bit of the register. Refer to figure below. Each interrupt can be enabled or disabled by setting bits of the IE register. Necessary details of external interrupts- INT0 and INT1are explained below. If the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated automatically on high to low transition, i.e. on the falling pulse edge. EA bit7 bit6 ET2 bit5 ES bit4 ET1 bit3 EX1 bit2 ET0 bit1 EX0 bit0

EA - global interrupt enable/disable

o 0- disables all interrupt requests. o 1 - enables all individual interrupt requests.

ES - enables or disables serial interrupt.

o 0 - UART system cannot generate an interrupt.

1 - UART system can generate an interrupt.

ET1 - bit enables or disables Timer 1 interrupt.

o 0 - Timer 1 cannot generate an interrupt.

1 - Timer 1 enables an interrupt.

EX1 - bit enables or disables external 1 interrupt: 0 - change of the pin INT0 logic state cannot generate an interrupt. 1 - enables an external interrupt on the pin INT0 state change.

ET0 - bit enables or disables timer 0 interrupt:

0 - Timer 0 cannot generate an interrupt.

1 - enables timer 0 interrupt.

EX0 - bit enables or disables external 0 interrupt:

0 - change of the INT1 pin logic state cannot generate an interrupt. 1 - enables an external interrupt on the pin INT1 state change.

3.9 Microcontroller Power Consumption Control

jUntil the IDL bit of a PCON register is set to logic 1, the microcontroller turns off the greatest power consumer- CPU unit at that time serial port,timers and interrupt system peripheral units operating normally with 6.5mA.In IDLE mode all registers and I/O ports states remain unchanged. For the purpose of making the microcontroller operated in normal condition,it is must either to execute and enable any interrupt or reset.It is beneficial if we execute first three instructions which are of NOP.If we do above then it doesnt perform any operation and microcontroller get sometime to stabiize and it prevents unneccessary changes on the I/O ports.

3.9.1 Idle mode Upon the IDL bit of the PCON register is set, the microcontroller turns off the greatest power consumer- CPU unit while peripheral units such as serial port, timers and interrupt system continue operating normally consuming 6.5mA. In Idle mode, the state of all registers and I/O ports remains unchanged. In order to exit the Idle mode and make the microcontroller operate normally, it is necessary to enable and execute any interrupt or reset. It will cause the IDL bit to be automatically cleared and the program resumes operation from instruction having set the IDL bit. It is recommended that first three instructions to execute now are NOP instructions. They don't perform any operation but provide some time for the microcontroller to stabilize and prevents undesired changes on the I/O ports.

3.9.2 Power down mode

If the PD bit of the PCON register is set then microcontroller goes into power down mode thus internel oscillator turned off and power consumption reduced enormously. In powerdown mode the microcontroller can operate with 2V,though it requires 2V power supply it consumed only 40uA.By reset only it is possible to get the microcontroller in normal mode. When the microcontroller is at Power Down mode, all SFR registers and I/O ports states remains unchanged. In the process of put the microcontroller in the normal mode,the SFR register contents get lost, but the internal RAM contents get saved. To activate stable operation of the quartz oscillator, Reset signal must be , approximately 10mS.

3.9.3 PCON register

SMOD bit7 bit6 bit5 bit4 GF1 bit3 bit2 GF0 bit1 PD IDL bit0

The purpose of the bits of the PCON register is:

SMOD Baud rate is twice as much higher by setting this bit. GF1 indicates that it is a General-purpose bit . GF0 indicates that it is a General-purpose bit. If PD set to logic 1 then the microcontroller enters into the Power down mode. If IDL set to logic 1 then the microcontroller enters into the Idle mode.