1

GITAM UNIVERSITY
(Declared as Deemed to be University U/S 3 of UGC Act, 1956)














REGULATIONS & SYLLABUS
OF
M.Tech. (Embedded Systems)
(w.e.f -2012-13 admitted batch)







Gandhi Nagar Campus, Rushikonda
VISAKHAPATNAM 530 045
Website: www.gitam.edu




2

REGULATIONS
(w.e.f. 2012-13 admitted batch)


1.0 ADMISSIONS

1.1 Admissions into M.Tech (Embedded system) programme of GITAM University are governed by
GITAM University admission regulations.


2.0 ELIGIBILTY CRITERIA

2.1 A pass in B. E. / B. Tech. in ECE / EIE / EEE/ CSE

2.2 Admissions into M.Tech will be based on the following:

(i) Score obtained in GAT (PG), if conducted.
(ii) Performance in Qualifying Examination / Interview.

The actual weightage to be given to the above items will be decided by the authorities before the
commencement of the academic year. Candidates with valid GATE score shall be exempted from
appearing for GAT (PG).

3.0 STRUCTURE OF THE M.TECH. PROGRAMME

3.1 The Programme of instruction consists of :

(i) A core programme imparting to the student specialization of engineering branch
concerned.
(ii) An elective programme enabling the students to take up a group of departmental
courses of interest to him/her.
(iii) Carry out a technical project approved by the Department and submit a report.

3.2 Each academic year consists of two semesters. Every branch of the M.Tech programme has a
curriculum and course content (syllabi) for the subjects recommended by the Board of Studies
concerned and approved by Academic Council.

3.3 Project Dissertation has to be submitted by each student individually.


4.0 CREDIT BASED SYSTEM

4.1 The course content of individual subjects - theory as well as practicals is expressed in terms of a
specified number of credits. The number of credits assigned to a subject depends on the number of
contact hours (lectures & tutorials) per week.

4.2 In general, credits are assigned to the subjects based on the following contact hours per week per
semester.

One credit for each Lecture hour.
One credit for two hours of Practicals.
Two credits for three (or more) hours of Practicals.

4.3 The curriculum of M.Tech programme is designed to have a total of 70 -85 credits for the award
of M.Tech degree. A student is deemed to have successfully completed a particular semesters
3

programme of study when he / she earns all the credits of that semester i.e., he / she has no F
grade in any subject of that semester.


5.0 MEDIUM OF INSTRUCTION

The medium of instruction (including examinations and project reports) shall be English.


6.0 REGISTRATION

Every student has to register himself/herself for each semester individually at the time specified by the
College / University.


7.0 CONTINUOUS ASSESSMENT AND EXAMINATIONS

7.1 The assessment of the students performance in each course will be based on continuous internal
evaluation and semester-end examination. The marks for each of the component of assessment are
fixed as shown in the Table 2:


Table 2: Assessment Procedure

S.No. Component of
assessment
Marks allotted Type of
Assessment
Scheme of Examination






1







Theory





Total




40




Continuous
evaluation
1. Best two mid examinations
of the three mid examinations
for 15 marks each for a total of
30 marks
2. Remaining 10 marks are
given by the teacher by
conducting quiz / assignments /
surprises tests etc.


60

Semester-end
examination
The semester-end examination
in theory subjects will be for a
maximum of 60 marks.
100





2





Practicals





100




Continuous
evaluation
(i) 40 marks are allotted for
record work and regular
performance of the student in
the lab.
(ii) One examination for a
maximum of 20 marks shall be
conducted by the teacher
handling the lab course at the
middle of the semester
(iii) One examination for a
maximum of 40 marks shall be
conducted at the end of the
semester (as scheduled by the
Head of the Department
concerned).








(i) 50 marks are allotted for
continuous evaluation of the
4


3

Project work


100

Project evaluation
project work throughout the
semester by the guide.
(ii) 50 marks are allotted for the
presentation of the project work
& viva-voce at the end of the
semester.*


4
Comprehensive
Viva


100

Viva-voce
100 marks are allotted for
comprehensive viva to be
conducted at the end of
programme.*
* Head of the Department concerned shall appoint two examiners for conduct of the examination.

8.0 REAPPEARANCE

8.1 A Student who has secured F Grade in any theory course / Practicals of any semester shall have
to reappear for the semester end examination of that course / Practicals along with his / her juniors.

8.2 A student who has secured F Grade in Project work shall have to improve his report and
reappear for viva voce Examination of project work at the time of special examination to be
conducted in the summer vacation after the last academic year.


9.0 SPECIAL EXAMINATION

9.1 A student who has completed the stipulated period of study for the degree programme concerned
and still having failure grade (F) in not more than 5 courses (Theory / Practicals), may be
permitted to appear for the special examination, which shall be conducted in the summer vacation
at the end of the last academic year.

9.2 A student having F Grade in more than 5 courses (Theory/practicals) shall not be permitted to
appear for the special examination.



10.0 ATTENDANCE REQUIREMENTS

10.1 A student whose attendance is less than 75% in all the courses put together in any semester will
not be permitted to attend the end - semester examination and he/she will not be allowed to
register for subsequent semester of study. He / She has to repeat the semester along with his / her
juniors.

10.2 However, the Vice Chancellor on the recommendation of the Principal / Director of the University
College / Institute may condone the shortage of attendance to the students whose attendance is
between 66% and 74% on genuine medical grounds and on payment of prescribed fee.

11.0 GRADING SYSTEM

11.1 Based on the student performance during a given semester, a final letter grade will be awarded at
the end of the semester in each course. The letter grades and the corresponding grade points are as
given in Table 3.
5


Table 3: Grades & Grade Points










11.2 A student who earns a minimum of 5 grade points (C grade) in a course is declared to have
successfully completed the course, and is deemed to have earned the credits assigned to that
course. However, a minimum of 24 marks is to be secured at the semester end examination of
theory courses in order to pass in the theory course.

12.0 GRADE POINT AVERAGE

12.1 A Grade Point Average (GPA) for the semester will be calculated according to the formula:
[ C x G ]
GPA =----------------
C
Where
C =number of credits for the course,
G =grade points obtained by the student in the course.

12.2 Semester Grade Point Average (SGPA) is awarded to those candidates who pass in all the subjects
of the semester.


12.3 To arrive at Cumulative Grade Point Average (CGPA), a similar formula is used considering the
students performance in all the courses taken in all the semesters completed up to the particular
point of time.


12.4 The requirement of CGPA for a student to be declared to have passed on successful completion of
the M.Tech programme and for the declaration of the class is as shown in Table 4.


Table 4: CGPA required for award of Degree

Distinction 8.0*
First Class 7.0
Second Class 6.0
Pass 5.0

* In addition to the required CGPA of 8.0, the student must have necessarily passed all the courses of every
semester in first attempt.


Grade Grade points Absolute Marks
O 10 90 and above
A+ 9 80 89
A 8 70 79
B+ 7 60 69
B 6 50 59
C 5 40 49
F Failed, 0 Less than 40
6



13.0 ELIGIBILITY FOR AWARD OF THE M.TECH DEGREE

13.1 Duration of the programme:
A student is ordinarily expected to complete the M Tech. programme in four semesters of two
years. However a student may complete the programme in not more than four years including
study period.

13.2 However the above regulation may be relaxed by the Vice Chancellor in individual cases for
cogent and sufficient reasons.

13.3 Project dissertation shall the submitted on or before the last day of the course. However, it can be
extended up to a period of 6 months maximum, with the written permission of the Head of the
Department concerned.

13.4 A student shall be eligible for award of the M.Tech degree if he / she fulfils all the following
conditions.

a) Registered and successfully completed all the courses and projects.
b) Successfully acquired the minimum required credits as specified in the
curriculum corresponding to the branch of his/her study within the stipulated time.
c) Has no dues to the Institute, hostels, Libraries, NCC / NSS etc, and
d) No disciplinary action is pending against him / her.


13.5 The degree shall be awarded after approval by the Academic Council.




7

RULES


1. With regard to the conduct of the end-semester examination in any of the practical courses of the
programme, the Head of the Department concerned shall appoint one examiner from the department not
connected with the conduct of regular laboratory work, in addition to the teacher who handled the
laboratory work during the semester.

2. In respect of all theory examinations, the paper setting shall be done by an external paper setter having a
minimum of three years of teaching experience. The panel of paper setters for each course is to be prepared
by the Board of Studies of the department concerned and approved by the Academic Council. The paper
setters are to be appointed by the Vice Chancellor on the basis of recommendation of Director of
Evaluation / Controller of Examinations.

3. The theory papers of end-semester examination will be evaluated by two examiners. The examiners may
be internal or external. The average of the two evaluations shall be considered for the award of grade in
that course.

4. If the difference of marks awarded by the two examiners of theory course exceeds 12 marks, the paper will
have to be referred to third examiner for evaluation. The average of the two nearest evaluations of the three
shall be considered for the award of the grade in that course.

5. Panel of examiners of evaluation for each course is to be prepared by the Board of Studies of the
department concerned and approved by the Academic Council.

6. The examiner for evaluation should possess post graduate qualification and a minimum of three years
teaching experience.

7. The appointment of examiners for evaluation of theory papers will be done by the Vice Chancellor on the
basis of recommendation of Director of Evaluation / Controller of Examinations from a panel of examiners
approved by the Academic Council.

8. Project work shall be evaluated by two examiners at the semester end examination. One examiner shall be
internal and the other be external. The Vice Chancellor can permit appointment of second examiner to be
internal when an external examiner is not available.






8

SYLLABUS
M.Tech. (Embedded Systems)
Programme Code: EPRES201201

I Semester



Course code

Name of the Course
Marks Hours per week

Credits
S
e
m
e
s
t
e
r

E
n
d


E
x
a
m
i
n
a
t
i
o
n

C
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v
a
l
u
a
t
i
o
n

T
o
t
a
l

L T P
T
o
t
a
l

EPRES 101 Optimization Techniques 60 40 100 3 - - 3 3
EPRES 102 Microcontrollers for
Embedded System
Design
60 40 100 4 - - 4 4
EPRES 103 Advanced Digital Signal
Processing
60 40 100 3 - - 3 3
EPRES 104 Embedded programming 60 40 100 3 - - 3 3
EPRES 105 Operating Systems 60 40 100 3 - - 3 3
EPRES 121-
124
Elective I 60 40 100 3 - - 3 3
EPRES 111 Technical Seminar - - 100 2 2 2
EPRES 112 Advanced
Microcontrollers lab.
- 100 100 - - 3 3 2
Total 23


List of Electives: Elective-1

EPRES 121 Advanced Computer Networks
EPRES 122 Digital Image Processing
EPRES 123 VLSI Design
EPRES 124 Robotics and Automation


















9



M.Tech. (Embedded Systems)

II semester



Course code

Name of the Course
Marks Hours per week

Credits
S
e
m
e
s
t
e
r

E
n
d


E
x
a
m
i
n
a
t
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n

C
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u
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s

E
v
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l
u
a
t
i
o
n

T
o
t
a
l

L T P
T
o
t
a
l

EPRES 201 Real Time Operating
Systems
60 40 100 4 - - 4 4
EPRES202 Advanced
microcontrollers
60 40 100 3 - - 3 3
EPRES203 Neural Networks and
Fuzzy Logic
60 40 100 3 - - 3 3
EPRES204 Embedded Networks and
protocols
60 40 100 3 - - 3 3
EPRES205 DSP processors and
architecture
60 40 100 3 - - 3 3
EPRES231-
234
Elective II - 100 100 3 - - 3 3
EPRES211 Comprehensive Viva 100 - 100 - - - - 2
EPRES212 Embedded System Lab - 100 100 - - 6 6 2
Total 23

List of Electives: Elective-II

EPRES231 Micro Electronic Mechanical Systems
EPRES232 Testing and Testability
EPRES233 Digital System Design
EPRES234 Virtual Instrumentation






10

M.Tech. (Embedded Systems) III semester



Course code


Name of the Course
Marks

Credits
S
e
m
e
s
t
e
r

E
n
d


E
x
a
m
i
n
a
t
i
o
n

C
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t
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n
u
o
u
s

E
v
a
l
u
a
t
i
o
n

T
o
t
a
l

EPRES311 Project Phase-I 50 50 100 8
Total 8



M.Tech. (Embedded Systems) IV semester



Course code


Name of the Course
Marks

Credits
S
e
m
e
s
t
e
r

E
n
d


E
x
a
m
i
n
a
t
i
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n

C
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u
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E
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i
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T
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t
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l

EPRES411 Project Phase-II 50 50 100 Project Phase-II
Total 16





Total Credits: 70
11

M.Tech. (Embedded Systems) I SEMESTER

EPRES101 OPTIMIZATION TECHNIQUES

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPREI101 3 - -- 3 40 60 100 3 Mathematics

UNIT I
Introduction to Optimization, Engineering Applications of Optimization, problem formulation.
Classical Optimization Techniques (With out Constraints): Necessary and Sufficient conditions of the general
problem, Single variable optimization, Multivariable optimization with no constraints.

UNIT II
Classical Optimization Techniques (With Constraints): Multivariable optimization with Equality constraints
Solution by Direct Substitution method, Method of constrained variation, Method of Lagrangian multipliers;
Multivariable optimization with inequality constraints: Kuhn-Tucker conditions.

UNIT III
Linear programming: Basic Terminology and Definitions, Exceptional cases, Simplex method, Big-M method,
Two-phase method, Revised Simplex method..

UNIT IV
Linear programming: Transportation Problems, Degeneracy in transportation problem, Assignment problems.

Unit-V
Non-Linear programming: Unconstrained optimization-Powells method, steepest descent method, Newtons
method, constrained optimization, Direct method, methods of feasible directions.

Text Books:

1. Engineering Optimization, Theory and Practice, by S.S.Rao, New age International (P) Limited Publishers.
2. Higher Engineering Mathematics by B.S. Grewal, Khanna Publishers

References:

1. Operations Research By S.D.Sharma, Kedar Nath Ram Nath & Co, Publishers
2. Introduction to Operations Research By Taha, PHI Publishers
12

M.Tech. (Embedded Systems) I SEMESTER

EPRES 102 MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES102 4 - -- 4 40 60 100 4 EIE
UNIT I
Introduction to Microcontroller: Introduction to concept of microcontroller, comparison of microprocessor and
Microcontroller, Intel 8051 microcontroller architecture, pin diagram, Addressing Modes, special function registers,
external memory interface with 8051, and operation of I/O ports.

UNIT II
Microcontrollers and Processor Architecture & Interfacing: Counters and timers in 8051, timer modes, Serial
data input, output, serial data modes, interrupts, timer flag interrupt, serial port interrupt, external interrupts,
software generated interrupt control, Addressing modes, external data moves, code memory, read only data moves.
Push and Pop. Instruction set of 8051. Member of MCS-51 family with special reference to 89C51 IC. Programming
of 8051 Calls and subroutines, interrupts and returns.

UNIT III
Devices and Buses for Device Networks: I/O Devices, Device I/O Types and Examples, Synchronous and
Asynchronous Communications from Serial Devices ,Examples of Internal Serial-Communication Devices, UART
and HDLC, Parallel Port Devices , Sophisticated interfacing features in Devices/Ports, Timer and Counting
Devices,I
2
C, USB, CAN and advanced I/O Serial high speed buses, ISA, PCI bus.

UNIT IV
Introduction PIC Microcontroller: General Introduction, PIC 16F877 Architecture, Registers, Memory
Organization, Addressing Modes, Instruction Set of PIC Microcontroller, PIC16F877 PERIPHERALS: Timers,
CCP modules, ADC modules, configuration word and programming.

UNIT V
Applications: Stepper motor control, speed control of ac,dc motors , position control of ac, dc motors, Traffic Light
controller, LED Interfacing, LCD Interfacing, control of physical parameters like temp, pressure, flow, level and
humidity

TEXT BOOKS:
1. 8051 Microcontroller and Embedded Systems, By Muhammad Ali Mazidi, Janice Mazidi, Rolin McKinlay, 2nd
Edition 2005
2. Embedded Systems - Architecture Programming and Design Raj Kamal, 2
nd
ed., 2008,TMH.
3. PIC Microcontroller and Embedded Systems Muhammad Ali Mazidi, Rolin D.Mckinaly, Danny Causy PE.
4. Jan Axelson Embedded Ethernet and Internet Complete, Penram publications

REFERENCES:
1. Embedded Microcomputer Systems, Real Time Interfacing Jonathan W. Valvano Brookes / Cole, 1999,
Thomas Learning.
2. Designing with PIC Microcontrollers- John B. Peatman, 1998, PH Inc.

13

M.Tech. (Embedded Systems) I SEMESTER

EPRES103 ADVANCED DIGITAL SIGNAL PROCESSING

Code L T P Total
Hrs
S E T Credits

Dept.
EPRES103 3 - - 3 40 60 100 3 EIE

UNIT I

Discrete-Time Fourier transform, Discrete Time Fourier Series, Discrete Fourier transform (DFT), properties of
DFT, Computation of DFT, Circular convolution and linear convolution using DFT, Fast Fourier Transform (FFT),
Radix-2 decimation-in-time and decimation-in -frequency algorithms, Inverse FFT.

UNIT II

Multirate Digital Signal Processing: Introduction, Decimation by a Factor D, Interpolation by a Factor I,
Sampling Rate Conversion by a Rational Factor I/D, Implementation of Sampling Rate Conversion, digital filter
banks, quadrature mirror filter banks; Introduction to time frequency analysis, Short Time Fourier Transform,
continuous time Wavelet Transform, Discrete wavelet transform, construction of wavelets, Multiresolution
Analysis.

UNIT III

Linear Prediction And Optimum Linear Filters: Random Signals, Correlation Functions and Power Spectra,
Innovations Representation of a Stationary Random Process, Forward and Backward Linear Prediction, Solution
of the Normal Equations, The Levinson-Durbin algorithm, AR Lattice and ARMA Lattice-Ladder Filters, Wiener
Filters for Filtering and Prediction

UNIT IV

Adaptive Filters: Applications of Adaptive Filters, Adaptive Direct-Form FIR Filters-The LMS Algorithm,
Adaptive Direct-Form FIR Filters-RLS Algorithms.

UNIT V

Power Spectrum Estimation: Estimation of Spectra from Finite-Duration Observations of Signals,
Nonparametric Methods for Power Spectrum Estimation, Parametric Methods for Power Spectrum Estimation.

Textbooks:
1. Digital Signal Processing Principles, Algorithms, Applications, J.G.Proakis & D. G. Manolakis Fourth
Edition PHI/ Pearson Education 2007.
2. Digital Signal Processing, A ComputerBased approach, by Sanjit K. Mitra, Tata Mc Graw-Hill, 1998.
3. Statistical Signal Processing, Monsom H.Hayes, John Wliley & Sons, INC.
4. Wavelet Transforms: Introduction to Theory and Applications, Raghuveer M Rao, Ajit S, Bopardikar, Pearson
Education 2000.









14

M.Tech. (Embedded Systems) I SEMESTER

EPRES104 EMBEDDED PROGRAMMING

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES104 3 - - 3 40 60 100 3 EIE

UNIT I
PROGRAMMING IN C: Introduction to C - Data types Structures Functions Arrays Pointers strings -
Hello world program - Super Loop architecture - delay function - Controlling the port pins - Reading switches -
Basic techniques for reading and writing the port pins Dealing with switch bounce - Adding structure to your code.

UNIT II
EMBEDDED C: Selection of processors - programming language - operating system - Object-oriented
programming with C - The Project Header (MAIN.H) The Port Header (PORT.H) Meeting real-time constraints -
Creating hardware delays using Timer - need for timeout mechanisms - Creating loop timeouts - Testing loop
timeouts Creating hardware timeout - Testing a hardware timeout.

UNIT III
MULTI-STATE SYSTEMS AND FUNCTION SEQUENCES IN C: Introduction-Implementing a Multi-State
(Timed) system - Traffic light sequencing - Implementing a Multi-State (Input/Timed) system - Controller for a
washing machine Using the serial interface - Basic RS-232 protocol - Asynchronous data transmission and baud
rates - Flow control - The software architecture - Using the on-chip UART for RS-232 communications - Memory
requirements - Displaying elapsed time on a PC 225 -The Serial-Menu architecture 237- Data acquisition.

UNIT IV
PROGRAMMING IN C++ : C++Initiation - The main() Function-C++Comments-C++Preprocessor - iostream
File - Header Filenames - C++Output Statements Functions - User-Defined Functions -Dealing with Data,
Simple Variables -Floating-Point Numbers - C++Arithmetic Operators- Pointers, Arrays, and Pointer Arithmetic .-
Loops and Relational Expressions- Function Overloading - Objects and Classes - Working with Classes - Classes
and Dynamic Memory Allocation - Class Inheritance.

UNIT-V
EMBEDDED C++: Introduction-conceptual and physically realizable objects - Real objects - Object classes-
Encapsulation - Abstract classes - Dynamic Memory Allocation - Class hierarchies- Inheritance - Multiple
inheritance - Polymorphism - An example object hierarchy - Naming convention - Developing an object class -
Parallel port class stage I, stage II & III - Advantages and disadvantages.

TEXT BOOKS:

1. Michael J. Pont, Embedded C Addison Wesley, Pearson Education Limited 2002.
2. Dr. Jayantha Katupitiya, Mr. Kim Bentley Interfacing with C++-Programming Real-World Applications
Pringer Verlag Berlin Heidelberg 2006

REFERENCE BOOKS:

1. Matthew Wilson, Imperfect C++Practical Solutions for Real-Life programmingAddison Wesley Professional
2004.
2. Stephen Prata, C++Primer Plus Sams Publishing, 2005.
3. Michael Barr, Programming Embedded Systems in C and C++Publisher:O'Reilly 1999.
4. Jean Labrosse , Jack Ganssle, Tammy Noergaard , Robert Oshana, Colin Walls,Keith Curtis, Jason Andrews,
David J. Katz, Rick Gentile, Kamal Hyder, Bob Perrin, Embedded Software Elsevier 2008.
5. Alan Holub, Compiler Construction In C Prentice Hall, 2005
15

M.Tech. (Embedded Systems) I SEMESTER

EPRES105 OPERATING SYSTEMS

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES105 3 - -- 3 40 60 100 3 CSE

UNIT I

INTRODUCTION: Operating system definition, operating system structure, operating system operations, operating
system services, , user operating system interface, system calls, types of system calls, system programs, operating
system design and implementation, virtual machines.

UNIT II

PROCESS MANAGAMENT AND COORDINATION: Definition of a process, Operations on processes, Inter-
process Communication, Multithreading models, Threading issues, Process scheduling, Scheduling algorithms,
Multiple processor, Scheduling, Thread scheduling. Process Synchronization, Deadlocks: Prevention, detection and
avoidance.

UNIT III

MEMORY MANAGEMENT: Swapping, Contiguous memory allocation, Paging, Segmentation, Virtual
Memory: Demand paging, Copy-on-write, Page replacement, Thrashing.

UNIT IV

STORAGE MANAGEMENT: File system (function of a file system): Access methods, Directory structure, file
sharing and protection. Disk structure, attachment, scheduling, management, RAID structure.

UNIT V

PROTECTION AND SECURITY: Goals of protection, Principles of protection, Domain of protection, Access
Matrix, Access control, Revocation of Access rights, System security: Security problem, Program threats, Network
threats, Cryptography as a security tool, User authentication, Security classifications.

TEXT BOOKS:
1. Silberschatz . A, Galvin.p and Gagne.G, Operating System Concepts, John Wiley and Sons. Singapore,,
Seventh Edition, 2008.

REFERENCES:
1. Dietal H.M , An Introduction to OS Pearson Education pvt.Ltd/PHI New Delhi, 12
th
Indian Reprint 2003.
2. Andrew S.Tanenbaum, Modern OSPHI Pearson Education pvt.Ltd New Delhi, 3
rd
Indian Reprint 2004.
3. William Stallings, Operating Systems, Pearson Education pvt.Ltd.
4. D.M. Dhamdhere,Operating Systems A Concept Approach, Tata McGraw Hill, 2003.






16

M.Tech. (Embedded Systems) I SEMESTER

EPRES121 ADVANCED COMPUTER NETWORKS
Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES121 3 - -- 3 40 60 100 3 EIE

UNIT I
Congestion and Quality of Service (QoS): Data traffic, Congestion, Congestion Control, Open loop and Closed
Loop Congestion Control in TCP and Frame Relay, Quality of Service, Flow Characterization, Flow Classes, Need
For QoS, Resource Allocation, Best Effort Service Features, Techniques to Improve QoS.
Queue Management: Passive, Active (RED), and Fair (BRED, Choke) Queue Management Schemes, Scheduling,
Traffic Shaping, Resource Reservation and Admission Control Scheduling, Integrated and Differential Services.

UNIT II
Wireless Local Area Networks: Introduction, Wireless LAN Topologies, Wireless LAN Requirements, the
Physical Layer, the Medium Access Control (MAC) Layer, Latest Developments.
Wireless Personal Area Networks (WPANs): Introduction to PAN Technology and Applications, Commercial
Alternatives- Bluetooth, Home RF.
Wireless Wide Area Networks and MANS: The Cellular Concept, Cellular Architecture, The First- Generation
Cellular Systems, The Second- Generation Cellular Systems, The Third- Generation Cellular Systems, Wireless in
Local Loop, Wireless ATM, IEEE 802.16 Standard.

UNIT III
Cellular Systems and Infrastructure- Based Wireless Networks: Cellular Systems Fundamentals, Channel
Reuse, SIR and User Capacity, Interference Reduction Techniques, Dynamic Resource Allocation, Fundamental
Rate Limits.
Virtual Private Network (VPN): Types of VPN, VPN General Architecture, Current VPN Advantages and
Disadvantages, VPN Security Issues, VPN Standards.

UNIT IV
ATM Protocol Reference Model: Introduction, Transmission Convergence (TC) Sub-layer, Physical Medium
Dependent (PMD) Sub-layer, Physical Layer Standards for ATM.
ATM Layer: ATM Cell Header Structure at UNI, ATM Cell Header Structure at NNI, ATM Layer Functions.
ATM Adaptation Layer: Service Classes and ATM Adaptation Layer, ATM Adaptation Layer 1 (AAL1), ATM
Adaptation Layer 2 (AAL2), ATM Adaptation Layer 3/4 (AAL3/4), ATM Adaptation Layer 5 (AAL5).
ATM Traffic and Service Parameterization: ATM Traffic Parameters, ATM Service Parameters, Factors
Affecting QoS Parameters, ATM Service Categories, QoS and QoS Classes.

UNIT V
Interconnection Networks: Introduction, Banyan Networks- Properties, Crossbar Switch, Three Stage Class
Networks, Rearrangeable Networks, Folding Algorithm, Benes Networks, Looping Algorithm, Bit- Allocation
Algorithm.
SONET/SDH: SONET/SDH Architecture, SONET Layers, SONET Frames, STS Multiplexing, SONET Networks.

TEXT BOOKS:
1. Wireless Communications - Andrea Goldsmith, 2005, Cambridge University Press.
2. Ad Hoc Wireless Networks: Architectures and Protocols - C. Siva Ram Murthy and B.S.Manoj, 2004, PHI.
3. Data Communication and Networking - B. A.Forouzan, 2
nd
updating, 2004,TMH
REFERENCES:
1. Introduction to Broadband Communication Systems- Sadiku, Mathew N.O., Akujuobi, Cajetan.M, PHI
2. Wireless Networks- P. Nicopolitidis, A. S. Pomportsis, G. I. Papadimitriou, M. S. Obaidat, 2003, JohnWiley &
Sons
3. High Performance TCP / IP Networking Mahaboob Hassan, Jain Raj, PHI.
4. Telecommunication System Engineering Roger L. Freeman, 4/ed., Wiley-Interscience, John Wiley & Sons,
2004.
17

M.Tech. (Embedded Systems) I SEMESTER

EPRES122 DIGITAL IMAGE PROCESSING

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES122 3 - - 3 40 60 100 3 EIE

UNIT I

Digital Image Fundamentals: Basic concepts in digital image processing, General structure of digital image
processing systems. Elements of visual perception, Mathematical representation of digital images. Image
digitization, Image sampling, Image quantization, spatial and gray level resolution, zooming and shrinking digital
images, Some basic relationships between pixels.

UNIT II

Image Enhancement: Basic gray level transformations, histogram processing, Smoothing and sharpening spatial
filters, Image enhancement in frequency domain, Smoothing and sharpening frequency domain filters, Image
restoration, Types of noises, noise reduction by spatial and frequency domain filtering, Wavelets in image
processing.

UNIT III

Image Compression: Coding redundancy, Interpixel redundancy, Psycho visual redundancy, Image compression
models, Elements of Information theory, Error free compression, Huffman coding, arithmetic code, LZW coding,
bit-plane coding, lossless predictive coding, lossy predictive coding, transform coding, wavelet coding.

UNIT IV

Morphological Image Processing: Dilation and Erosion, Opening and Closing, Boundary extraction, Region
filling, Convex hull, Thinning, Thickening, Skeletons, Pruning.

UNIT V

Image Segmentation: Point Detection, Line Detection, Edge Detection, Edge linking and boundary detection,
basic global Thresholding, Region based segmentation, Segmentation by morphological watersheds.

Text Books:

1. Digital Image Processing by Rafeal C. Gonzalez, Richard E. Woods, Pearson Education Asia.
2. Fundamentals of Digital Image Processing by Anil K.Jain












18

M.Tech. (Embedded Systems) I SEMESTER

EPRES123 VLSI DESIGN




UNIT I

Introduction: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation,
Lithography, Diffusion, Ion implantation, Metallisation, Encapsulation, Probe testing, Integrated Resistors and
Capacitors.
Basic Electrical Properties: Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships,
MOS transistor threshold Voltage, gm, gds, figure of merit
o
; Pass transistor, NMOS Inverter, Various pull ups,
CMOS Inverter analysis and design, Bi-CMOS Inverters.

UNIT II

VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2
m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and
Gates, Scaling of MOS circuits, Limitations of Scaling.

UNIT III

Gate Level Design: Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Basic circuit
concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance Units, Calculations - - Delays, Driving
large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers

UNIT IV

Subsystem Design : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators,
Zero/One Detectors, Counters, High Density Memory Elements.

UNIT V

Semiconductor Integrated Circuit Design: PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic,
Design Approach. VHDL SYNTHESIS : VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation,
Layout, Design capture tools, Design Verification Tools, Test Principles. CMOS Testing, Need for testing, Test
Principles, Design Strategies for test, Chip level Test Techniques, System-level Test Techniques, Layout Design for
improved Testability.

Text Books:

1. Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles
and A. Pucknell, PHI, 2005 Edition.
2. Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 1999.

References:

1. Chip Design for Submicron VLSI: CMOS Layout & Simulation- John P. Uyemura,
Thomson Learning.
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997
Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES123 3 - - 3 40 60 100 3 EIE
19

M.Tech. (Embedded Systems) I SEMESTER

EPRES124 ROBOTICS AND AUTOMATION

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES233 3 - -- 3 40 60 100 3 EIE

UNIT I

BASIC CONCEPTS: Definition and origin of robotics different types of robotics various generations of robots
degrees of freedom Asimovs laws of robotics anatomy of robot- applications of robots.

UNIT II

POWER SOURCES AND SENSORS: Hydraulic, pneumatic and electric drives determination of HP of motor
and gearing ratio variable speed arrangements path determination micro machines in robotics machine vision
ranging laser acoustic magnetic, fiber optic and tactile sensors.

UNIT III

MANIPULATORS, ACTUATORS AND GRIPPERS: Construction of manipulators manipulator dynamics and
force control types of control modes- electronic and pneumatic manipulator control circuits end effectors
various types of grippers.

UNIT IV

KINEMATICS AND PATH PLANNING Forward kinematics-solution of inverse kinematics problem multiple
solution jacobian work envelop hill climbing techniques robot programming languages

UNIT V

CASE STUDIES Mutiple robots machine interface robots in manufacturing and non- manufacturing
applications robot cell design selection of robot.

Text books:

1. Saeed B. Niku, Introduction to Robotics Analysis, Systems, Applications, Prentice Hall of
India/PearsonEducation, Asia, 2001.
2. Mikell P. Groover, et.al Industrial Robots - Technology Programming and applications, McGraw Hill, 1980.

References:

1. Yoran Koren, Robotics for Engineers, McGraw Hill. 1980
2. Craig, Introduction to Robotics Mechanics and Control, Second edition, Pearson Education, Asia, 2004.
3. Robotics Technology and Flexible Automation, Satya Ranjan Deb, TMH, New Delhi, 2001










20

M.Tech. (Embedded Systems) I SEMESTER

EPRES111 TECHNICAL SEMINAR

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES111 - - - - 100 - 100 2 EIE



M.Tech. (Embedded Systems) I SEMESTER

EPRES112 ADVANCED MICROCONTROLLERS LAB

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES111 - - 3 3 100 - 100 2 EIE


1. Program in C & Assembly Language to blink LED with 1sec software delay using Microcontroller 8051.

2. Program to blink LED using Timers in Microcontroller 8051.

3. Program to DisplayHello World on LCD using Microcontroller 8051.

4. Program to obtain Serial Communication using Microcontroller 8051.

5. Interface Keyboard & 7 Segment to using Microcontroller 8051.

6. Program to blink LED using Microcontroller PIC 16F877.

7. Program to measure Temperature using Microcontroller PIC 16F877.

8. Program to Interface Seven Segment using Microcontroller PIC 16F877.

9. Program to Test Memory using Microcontroller PIC 16F877.

10. Program to generate PWM using Microcontroller PIC 16F877.

11. Stepper Motor Control Microcontroller PIC 16F877.

12. DC Motor Control Microcontroller PIC 16F877.

21

M.Tech. (Embedded Systems) II SEMESTER

EPRES201 REAL TIME OPERATING SYSTEMS

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES201 4 - -- 4 40 60 100 4 EIE

UNIT I

Introduction: Introduction to Operating System: Computer Hardware Organization, BIOS and Boot Process,
Multi-threading concepts, Processes, Threads, Scheduling

UNIT II

Basics of real-time concepts: Terminology: RTOS concepts and definitions, real-time design issues, examples,
Hardware Considerations: logic states, CPU, memory, I/O, Architectures, RTOS building blocks, Real-Time Kernel

UNIT III

Process Management: Concepts, scheduling, IPC, RPC, CPU Scheduling, scheduling criteria, scheduling algorithms

Threads: Multi-threading models, threading issues, thread libraries, synchronization Mutex: creating, deleting,
prioritizing mutex, mutex internals

UNIT IV

Inter-process communication: buffers, mailboxes, queues, semaphores, deadlock, priority inversion, Pipes

Memory Management: process stack management, run-time buffer size, swapping, overlays, block/page
management, replacement algorithms, real-time garbage collection

UNIT V

Case study Linux POSIX system, RTLinux / RTAI, Windows system, Vxworks, uItron Kernel Design Issues:
structure, process states, data structures, inter-task communication mechanism, Linux Scheduling


TEXT BOOKS:

1. MicroC/OS-II : The Real-Time Kernel by J. J. Labrosse
2. Real-Time and Embedded Guide by Herman B.
3. Real-Time System Design and Analysis by Philips A. Laplante
4. Linux for Embedded and Real-Time Applications by Doug Abbott

REFERENCES:

1. Advanced UNIX Programming, Richard Stevens
2. VX Works Programmers Guide
22

M.Tech. (Embedded Systems) II SEMESTER
EPRES202 ADVANCED MICROCONTROLLERS

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES202 3 - - 3 40 60 100 3 EIE

UNIT I

AVR MICROCONTROLLER ARCHITECTURE: Architecture memory organization addressing modes
instruction set programming techniques Assembly language & C rogramming- Development Tools Cross
Compilers Hardware Design Issues .

UNIT II

PERIPHERAL OF AVR MICROCONTROLLER:I/O Memory EEPROM I/O Ports SRAM Timer
UART Interrupt Structure- Serial Communication with PC ADC/DAC Interfacing


UNIT III

ARM ARCHITECTURE AND PROGRAMMING: Arcon RISC Machine Architectural Inheritance Core &
Architectures - Registers Pipeline - Interrupts ARM organization - ARM processor family Co-processors.
Instruction set Thumb instruction set Instruction cycle timings - The ARM Programmers model ARM
Development tools ARM Assembly Language Programming and Ccompiler programming.

UNIT IV

ARM APPLICATION DEVELOPMENT: Introduction to DSP on ARM FIR Filter IIR Filter Discrete
Fourier transform Exception Handling Interrupts Interrupt handling schemes- Firmware and bootloader
Example: Standalone - Embedded Operating Systems Fundamental Components - Example Simple little Operating
System

UNIT V

DESIGN WITH ARM MICROCONTROLLERS: Integrated development environment - STDIO Libraries - User
Peripheral Devices Application of ARM processor: Wireless Sensor Networks, Robotics.

Text Books:

1. Steve Furber, ARM system on chip architecture, Addision Wesley
2. Dananjay V. Gadre Programming and Customizing the AVR microcontroller,
McGraw Hill 2001

Reference books:

3. Andrew N. Sloss, Dominic Symes, Chris Wright, John Rayfield ARM System Developers Guide Designing and
Optimizing System Software, Elsevier 2007.
4. Trevor Martin, The Insider's Guide To The Philips ARM7-Based Microcontrollers, An Engineer's Introduction
To The LPC2100 Series Hitex (UK) Ltd.,
5. ARM Architecture Reference Manual
23

M.Tech. (Embedded Systems) II SEMESTER

EPRES203 NEURAL NETWORKS AND FUZZY LOGIC

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES203 3 - - 3 40 60 100 3 EIE

UNIT I

Introduction to Artificial Neural Networks: Artificial neural networks and their biological motivation
Terminology Models of neuron Topology characteristics of artificial neural networks types of activation
functions. Learning Laws: Learning methods error correction learning Hebbian learning Perceptron XOR
Problem Perceptron learning rule convergence theorem Adaline

UNIT II

Feed forward networks: Multilayer Perceptron Back Propagation learning algorithm Universal function
approximation Associative memory: auto association, heteroassociation, recall and cross talk. Recurrent neural
networks: Linear auto associator Bi-directional associative memory Hopfield neural network Traveling
Salesman Problem

UNIT III

Unsupervised Learning: Competitive learning neural networks Max net Mexican Hat Hamming net. Self
Organizing networks: Kohonen Self organizing Feature Map Counter propagation Learning Vector Quantization
Adaptive Resonance Theory. Applications of neural networks in image processing signal Processing, modeling and
control.

UNIT IV

Fuzzy Sets and Fuzzy Relations: Introduction classical sets and fuzzy sets classical relations and fuzzy relations
membership functions fuzzy to crisp conversion, fuzzy arithmetic, numbers, vectors, and extension principle

UNIT V

Fuzzy Decision Making: Classical logic and fuzzy logic fuzzy rule based systems fuzzy nonlinear simulation
fuzzy decision making fuzzy control systems fuzzy optimization one-dimensional optimization.
Neuro Fuzzy: Mathematical formulation of adaptive neuro-fuzzy inference systems.

Text Books:

1. Laurence Fausett, Fundamentals of Neural Networks-Architectures, algorithms and
applications, Pearson Education Inc., 2004.
2. Timothy J. Ross, Fuzzy Logic with Engg. Applications, John Wiley and sons, 2004.
3. S.Haykin,Neural Networks, A Comprehensive Foundation, Pearson Edu. 2004.
4. Jacek.M.Zurada,Introduction to Artificial Neural Systems,Jaico Publishing House, 2001.

Reference:

1. J.S.R. Jang, C.T. Sun, E. Mizutani,, Neuro Fuzzy and Soft Computing - A computational
Approach to Learning and Machine Intelligence, Pearson Education Inc., 2002.


24

M.Tech. (Embedded Systems) II SEMESTER

EPRES204 EMBEDDED NETWORKS AND PROTOCOLS

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES205 3 - - 3 40 60 100 3 EIE

UNIT I

INTRODUCTION TO CAN
The CAN bus - General - Concepts of bus access and arbitration - Error processing and management - From concept
to reality -Patents, licenses and certification CAN protocol: ISO 11898-1-Content of the different ISO/OSI layers
of the CAN bus-Compatibility of CAN 2.0A and CAN 2.0B.

UNIT II

ETHERNET BASICS
Elements of a network Inside Ethernet Building a Network: Hardware options Cables, Connections and
network speed Design choices: Selecting components Ethernet Controllers Using the internet in local and
internet communications Inside the Internet protocol.

UNIT III

EMBEDDED ETHERNET
Exchanging messages using UDP and TCP Serving web pages with Dynamic Data Serving web pages that
respond to user Input Email for Embedded Systems Using FTP Keeping Devices and Network secure.

UNIT IV

INDUSTRIAL NETWORKING PROTOCOL
LIN Local Interconnect Network - Basic concept of the LIN 2.0 protocol - Fail-safe SBC Gateways - Managing
the application layers - Safe-by-Wire - Safe-by-Wire Plus - Audio-video buses - I2C Bus - D2B (Domestic digital)
bus - MOST (Media oriented systems transport) bus - IEEE 1394 bus or FireWire- profi bus.

UNIT V

RF COMMUNICATION
Radio-frequency communication: internal and external - Remote control of opening parts - PKE (passive keyless
entry) and passive go- TPMS (tyre pressure monitoring systems) -Wireless networks- GSM-Bluetooth - IEEE
802.11x - NFC (near-field communication).


TEXT BOOKS:

1. Dominique Paret , Multiplexed Networks for Embedded Systems- CAN, LIN, Flexray, Safe-by-Wire... John
Wiley & Sons Ltd- 2007.
2. Jan Axelson Embedded Ethernet and Internet Complete, Penram publications

REFERENCE BOOKS:

1. Glaf P.Feiffer, Andrew Ayre and Christian Keyold, Embedded networking with
CAN and CAN open. Embedded System Academy 2005.
2. Gregory J. Pottie, William J. Kaiser Principles of Embedded Networked Systems
Design, Cambridge University Press, Second Edition, 2005.
25

M.Tech. (Embedded Systems) II SEMESTER

EPRES205 DSP PROCESSORS AND ARCHITECTURE

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES204 3 - - 3 40 60 100 3 EIE

UNIT I

Introduction to digital signal processing, the sampling process, Discrete time sequences,
discrete fourier transform and FFT, Linear time invariant systems, digital filters, decimation and Interpolation,
analysis and design tool for DSP systems, MATLAB, DSP
using MATLAB.

UNIT II

Computational accuracy in DSP Implementations: Number formats for signals and coefficients in DSP systems,
Dynamic Range and Precision, Sources of error in DSP implementations, A/D conversion errors, DSP
computational errors, D/A conversion errors, compensating filter.

UNIT III

Architectures for programmable DSP devices: Basic architectural features, DSP computational building blocks, Bus
architecture and memory, data addressing capabilities, address generation unit, programmability and program
execution, speed issues, features for external interfacing.

UNIT IV

Execution control and Pipelining: hard ware looping, Interrupts stacks, relative branch support, pipelining and
performance, Pipeline depth, interlocking, branching effects, Interrupt effects, Pipeline programming models.

UNIT V

Interfacing Memory and Peripherals to Programmable DSP devices: Memory space organization, External bus
interfacing signals, Memory interface, parallel I/O interface, programmable I/O, Interrupt and I/O, direct memory
access. Multi channel buffered serial port (McBSP), McBSP programming..

Text Books

1. Digital Signal Processing- Avtar Singh and S. Srinivasan, Thompson Publications, 2004.
2. DSP processor fundamentals, Architecture & Features-Lapsley et al. S. Chand & Co.2000

Reference Books:

1. Digital signal processors, Archtecture, programming and applications- B. venkata ramani and
M.Bhaskar, TMH, 2004.
2. Sen. M. Kuo, Real-Time Digital Signal Processing: Implementations and Applications 2/e,
Wiley Publications, 2006
3. Rulph Chassaing, Digital Signal Processing with C6713 and C6416 DSK, 2/e Wiley
Publications,2005
26

M.Tech. (Embedded Systems) II SEMESTER

EPRES231 MICRO ELECTROMECHANICAL SYSTEMS

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES232 3 - - 3 40 60 100 3 EIE

UNIT I

INTRODUCTION, BASIC STRUCTURES OF MEM DEVICES: (Canti Levers, Fixed Beams diaphragms).
Broad Response of Micro Electromechanical Systems (MEMs) to Mechanical (force, pressure etc.) Thermal,
Electrical, Optical and Magnetic stimuli, Compatability of MEMS from the point of Power Dissipation, Leakage etc.

UNIT II

REVIEW OF MECHANICAL CONCEPTS: Stress, Strain, Bending Moment, Deflection Curve. Differential
Equations Describing the Deflection under Concentrated Force, Distributed Force, Deflection Curves for Canti
Levers Fixed Beam. Electrostatic Excitation Columbic Force between the Fixed and Moving Electrodes.
Deflection with Voltage in C.L, Deflection Vs Voltage Curve, Critical Fringe Fields Field Calculations using
Laplace Equation. Discussion on the Approximate Solutions Transient Response of the MEMS.

UNIT III

TWO TERMINAL MEMS: Capacitance Vs Voltage Curve Variable Capacitor. Applications of Variable
Capacitors. Two Terminal MEM Structures. Three Terminal MEM Structures Controlled Variable Capacitors
MEM as a Switch and Possible Applications.

UNIT IV

MEM CIRCUITS & STRUCTURES FOR SIMPLE GATES: AND, OR, NAND, NOR, Exclusive OR, simple
MEM Configurations for Flip-Flops Triggering, Applications to Counters, Converters. Applications for Analog
Circuits like Frequency Converters, Wave Shaping. RF Switches for Modulation. MEM Transducers for Pressure,
Force Temperature. Optical MEMS.

UNIT V

MEM TECHNOLOGIES: Silicon Based MEMS Process Flow Brief Account of Various Processes and Layers
like Fixed Layer, Moving Layers, Spacers Etc., Etching Technologies. Metal Based MEMS: Thin and Thick Film
Technologies for MEMS. PROCESS flow and Description of the Processes. Status of MEMS in the Current
Electronics scenario.

TEXT BOOKS:

1. Gabriel.M.Review, R.F. MEMS Theory, Design and Technology, John Wiley & Sons, 2003.
2. Thimo Shenko, Strength of Materials, CBS Publishers & Distributors., 2000.
3. Ristic L. (Ed.), Sensor Technology and Devices, Artech House, London 1994.
4. Servey E.Lyshevski, MEMS and NEMS, Systems Devices; and Structures, CRC Press, 2002.


27


M.Tech. (Embedded Systems) II SEMESTER

EPRES232 TESTING AND TESTABILITY

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES233 3 - -- 3 40 60 100 3 EIE

UNIT I

INTRODUCTION TO TEST AND DESIGN FOR TESTABILITY (DFT) FUNDAMENTALS: Modeling:
Modeling Digital Circuits at Logic Level, Register Level and Structural Models. Levels of Modeling. Logic
Simulation: Types of Simulation, Delay Models, Element Evaluation, Hazard Detection, Gate Level Event Driven
Simulation.

UNIT II

FAULT MODELING: Logic Fault Models, Fault Detection and Redundancy, Fault Equivalence and Fault
Location. Single Stuck and Multiple Stuck Fault Models. Fault Simulation Applications, General Techniques for
Combinational Circuits.

UNIT III

TESTING FOR SINGLE STUCK FAULTS (SSF): Automated Test Pattern Generation (ATPG/ATG) For Ssfs In
Combinational and Sequential Circuits, Functional Testing With Specific Fault Models. Vector Simulation ATPG
Vectors, Formats, Compaction and Compression, Selecting ATPG Tool.

UNIT IV

DESIGN FOR TESTABILITY: Testability Trade-Offs, Techniques. Scan Architectures and Testing
Controllability and Absorbability, Generic Boundary Scan, Full Integrated Scan, Storage Cells for Scan Design.
Board Level and System Level DFT Approaches. Boundary Scans Standards. Compression Techniques Different
Techniques, Syndrome Test and Signature Analysis.

UNIT V

BUILT-IN SELF-TEST (BIST): BIST Concepts and Test Pattern Generation. Specific BIST Architectures
CSBL, BEST, RTS, LOCST, STUMPS, CBIST, CEBS, RTD, SST, CATS, CSTP, BILBO. Brief Ideas on Some
Advanced BIST Concepts and Design for Self-Test at Board Level.
MEMORY BIST (MBIST): Memory Test Architectures and Techniques Introduction to Memory Test, Types of
Memories and Integration, Embedded Memory Testing Model. Memory Test Requirements for MBIST.

TEXT BOOKS:

1. Miron Abramovici, Melvin A. Breur, Arthur D.Friedman, Digital Systems Testing and Testable Design, Jaico
Publishing House, 2001.


28

M.Tech. (Embedded Systems) II SEMESTER

EPRES233 DIGITAL SYSTEM DESIGN





UNIT I

Introduction to Verilog: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis,
Functional Verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and Synthesis
Tools, Test Benches. Language Constructs and Conventions.

UNIT II

Gate Level & Behavioral Modeling: Introduction, AND Gate Primitive, Other Gate Primitives, Illustrative
Examples, Tri-State Gates, Array of Instances of Primitives, Design of Flip-flops with Gate Primitives, Delays,
Strengths and Contention Resolution, Net Types, Design of Basic Circuits, Exercises.

UNIT III

Behavioral Modeling: Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always
Construct, Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Designs at Behavioral
Level, Blocking and Non blocking Assignments, case, if, assign, repeat, for-loop, disable , while, forever,
constructs. Parallel blocks, force-release construct, Event

UNIT IV

Digital Design with State Machine Charts: State Machine Charts, Derivation of SM Charts, Realization of SM
Charts, Implementation of the Dice Game, Alternative realizations for SM Charts using Microprogramming

UNIT V

Designing with FPGAs and CPLDs: Xilinx 3000 Series FPGAs, Designing with FPGAs, Using a One-Hot State
Assignment, Altera Complex Programmable Logic Devices (CPLDs), Altera FLEX 10K Series CPLDs, Verilog
Models: Static RAM Memory, A simplified 486 Bus Model, Interfacing Memory to a Microprocessor Bus, UART
Design.

Text Books:

1. Design through Verilog HDL T.R. Padmanabhan and B. Bala Tripura Sundari, WSE, 2004 IEEE Press.
2. Fundamentals of Logic Design with Verilog Stephen. Brown and Zvonko Vranesic, TMH, 2005.
3. Digital Systems Design using VHDL Charles H Roth, Jr. Thomson Publications, 2004.

Reference Books:
1. A Verilog HDL Premier by J.Bhasker.
2. Verilog system design by Zainalabedin navabi.
3. Advanced Digital Design with the Verilog HDL by Michael D. Ciletti



Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES102 3 - - 3 40 60 100 3 EIE
29

M.Tech. (Embedded Systems) II SEMESTER

EPRES234 VIRTUAL INSTRUMENTATION





UNIT I

Introduction: Virtual Instrumentation Definition, flexibility Block diagram and Architecture of Virtual
Instruments Virtual Instruments versus Traditional Instruments Data flow techniques-graphical programming in
dataflow Review of Popular softwares in virtual Instrumentation.

UNIT II

VI Programming Techniques: VI- sub VI- Loops-structures-charts- arrays- clusters graphs- formula node-math
script- local and global variable- strings- file I/O-execution control- Instrument drivers.

UNIT III

Data Acquisition in VI: Introduction to data acquisition-signal conditioning-classes of signal conditioning-field
wiring and signal measurement-ground loops-A/D, D/A converters, plug-in DAQ boards- Analog input/output
cards - Digital Input/Output cards-counter and timer I/o boards-Isolation-techniques- Opt isolation -Data
acquisition modules with serial communication.
UNIT IV

Communication networked modules: Introduction to PC Buses Local bus: ISA PCI RS232 RS422
RS485 Interface Bus USB, PCMCIA, VXI, SCXI, PXI. Instrumentation buses: Modbus GPIB - Networked
bus ISO/OSI Reference model, Ethernet, and VISA

UNIT V

Real time control and Applications: Design of ON/OFF controller- PID controller -electronic prototyping and
testing with ELVIS- real-time data acquisition-transducer analysis-signal processing with DSP module-real-time
embedded control with CRIO-case studies on developments in the areas such as SCADA and HMI.


Text Books :

1. LabVIEW based advanced Instrumentation System, PSumathi, Springer science Elsievier 2007.
2. Practical Data Acquisition for Instrumentation and Control Systems, John Park and Steve Mackay, Elsevier
Publications.

References:

1. Labview Graphical programming, Gary Jhonson, Mc Graw Hill, Newyork, 1997.
2. Labview for everyone, Lisa K.Wells and Jeffrey Travis, Prentice Hall, NewJersey, 1997.
Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES102 3 - - 3 40 60 100 3 EIE
30

M.Tech. (Embedded Systems) II SEMESTER

EPRES211 COMPREHENSIVE VIVA

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES211 - - - - - 100 100 2 EIE




M.Tech. (Embedded Systems) II SEMESTER

EPRES212 EMBEDDED SYSTEM LAB

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES212 - - 6 6 100 - 100 2 EIE

Part -1

1. Blinking of led using ARM microcontroller
2. Measurement of temperature and display on hyper terminal using ARM microcontroller
3. Measurement of temperature and display on LCD using ARM microcontroller.
4. Simple Task scheduling of blinking LEDs using ucos OS
5. LCD and serial port task scheduling using ucos OS
6. I2C interfacing to ARM
7. Introduction to Vxworks
8. Task scheduling using Vxworks.

Part -II

1. Combinational Logic: Basic Gates, Multiplexer, Comparator, Adder/ Subtracter,
Multipliers, Decoders, Address decoders, parity generator, ALU Using verilog.

2. Sequential Logic: D-Latch, D-Flip Flop, JK-Flip Flop, Registers, Ripple Counters,Synchronous Counters, Shift
Registers ( serial-to-parallel, parallel-to-serial), Cyclic Encoder /Decoder using verilog.

3. Synthesis and verification of combinational and sequential circuits using FPGA.

4. Review of DSP Processor Basics, Study of TMS320C6713 DSP Processor architecture, Study of DSK6713
Hardware and Software API, LED Blinking, Line-In Line-Out, Sine Wave Generation(using Look Up Table
Method), FIR Filter Implementation, IIR Filter Implementation, FFT Implementation












31

M.Tech. (Embedded Systems) III SEMESTER
EPRES311 PROJECT PHASE-I
Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES311 - - - - 50 50 100 8 EIE







M.Tech. (Embedded Systems) IV SEMESTER
EPRES411 PROJECT PHASE-II

Course Code L T P Total
Hrs
C S T Credits

Dept.
EPRES411 - - - - 50 50 100 16 EIE