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6 Silicon Design Structures and Rules

6.1 Basic silicon structures Simple Digital CMOS integrated circuits are composed of ve layers of conducting materials insulated by silicon dioxide, Si02 , as diagrammatically shown in Figure 61

METAL 2 Dioxide via (m2 to m1)                                                                  

                                                          
            METAL      1                                     
  PolyCut  pDiffCut

   nDiffCut   POLYSILICON        nWellCut

     pWellCut             gate oxide                               

glass p DIFFUSIOSN n - WELL n DIFFUSION p - WELL

SUBSTRATE (SILICON - Si)

Figure 61: Diagrammatic cross-sectional view of a CMOS integrated circuit

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The conducting material layers are as follows: Wells (n and p), Diffusion regions Polysilicon paths, Metal 1 paths, Metal 2 paths. Wells For simplicity we presented a double-well structure: n-well in which pMOS transistors are fabricated, and p-well with nMOS transistors. In practice, however, we often have a single well, (say n-well) and the substrate plays the role of the opposite well. Diffusion Note that n diffusion is created in the p-well (or p substrate) and p diffusion in the n well. Diffusion regions are also called the active regions and they form the sources and drains of the transistors. Polysilicon Polysilicon paths are separated from the diffusion by a very thin layer of the gate oxide. Polysilicon forms the gates of the transistors and short interconnections. Metal 1 Metal 1 layer is used to created major interconnections including the VDD and the GND connections. Note that from the metal 1 the contacts are made to the wells, diffusion regions and to polysilicon layer. Such connections are made by metal lling in the cuts through the insulating silicon dioxide.

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Metal 2 Metal 2 layer is used to create connections in the direction orthogonal to metal 1 paths. Note that the metal 2 layer can be connected only to the metal 1 layer through vias in the oxide. There are no direct connections possible between the metal 2 layer and layers below the metal 1, say polysilicon. Contacts Note that we have six different types of contacts marked in Figure 61 as: pDiffCut, nDiffCut between diffusion regions and metal 1, pWellCut, nWellCut between wells (substrate) and metal 1, PolyCut between polysilicon and metal 1, via between metal1 and metal 2. Finally, in Figure 61, it is shown that the whole chip structure is insulated by a layer of glass with openings to solder in wires forming the external connectors.

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6.2 Layout Design Rules Layout design rules specied dimensions of all objects created on the silicon surface and separation between them. Traditionally two sets of rules are used: Micron rules, in which all circuit layout dimensions such as minimum feature sizes and their separations are stated in terms of their absolute dimensions in micrometers. These rules specify the manufacturing limits. Lambda rules, in which all layout dimensions are specied in multiples of a single parameter . This parameter is related to the minimum feature available in a given technology and for our purpose can be assumed to be in the range: 0.25m One of the best sources of the current design rules is available from an American MOSIS company offering small-volume production services for VLSI circuit development. The design rules are available from
http://www.mosis.com/Technical/Designrules/scmos/

Two excerpts from those rules are appended as: Lnts/DR/scmos-active.html and Lnts/DR/scmos-contact.html Using a CAD package like Mentor Graphics, a set of the design rules is incorporated into the specication of the technology.

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Basic design rules associated with transistors, that is, with polysilicon and active (diffusion) areas are illustrated in Figure 62.
2 2 2 1 3 3
Figure 62: Design rules for polysilicon and active (diffusion) areas.

The design rules for metal 1 and metal 2 paths are illustrated in Figure 63.
3 3

Figure 63: Metal design rules.

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The design rules for polysilicon and diffusion contacts and the metal 1 to metal 2 via, and cross-sectional views of the contacts are illustrated in Figure 64.

polycut diffcut

via 4

Figure 64: Polysilicon (polycut), diffusion (diffcut), and Metal1-to-

Metal2 contacts (via). a. Constituent masks and related design rules. b. Layout view of the contacts c. Cross-sections of the contact silicon structures It can be observed that the cut which is lled with metal to make an electrical connection between layers is 2 2. In addition there should be at least one of the overlapping materials. In the cross-sectional views, it can be noticed that the contacts are surrounded with insulated silicon dioxide.

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Finally there are a common-sense crossing rules illustrated in Figure 65. This time, for simplicity, we use the stick diagram convention.
a b c

Figure 65: Crossing rules

The crossing rules can be summarized as follows: a When a polysilicon crosses the active (diffusion) paths, transistors are made. b Metal 1 and metal 2 paths can go over polysilicon, diffusion and each other without any connections made. c In order to connect metal 1 to polysilicon, diffusion, or metal 2, a contact must be made. Metal 2 can be connected only to metal 1 through the via contact.

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6.3 Principles of a good circuit layout at the cell level Designing a low level library cell, we have to obey the following rules of a good layout presented in Figure 66

Figure 66: Illustration of the good layout principles at the cell level

Two horizontal, preferably continuous (!) strips of p-type and n-type diffusion in their respective wells/substrates, Vertical polysilicon paths to form p-MOS and n-MOS transistors and to implement short, local, connections, Primarily horizontal metal1 paths to implement VDD , GND, and other longer connections in the circuit, Primarily vertical metal2 paths to implement long inter-gate connections Remember about the well/substrate contacts to DD . The p GND diffusion area of these contacts should be adjacent to the native diffusion area in the given well.
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6.4 Serial connection of MOS transistors Let us consider a serial connection of two nMOS transistors connected between GND and an output Y terminal. According to the rules of the good layout the stick diagram and the layout of such a serial connection should look as in Figure 67.
A A B Y Y GND B

      A   B         
      
      Y

           

                  
      

        
                                                                    GND                                                                                                                                                                                   
Figure 67: A schematic, stick diagram and a layout of a serial connection of two nMOS transistors.

GND

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6.5 Parallel connection of transistors A serial connection of transistors implements the AND function in the switch logic: a connection is made when both transistors are ON. Similarly, a parallel connection of transistors implements the OR function in the switch logic: a connection is made when either or both transistors are ON. As an example let us consider a parallel connection of pMOS transistors as in Figure 68.
VDD A B Y VDD VDD

B Y VDD

                              VDD                                                                                                

               

         

                                                  Y                                        
A B

Figure 68: Two possible schematics, the stick diagrams and a layout of a parallel connection of two pMOS transistors.
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