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Designing Ultra-High Throughput FIR Filters with no Multiplier on NI FPGA Platforms
Publish Date: Aug 23, 2013
Overview
Filtering operations, or more generally speaking, inner products, are the core operations existing in digital signal processing. Almost every digital signal processing application involves several filters,
a great amount of which are Finite Impulse Response (FIR) filters. Their stability and linear phase properties make FIR filters very popular. Moreover, the inherent parallelism of FPGA chips makes
FPGAs more suitable for high-throughput applications. The limited number of multipliers on FPGAs can be an issue, because parallelizing the FIR filter implementation in order to meet throughput
requirements requires many multipliers. This article focuses on how to implement an ultra-high throughput FIR filter without using multipliers to address this problem using NI FPGA platforms.
Table of Contents
What Is Distributed Arithmetic?
Implementing a DA FIR Filter on NI FPGA Platforms
Conclusion
1. What Is Distributed Arithmetic?
The traditional ways to implement an FIR filter all rely on the Multiply-Accumulate (MAC) structure. Although the MAC structure is intuitive and easy to implement, the cycle count when processing
one sample is proportional to the tap count. You have to use multiple multipliers to parallelize the calculation in order to achieve higher throughput, but multipliers are a rather limited resource on
FPGAs. The following equation describes the throughput of MAC-based FIR filters.
The Distributed Arithmetic (DA) structure is a totally different method to implement FIR filters on an FPGA. The DA structure relies on Look-Up-Tables (LUT), shift registers, and scaling accumulators
to implement FIR filters. The DA structure does not need any multiplier. Figure 1 shows the basic diagram of the DA structure:
Figure 1. Basic Diagram of the DA Structure
You can see from the diagram that the input signal shifts into the filter bit by bit. The cycle count when processing one sample is proportional to the length of the input word. The following equation
calculates the throughput of a DA FIR filter:
To improve the throughput, you can duplicate the LUT so that several bits of input signal can shift within one cycle. Besides, because there is no multiplier in a DA FIR filter, the compiling rate can be
much higher than in the case of a MAC-based FIR filter. However, the implementation of DA FIR filters may need more logic resources.
Table 1 shows a performance and resources benchmark for a MAC-based FIR filter and a DA FIR filter, with a typical 40-tap FIR (16bits input, 24bits output, and 16bits coefficients) on the FPGA
target of the NI cRIO-9104.

FIR Implementation Compiling Rate (MHz) Maximum Throughput (MS/s) Logic Resources (Slices)
Single MAC traditional FIR 80 2 534
4-MAC traditional FIR 80 8 631
4-bit per cycle DA 120 30 1666
8-bit per cycle DA 120 60 2767
Table 1. Performance Benchmark Comparison between MAC-Based and DA-Based FIR Filters
In conclusion, DA is a good choice to implement ultra-high throughput FIR filter on an FPGA, which has enough logic resources and a limited number of multipliers.
2. Implementing a DA FIR Filter on NI FPGA Platforms
Building a DA FIR filter on an FPGA with VHDL requires substantial work. Using the LabVIEW Digital Filter Design Toolkit, you can implement a DA FIR filter for different configurations more easily.
Follow the instructions to implement an ultra-high throughput DA FIR filter on NI FPGA platforms.
Designing a Fixed-Point FIR Filter and Saving It to a File
In this step, you design a fixed-point FIR filter and save it to a file using the Digital Filter Design Toolkit. Figure 2 shows the common process to design a fixed-point FIR filter: design, quantize, model,
and then save the filter in a file.
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Figure 2. Design a Fixed-Point FIR Filter and Save it in a File
Table 2 displays the configuration of the filter.
Filter Order Filter Structure Coefficients Word Length Input Type Output Word Length
52 FIR Symmetric 16 I12.1 24
Table 2. Configuration of the Test Filter
Starting the IP Generator for a DA FIR Filter
The IP Generator is an interactive way for users to generate an FPGA IP under a specific FPGA target. You can start the IP Generator in the pop-up menu of an FPGA target, select a specific IP, set
the configurations, and generate the selected IP under the FPGA target. With the LabVIEW 2009 FPGA Module and the LabVIEW 2009 Digital Filter Design Toolkit, you also can generate an FIR
filter by using the dialog box, as shown in Figure 3. Start IP Generator
Figure 3. Start IP Generator for a Single-Rate Filter.
Complete the following steps to use the dialog box. Start IP Generator
Create a LabVIEW project.
Create an FPGA target under My Computer and save the project.
Right-click the FPGA target you create and select . The dialog box appears and displays all the available IPs. Start IP Generator Start IP Generator
Because the saved filer is a single-rate FIR filter, select and click the button for further configurations. Single-Rate Filter OK
Configurations for a DA FIR Filter
Use the Generate LabVIEW FPGA Code for Single-Rate Filter dialog box to configure the DA FIR filter, as shown in Figure 4.
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Figure 4. Configuration Dialog Box for a Single-Rate Filter
Use the option to load the saved filter file. You can configure the input and output data type, the number of channels, and the expected throughput via the dialog box. The dialog Filter file to load
box lists all available implementation methods for the loaded filter. You can choose the DA or MAC method for single-rate FIR filters. For both methods, there is a list of throughput options.
Cycles/sample indicates the minimum input intervals between two adjacent inputs. So the smaller the cycles/sample is, the higher the throughput is. Figure 5 points out that for the same single-rate
FIR filter, a DA implementation can provide a much higher throughput than a MAC implementation. However, the DA FIR filter costs more resources for a higher throughput.
Figure 5. Throughput Comparison for DA and MAC Implementations
Select the throughput you expect, for example , and click the button. The filters block diagram generates under the FPGA target. There is a virtual folder that contains a VI and 4 cycles/sample OK
two FIFOs under the . The VI is the generated filter and the FIFOs are the data interfaces for both the input and the output. Figure 6 shows you the block diagram of the generated filter FPGA target
and the project explorer displaying the virtual folder and its components.
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Figure 6. Generated DA FIR Filter and the Project Explorer
Improving the Filter Throughput
It is important to note that the unit of the selected throughput in the IP Generator is cycle/sample. The following equation calculates the actual throughput in MSample/second (MS/s):
The default FPGA clock rate for a DA FIR filter is 40 MHz and the selection is 4 cycles/sample in the IP generator. Therefore, the actual throughput of the generated filter is 10 MS/s. However, for
most common configurations, a DA FIR filter can run at 120 MHz on a Virtex II target and at 200 MHz on a Virtex 5 target.
The (SCTL) is a special use of the LabVIEW Timed Loop structure. In this section, increasing the FPGA clock of the SCTL further improves the DA FIR filter throughput. Single-Cycle Timed Loop
When you create an FPGA target, there are only some default clocks on the target. You can based on the default clocks. create a 120 MHz derived clock
You can double-click the of the SCTL in the filter VI and set the clock as the loop clock. Thus, the DA FIR filter throughput increases three times to 30 MS/s, as shown in Figure input node 120MHz
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Figure 7. Set the Clock of the SCTL in the Filter VI to 120 MHz
3. Conclusion
This article explains how to use the Digital Filter Design Toolkit to implement a DA FIR filter on NI FPGA platforms. The IP generator in the LabVIEW FPGA Module can help configure and generate
the LabVIEW FPGA code for the DA FIR filter, which needs no multiplier to implement a high-throughput FIR filter.
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