Advanced Digital Hardware Design

Function Generator using VHDL

Sailesh Kumar G
Electronics and Communication Engineering
AAA0188
sailesh-ece15@snu.edu.in









Declaration


Abstract
A function generator is a useful machine which is used in electronics and
communication, mechanics and various fields. It allows one to generate a range
of electrical signals and waveforms for testing and diagnostic purposes. In this
project I designed a function generator which is capable of synthesising various
waveforms such as sine, square, saw tooth or ramp and triangular waves. These
waveforms can be of low frequency or high frequency depending upon the user
preference.


















Description
Here the Lookup Table Method is used to create all the waveforms. This
method is done by, first, generating all the required values of the particular
waveform for n samples and store it in a memory. In this whole project I have
taken the fundamental time period of each waveform to be 2*pi. This method
gives very less error and therefore the accuracy in the values of the wave
function in a particular angle will be higher.
I have also included the input option of using whether a low frequency
waveform or a high frequency waveform. This module gives the data output of
integer values of the wave from the look up table. For this purpose, I have
declared an array of size 50 byte, which stores the value of each waveform at
various angles. The more values that we use in the code from the table, the more
accurate is the measurement of the waves. But if we just keep on increase the
values more accuracy, then the more bits gets used. So the memory requirement
will be more and results in the costs.
Here the 50 byte array is used for storing the values from the look up
table; this automatically results in a low frequency waveform. Therefore another
10 byte array is initialised for generating the same waveform but in higher
frequency. This is done by the same Look up table method but taking the
appropriate values for a high frequency waveform.
This program can be further synthesised and interfaced in a Field
Programmable Gate Array (FPGA) board using a Digital to Analog Convertor
(DAC), by connecting the output of DAC to an oscilloscope.
This can be well explained by seeing the following waveforms generated
in MATLAB. The same values are used in the program for generating the
waves. This program is more understandable and also very less chance of
getting an error since the values is directly taken from the look up table which is
generated by MATLAB.
The left column waveforms are a low frequency waveform and hence the values
obtained are mare whereas in the right column there are high frequency
waveforms and so the values are less.


SAWTOOTH:

TRIANGULAR:

SQUARE:

SINE:

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity waves is
port (clk :in std_logic;
wavegen :in std_logic_vector(1 downto 0);
freq: in std_logic;
output : out integer range -128 to 127);
end waves;

architecture signals of waves is
signal i : integer range 0 to 50:=0;
signal j : integer range 0 to 10:=0;
type memory_type1 is array (0 to 49) of integer range -128 to 127;
type memory_type2 is array (0 to 9) of integer range -128 to 127;

signal sine : memory_type1
:=(0,10,19,29,38,46,53,60,66,71,74,77,78,78,77,74,71,66,60,53,46,38,29,19,10,0,
-10,-19,-29,-38,-46,-53,-60,-66,-71,-74,-77,-78,-78,-77,-74,-71,-66,-60,-53,-46,-38,-29,-19,-
10);

signal saw : memory_type1 :=(-78,-75,-72,-69,-66,-63,-59,-56,-53,-50,-47,-44,-41,-38,-34,-
31,-28,-25,-22,-19,-16,
-12,-9,-6,-3,0,3,6,9,12,16,19,22,25,28,31,34,38,41,44,47,50,53,56,59,63,66,69,72,75);

signal square : memory_type1
:=(78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,
-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-78,-
78,-78);

signal triangle : memory_type1 :=(-78,-72,-66,-59,-53,-47,-41,-34,-28,-22,-16,-9,-
3,3,9,16,22,28,34,41,47,53,59,
66,72,78,72,66,59,53,47,41,34,28,22,16,9,3,-3,-9,-16,-22,-28,-34,-41,-47,-53,-59,-66,-72);

signal sine_high : memory_type2 :=(0,46,74,74,46,0,-46,-74,-74,-46);

signal saw_high : memory_type2 :=(-78,-63,-47,-31,-16,0,16,31,47,63);

signal square_high : memory_type2 :=(78,78,78,78,78,-78,-78,-78,-78,-78);

signal triangle_high : memory_type2 :=(-78,-47,-16,16,47,78,47,16,-16,-47);

begin

process(clk,wavegen)

begin

if(rising_edge(clk)) then
case wavegen is

when "00" =>
if(freq = '0') then
output <= sine(i);
i <= i+ 1;
if(i = 49) then
i <= 0;
end if;
else
output <= sine_high(j);
j <= j+ 1;
if(i = 9) then
j <= 0;
end if;
end if;

when "01" =>
if(freq = '0') then
output <= saw(i);
i <= i+ 1;
if(i = 49) then
i <= 0;
end if;
else
output <= saw_high(j);
j <= j+ 1;
if(i = 9) then
j <= 0;
end if;
end if;

when "10" =>
if(freq = '0') then
output <= square(i);
i <= i+ 1;
if(i = 49) then
i <= 0;
end if;
else
output <= square_high(j);
j <= j+ 1;
if(i = 9) then
j <= 0;
end if;
end if;

when "11" =>
if(freq = '0') then
output <= triangle(i);
i <= i+ 1;
if(i = 49) then
i <= 0;
end if;
else
output <= triangle_high(j);
j <= j+ 1;
if(i = 9) then
j <= 0;
end if;
end if;

when others => null;
end case;
end if;

end process;
end signals;
Waveforms

SINE:


SAW TOOTH:


SQUARE:


TRIANGULAR:

All the output waveforms which include both low frequency and high frequency
waves both are generated and have been displayed.

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY wavesfinale IS
END wavesfinale;

ARCHITECTURE behavior OF wavesfinale IS

COMPONENT waves
PORT(
clk : IN std_logic;
wavegen : IN std_logic_vector(1 downto 0);
freq : IN std_logic;
output : out integer range -128 to 127
);
END COMPONENT;

signal clk : std_logic := '0';
signal wavegen : std_logic_vector(1 downto 0) := (others => '0');
signal freq : std_logic := '0';


signal output : integer range -128 to 127;


constant clk_period : time := 10 ns;
BEGIN

uut: waves PORT MAP (
clk => clk,
wavegen => wavegen,
freq => freq,
output => output
);


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

stim_proc: process
begin

wait for 100 ns;

wait for clk_period*10;

freq<='0'; wavegen<="00"; wait for 20 ns;
freq<='1'; wavegen<="00"; wait for 10 ns;
freq<='0'; wavegen<="01"; wait for 20 ns;
freq<='1'; wavegen<="01"; wait for 10 ns;
freq<='0'; wavegen<="10"; wait for 20 ns;
freq<='1'; wavegen<="10"; wait for 10 ns;
freq<='0'; wavegen<="11"; wait for 20 ns;
freq<='1'; wavegen<="11"; wait for 10 ns;

wait;
end process;

END;

The corresponding waveform is shown in different pictures so as to understand the values at
each point in the wave.








Synthesis





Reference
https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_w
ave_generator/
http://electronicsinourhands.blogspot.in/2012/12/hi-everyone-its-long-
time-that-i-have.html
http://vhdlguru.blogspot.in/2010/03/simple-sine-wave-generator-in-
vhdl.html