ELEC 483-Microwave & RF Circuits & Systems

FET Matching Networs

We will look at how we can design matching networks to design a high gain amplifier using
simultaneous conjugate matching.
You make sure that you keep track of the work you do in your design notebooks. Much of the work we
are doing will be helpful for your project.
Part I: Simple matching network
In this part, you will create a simple matching network to match the input of your transistor, at your
design frequency, to a 5 ohm source.
!. "pen the #$% project elec483_2006_prj, and then open the schematic
SP_NF_GainMatchK.dsn. %imulate your transistor, ensuring that the %&#'& and %&"(
frequencies include your design frequency. In the data display window, select the S
!arameters" #rou$ %e&ay page, and put a marker on the %!! plot. )ote the *alue of %!! for
your transistor. &his is also +amma,in for your transistor, when the output is terminated in a 5
"hm load.
-. .sing the *alue of %!! for your transistor, add a two element /0section matching network
between the input of the transistor and the decoupling capacitor 1- so that the input reflection
coefficient 2i.e. %!!3 is as close to 4ero as possible at your design frequency. &hink about the
effect of your matching network on the bias conditions of the 56&. #dd a rectangular plot to the
data display window, and plot %!! in d7. You should be able to get %!! below 0- d7 at your
design frequency.
8. Make note of the matching network that you designed in your design log. &his may be helpful
to you later on. #lso sketch the matching network below, and show the %!! below.
#nswers9
ELEC 483-Microwave & RF Circuits & Systems
FET Matching Networs
Part II: Gain and Matching Networks
In this simulation, you will design /1 matching networks at the input and output of the 56& at your
design frequency.
!. In the pre*ious session, we found that the transistor is potentially unstable at certain frequencies, and
so we stabili4ed the transistor. %ince with this resistor the transistor is unconditionally stable at your
frequency, we will design source and load matching networks to produce simultaneous conjugate
match at the input and output. .sing the procedure from last class, which used the NF, Gain, Stab.
Fact., Matchin page, 2or by looking up the results from the last class in your design notebook:3
determine the source and load impedances that result in a simultaneous conjugate match.
-. 1reate a matching network at the input that produces the necessary source impdance 2or
+amma,M%3 needed by your transistor for a simultaneous conjugate match. "ne way to do this is to
disconnect &6'M! from the transistor, and mo*e your &6'M- element beside it, lea*ing space
between the two for a matching network. &hen add the appropriate elements, and check that the %--
measured gi*es the *alue you want for +amma,M%.
8. 'epeat this procedure to design the output matching network that produces +amma,M/.
;. Insert the matching networks at the input and output of the 56&. 6nsure that you include the e<tra
stabili4ing resistor. 'econnect the &6'M! and &6'M- elements, and simulate. 6<amine your %0
parameters on the S !arameters" #rou$ %e&ay page. If designed perfectly the first time, you should
see %!! and %-- *ery close to the center of the %mith chart at your design frequency, and
equi*alently dipping quite low in magnitude on a d7 scale. %-! should reach a ma<imum at your
design frequency. If it does not, recheck your matching networks.
5. %ketch your matching networks here, and show the plots of your final %0parameters 2%!! and %-- on
a %mith chart, and the magnitudes of %!!, %--, %!-, and %-! in d7 on a rectangular plot3.
ELEC 483-Microwave & RF Circuits & Systems
FET Matching Networs
#nswers9