UNIT 6 : INTEL 8051 MICRCONTROLLER

Distinguish between Microrocessor !n" Microcontro##er

$%No Microrocessor Microcontro##er
1
2 A microprocessor is a general
purpose device which is called a
CPU
A microcontroller is a dedicated chip which
is also called single chip computer.
3 A microprocessor do not contain
onchip I/OPorts, Timers, emories
etc..
A microcontroller includes !A, !O,
serial and parallel inter"ace, timers,
interrupt circuitr# $in addition to CPU% in a
single chip.
& icroprocessors are most
commonl# used as the CPU in
microcomputer s#stems
icrocontrollers are used in small,
minimum component designs per"orming
control&oriented applications.
' icroprocessor instructions are
mainl# ni((le or (#te addressa(le
icrocontroller instructions are (oth (it
addressa(le as well as (#te addressa(le.
) icroprocessor (ased s#stem
design is comple* and e*pensive
icrocontroller (ased s#stem design is
rather simple and cost e""ective
' The Instruction set o"
microprocessor is comple* with
The instruction set o" a icrocontroller is
ver# simple with less num(er o"
+
large num(er o" instructions. instructions. ,or, e*- PIC microcontrollers
have onl# 3' instructions%
. /g- .0.',.0.) /g- .0'+,A1!
T()E$ O* MICROCONTROLLER$:
icrocontrollers can (e classi"ied on the (asis o" internal (us width, architecture, memor# and
instruction set as 2&(it,.&(it,+)&(it and 32&(it micrcontrollers.
+% &+bit Microcontro##ers- These 2&(it microcontrollers are small si3e, minimum pin count
and low cost controllers which are widel# used "or 4/5 6 4C5 displa# drivers
,porta(le (atter# chargers etc.. Their power consumption is also low.
2% 8+bit Microcontro##ers: These are the most popular and widel# used
microcontrollers .A(out ''7 o" all CPUs sold in the world are .&(it microcontrollers
onl#. The well 8nown .&(it microcontroller is .0'+ which was designed (# Intel in the
#ear +9.0 "or the use in em(edded s#stems. A1! icrocontrollers.
3% 16+bit Microcontro##ers : :hen the microcontroller per"orms +)&(it arithmetic and
logical operations at an instruction, the microcontroller is said to (e a +)&(it
microcontroller. The# "ind applications in dis8 drivers, modems,printers,scanners and
servomotor control. /*amples o" +)&(it microcontrollers are Intel .09) "amil#
2% ,-+.it Microcontro##ers: These microcontrollers used in applications li8e Automative
control, Communication networ8s,!o(otics,Cell phones ,;P!< 6 P5As etc. /*amples
o" +)&(it microcontrollers are A! =.
INTEL 8051 MICRCONTROLLER :
2
The .0'+ microcontroller is a ver# popular .&(it microcontroller introduced (# Intel in
the #ear +9.+.The .0'+ is (ased on an .&(it CI<C core with >arvard architecture.
<alient "eatures :
The salient "eatures o" .0'+ icrocontroller are
i. 2 ?@ on chip program memor# $!O or /P!O%%.
ii. +2. (#tes on chip data memor#$!A%.
iii. .&(it data (us
iv. +)&(it address (us
v. 32 general purpose registers each o" . (its
vi. Two &+) (it timers T
0
and T
+
vii. ,ive Interrupts $3 internal and 2 e*ternal%.
i*. ,our Parallel ports each o" .&(its $PO!T0, PO!T+,PO!T2,PO!T3% with a total o" 32 I/O
lines.
*. One +)&(it program counter and One +)&(it 5PT! $ data pointer%
*i. One .&(it stac8 pointer
*ii. One icrosecond instruction c#cle with +2 >3 Cr#stal.
*iii. One "ull duple* serial communication port.
/rchitecture 0 b#oc1 "i!gr!2 o3 8051 2icrocontro##er:
The architecture o" the .0'+ microcontroller can (e understood "rom the (loc8 diagram.
The (loc8 diagram o" .0'+ microcontroller is shown in ,ig 3. (elow+.It consists o" an .&(it
A4U, one .&(it P<:$Program <tatus !egister%, A and @ registers , one +)&(it Program counter ,
one +)&(it 5ata pointer register$5PT!%,+2. (#tes o" !A and 28@ o" !O and "our parallel
I/O ports each o" .&(it width.
3
*ig%,% .#oc1 Di!gr!2 o3 8051 Microcontro##er
.0'+ has .&(it A4U which can per"orm all the .&(it arithmetic and logical operations in one
machine c#cle. The A4U is associated with two registers A 6 @
/ !n" . Registers - The A and @ registers are special "unction registers which hold the results
o" man# arithmetic and logical operations o" .0'+.The A register is also called the /ccu2u#!tor
and as itAs name suggests, is used as a general register to accumulate the results o" a large
num(er o" instructions. @# de"ault it is used "or all mathematical operations and also data
trans"er operations (etween CPU and an# e*ternal memor#.
The @ register is mainl# used "or multiplication and division operations along with A register.
U4 A@ - 5I1 A@.
It has no other "unction other than as a location where data ma# (e stored.
The R registers- The B!B registers are a set o" eight registers that are named !0, !+, etc. up to
2
and including !=. These registers are used as au*illar# registers in man# operations. The B!B
registers are also used to temporaril# store values.
)rogr!2 Counter4)C5 : .0'+ has a +)&(it program counter .The program counter alwa#s points
to the address o" the ne*t instruction to (e e*ecuted. A"ter e*ecution o" one instruction the
program counter is incremented to point to the address o" the ne*t instruction to (e e*ecuted.It is
the contents o" the PC that are placed on the address (us to "ind and "etch the desired
instruction.<ince the PC is +)&(it width ,.0'+ can access program addresses "rom 0000> to
,,,,> ,a total o" )8@ o" code.
$t!c1 )ointer Register 4$)5 : It is an .&(it register which stores the address o" the stac8 top. i.e
the <tac8 Pointer is used to indicate where the ne*t value to (e removed "rom the stac8 should
(e ta8en "rom. :hen a value is pushed onto the stac8, the .0'+ "irst increments the value o" <P
and then stores the value at the resulting memor# location. <imilarl# when a value is popped o""
the stac8, the .0'+ returns the value "rom the memor# location indicated (# <P, and then
decrements the value o" <P. <ince the <P is onl# .&(it wide it is incremented or decremented (#
two . <P is modi"ied directl# (# the .0'+ (# si* instructions- PU<>, POP, ACA44, 4CA44,
!/T, and !/TI. It is also used intrinsicall# whenever an interrupt is triggered.
$T/C6 in 8051 Microcontro##er: The stac8 is a part o" !A used (# the CPU to store
in"ormation temporaril#. This in"ormation ma# (e either data or an address .The CPU needs this
storage area as there are onl# limited num(er o" registers. The register used to access the stac8 is
called the <tac8 pointer which is an .&(it register..<o,it can ta8e values o" 00 to ,, >.:hen the
.0'+ is powered up ,the <P register contains the value 0=.i.e the !A location value 0. is the
"irst location (eing used "or the stac8 (# the .0'+ controller
There are two important instructions to handle this stac8.One is the PU<> and the Other
is the POP. The loading o" data "rom CPU registers to the stac8 is done (# PU<> and the
loading o" the contents o" the stac8 (ac8 into aCPU register is done (# POP.
/C - O1 !) ,D3' >
O1 !+ ,D2+ >
PU<> )
PU<> +
'
In the a(ove instructions the contents o" the !egisters !) and !+ are moved to stac8 and
the# occup# the 0. and 09 locations o" the stac8.Eow the contents o" the <P are incremented (#
two and it is 0A
<imilarl# POP 3 instruction pops the contents o" stac8 into !3 register.Eow the contents o" the
<P is decremented (# +
In .0'+ the !A locations 0. to +, $22 (#tes% can (e used "or the <tac8.In an# program i" we
need more than 22 (#tes o" stac8 ,we can change the <P point to !A locations 30&=, >.this
can (e done with the instruction O1 <P,D CC.
D!t! )ointer Register4D)TR5 : It is a +)&(it register which is the onl# user&accessi(le.
5PT!, as the name suggests, is used to point to data. It is used (# a num(er o" commands which
allow the .0'+ to access e*ternal memor#. :hen the .0'+ accesses e*ternal memor# it will
access e*ternal memor# at the address indicated (# 5PT!. This 5PT! can also (e used as two
.&registers 5P> and 5P4.
)rogr!2 $t!tus Register 4)$75 : The .0'+ has a .&(it P<: register which is also8nown as
,lag register.In the .&(it register onl# )&(its are used (# .0'+.The two unused (its are user
de"ina(le (its.In the )&(its "our o" them are conditional "lags .The# are Carr# FCG,Au*iliar#
Carr#&AC, Parit#&P,and Over"low&O1 .These "lag (its indicate some conditions that resulted
a"ter an instruction was e*ecuted.
The (its P<:3 and P<:2 are denoted as !<0 and !<+ and these (its are used th select the
(an8 registers o" the !A location. The meaning o" various (its o" P<: register is shown
(elow.
CG P<:.= Carr# ,lag
AC P<:.) Au*iliar# Carr# ,lag
,O P<:.' ,lag 0 availa(le "or general purpose .
!<+ P<:.2 !egister @an8 select (it +
)
!<0 P<:.3 !egister (an8 select (it 0
O1 P<:.2 Over"low "lag
&&& P<:.+ User di"ina(le "lag
P P<:.0 Parit# "lag .set/cleared (# hardware.
The selection o" the register @an8s and their addresses are given (elow.
R$1 R$0 Register .!n1 /""ress
0 0 0 00>&0=>
0 + + 0.>&0,>
+ 0 2 +0>&+=>
+ + 3 +.>&+,>
Me2or8 org!ni9!tion in 8051
The .0'+ microcontroller has +2. (#tes o" Internal !A and 28@ o" on chip !O .
The !A is also 8nown as 5ata memor# and the !O is 8nown as program memor#. The
program memor# is also 8nown as Code memor# .
This Code memor# holds the actual .0'+ program that is to (e e*ecuted. In .0'+ this memor#
is limited to )2? .Code memor# ma# (e "ound on&chip, as !O or /P!O. It ma# also (e
stored completel# o""&chip in an e*ternal !O or, more commonl#, an e*ternal /P!O. The
.0'+ has onl# +2. (#tes o" Internal !A (ut it supports )28@ o" e*ternal !A. As the name
suggests, e*ternal !A is an# random access memor# which is o""&chip. <ince the memor# is
o""&chip it is not as "le*i(le interms o" accessing, and is also slower. ,or e*ample, to increment
an Internal !A location (# +,it reHuires onl# + instruction and + instruction c#cle (ut to
increment a +&(#te value stored in /*ternal !A reHuires 2 instructions and = instruction c#cles.
<o, here the e*ternal memor# is = times slower.
=
15 Intern!# R/M O* 8051 :
This Internal !A is "ound on&chip on the .0'+ .<o it is the "astest !A availa(le, and it is also
the most "le*i(le in terms o" reading, writing, and modi"#ing itAs contents. Internal !A is
volatile, so when the .0'+ is reset this memor# is cleared. The +2. (#tes o" internal !A is
organi3ed as (elow.
$i% ,our register (an8s $@an80,@an8+, @an82 and @an83% each o" .&(its $total 32 (#tes%. The
de"ault (an8 register is @an80. The remaining @an8s are selected with the help o" !<0 and
!<+ (its o" P<: !egister.
$ii% +) (#tes o" (it addressa(le area and
$iii% .0 (#tes o" general purpose area $<cratch pad memor#% as shown in the diagram (elow.
This area is also utili3ed (# the microcontroller as a storage area "or the operating stac8.
.
The 32 (#tes o" !A "rom address 00 > to +,> are used as wor8ing registers organi3ed as "our
(an8s o" eight registers each.The registers are named as !0&!= ./ach register can (e addressed
(# its name or (# its !A address.
,or /C - O1 A, != or O1 !=,D0'>
2% Intern!# ROM 4On :chi ROM5: The .0'+ microcontroller has 28@ o" on chip !O
(ut it can (e e*tended up to )28@.This !O is also called program memor# or code
memor#. The CO5/ segment is accessed using the program counter $PC% "or opcode
"etches and (# 5PT! "or data. The e*ternal !O is accessed when the /A$active low%
pin is connected to ground or the contents o" program counter e*ceeds 0,,,>.:hen the
Internal !O address is e*ceeded the .0'+ automaticall# "etches the code (#tes "rom the
e*ternal program memor#.
9
$)ECI/L *UNCTION RE;I$TER$ 4$*Rs5 :
In .0'+ microcontroller there certain registers which uses the !A addresses "rom .0h to ,,h
and the# are meant "or certain speci"ic operations .These registers are called <pecial "unction
registers $<,!s%.<ome o" these registers are (it addressa(le also.
The list o" <,!s and their "unctional names are given (elow. In these <,!s some o" them are
related to I/O ports $P0,P+,P2 and P3% and some o" them are meant "or control operations
$TCOE,<COE, PCOE..% and remaining are the au*illar# <,!s, in the sense that the# donIt
directl# con"igure the .0'+.
$%No $82bo# N!2e o3 $*R /""ress 4<e=5
+ ACCJ Accumulator 0E0
2 @J @&!egister 0*0
3 P<:J Program <tatus word register 0DO
2 <P <tac8 Pointer !egister 81
'
5PT!
5P4 5ata pointer low (#te 8-
5P> 5ata pointer high (#te 8,
) P0J Port 0 80
P+J Port + >0
. P2J Port 2 0/
9 P3J Port 3 0.
+0 IPJ Interrupt Priorit# control 0.8
++ I/J Interrupt /na(le control 0/8
+2 TO5 Tmier mode register 8>
+3 TCOEJ Timer control register 88
+2 T>0 Timer 0 >igher (#te 8C
+' T40 Timer 0 4ower (#te 8/
+0
+) T>+ Timer +>igher (#te 8D
+= T4+ Timer + lower (#te 8.
+. <COEJ <erial control register >8
+9 <@U, <erial (u""er register >>
20 PCOE Power control register 8'
The J in"ic!tes the bit !""ress!b#e $*Rs
T!b#e:$*Rs o3 8051 Microcontro##er
)/R/LLEL I ?O )ORT$ :
The .0'+ microcontroller has "our parallel I/O ports , each o" .&(its .<o, it provides the user 32
I/O lines "or connecting the microcontroller to the peripherals. The "our ports are P0 $Port 0%,
P+$Port+% ,P2$Port 2% and P3 $Port3%. Upon reset all the ports are output ports. In order to ma8e
them input, all the ports must (e set i.e a high (it must (e sent to all the port pins. This is
normall# done (# the instruction K</T@L.
/*- O1 A,D0,,> M A N ,,
O1 P0,A M ma8e P0 an input port
)ORT 0:
Port 0 is an .&(it I/O port with dual purpose. I" e*ternal memor# is used, these port pins are used
"or the lower address (#te address/data $A5
0
&A5
=
%, otherwise all (its o" the port are either input
or output.
Port 0 can also (e used as address/data (us$A50&A5=%, allowing it to (e used "or (oth address
and data. :hen connecting the .0'+ to an e*ternal memor#, port 0 provides (oth address and
data.
The .0'+ multiple*es address and data through port 0 to save the pins. A4/ indicates whether
P0 has address or data. :hen A4/ N 0, it provides data 50&5=, and when A4/ N+ it provides
address and data.
)ort 1: Port + occupies a total o" . pins $pins + through .%. It has no dual application and acts
onl# as input or output port. In contrast to port 0, this port does not need an# pull&up resistors
++
since pull&up resistors connected internall#. Upon reset, Port + is con"igured as an output port.
To con"igure it as an input port , port (its must (e set i.e a high (it must (e sent to all the port
pins. This is normall# done (# the instruction K</T@L. ,or /* -
O1 A, D0,,> M AN,, >/C
O1 P+,A M ma8e P+ an input port (# writing +As to all o" its pins
)ort - : Port 2 is also an eight (it parallel port. $pins 2+& 2.%. It can (e used as input or output
port. As this port is provided with internal pull&up resistors it does not need an# e*ternal pull&up
resistors. Upon reset, Port 2 is con"igured as an output port.
Port2 lines are also associated with the higher order address lines A.&A+'. In s#stems (ased on
the .='+, .9'+, and 5<'000, Port2 is used as simple I/O port.. @ut, in .03+&(ased s#stems, port
2 is used along with P0 to provide the +)&(it address "or the e*ternal memor#. <ince an .03+ is
capa(le o" accessing )2? (#tes o" e*ternal memor#, it needs a path "or the +) (its o" the address.
:hile P0 provides the lower . (its via A0&A=, it is the Oo( o" P2 to provide (its A.&A+' o" the
address. In other words, when .03+ is connected to e*ternal memor#, Port 2 is used "or the upper
. (its o" the +) (it address, and it cannot (e used "or I/O operations.
)ORT , - Port3 is also an .&(it parallel port with dual "unction.$ pins +0 to +=%. The port pins
can (e used "or I/O operations as well as "or control operations. The details o" these
additional operations are given (elow in the ta(le. Port 3 also do not need an# e*ternal pull&up
resistors as the# are provided internall# similar to the case o" Port2 6 Port +. Upon reset port 3
is con"igured as an output port . I" the port is to (e used as input port, all the port (its must (e
made high (# sending ,, to the port. ,or e*,
P3.0 and P3.+ are used "or the !*5 $!eceive 5ata% and T*5 $Transmit 5ata% serial
communications signals.
@its P3.2 and P3.3 are meant "or e*ternal interrupts.
@its P3.2 and P3.' are used "or Timers 0 and + and P3.) and P3.= are used to provide the write
and read signals o" e*ternal memories connected in .0'+ (ased s#stems
$%No )ort , bit )in No *unction
+ P3.0 +0 !*5
+2
2 P3.+ ++ T*5
3 P3.2 +2
2 P3.3 +3
' P3.2 +2 T0
) P3.' +' T+
= P3.) +)
. P3.= +=
T!b#e: )ORT , !#tern!te 3unctions
)IN Di!gr!2 o3 8051 Microcontro##er :
The .0'+ microcontroller is availa(le as a 20 pin 5IP chip and it wor8s at P' volts 5C.
+3
Among the 20 pins , a total o" 32 pins are allotted "or the "our parallel ports P0,P+,P2 and P3 i.e
each port occupies .&pins .The remaining pins are 1CC, ;E5, CTA4+, CTA42, !<T, /A
,P</E.
+2
@T/L1A@T/L-- These two pins are connected to Quart3 cr#stal oscillator which runs the on&
chip oscillator. The Huart3 cr#stal oscillator is connected to the two pins along with a capacitor o"
30p, as shown in the circuit. I" we use a source other than the cr#stal oscillator, it will (e
connected to CTA4+ and CTA42 is le"t unconnected.
R$T- The !/</T pin is an input pin and it is an active high pin. :hen a high pulse is applied to
this pin the microcontroller will reset and terminate all activities. Upon reset all the registers
e*cept PC will reset to 0000 1alue and PC register will reset to 000= value.
4E=tern!# /ccess5: This pin is an active low pin. This pin is connected to ground when
microcontroller is accessing the program code stored in the e*ternal memor# and connected to
1cc when it is accessing the program code in the on chip memor#. This pin should not (e le"t
unconnected.
4)rogr!2 $tore En!b#e5 : This is an output pin which is active low. :hen the
microcontroller is accessing the program code stored in the e*ternal !O ,this pin is connected
to the O/ $Output /na(le% pin o" the !O.
/LE 4/""ress #!tch en!b#e5: This is an output pin, which is active high% :hen connected to
e*ternal memor# , port 0 provides (oth address and data i.e address and data are multiple*ed
+'
through port 0 .This A4/ pin will demultiple* the address and data (us .:hen the pin is >igh ,
the A5 (us will act as address (us otherwise the A5 (us will act as 5ata (us.
)0%0+ )0%'4/D0+/D'5 : The port 0 pins multiple*ed with Address/data pins .I" the
microcontroller is accessing e*ternal memor# these pins will act as address/data pins otherwise
the# are used "or Port 0 pins.
)-%0+ )-%'4/8+/155 : The port2 pins are multiple*ed with the higher order address pins %:hen
the microcontroller is accessing e*ternal memor# these pins provide the higher order address
(#te otherwise the# act as Port 2 pins.
)1%0+ )1%' :These .&pins are dedicated "or Port+ to per"orm input or output port operations.
),%0+ ),%' :These .&pins are meant "or Port3 operations and also "or some control operations
li8e !ead,:rite,Timer0,Timer+ ,IET0,IET+ ,!*5 and T*5
/DDRE$$IN; MODE$ O* 8051 :
+)
The wa# in which the data operands are accessed (# di""erent instructions is 8nown as the
addressing modes. There are various methods o" denoting the data operands in the instruction.
The .0'+ microcontroller supports mainl# ' addressing modes. The# are
+.Immediate addressing mode
2.5irect Addressing mode
3.!egister addressing mode
2. !egister Indirect addressing mode
'.Inde*ed addressing mode
I22e"i!te !""ressing 2o"e : The addressing mode in which the data operand is a constant and
it is a part o" the instruction itsel" is 8nown as Immediate addressing mode. Eormall# the data
must (e preceded (# a D sign. This addressing mode can (e used to trans"er the data into an# o"
the registers including 5PT!.
/*- O1 A , D 2= > - The data $constant% 2= is moved to the accumulator register
A55 !+ ,D2' > - Add the constant 2' to the contents o" the accumulator
O1 5PT! ,D .22'> -ove the data .22' into the data pointer register.
O1 P+,D2+ >
Direct !""ressing 2o"e- The addressing mode in which the data operand is in the !A
location $00 &=,>% and the address o" the data operand is given in the instruction is 8nown as
5irect addressing mode. The direct addressing mode uses the lower +2. (#tes o" Internal !A
and the <,!s
O1 !+, 22> - ove the contents o" !A location 22 into !+ register
O1 29>,A - ove the contents o" the accumulator into the !A location 29.
A55 A, ')> - Add the contents o" the !A location ') to the accumulator
Register !""ressing 2o"e -The addressing mode in which the data operand to (e manipulated
lies in one o" the registers is 8nown as register addressing mode.
+=
O1 A,!0 - ove the contents o" the register !0 to the accumulator
A55 A,!) -Add the contents o" !) register to the accumulator
O1 P+, !2 - ove the contents o" the !2 register into port +
O1 !', !2 - This is invalid .The data trans"er (etween the registers is not allowed.
Register In"irect !""ressing 2o"e :The addressing mode in which a register is used as a
pointer to the data memor# (loc8 is 8nown as !egister indirect addressing mode.
O1 A,R !0 -ove the contents o" !A location whose address is in !0 into /
$accumulator%
O1 R !+ , @ - ove the contents o" @ into !A location whose address is held (# !+
:hen !0 and !+ are used as pointers, the# must (e preceded (# R sign
One o3 the !"B!nt!ges o3 register in"irect !""ressing 2o"e is th!t it 2!1es !ccessing the
"!t! 2ore "8n!2ic th!n st!tic !s in the c!se o3 "irect !""ressing 2o"e%
In"e=e" !""ressing 2o"e : This addressing mode is used in accessing the data elements o"
loo8up ta(le entries located in program !O space o" .0'+.
/* - O1C A,R AP5PT!
The +)&(it register 5PT! and register A are used to "orm the address o" the data element stored
in on&chip !O. >ere C denotes code .In this instruction the contents o" A are added to the
+)&(it 5PT! register to "orm the +)&(it address o" the data operand.
+.
+9