Encoders,Decoder

Demulti Demulti
Shr
rs,Multiplexers and
iplexers iplexers
Prepared By:
Shruti Khatri
ruti_0802@yahoo.co.in
Objec Objec
Decoders
Encoders Encoders
Multiplexers
DeMultiplexers
ctives ctives
Multiplexers
44
Multip Multip
A multiplexer has
N control inputs p
2
N
data inputs
1 output 1 output
A multiplexer routes (o
data input to the outpu data input to the outpu
The value of the
th d t i t th the data input tha
lexers lexers
or connects) the selected
ut ut.
control inputs determines
t i l t d
5
at is selected.
5
Multip Multip
Z = A I
Data
inputs
Z A .I
Control
input
lexers lexers
I
0
+ A I
1
6
I
0
+ A.I
1
6
Multip Multip
MSB L
Z = A.B'.I
0
+ A'.B.I
lexers lexers
A B F
0 0 I
0
0 1 I
1
1 0 I
2
1 1 I 1 1 I
3
LSB
7
I
1
+ A.B'.I
2
+ A.B.I
3
7
Multip Multip
MSB LS
Z = A.B'.C'.I
0
+ A'.B'.C.I
A.B'.C'.I
0
+ A.B'.C.I
1
lexers lexers
A B C F A B C F
0 0 0 I
0
0 0 1 I
1
0 1 0 I
2
0 1 1 I
3
1 0 0 I
4
1 0 1 I
5
1 1 0 I
6
1 1 1 I
7
SB
1 1 1 I
7
8
I
1
+ A'.B.C'.I
2
+ A'.B.C.I
3
+
+ A'.B.C'.I
2
+ A.B.C.I
3
8
Demultiiplexers
99
Demulti Demulti
A demultiplexer has de u t p e e as
N control inputs
1 data input 1 data input
2
N
outputs
A demultiplexer routes (o A demultiplexer routes (o
the selected output.
The value of the co The value of the co
that is selected.
A demultiplexer performs A demultiplexer performs
multiplexer.
iplexers iplexers
or connects) the data input to or connects) the data input to
ntrol inputs determines the output ntrol inputs determines the output
s the opposite function of a
10
s the opposite function of a
10
Demulti Demulti
O t
W
Out
0
In
I
W
X
Y
Out
1
Out
2
S
1
S
0
Z
Out
3
A B W
A B
A B W
0 0 I
0 1 0
1 0 0
1 1 0
iplexers iplexers
W A' B' I W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I
X Y Z X Y Z
0 0 0
I 0 0
11
0 I 0
0 0 I
11
Decooders
12 12
Deco Deco
n-to-2
n
.
n inputs
n to 2
Decode
Information is represented
Decoding - the conversion
m-bit output code with n <=
valid code word produces a p
Circuits that perform decod
A decoder is a minterm ge A decoder is a minterm ge
oder oder
n
.
.
.
2
n
outputs
er
by binary codes
n of an n-bit input code to an
= m <= 2
n
such that each
a unique output code q p
ding are called decoders
nerator nerator
Deco Deco
A decoder has
N inputs
2
N
outputs 2 outputs
A decoder selects one
decoding the binary va decoding the binary va
The decoder generate
th N i t i bl the N input variables.
Exactly one outp
combination of th
oders oders
e of 2
N
outputs by
alue on the N inputs alue on the N inputs.
es all of the minterms of
put will be active for each
14
he inputs.
What does active mean?
14
Deco Deco
B
I
0
Out
0
Out
1
O t
I
1
A
Out
2
Out
3
msb
A B W
Active-h
A B W
0 0 1
0 1 0
1 0 0
1 1 0
oders oders
W A' B'
W
X
Y
W = A'.B'
X = A.B'
Y
Z
Y = A'.B
Z = A.B
X Y Z
high outputs
X Y Z
0 0 0
1 0 0
15
0 1 0
0 0 1
15
Deco Deco
B
I
0
Out
0
Out
1
O t
msb
I
1
A
Out
2
Out
3
A B W
Active-l
A B W
0 0 0
0 1 1
1 0 1
1 1 1
oders oders
W (A' B')' W = (A'.B')'
X = (A.B')'
W
X
Y
Y = (A'.B)'
Z = (A.B)'
Y
Z
X Y Z
ow outputs
X Y Z
1 1 1
0 1 1
16
1 0 1
1 1 0
16
Deco Deco
msb
oders oders
17 17
Decoder w Decoder w
high-level
enable
B
I
0
I
1
A
enable
Enable
I
1
A
En
En A B
1 0 0 1 0 0
1 0 1
1 1 0
enabled
1 1 1
0 x x
disabled
with Enable with Enable
W
X
Y
Out
0
Out
1
O t
Y
Z
Out
2
Out
3
W X Y Z
1 0 0 0 1 0 0 0
0 1 0 0
0 0 1 0
18
0 0 0 1
0 0 0 0
18
Decoder w Decoder w
B
I
0
I
1
A
low-level
enable
Enable
I
1
A
En
En A B
0 0 0 0 0 0
0 0 1
0 1 0
enabled
0 1 1
1 x x
disabled
with Enable with Enable
W
X
Y
Out
0
Out
1
O t
Y
Z
Out
2
Out
3
W X Y Z
1 0 0 0 1 0 0 0
0 1 0 0
0 0 1 0
19
0 0 0 1
0 0 0 0
19
Decoder-Based
Circuits (E
X Y Z C S
S = m (1,2,4,7
C = m (3,5,6,
X Y Z C S
0 0 0 0 0
0 0 1 0 1
3 inputs and 8
3-to-8 decoder
0 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
Ah d Al lh
1 1 0 1 0
1 1 1 1 1
Ahmad Almulhe
d Combinational
Example)
7)
7)
possible minterms
can be used for implementing this circuit
KFUPM 2009 em, KFUPM 2009
3 to 8 D 3-to-8 D
3-to-8
D
0
D
1
D
2
D
3
D
A
0
A
Decoder
D
4
D
5
D
6
D
7
A
1
A
2
Ah d Al lh Ahmad Almulhe
Decoder Decoder
KFUPM 2009 em, KFUPM 2009
Encooders
22 22
Enco Enco
.
.
2
n
inputs
2
n
-to-n
Encoder
Encoding - the opposite of d
.
.
Encoder
Encoding the opposite of d
m-bit input code to a n-bit ou
that each valid code word pro
Circuits that perform encodin Circuits that perform encodin
An encoder has 2
n
(or fewer)
which generate the binary co
values values
Typically, an encoder conver
one bit that is 1 to a binary co
iti i hi h th 1 position in which the 1 appea
oder oder
.
n outputs
r
decoding - the conversion of an
r
decoding the conversion of an
tput code with n m 2
n
such
oduces a unique output code
ng are called encoders ng are called encoders
) input lines and n output lines
ode corresponding to the input
rts a code containing exactly
ode corresponding to the
ars.
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0 0
0 0
0 0
0 0
0 1 0 1
1 0
er (truth table) er (truth table)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
1
0
0
0
0
0
0
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0
0
0
0
0
0 0 0
0 0
0 0
0 0
0 1 0 1
1 0
er (truth table) er (truth table)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
0
1
0
0
0
1
0
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0
0
0
0
0
0 0 0
0 0
0 0
0 0
0 1 0 1
1 0
er (truth table) er (truth table)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
0
0
0
0
0
1
0
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0
1
0
0
0
1 0 0
0 0
0 0
0 0
0 1 0 1
1 0
er (truth table) er (truth table)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
0
0
0
0
0
1
1
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0
0
0
1
1
1 0 0
0 0
0 0
0 0
0 1 0 1
1 0
er (truth table) er (truth table)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0 0
0 0
0 0
0 0
0 1
Output equations:
0 1
1 0
Note:
A
0
= ?
A
1
= ?
A
2
= ?
Note:
er (equations) er (equations)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
This truth table is not complete! Why? This truth table is not complete! Why?
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0 0
0 0
0 0
0 0
0 1
Output equations:
0 1
1 0
A
0
= D
1
+ D
3
+ D
5
+ D
7
A
1
= ?
A
2
= ?
er (equations) er (equations)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0 0
0 0
0 0
0 0
0 1
Output equations:
0 1
1 0
A
0
= D
1
+ D
3
+ D
5
+ D
7
A
1
= D
2
+ D
3
+ D
6
+ D
7
A
2
= ?
er (equations) er (equations)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Encode 8-to-3 Encode
D
7
D
6
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
D
7
D
6
0 0
0 0
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
0 0
0 0
0 0
0 0
0 1
Output equations:
0 1
1 0
A
0
= D
1
+ D
3
+ D
5
+ D
7
A
1
= D
2
+ D
3
+ D
6
+ D
7
A
2
= D
4
+ D
5
+ D
6
+ D
7
er (equations) er (equations)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
8 to 3 Enco 8-to-3 Enco
8-to-3
D
0
D
1
D
2
D
3
D
A
0
A
Encoder
D
4
D
5
D
6
D
7
A
1
A
2
Output equations:
A
0
= D
1
+ D
3
+ D
5
+ D
7
A
1
= D
2
+ D
3
+ D
6
+ D
7
A
2
= D
4
+ D
5
+ D
6
+ D
7
oder (circuit) oder (circuit)
D
A
0
D
1
D
3
D
5
D
7
A
1
D
2
D
3
D
6
D
7
A
2
D
4
D
5
D
6
D
7
8 to 3 Encode 8-to-3 Encode
D
7
D
6
Two Limitations:
D
7
D
6
0 0
0 0
1. Two or more inputs = 1
Example: D
3
= D
6
= 1
A
2
A
1
A
0
= 111
0 0
0 0
2. All inputs = 0
Same as D
0
=1
Output equations:
0 0
0 0
0 1
A
0
= D
1
+ D
3
+ D
5
+ D
7
A
1
= D
2
+ D
3
+ D
6
+ D
7
A
2
= D
4
+ D
5
+ D
6
+ D
7
0 1
1 0
er (limitations) er (limitations)
inputs outputs
6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0 6
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1