Chapter 6 - Analog Integrated Circuit Design by John Choma

LECTURE SUPPLEMENT #6 . . .
[LS #6]
CHAPTER #06

Analog MOSFET Circuits

Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 900890271
2137404692 [USC Office]
2137407581 [USC Fax]
8183841552 [Cell]
johnc@usc.edu

PRELUDE:
In this chapter, we study the low frequency properties of the basic, canonic circuit cells that are
foundational to active analog integrated circuits realized in MOSFET technology. Our study is
limited to linear amplifiers and related circuits for which the fundamentally important properties
are input to output (I/O) gain, input resistance, and output resistance. In the course of our
investigations, we shall learn to appreciate the utility of such fundamental circuit and system con-
cepts as Thvenins theorem, Nortons theorem, and mathematical ohmmeter methods of
determining resistance levels established at circuit ports. We shall also exploit elementary
feedback principles, as they apply to linear active networks. Most importantly, we shall examine
our analytical results carefully to forge the circuit and system insights that enable a meaningful
circuit assessment, largely by inspection. Our fundamental goal is to exploit foundational circuit
and system concepts that allow for a computationally efficient analysis of relatively complex ana-
log network topologies.
August 2013
Chapter 6 Analog MOS

- 500 -
6.1.0. INTRODUCTION
The preponderance of linear amplifiers realized in MOSFET technology is comprised of
interconnections of only three basic, or canonic, circuit cells. These cells are the common source
amplifier, the common drain amplifier, which is also known as a source follower, and the com-
mon gate amplifier. In a common source amplifier, we apply the input signal earmarked for li-
near processing as a voltage between the transistor gate terminal and signal ground. In turn, we
extract the output response to this applied signal as either a drain current or a voltage developed
with respect to ground at the drain terminal of the utilized MOSFET. Because the input port of a
common source stage is the MOSFET gate terminal, which conducts virtually no current at low
to even moderately high signal frequencies, its input resistance is very high. It is therefore
amenable to input signal application as a voltage source characterized by a broad range of
Thvenin source resistances. The common source stage also delivers a reasonably high output
resistance, thereby encouraging an extracted current signal response to the applied excitation. It
follows that the common source stage operates best as a transconductor. We offer this opinion
because the aforementioned I/O impedances render its I/O transconductance, which is the ratio of
the output signal current to input signal voltage, nominally independent of both signal source and
terminating load resistances. The fact that the common source amplifier is optimally suited as a
transconductance signal processor does not preclude its viability as a voltage amplifier. It simply
means that because of its high output resistance, the observed voltage gain, which is the ratio of
output signal voltage to input signal voltage, is dependent on the terminating load resistance.
This dependence on load resistance limits the utility of the common source unit as a generic vol-
tage amplifier. Yet another important feature of the common source amplifier is I/O phase inver-
sion. In particular, the output voltage response is 180 out of phase with the applied input signal.
This means that as the input signal rises with time, the output voltage response decreases with
time and vice versa.
In a common drain amplifier, or source follower, we apply the input signal as a voltage
with respect to ground at the gate terminal of the MOSFET. The typical output response is a sig-
nal voltage developed with respect to ground at the source terminal. The source follower func-
tions as a voltage buffer because its input resistance is extremely large, while its output resis-
tance is reasonably low. Although an ideal voltage buffer delivers unity I/O voltage gain, a
MOSFET source follower delivers a gain that is always less than one. To its advantage, this vol-
tage gain is nominally insensitive to source and load resistances. The I/O gain can be markedly
less than one if the device gate aspect ratio and/or its quiescent drain current are too small. As is
the case with an ideal voltage buffer, the source follower offers no I/O phase inversion. This is
to say that the source voltage signal follows the gate (with almost unity gain) in that as the sig-
nal at the gate rises, so does the source terminal response to this signal. Although the source fol-
lower is capable of significant signal power gains, its less than unity voltage gain limits its utility
as a standalone stage in a small signal, electronic system application. Instead, and as we shall
demonstrate, the source follower is commonly inserted between the output port of a relatively
high gain common source amplifier and a terminating load whose impedance is small. For
example, the common drain amplifier serves as an interstage broadbanding vehicle when a com-
mon source amplifier is confronted with a strongly capacitive load, which indeed behaves as a
small branch impedance at high signal frequencies.
The input port of a common gate amplifier is formed by circuit ground and the source ter-
minal of the utilized MOSFET, while its output port is the drain terminal. Because the common
gate amplifier features a relatively small input resistance, we apply the input signal as a current.

- 501 -
Because of the high output resistance of a common gate cell, the output response to applied input
current is sensibly extracted as a signal current. The I/O current gain, which is always less than
one, but generally close to one, exhibits no phase inversion. This gain is always less than unity,
but generally, it is very nearly one. In effect, we can view the common gate amplifier as the dual
of the source follower. To this end, recall that the source follower establishes very high input
resistance, moderately low output resistance, and a voltage gain that can be made to approach
one. In contrast, the common gate configuration boasts moderately low input resistance, very
high output resistance, and a signal current gain that tends toward unity. Accordingly, the com-
mon gate amplifier can be thought of as a current buffer. It can serve as a standalone network in
a variety of high frequency applications. But additionally, the common gate amplifier often ap-
pears in tandem with a common source amplifier in electronic systems for which the common
source stage is required to supply substantial I/O transconductance to a relatively high imped-
ance load.
Table (6.1) summarizes the foregoing operating contentions. We should interject that
interconnections of these three canonic topologies or simple variants thereof comprise better than
90% of the analog MOS circuits that we encounter in commercial, military, or space system
applications. Because these three cells comprise the foundation of analog MOS networks, we
shall soon appreciate that an insightful understanding of their operation is indispensable.

AMPLIFIER
TYPE
INPUT
RESISTANCE
OUTPUT
RESISTANCE
I/O PHASE
INVERSION
NETWORK
APPLICATION
Common
Source
Very
High
Moderately
High
To High
Yes Voltage
Amplifier;
Transconductor
Common
Drain
Very
High
Low To
Moderately
Low
No Voltage
Buffer
Common
Gate
Low To
Moderately
Low
Very
High
No Current
Buffer

Table (6.1). Summary of the salient performance characteristics of the three basic circuit cells of analog
MOSFET technology.
6.2.0. REVIEW OF SMALL SIGNAL MOSFET MODELS
Recall that we chose to review static MOSFET modeling in advance of a detailed
consideration of MOS technology biasing circuits. Similarly, we now elect to commence the
analytical portion of this chapter with an overview of the salient aspects of small signal MOS
technology models, as we discussed in Section (4.6.0).
To this end, consider the diagram in Figure (6.1a), which shows an NMOS transistor
with positive reference polarities delineated for the quiescent and signal components of drain
current and all relevant transistor voltages. For example, the net gate-source voltage, V
gs
, is a
positive quantity when the gate potential lies above the corresponding source terminal potential.
This net voltage is a superposition of its static, or quiescent, component, V
gsQ
and its signal
constituent, V
ga
, which can assume positive or negative values. From a notational perspective,

- 502 -
the low frequency version of the small signal model in Figure (6.1b) conflates with the diagram
in Figure (6.1a). In this structure, g
m
, termed the forward transconductance, is a measure of the
achievable gain in a common source amplifier. The parameter,
b
g
m
, is the bulk transconduc-
tance, which accounts for the influence that bulk-source signal voltage, V
ba
, has on the signal
component, I
da
, of MOSFET drain current. Model parameter r
o
, to which we refer as the channel
resistance of a MOSFET, accounts for channel length modulation (CLM) in the transistor. Fi-
nally, we should interject our tacit neglect of the gate resistance, r
g
. This large gate to source
resistance is especially large at low signal frequencies in that r
g
is inversely proportional to the
square of radial signal frequency.

Figure (6.1). (a). Schematic depiction of an NMOS transistor with the polarities of the static and sig-
nal components of device drain currents and all relevant device voltages defined. (b).
The low frequency, small signal model of the NMOS transistor. The controlled current
sources are couched in terms of the signal component variables introduced in (a). (c).
The high frequency version of the model in (b).
On the assumption that static voltages V
gsQ
, V
dsQ
, and V
bsQ
place the transistor before us
in saturation, transconductance g
m
is given by
( )
dQ
d
m n dQ
gs dsatQ
Q
2I
i
g 2K W L I .
v V
c
~ ~
c
(6-1)
where W/L is the gate aspect ratio of the device, V
dsat
is the quiescent value of the drain satura-
tion, or pinch off, voltage, and K
n
=
n
C
ox
. Parameter
n
represents the average mobility of
charge carriers in the strongly inverted portion of the drain-source channel, and C
ox
is the density
r
o
(G)
g V
m ga
(D)
(D)
b m ba
g V
(S)
V
ga
V
ba
V +V
gsQ ga
V +V
bsQ ba
V +V
dsQ da
I +I
dQ da
I
da
(B) (G)
(S) (S)
V
da
(S) (B)
(b).
r
o
(G)
g V
m ga
(D)
b m ba
g V
(S)
V
ga
V
ba
I
da
V
da
(S)
(B)
(c).
(a).
C
gs
C
bs
C
gd
C
bd

- 503 -
of net gate capacitance. The latter is inversely proportional to the thickness, T
ox
, of the gate sili-
con dioxide layer. We take note that the forward transconductance increases with increases in
the gate aspect ratio and/or augmented quiescent drain current. Increases in the drain current
naturally lead to enhanced static power dissipation. On the other hand, large gate aspect ratios
increase the footprint of the transistor. Another shortcoming of a large gate aspect ratio is that
large geometry transistors produce increased device capacitances and the concomitant prospect
of compromised circuit bandwidths.
The bulk transconductance factor,
b
, which is a small signal ramification of bulk-
induced threshold modulation (BITM), or body effect, is given by
( )
d gs
ox sub s
b
m ox
F bsQ
i V
T qN
.
g
2 2V V
c c
| |
| ~
|

\ .
c
(6-2)
In this expression, N
sub
is the impurity concentration in the bulk substrate,
s
and
ox
denote the
dielectric constants of the gate oxide and silicon semiconductor, respectively, and V
F
is the Fermi
potential. The channel resistance r
o
, is approximately
Q dsQ dsatQ
d
o
ds dQ
Q
V V V
i
r 1 .
v I
+
c
~
c
(6-3)
In this relationship,
( )
2
j
Q T dsQ dsatQ j
b F
V
L
V 32 V V V V
D V
| | | |
= +
| |
\ .\ .
(6-4)
is the semi-empirical Q-point value of the CLM modulation voltage. In (6-4), L is the drawn
channel length of the transistor, D
b
is the electron screening length, V
j
is the built-in potential of
the substrate-drain PN junction, and V
T
is our ubiquitous Boltzmann voltage.
In the interest of completeness, we offer Figure (6.1c) as the high frequency, small sig-
nal model of the transistor. This structure appends four capacitances to the low frequency topol-
ogy of Figure (6.1b). Specifically, the high frequency model incorporates the net gate-source
capacitance, C
gs
, whose active component is proportional to gate area WL. This active capacitive
component superimposes with the parasitic capacitance engendered by gate metal and oxide
overlap with the source volume. A second capacitance in the high frequency model is the gate-
drain capacitance, C
gd
, which is almost exclusively an overlap component in saturation. Overlap
components are minimal, but not zero, in transistors manufactured in a self-aligned gate mono-
lithic process. Finally, bulk-drain (C
bd
) and bulk-source (C
bs
) depletion capacitances, which
respectively superimpose planar and lineal constituents, are included in the high frequency
model. Detailed expressions and corresponding explanations for all four capacitance compo-
nents are provided in Section (4.5.6). For the present, we should simply remark that all of these
capacitances are proportional to gate width W, which hoists the proverbial red flag when we
ponder the use of large gate geometry transistors in circuits earmarked for very high frequency
systems. We should also understand that the bulk-drain and bulk-source depletion capacitances
are inversely related to nominally a square root function of bulk-drain and bulk-source voltages,
respectively. Thus, in addition to potentially limiting circuit bandwidth, C
bd
and C
bs
can incur
high frequency distortion if large signal swings are permitted at either or both of the MOSFET
source or drain terminals.
It is critically important for us to acquire complete comfort with the small signal
MOSFET model. To this end, we note from a tacit inspection of Figure (6.1b) that the low fre-

- 504 -
quency model embraces precisely three branch elements that shunt the drain-source path. The
first, and arguably the most significant, of these shunting branches is the controlled source,
g
m
V
ga
, which is directed from the drain terminal to the source terminal. This controlled source is
important because it transfers an applied gate-source signal voltage, V
ga
, to the drain, or output,
terminal of the transistor. If the applied gate-source voltage happens to be a constant, as it com-
monly is in biasing configurations, no signal component of gate-source voltage materializes. In
this case g
m
V
ga
= 0, and therefore, the controlled current source, g
m
V
ga
, vanishes from the low
frequency MOSFET model.
The second branch element is the controlled current
b
g
m
V
ba
, which like g
m
V
ga
, is di-
rected from the drain terminal to the source terminal. It measures the influence of bulk-induced
threshold modulation (BITM) on signal drain current. The bulk-source signal voltage, V
ba
, is
commonly manifested when source degeneration is used in concert with a bulk terminal that is
returned to constant circuit potential and therefore, a signal ground
1
. While no signal can be sup-
ported at a bulk terminal that is incident with signal ground, a source to ground signal voltage is
assuredly generated in this operating environment. Consequently, V
ba
is nonzero since it is equal
to, or at least intimately related to, the negative of the signal voltage manifested at the source ter-
minal node of the transistor. With V
ba
= 0, which occurs, for example, when both the bulk and
source terminals are grounded or at least connected together,
b
g
m
V
ba
= 0 is hardly magical. In
this special case, this controlled source is an open circuit. In other words, no BITM materializes
at the small signal level. Minimal
b
g
m
V
ba
results despite V
ba
0 if the transistor has a very thin
gate oxide layer, T
ox
. Very thin gate oxides, which, to be sure, can promote undesirable hot car-
rier phenomena immediately beneath the gate metal, give rise to small
b
since (6-2) projects
parameter
b
as proportional to T
ox
.
The third and final branch element in the drain-source circuit is channel resistance r
o
.
This element tends toward a large, and therefore insignificant, shunting resistance when CLM is
negligible. In turn, negligible CLM derives from large V
Q
, which by (6-4) requires a large
drawn channel length. It can also be achieved for small static drain currents, I
dQ
.
In Figure (6.2a), we show a PMOS transistor that depicts its positive drain current and
all relevant positive terminal voltages as an individual superposition of quiescent and signal
components. For example, the drain current, which flows out of a PMOS drain terminal, is indi-
cated as (I
dQ
I
da
). This notation asserts that in the present case, we choose to interpret I
da
as a
positive signal current flowing into the drain; that is, in a direction opposite to that of I
dQ
. The
net drain current is a function of three positive voltages; the source-gate voltage, (V
sgQ
V
ga
), the
source-bulk voltage, (V
sbQ
V
ba
), and the source-drain voltage (V
sdQ
V
da
). We note that while
V
sgQ
, V
sbQ
, and V
sdQ
are static source to gate, source to bulk, and source to drain voltages, respec-
tively, the associated signals, V
ga
, V
ba
, and V
da
, are polarized from gate to source, bulk to source,
and drain to source. In other words, the signal variable polarities are the converse of their
corresponding quiescent variable polarities. But most significantly, they are identical to the sig-
nal polarities invoked for the NMOS device. These declarations and the fact that signal drain
current I
da
is directed to flow into the transistor drain terminal give rise to the low frequency,
small signal PMOS transistor model diagrammed in Figure (6.2b). The only statement that need
be proffered here is that because of the way we have chosen to polarize our small signal va-
riables, there is no difference whatsoever between PMOS and NMOS small signal equivalent

1
Recall that for NMOS transistors, which have p-type substrates, the bulk terminal is invariably returned to the
smallest of available constant circuit potentials. On the other hand, PMOS devices, which have n-type substrates,
generally have their bulk terminals incident with the most positive of constant circuit potentials.

- 505 -
circuits. In other words, just as in the NMOS case, the small signal PMOS model shows a con-
trolled source, g
m
V
ga
, directed from drain to source, where V
ga
is the small signal component of
the gate to source (not source to gate) voltage. Moreover, a current of
b
g
m
V
ba
is postured in the
PMOS model from drain to source, where V
ba
represents the bulk to source (not source to bulk)
signal voltage. And with a channel resistance of value r
o
connected between the drain and
source terminals, the resultant signal drain current, I
da
, is directed into (not out of) the drain ter-
minal. Hence, once we understand the NMOS small signal model, PMOS small signal modeling
requires us to learn nothing new!

Figure (6.2). (a). Schematic diagram of a PMOS transistor with the polarities of the static and signal
components of device drain currents and all relevant device voltages defined. (b). The
low frequency, small signal model of a PMOS transistor. The controlled current
sources are couched in terms of the signal component variables introduced in (a). (c).
The high frequency version of the model in (b). Observe that the models in (b) and (c)
are identical to those of Figure (6.1b) and (6.1c), respectively.
Finally, (6-1) through (6-4) remain in force, subject to the provisos that for PMOS, we
must replace V
bsQ
by V
sbQ
, V
dsQ
by V
sdQ
, and V
dsatQ
= (V
gsQ
V
hnQ
) by V
ssatQ
= (V
sgQ
V
hnQ
),
where V
hnQ
is maintained as a positive threshold voltage. Naturally, the high frequency version
of the PMOS small signal model, which we display in Figure (6.2c), is identical to its NMOS
counterpart in Figure (6.1c).
6.3.0. COMMON SOURCE AMPLIFIER
Figure (6.3a) depicts the basic schematic diagram of a common source amplifier rea-
lized with a single n-channel MOSFET. Figure (6.1b) is the PMOS equivalent to the NMOS
r
o
(G)
g V
m ga
(D)
b m ba
g V
(S)
V
ga
V
ba
I
da
V
da
(S) (B)
(b).
r
o
(G)
g V
m ga
(D)
b m ba
g V
(S)
V
ga
V
ba
I
da
V
da
(S)
(B)
(c).
C
gs
C
bs
C
gd
C
bd
(S)
V V
sgQ ga
V V
sbQ ba
V V
sdQ da
I I
dQ da
(B) (G)
(a).
(S)
(D)

- 506 -
common source unit. In the discussion that follows, we shall focus on only the NMOS circuit in
the hope that the following discourse motivates the reader to pursue similar investigations on the
PMOS circuit. These investigations will confirm that the relationships for the gain, input resis-
tance, output resistance, and related other performance metrics for the PMOS stage are identical
to the respective expressions deduced for the NMOS network.

Figure (6.3). (a). Simplified schematic diagram of a common source amplifier realized with an n-channel
transistor. (b). The p-channel counterpart to the n-channel common source amplifier in (a).
Two sources of constant voltage, V
dd
and V
gg
, are exploited in each of the circuits in
Figure (6.3) to bias the transistor in saturation. MOSFETs used in continuous time analog cells
are invariably biased in their saturation regimes. Accordingly, we can assert that the principle
purpose of static voltages V
dd
and V
gg
is to ensure that the utilized transistor operates in saturation
for all anticipated values of the signal source voltage, V
s
, which we presume has zero average
value. In practice, it is likely that only one such biasing source is used in that V
gg
can derive as a
voltage divider off V
dd
. Moreover, if the amplifier undergoing study is an internal stage of a
multistage network, V
gg
might be extracted as the static output voltage of the preceding stage. In
another words, it may be possible to use the available static voltages of a predecessor stage to
support the requisite biasing of the present stage without explicitly incorporating a separate
source of constant voltage V
gg
.
Two operating conditions must be satisfied to ensure transistor saturation. First, the
gate-source voltage, V
gs
, of the transistor in Figure (6.3a) must exceed the threshold potential,
V
hn
. If V
gs
does not exceed this threshold potential, no significant drain current, I
d
, flows, and the
transistor is effectively cut off. Second, the drain-source voltage, V
ds
, must remain at least as
large as the drain saturation voltage, which ideally is (V
gs
V
hn
), for all expected values of the
signal source voltage, V
s
. The fact that zero gate current is conducted at low signal frequencies
renders the source and drain terminal currents identical. Thus, the voltage drop, manifested
across R
ss
, which is termed a source degeneration resistance, is I
d
R
ss
. This means that in terms of
the input port voltage, V
i
, the gate-source voltage, V
gs
, which serves to activate the MOSFET, is
(V
i
I
d
R
ss
). But with zero gate current flowing into the transistor, V
i
is little more than the vol-
tage sum, (V
gg
+ V
s
). Thus, the first of the aforementioned biasing requirements is
+
V
gg

R
ss
R
is
R
os
R
l
R
s
V
s
+V
dd
V
o
I
d
V
i
(a).
+
V
gg

R
l
R
is
R
os
R
ss
R
s
V
s
+V
dd
V
o
I
d
V
i
(b).

- 507 -
gg s hn d ss
V V V I R . + > + (6-5)
Equation (6-5) must be satisfied for all values of signal voltage V
s
. To this end, we observe
something that even relatively experienced circuit designers are prone to miss. In particular, the
satisfaction of (6-5) under quiescent operating conditions (V
s
= 0 and I
d
= I
dQ
), which entails
gg hn dQ ss
V V I R , > + (6-6)
is only a necessary, and not a sufficient, condition for continual transistor conduction. Suffi-
ciency is achieved when (6-5) is satisfied for the most negative of anticipated signal source vol-
tage, V
s
.
Continuing with the transistor biasing constraints, we observe a drain-source voltage,
V
ds
, that is the difference between the output port voltage, V
o
, and the potential drop, I
d
R
ss
, across
source lead resistance R
ss
. Hence,
o d ss gs hn gg s d ss hn
V I R V V V V I R V . > = + (6-7)
Since
o dd d l
V V I R , = (6-8)
(6-7) can be formulated as
dd gg s d l hn
V V V I R V . > + + (6-9)
Equation (6-9) proscribes the minimum permissible power supply voltage, V
dd
. As is the case
with the transistor turn on condition in (6-5), the saturation constraint in (6-9) must be satisfied
for all values of V
s
. It would appear that while maximally negative V
s
comprises a worst-case
situation in (6-5), maximally positive V
s
is the worst-case condition implicit to (6-9). But a
double-barreled concern accompanies this large V
s
condition. First and most obviously, large V
s

transparently increases the right hand side of (6-9), thereby making it more difficult to satisfy the
inequality. But in addition, large V
s
increases the input port voltage, V
i
, in Figure (6.3a), which
increases the gate-source voltage, V
gs
, applied to the transistor. Because of the nominal square
law dependence of drain current on gate-source voltage, drain current I
d
increases potentially ra-
pidly with V
s
and hence, V
gs
. We see then that in addition to increasing the right hand side of (6-
9) through increased V
s
, a larger signal source voltage also expands the voltage term, I
d
R
l
, on the
right hand side of the subject inequality.
6.3.1. SMALL SIGNAL PERFORMANCE
If the conditions stipulated by (6-5) and (6-9) are met, the subject transistor is saturated.
And if the applied signal, V
s
, is sufficiently small, the small signal components of all circuit
branch currents and circuit node voltages interrelate to one another in an approximately linear
fashion. We can quantify the degree of linearity through a nonlinear analysis of the amplifier
undergoing investigation. But such an analysis is outside the scope of this chapter. Suffice it for
the present to assert that linearity among signal components of all circuit variables is tacitly pre-
sumed when saturation domain operation is ensured. Additionally, input/output (I/O) linearity is
promoted when only sufficiently small input signals earmarked for linear processing are applied.
When small signal linearity prevails, the pertinent equivalent circuit of the amplifier in
either Figure (6.3a) or Figure (6.3b) is the topology of Figure (6.4). This model is applicable to
only low signal frequencies since gate-source, gate-drain, bulk-drain, and bulk-source device
capacitances are ignored, as are any parasitic energy storage elements that may be associated
with the load or source circuits. As we espoused earlier, the low frequency model consists of
three parallel branch elements: a voltage-controlled current source, g
m
V
1
, directed from drain to

- 508 -
source, a second voltage-controlled current source,
b
g
m
V
2
, which is similarly directed from drain
to source, and a drain-source channel resistance, r
o
. We must be mindful of the fact that in the
model of Figure (6.4), V
1
is assuredly not the gate-source voltage applied to the transistor. In-
stead, V
1
is only the signal component of the net gate-source voltage. This net gate-source vol-
tage consists of a vestigial Q-point component that superimposes with its small signal compa-
nion, V
1
. Analogously, V
2
is not the net bulk-source voltage; it is merely the signal component of
the net bulk-source voltage.

Figure (6.4). Small signal, low frequency equivalent circuit of either of the com-
mon source amplifiers diagrammed in Figure (6.3).
Continuing with the small signal model advanced by Figure (6.4), we see that the bat-
tery voltages, V
dd
and V
gg
, are supplanted by short circuits. In truth, they are replaced by their
small signal voltage values. Specifically, V
dd
is substituted by its signal-induced change, AV
dd
,
and V
gg
is supplanted by its signal-induced value, AV
gg
. But since V
dd
and V
gg
are presumably
constant voltage sources, their perturbed values, AV
dd
and AV
gg
, are zero. Formally, V
dd
is re-
placed by AV
dd
= 0, while voltage V
gg
is replaced by AV
gg
= 0. Credence is therefore lent to the
appearance that these two static sources of voltage are seemingly supplanted by electrical short
circuits.
Exceptions to the foregoing voltage modeling scenario occur. For example, if electrical
noise appears on the power bus carrying voltage V
dd
to the amplifier, V
dd
in the small signal
model necessarily becomes the analytical representation of this noise effect; namely, an indepen-
dent voltage source whose value, AV
dd
, typifies the offending noise perturbation. Moreover, if
either V
dd
or V
gg
derive as Thvenin equivalent voltages of poorly regulated sources of energy,
these static voltages would individually be represented in the small signal amplifier model by
their respective Thvenin impedances. The latter situation commonly surfaces in conjunction
with V
dd
in relatively large footprint, mixed signal architectures whose analog cells perform sig-
nal processing at very high frequencies. In such a case, the relatively long routing of the bus line
forges parasitic resistive, capacitive, and even inductive effects so that battery V
dd
appears as a
finite quality factor, complex, and frequency-dependent impedance connected from the power
end of the drain load resistance (or source degeneration resistance in the p-channel version of the
amplifier) to ground.
Because of the foregoing battery voltage disclosures, the signal source comprised of the
series interconnection of voltage V
s
and resistance R
s
is connected from the gate, or input ter-
minal, of the common source amplifier to ground. Analogously, the drain load resistance returns
the drain terminal of the transistor to signal ground. Since the bulk terminal of the transistor is
+
g V
m 1

b m 2
g V r
o
R
ss
R
s
V
s
V
1
V
2
R
l
V
os
I
da
I
da
R
is
R
os
(S)
(G)
(B)
(D)

- 509 -
grounded in the NMOS version of the amplifier, the signal component of the bulk-source vol-
tage, V
2
, is generated from ground to source terminal, which is effectively the voltage developed
across the resistance R
ss
in the model of Figure (6.4). In the PMOS amplifier in Figure (6.3b),
the bulk is returned to the positive bus voltage. We note in this circumstance, however, that be-
cause V
dd
is presumed to be a constant voltage, the bulk terminal in the PMOS amplifier is simi-
larly grounded.
6.3.2. ANALYTICAL STRATEGY
In principle, loop and/or nodal equilibrium equations can be written for the model of
Figure (6.4) to generate the expression for the small signal voltage gain, A
vs
= V
os
/V
s
of the com-
mon source amplifier. Subsequent to replacing the drain load resistance, R
l
, by a mathematical
ohmmeter, a similar set of loop and/or nodal equations fosters the expression for the indicated
common source output resistance, R
os
. No such ohmmeter game need be played at the input port
where the open circuited nature of the gate transparently intimates an infinitely large input resis-
tance, R
is
. Thus, and for frequencies that are low enough to warrant the tacit neglect of all
transistor and circuit capacitances (layout parasitic capacitances and otherwise),
is
R . = (6-10)
Rather than engage in involved circuit analyses, it proves expedient to contrive a more
formalized analytical strategy that can be systematically adapted to analyze numerous variants of
the common source amplifier and even certain types of other active topologies. To this end, we
know that the equivalent circuit shown in Figure (6.4) is a linear network. As such, we are
encouraged to reacquaint ourselves with Messrs. Thvenin and Norton. They taught us, respec-
tively, that any port of a linear network could be replaced by a voltage source in series with a
resistance/impedance or a current source in shunt with the same resistance/impedance. The
choice of adopting Thvenins or Nortons representation of a port is largely arbitrary. But an
intelligent selection of an output model structure for the common source amplifier entails observ-
ing that the output resistance delineated in Figure (6.4) is likely to be large. It is certainly going
to be larger than the source degeneration resistance, R
ss
. This contention follows from the
observation that the drain to ground circuit where output resistance R
os
is measured is a series
interconnection of the drain-source port of the transistor and the two terminals of resistance R
ss
.
Alternatively and arguably more dramatically, this output resistance can be expected to exceed
the relatively large channel resistance, r
o
, of the transistor. Although we would not risk indict-
ment for imprudently adopting a Thvenin format, we shall succumb to Nortons charismatic
lobbying to take advantage of the presumably large output resistance that we surmise intuitively.
Accordingly, we represent the output port of the model in Figure (6.4) by the Norton architecture
displayed in Figure (6.5a). In this equivalent circuit, we understand that the current, I
N
, is the
Norton, or short circuit, current that flows through the load. Specifically, I
N
is the current con-
ducted by a load that is replaced by a short circuit. Moreover, network linearity allows us to ex-
press current I
N
as a linear function of any small signal branch or node variable. We elect to
write I
N
as a current proportional to the applied signal voltage, V
s
. This tack enables an unambi-
guous analytical link between the input signal applied to the gate and its resultant signal drain
current response. As we indicate in Figure (6.5b),
N me s
I g V , = (6-11)
where the parameter, g
me
, is introduced as the ratio of the Norton output port current (short cir-
cuit load current) to the signal voltage (V
s
). Qualitatively, g
me
can be interpreted as an effective
I/O transconductance linking the input port to the output port of either amplifier in Figure (6.3).

- 510 -
Finally, resistance R
os
in the Norton model is the Thvenin output resistance facing the load that
terminates the output port of the common source amplifier.

Figure (6.5). (a). Norton equivalent circuit of the output port for the small signal model
of the common source amplifier in Figure (6.3). (b). The model of (a)
with Norton current I
N
expressed as linearly dependent on the signal vol-
tage, V
s
, applied to the common source configuration.
Figure (6.6a) is the equivalent circuit appropriate to the calculation of the foregoing
Norton output current and effective I/O transconductance. This circuit is identical to that of Fig-
ure (6.4), with the exception that the drain load resistance is replaced by the short circuit pre-
scribed by Norton. The indicated short circuit forces the drain signal current, I
da
, to be identical
to the short circuit, or Norton, load current, I
N
. Since current I
N
flows through the source
degeneration resistance, R
ss
, as well as through the short circuited load, the model at hand con-
firms that
2 N ss
1 s 2 s ss N
V I R
.
V V V V R I
=
= + =
(6-12)
By KVL,
( )
o N m 1 b m 2 ss N
0 r I g V g V R I . = + (6-13)
After we substitute (6-12) into (6-13) to banish the two voltage variables, V
1
and V
2
, we get
( )
m o s
N
ss b m ss o
g r V
I ,
R 1 1 g R r
=
( + + +

(6-14)
from which we deduce an effective I/O transconductance, g
me
, of
+
g V
m 1

b m 2
g V r
o
R
ss
R
s
V
s
V
1
V
2
R
l
V
os
I
da
I
da
R
is
R
os
(S)
(G)
(B)
(D)
I
N
R
os
R
l
V
os
I
da
(a).
g V
me s
R
os
R
l
V
os
I
da
(b).

- 511 -

Figure (6.6). (a). Model used in the determination of the Norton equivalent output port current, I
N
, for the com-
mon source amplifier modeled in Figure (6.4). (b). The small signal model of Figure (6.6a) with
channel resistance r
o
presumed infinitely large. (c). Small signal model of Figure (6.6a) with bulk-
induced threshold modulation phenomena ignored (
b
= 0). (d). Small signal model of Figure
(6.6a) with both CLM and BITM ignored (r
o
= and
b
= 0).
( ) ( )
o
m
o ss m
me
m ss b m o ss
r
g
r R g
g .
1 g R 1 1 g r R
| |
|
+
\ .
= ~
+ + +
(6-15)
The indicated approximation stems from the reasonable assumptions, r
o
>> R
ss
and
b
<< 1.
It is always sensible to check algebraically intricate results for consistency with special
case circumstances that lend themselves to transparent circuit level interpretations. For example,
consider the special case of zero source degeneration resistance; that is, R
ss
= 0. For this special
case, (6-15) yields an effective transconductance, g
me
, which is identical to the transistor
transconductance, g
m
. From Figure (6.4), we see that R
ss
= 0 forces V
2
= 0 which, in turn, con-
strains the dependent current source,
b
g
m
V
2
, to zero. Moreover, with R
ss
= 0, the gate-source
signal voltage, V
1
, becomes a gate to ground voltage that is identical to the signal source voltage,
V
s
. Accordingly, g
m
V
1
equates to g
m
V
s
in the model. But with a short circuited load resistance,
R
l
, and again, R
ss
= 0, no current can flow through the device channel resistance, r
o
, in Figure
(6.4). Thus, the current conducted by the short circuit imposed across resistance R
l
is identical to
g
m
V
s
, which indeed verifies an effective transconductance that equals the transistor transconduc-
tance, g
m
. Equation (6-15) therefore appears consistent with the specialized operating circums-
tance of a zero-valued source degeneration resistance. To be sure, such consistency does not
guarantee the correctness of the equation under investigation, but an inconsistency spun from
+
g V
m 1

b m 2
g V r
o
R
ss
R
s
V
s
V
1
V
2
I = I
da N
I
N
(a).
+
g V
m 1

b m 2
g V
R
ss
R
s
V
s
V
1
V
2
I = I
da N
I
N
+
g V
m 1
r
o
R
ss
R
s
V
s
V
1
V
2
I = I
da N
I
N
(c).
+
g V
m 1
R
ss
R
s
V
s
V
1
V
2
I = I
da N
I
N
(d).
(b).

- 512 -
logical circuit level reasoning implies analytical error or inconsistency that demands meaningful
and understandable resolution.
Since the network we are currently examining is our first example of a practical
MOSFET amplifier, it may prove profitable to execute a few other sanity checks on the effective
transconductance put forth by (6-15). To this end, consider the model shown in Figure (6.6b),
which approximates the originally considered model in Figure (6.6a) by invoking the simplifica-
tion of an infinitely large channel resistance, r
o
. We should understand that setting r
o
= is
tantamount to a tacit neglect of CLM. A conventional analysis of the circuit in Figure (6.6b) rea-
dily produces an effective transconductance, g
me
, of
( )
o
o
N m
me
r
s m b ss
r
I g
g ,
V 1 g 1 R
=
=
= =
+ +
(6-16)
which is synergistic with the first term on the right hand side of (6-15). Note herewith that in the
absence of CLM, the engineering upshot of BITM is to increase the source degeneration resis-
tance by a factor of (1 +
b
). If on the other hand, we ignore, BITM, as opposed to CLM, by set-
ting
b
= 0 and retaining finite r
o
, the model depicted in Figure (6.6c) results. An analytical
study of this structure delivers
( )
b
b
o
m
o ss N
me
0
s m o ss
0
r
g
r R I
g ,
V 1 g r R
=
=
| |
|
+
\ .
= =
+
(6-17)
which, once again, concurs with the first term on the right hand side of (6-15). Finally, consider
the simplified equivalent circuit of Figure (6.6d), which represents the original model in Figure
(6.6a) under the special case of negligible CLM and BITM. Our dutiful analysis reveals
o
o b
b
N m
r
me
r 0
s m ss
0
I g
g ,
V 1 g R
=
= =
=
= =
+
(6-18)
which agrees with the first term on the right hand side of (6-15), as well as with (6-16) and (6-
17). The precise agreement we have garnered among the exact effective transconductance and
all of the foregoing approximated transconductances makes betting on the validity of (6-15) a
non-gamble. Equally important is the fact that the foregoing exercises succeed in relating simple
algebraic approximations we might logically execute on (6-15) to respective circuit level
implications. In short, we have accomplished far more than mere algebraic simplifications. In
fact, we have successfully witnessed the circuit level ramifications of relevant mathematical
approximations.
Equations (6-15) through (6-18) clarify why resistance R
ss
is said to degenerate the
forward transconductance of a transistor. All four of these relationships confirm g
me
< g
m
for R
ss

> 0. A simplified, but nonetheless reasonably accurate, estimate of the factor by which the
transistor transconductance is reduced by source degeneration resistance is, by (6-18), (1 +
g
m
R
ss
). We should keep in mind that while the approximations implicit to (6-18) are generally
valid in reasonably biased MOSFETs, all such approximations are further supported by a prac-
tical inability to implement too large of a source degeneration resistance. Rarely is R
ss
larger
than the mid tens of ohms. Two engineering reasons encourage a design strategy that obviates a
large source degeneration resistance. First, excessively large R
ss
generates considerable elec-
trical noise (random current and voltage spikes associated with the resistor terminals.) In ex-
treme circumstances, this noise can mask much of an applied signal, particularly when said sig-

- 513 -
nal is very small, as it often is in communication systems. Additionally, large R
ss
requires
correspondingly large power supply voltages to achieve proper biasing. But large V
dd
is not
compliant with the pragmatic operating requirements mandated by present day portability cul-
tures. As far as the bulk transconductance factor,
b
, is concerned, modern transistors deliver
values of
b
that make BITM invariably inconsequential in the majority of small signal
amplifiers.
In order to determine an expression for the common source output resistance, R
os
, resis-
tance R
l
in the model of Figure (6.4) is supplanted by our trusty mathematical ohmmeter. The
ohmmeter current, I
x
, injected into the output port of the amplifier manifests a voltage response,
V
x
, across the port, as illustrated in Figure (6.7). The model also imposes a null value to the lone
independent energy source, V
s
, applied to the circuit in Figure (6.4). We see in the equivalent
circuit that

Figure (6.7). The small signal model used to determine an expression for
the output resistance, R
os
, of either common source amplifier
in Figure (6.3). This resistance is the ratio, V
x
/Ix, of the
mathematical ohmmeter variables, V
x
and I
x
.
1 2 ss x
V V R I , = = (6-19)
and by KCL and KVL,
( )
x o x m 1 b m 2 ss x
V r I g V g V R I . = + (6-20)
The combination of these two equilibrium relationships leads to
( )
x
os ss b m ss o
x
V
R R 1 1 g R r .
I
( = = + + +

(6-21)
We can test this expression by once again resorting to the special and easily understandable case
of R
ss
= 0, for which (6-21) collapses to R
os
= r
o
. Because R
ss
= 0 forces V
1
= 0 and V
2
= 0 in
the model of Figure (6.7), we see that the output port of the subject model reduces to simply a
channel resistance, r
o
. Accordingly, we conclude a Thvenin output resistance of r
o
, as projected
by (6-21), for the resultant output resistance of the common source network. We note, however,
that when R
ss
> 0, R
os
can be substantially larger than r
o
, depending on the numerical value of the
transconductance-resistance product, g
m
R
ss
. For (1 + g
m
R
ss
) >> 1 (an approximation that should
be carefully tested when a deep submicron transistor is used), (6-21) becomes
( ) ( )
os ss b m ss o m ss o
R R 1 1 g R r 1 g R r . ( = + + + ~ +

(6-22)
Armed with the pertinent relationships for the short circuit transconductance, g
me
, and
os
, we can represent the somewhat cumbersome common source equiva-
g V
m 1

b m 2
g V r
o
R
ss
R
s
V
1
V
2
I
x
I
x
I
x
V
x
+
R
os

- 514 -
lent circuit in Figure (6.4) by the Norton output model offered in Figure (6.5b). An obvious
advantage of this representation is that the voltage gain, A
vs
, now follows by mere inspection.
Specifically,
( )
os os
vs me os l me l
s os l
V R
A g R R g R .
V R R
| |
= = ~
|
+
\ .
(6-23)
We see that this I/O voltage gain, whose magnitude can be significantly larger than one, is
strongly dependent on the drain load resistance, R
l
. This gain dependence on R
l
is magnified if,
as is commonly the case, the common source output resistance, R
os
, is significantly larger than
R
l
. We suggest that R
os
>> R
l
is a typical operating circumstance because R
l
is necessarily li-
mited by the voltage drop it can support in light of its conduction of the Q-point drain current of
the transistor. Therefore, large R
l
necessitates an undesirably large power supply voltage, V
dd
,
which must deliver voltage, not only to R
l
, but also to the transistor drain-source terminals and
the source degeneration resistance.
With R
os
>> R
l
and additionally, r
o
>> R
ss
and
b
<< 1, (6-23) combines with (6-15) to
deliver the approximate voltage gain,
os m l
vs me l
os l m ss
R g R
A g R .
R R 1 g R
| |
= ~
|
+ +
\ .
(6-24)
In the somewhat questionable circumstance that g
m
R
ss
>> 1, we observe a gain magnitude that is
simply the resistance ratio, R
l
/R
ss
. Although this gain result is arguably improbable, it is
nonetheless interesting in that resistance ratios can be controlled accurately in monolithic
processes. Of course, this assertion assumes that both R
l
and R
ss
are on-chip resistances.
Accordingly, a highly predictable and reproducible voltage gain that is nominally independent of
parametric transistor uncertainties is theoretically possible.
The negative sign in the common source gain equations of (6-23) and (6-24) is, as ex-
plained earlier, indicative of a 180 phase inversion between the applied input signal and the
resultant signal voltage response. This negative sign is more than mere algebraic nuance. It is
an inherent, physically important property of a common source amplifier. In an attempt to
understand the phase inversion concept, return to the circuit of Figure (6.3a) and assume that sig-
nal voltage V
s
increases with time. The increase in V
s
elevates the input port voltage, V
i
, which,
in turn, translates to an increase in the gate-source voltage, V
gs
, applied to the transistor. To be
sure, the resultant increase in the gate-source voltage is likely to be smaller than the original rise
in signal source voltage, but it tracks nonetheless with V
s
to within some positive factor. As V
gs

rises, so must the drain current, I
d
, since the drain current obeys a nominally square law depen-
dence on the difference between the gate-source voltage and the threshold potential. But as I
d

increases, so must the drop across the load resistance, R
l
. However, the output voltage, V
o
, is lit-
tle more than (V
dd
R
l
I
d
). Since voltage V
dd
is a constant, V
o
diminishes as I
d
increases. The
scenario in brief flow chart form is as follows: V
s
rises V
i
increases V
gs
increases I
d
in-
creases whence, V
o
falls as V
s
rises. Of course, the opposite scenario continues to reflect
phase inversion; that is, a diminishing V
s
results in correspondingly larger V
o
. An identical
disclosure applies to the PMOS version of the common source amplifier in Figure (6.3b).
The fact that R
os
is typically much larger than is R
l
suggests that the common source
amplifier, while often exploited as a voltage amplifier, is better suited as a transconductor. The
overall forward transconductance, say G
mf
, of the amplifier is defined as the ratio of the load sig-

- 515 -
nal current (I
da
in this case) to the applied signal voltage, V
s
. In Figure (6.5b), we apply current
divider principles to deduce,
da os m
mf me me
s os l m ss
I R g
G g g ,
V R R 1 g R
| |
= ~ ~
|
+ +
\ .
(6-25)
which is essentially independent of the drain load resistance. In other words, the amplifier is
capable of transforming an applied signal voltage to a known and reasonably predictable level of
output signal current for a broad range of drain load resistances.
6.3.3. VARIATIONS TO THE COMMON SOURCE THEME
The common source cells depicted in Figure (6.3) are foundational to modified am-
plifier cells that increase common source practicality and utility in application specific systems.
In the subsections that follow, we explore a few of these variants from the perspective of increas-
ing our insightful understanding of electronic circuits.
6.3.3.1. Single Supply Biasing Via Passive Voltage Division
We quipped in conjunction with our investigation of the common source cells in Figure
(6.3) that the voltage source, V
gg
, which is required to raise the gate-source voltage of the transis-
tor to a level above threshold, can derive from division off the power line voltage, V
dd
. Equally
significant is our observation that since the gate conducts zero current and the signal source vol-
tage, V
s
, has no average value, voltage V
gg
is the Q-point value of the input port voltage, V
i
, in the
subject figure; that is, V
iQ
= V
gg
.
The simplest way of exploiting voltage division as a means of implementing the requi-
site static input port voltage is the R
1
-R
2
divider incorporated in the network of Figure (6.8). We
have added a so-called coupling capacitance, C, to connect (or to couple the signal source to
the gate of the transistor in the amplifier. The principle function of this appended capacitance is
to isolate the signal source from the DC voltage, V
iQ
, developed at the transistor gate. In
particular, we know that capacitance C is an open circuit for DC. With C behaving as an open
circuit for static current, the quiescent current conducted by resistance R
1
flows exclusively
through resistance R
2
. Equivalently, we assert that capacitance C preserves the series nature of
the R
1
-R
2
interconnection under quiescent, or standby, operating conditions. In contrast, if the
signal were to be coupled directly to the transistor gate, which effectively supplants C by a short
circuit, a static current of V
iQ
/R
s
flows back through the signal source. This means that the series,
and thus the simple voltage dividing, nature of the R
1
-R
2
interconnection is destroyed in that R
1

must now supply a supplemental current, V
iQ
/R
s
, to the baseline static current of V
iQ
/R. It should
be noted that this supplemental current can be appreciable in light of the fact that source resis-
tance R
s
is commonly of the order of only 50 . To be sure, a design-oriented, analytical ac-
count of the backflow can be made when selecting R
1
and R
2
values that are appropriate for
establishing a static input port voltage of V
iQ
= V
gg
.
Aside from the increased static power dissipation that arises from the additional current
that resistance R
1
must conduct, another, potentially serious problem accompanies direct coupl-
ing. In particular, the vast majority of practical signal sources, which may be antennas, compact
disk players, optical sensors, microphones, and other sensitive equipment, cannot handle signifi-
cant static currents. Indeed, even a minute flow of static current can catastrophically damage
many practical signal sources. Accordingly, placing the capacitor as shown in Figure (6.8)
solves the problem confronting us in that it isolates, or protects, the signal source from DC. Of

- 516 -
course, the capacitance problem is not completely solved until such time that we can assure that
the utilized coupling capacitor minimally attenuates the Thvenin source signal, V
s
. In a word,
we must ultimately mitigate any price we are compelled to pay for implementing the aforemen-
tioned static isolation.

Figure (6.8). A simple passive resistive divider used to implement a single
supply version of the common source amplifier in Figure (6.3a).
With the coupling capacitor in place, V
iQ
= V
gg
is seen as requiring
2
gg dd
1 2
R
V V ,
R R
| |
=
|
+
\ .
(6-26)
where use is made of the facts that neither capacitance C nor the transistor gate conducts any
static current. Since the static power, say P
r
, consumed by the resistive divider is
2
dd
r
1 2
V
P ,
R R
=
+
(6-27)
(6-26) is equivalent to
r 2
gg
dd
P R
V .
V
= (6-28)
Equation (6-28) is germane to design issues in that it allows us to stipulate the standby power, P
r
,
dissipated by the resistive divider we have chosen to deploy for biasing purposes. In general, we
wish to minimize circuit power dissipation. To this end, we may elect to make P
r
perhaps 10%
or even 5% of the power, V
dd
I
Q
, supplied by voltage V
dd
to the transistor drain circuit. Once a
satisfactory value of P
r
is enunciated, the known value of V
dd
and the desired value of V
gg
yield
resistance R
2
from (6-28), whence resistance R
1
derives from (6-26) or (6-27).
Although the capacitor isolates the signal source from biasing potentials in the network,
it remains a problematic element from the perspective of the small signal performance of the am-
plifier. For example, it is obvious that the capacitively coupled common source amplifier is una-
ble to provide gain at zero frequency, where capacitances act as open circuits. If C behaves as an
open circuit, the signal source comprised of signal voltage V
s
and Thvenin resistance R
s
is de-
coupled from the gate of the transistor in Figure (6.8), thereby resulting in a null signal output
response at the transistor drain terminal. In other words, the amplifier is no longer a strictly low-
pass configuration capable of gain down to zero frequency. However, suppose that for a particu-
+
R
ss
R
1
R
is
R
os
R
l
R
s
V
s
+V
dd
V
o
I
d
V
i
R
2
C

- 517 -
lar application, the lowest steady state frequency implicit to signal V
s
is the small, but nonzero,
radial value,
L
. Then, the coupling capacitance before us must emulate a short circuit connec-
tion between signal source and transistor gate for only those signal frequencies that exceed
L
.
As a result, the capacitively coupled amplifier exhibits a lowpass I/O response for frequencies
that are larger than
L
and ranging up to a high frequency, say
H
. At
H
, the gain magnitude
inevitably attenuates with increasing frequency because of transistor capacitances and parasitic
energy storage elements associated with the various nodes of the circuit. In such an event, the
amplifier bandwidth, B, is formally defined as the difference frequency, (
H

L
). This
declaration presumes tacitly that
H
and
L
are the radial signal frequencies where the I/O gain
magnitude is three decibels (3-dB) smaller than the gain magnitude registered at mid band, which
we often reference as the passband of the amplifier. In the passband, C ostensibly approximates
an electrical short circuit, while transistor and parasitic network capacitances are small enough to
remain inconsequential.
In most practical applications,
H
is far larger than
L
so that for all practical purposes,
the 3-dB bandwidth is
H
. For example, audio amplifiers are called upon to provide gain from
minimally 20 Hz to 20 KHz, wherein we see that
L
can presumably be set to 2t(20 Hz) and
H

= 2t(20 KHz). Since 20 KHz is three orders of a magnitude larger than 20 Hz, the audio band-
width is essentially just 20 KHz. On the other hand, cell phones operate in a relatively narrow
frequency passband centered around 2.4 GHz or larger radio frequency (RF). In these applica-
tions, no purpose is served by designing the system front end to provide gain down to zero fre-
quency Actually, a strictly low pass design in this and other types of communication networks is
disadvantageous from the standpoint that the total output electrical noise, which contaminates the
otherwise clean signal response, is nominally proportional to the implemented bandwidth.
Thus,
L
in such systems is invariably chosen to be a relatively large frequency metric.
In order to forge a meaningful strategy for choosing capacitance C, we draw the small
signal equivalent circuit of the input port of the amplifier in Figure (6.8) as the structure shown
in Figure (6.9a). In this circuit, resistances R
1
and R
2
appear as parallel branches at the amplifier
input port, where the signal voltage with respect to ground is denoted as V
is
. In particular, resis-
tance R
2
is connected directly across the input port, while R
1
is connected from the input node to
the power line voltage, V
dd
. But since V
dd
has zero signal value and is therefore effectively
grounded for signal conditions, resistances R
1
and R
2
are in parallel with one another under sig-
nal conditions. Letting

Figure (6.9). (a). Small signal model of the input port for the capacitively coupled common source am-
plifier in Figure (6.8). (b). The circuit of (a) at signal frequencies for which the coupling
capacitance, C, behaves as a signal short circuit. Resistance R
p
is the parallel combina-
tion of resistances R
1
and R
2
.
p 1 2
R R R (6-29)
R
1
R
s
+
V
s
R
2
C
V
is
(a).
R
p
R
s
+
V
s
V
is
(b).

- 518 -
denote the shunt combination value of resistances R
1
and R
2
, we get
( )
p p
is
s p s
p s
R jR C
V
.
V R R 1 jC
1 j R R C
= =
+ +
+ +
(6-30)
The magnitude of this transfer function is
( )
p
is
2
s
p s
R C
V
.
V
1 R R C
=
(
+ +

(6-31)
We observe that if [(R
p
+ R
s
)C]
2
>> 1 at a signal frequency of =
L
,
p
is
s p s
R
V
V R R
~
+
(6-32)
for all >
L
. This is to say that the electrical behavior of the input circuit shown in Figure
(6.9a) emulates that of the simple divider in Figure (6.9b). We note that the network in Figure
(6.9b) displays an architecture that is tantamount to replacing capacitance C in the former dia-
gram by a short circuit. Because of (6-32), we are compelled to accept the fact that the coupling
achieved by capacitance C is imperfect in the sense that we do lose a fraction, R
p
/(R
p
+ R
s
), of
the applied input signal, V
s
. But to the extent that resistance R
p
is substantially larger than the
signal source resistance, R
s
, the divider in (6-32) approaches unity.
The only remaining design task is the actual stipulation of the required capacitance
value. Since we require
( )
2
L p s
R R C 1 ,
(
+ >>

(6-33)
it suffices to ensure that
( )
L p s
R R C 10 3.2 , + > ~ (6-34)
whence
( ) ( )
L p s L p s
3.2 1
C .
R R 2 f R R
> ~
+ +
(6-35)
We note that in effect, the product of twice the lowest radial frequency of interest, 2f
L
, and the
time constant, (R
p
+ R
s
)C, associated with capacitance C must be at least as large as one.
Capacitances that are significantly larger than the right hand side of the last expression, which
more easily satisfy the requisite inequality, should be avoided because of their physical size,
cost, and in extreme cases, relatively poor reliability. In most coupling cases, we shall find that
the size of the requisite capacitance precludes its on chip realization.
Because of the resistive load imposed at the gate terminal of the capacitively coupled
common source amplifier in Figure (6.8), a few of the small signal performance metrics deduced
for the basic common source stage in Figure (6.3a), change slightly. For example, the input
resistance, R
is
, is no longer infinitely large but instead, it is now
is 1 2 p
R R R R . = (6-37)
for >
L
. Note, however, that large R
p
, which achieves large input resistance, mandates large
R
1
and large R
2
and therefore, large (R
1
+ R
2
). It follows, by (6-27), that large R
p
promotes low
static power dissipation in the resistive divider subcircuit. Moreover, the signal voltage devel-
oped at the input port is not V
s
and is now V
is
, per (6-30), for >
L
. Thus, the effective
transconductance and small signal voltage gain in (6-15) and (6-24), respectively, are slightly

- 519 -
attenuated by the voltage divider action inspired between resistance R
p
and signal source resis-
tance R
s
. In particular, our revised Norton transconductance and I/O voltage gain are
( ) ( )
p
o
m
o ss p s p
m
me
m ss p s b m o ss
R
r
g
r R R R R
g
g
1 g R R R 1 1 g r R
| |
| |
|
|
|
+ + | |
| |
\ .
\ .
= ~ |
|
|
+ + + +
\ .
\ .
(6-38)
and
p p
os m l
vs me l
os l p s m ss p s
R R
R g R
A g R .
R R R R 1 g R R R
| | | |
| | | |
= ~ | |
| |
| |
+ + + +
\ . \ .
\ . \ .
(6-39)
In contrast, the output resistance, R
os
in (6-21), is unchanged by the input port biasing divider.
6.3.3.2. Single Supply Biasing Via Active Voltage Division
The most appreciated types of design creativity are those that take the form of practical
circuit level solutions to problems that pervade existing topologies. In the case of the input resis-
tive divider that we used to establish an input port biasing potential, V
iQ
, of V
gg
in the circuit
schematic diagram of Figure (6.8), a potential shortfall surfaces from the need to achieve low
power dissipation in the resistive biasing branch. This design target manifests large values for
the resistances, R
1
and R
2
. Additionally, very large R
1
and R
2
are required if significant attenua-
tion of the transconductance and voltage gain in the amplifier passband is to be avoided.
Unfortunately, large on-chip resistances are difficult to fabricate accurately and to layout without
incurring potential high frequency performance degradation caused by the energy storage
parasitics that are implicit to these resistive elements. A possible solution is the modified com-
mon source stage in Figure (6.10) in which resistance R
1
in Figure (6.8) is supplanted by a
transistor, M1, and resistance R
2
is replaced by transistor M2. In effect, the passive divider
formed of resistances R
1
and R
2
is replaced by an active voltage divider formed of the diode-
connected transistors, M1 and M2. Transistors M1 and M2 are physically similar to the transis-
tor, M, which is embedded in the common source amplifier, but neither of their gate aspect ra-
tios, say
1
and
2
, respectively, need be the same as the gate aspect ratio of transistor M.
Two ramifications immediately surface from the diode-type connections of transistors
M1 and M2. First, both M1 and M2 are guaranteed to operate in their saturation domains, regard-
less of the current levels they conduct, because each device has a drain-source voltage that is
identical to its corresponding gate-source voltage. This voltage equality forces M1 and M2 to
support precisely zero gate-drain voltage, V
gd
, and since V
gd
= 0 assures V
gd
smaller than thre-
shold potential, the source to drain channels of M1 and M2 are pinched off and therefore, the de-
vices operate in saturation. The second ramification is that since the gate and drain are con-
nected together, the nominally three terminal transistor element (the bulk terminals are simply
grounded to inhibit any current conduction in the bulk) functions as an effective two terminal
device, as does a conventional PN junction diode. This state of affairs means that when either
M1 or M2 is modeled by its linear, small signal, low frequency equivalent circuit, either device
behaves as a memoryless, two terminal, linear branch element. But two terminal, linear,
memoryless behavior defines a classic linear resistance. In other words, M1 in Figure (6.10)
emulates the functionality of resistance R
1
in Figure (6.8) and analogously, M2 behaves electri-
cally in a fashion that is similar to that of a passive resistance, R
2
.
Before examining the nature of the small signal resistances presented to the circuit by
the diode-connected transistors, let us see how transistors M1 and M2 interact to establish the

- 520 -
desired Q-point value of input port voltage V
i
, which is V
iQ
= Vgg. The Q-point value, I
RQ
, of the
indicated current, I
R
, flows through the drains of both transistors M1 and M2 in the network of
Figure (6.10). Since these transistors are saturated, the Schichman-Hodges model stipulates

Figure (6.10). Common source amplifier of Figure (6.8) with passive resistive
divider formed of resistances R
1
and R
2
replaced by an active di-
vider formed of transistors M1 and M2.
( ) ( )
2 2
n n
RQ 1 dd iQ hn 2 iQ hn
K K
I V V V V V ,
2 2
= = (6-40)
where CLM is deemed insignificant in deference to drain-source voltages on each transistor that
are limited to their respective gate-source voltages. Additionally, we recall that
1
and
2

symbolize the gate aspect ratios of transistors M1 and M2, respectively. Choosing these ratios
small obviously leads to low-level current conduction of M1 and M2 and hence, low power
dissipation in the input biasing subcircuit.
We can easily solve (6-40) for voltage V
iQ
; namely,
1 2 1 2
iQ dd hn
1 2 1 2
1
V V V ,
1 1
| | | |
= +
| |
| |
+ +
\ . \ .
(6-41)
which affirms that the requisite value of Q-point voltage V
iQ
derives from the power line voltage,
V
dd
, through proper selection of the ratio,
1
/
2
, of device gate aspect ratios. Interestingly, if
1
=
2
, voltage V
iQ
is rendered independent of the threshold potential, V
hn
, which is advantageous in
light of the temperature sensitivity and at least a small degree of uncertainty that pervade this
transistor metric. Moreover, V
iQ
is simply V
dd
/2 when
1
=
2
, which is reasonable in light of the
fact that identical gate aspect ratios imply a simple voltage divider formed of a series
interconnection of two identical transistors operated effectively as identical two terminal resis-
tances.
In order to determine the effective resistance, R
1
, presented to the amplifier by transis-
tor M1 in Figure (6.10), the M1 subcircuit is redrawn for convenience in Figure (6.11a). The
traditional low frequency small signal model of this subcircuit appears in Figure (6.11b), where
the desired effective resistance, R
1
, is the ratio, V
x
/I
x
, of the introduced mathematical ohmmeter
variables. But we note in Figure (6.11b) that the gate-source signal voltage, V
1
is identical to the
negative of the ohmmeter voltage, V
x
; ditto for the bulk-source signal voltage, V
2
. It follows that
+
R
1 R
os
R
l
R
s
V
s
+V
dd
V
o
I
d
I
R
V
i
C
M
M1
R
ss
R
is
M2
R
2

- 521 -
the model in Figure (6.11b) is electrically identical to that of Figure (6.11c) where the directions
of the two dependent sources in Figure (6.9b) have been reversed to reflect the voltage con-
straint, V
1
= V
2
= V
x
. But in Figure (6.11c), we see that the ohmmeter voltage, V
x
, appears di-
rectly across, and in associated polarity convention with, the voltage controlled current source,
g
m1
V
x
. This situation implies that the subject dependent current source is equivalent to a branch
conductance of g
m1
or equivalently, a branch resistance of 1/g
m1
. The same argument applies to
the dependent source,
b1
g
m1
V
x
, which is seen to reflect a branch resistance of 1/
b1
g
m1
. Our
observations serve to reduce the model in Figure (6.11c) to the simple three branch circuit in Fig-
ure (6.11d). In the latter diagram, we see, by inspection and without need for our ohmmeter
crutch, that

Figure (6.11). (a). The use of diode-connected transistor M1 in the amplifier of Figure (6.10) to emulate a nominally
linear, two terminal resistance of value R
1
. (b). Low frequency, small signal model for determining the
effective resistance presented by transistor M1 between its source terminal and signal ground. (c).
Equivalent representation of the small signal model in (b). (d). Circuit level implication of the small
signal model in (c) as the shunt interconnection of three individual branch resistances.
( ) ( ) ( ) ( )
x o1
1
x o1 b1 m1 b1 m1 o1 b1 m1 m1
V r 1 1 1
R ,
I 1 r 1 g 1 1 g r 1 g g
= = = ~ ~
+ + + + +
(6-42)
where the approximation reflects the reasonable presumptions that (1 +
b1
)g
m1
r
o1
>> 1 and
b1

<< 1. With a small Q-point current, I
RQ
, conducted by transistor M1 to sustain low standby
power dissipation, transconductance g
m1
, which is proportional to the square root of I
RQ
, is
correspondingly small. It follows that the desired target of a relatively large R
1
can be achieved.
The electrical situation in which transistor M2 is immersed is analogous to that of M1.
R
1
R
1
+V
dd
M1
g V
m1 1
g V
m1 x
b1 m1 2
g V
b1 m1 x
g V
r
o1
r
o1
V
1
V
1
V
2
V
2
V
x
V
x
I
x
I
x
(b).
(c).
(a).
b1 m1
g
r
o1
g
m1
1 1
(d).
V
x
I
x
R
1
R
1

- 522 -
Actually, it is even a somewhat simpler scenario in that since both the bulk and the source
terminals of transistor M2 are grounded, the signal component of the bulk-source voltage of M2
is necessarily zero. This means that the bulk transconductance generator,
b2
g
m2
V
2
, which
theoretically appears in the small signal model of M2 is zero, whence resistance R
2
is simply
( )
o2
2
o2 m2 m2 o2 m2
r 1 1
R .
1 r g 1 g r g
= = ~
+ +
(6-43)
In the hope of fostering clarity, the passband values of the effective forward
transconductance and voltage gain for the common source unit in Figure (6.10) continues to be
defined by (6-38) and (6-39), respectively. The lone proviso to this declaration is that resistances
R
1
and R
2
in (6-37) through (6-39) are now given by either the exact or approximate forms in
(6-42) and (6-43).
6.3.3.3. Diode-Connected Degeneration And Load
The diode-connected transistor strategy invoked to bias the input port of a common
source amplifier can be applied to the source degeneration resistance, R
ss
, and the load resistance,
R
l
, as we postulate in Figure (6.12). In this diagram, which displays only simplified, battery-dri-
ven input port biasing, the source degeneration resistance in the amplifier of Figure (6.1a) is rea-
lized by the diode-connected transistor Ms, whose gate aspect ratio is
s
. Similarly, load resis-
tance R
l
is synthesized by transistor Ml, whose gate aspect ratio is taken as
l
. Appealing to the
diode-connected transistor results we disclosed in the preceding subsection, we understand that
in the amplifier under present consideration,

Figure (6.12). The amplifier in Figure (6.3) with the source degeneration
resistance, R
ss
, replaced by transistor Ms and the drain load
resistance, R
l
, supplanted by transistor Ml.
( )
( ) ( ) ( )
os
ss
os ms ms os ms
ol
l
ol bl ml bl ml ol ml
r 1 1
R
1 r g 1 g r g
.
r 1 1
R
1 r 1 g 1 1 g r g
= = ~
+ +
= = ~
+ + + +
(6-44)
+
V
gg

R
is
R
os
R
out
R
s
V
s
+V
dd
V
o
I
d
V
i
Ms
Ml
R
l
R
ss
M

- 523 -
It follows that the resultant effective transconductance and voltage gain metrics derive directly
from (6-15) and (6-23) into which we need only to substitute the foregoing expressions for R
ss

and R
l
. The interim results are
( )
ms o
m
ms o m
me
m
b m o
ms
ms o
g r
g
1 g r g
g
g
1 g r
1
1
g
1 g r
| |
|
+
\ .
= ~
+
+
+
+
(6-45)
and
( )
m os
ml
os ol
vs me os
m
s bl ml ol
ms
1
g R
g
V r
A g R .
g
V 1 1 g r
1
g
| |
|
|
(
\ .
= = ~ (
+ +
(
+
(6-46)
By (6-21) and (6-22), the output resistance, R
os
in (6-46), seen looking into the drain of transistor
M in Figure (6.12) is now given by
( )
os os m o
os b m o
ms os ms os ms
r r g r
R 1 1 g r .
1 g r 1 g r g
( | |
= + + + ~
( |
+ +
\ .
(6-47)
It is interesting to examine the gain expression in (6-46) from the perspective that out-
put resistance R
os
is likely to be appreciably larger than the inverse of the transconductance, g
ml
,
presented to the drain of driver transistor M by the diode-connected load device, transistor Ml.
With R
os
>> (1/g
ml
), (6-46) reduces to the approximate form,
m
os ml
vs
m
s
ms
g
V g
A .
g
V
1
g
= ~
+
(6-48)
We note, however, that the quiescent drain current, I
dQ
, flowing in transistor M is identical to the
Q-point drain current conducted by both transistors Ms and Ml. Since all transistors are fabri-
cated on the same monolithic chip, all of these devices have nominally identical transconduc-
tance coefficients, K
n
. Indeed, the three transistors in the schematic diagram of Figure (6.12) dif-
fer to first order only with respect to their gate aspect ratios, which are chosen by the circuit
designer. Remembering that transistors Ms and Ml have gate aspect ratios of
s
and
l
, respec-
tively, and taking as the gate aspect ratio of transistor M, (6-1) stipulates the pertinent forward
transconductances of these devices as
ms n s dQ
ml n l dQ
m n dQ
g 2K I
g 2K I .
g 2K I
~
~
~
(6-49)
We now see that the ratio of any two of these transistor transconductances is simply the square
root ratio of their corresponding gate aspect ratios. It follows that (6-48) can be expressed as
l os m ml
vs
s m ms s s
V g g
A .
V 1 g g 1
= ~ ~
+ +
(6-50)

- 524 -
This result is interesting in that gate aspect ratios, and especially ratios of gate aspect ratios, can
be controlled very accurately during chip fabrication. Accordingly, the gain of the amplifier at
hand is predictable and reliable since performance predictability usually reflects operational
stability and reliability. We should also note that the voltage gain in (6-50) is obviously smaller
than the square root ratio of driver to load gate aspect ratios because of the deployment of source
degeneration in the form of transistor Ms. Since a prime motivation underlying the use of source
degeneration is the reduction of performance sensitivity to ill-defined and ill-controlled transistor
parameters, this degeneration in the circuit of Figure (6.12) is superfluous. If the source terminal
of transistor M were grounded by implementing R
ss
= 0 in Figure (6.3a), the effect is, by (6-44),
an infinitely large g
ms
, as is projected by the modified amplifier in Figure (6.13). It follows that
the resultant small signal voltage gain at low to moderate signal frequencies is

Figure (6.13). The actively loaded common source amplifier of Figure
(6.12) operated without source degeneration.
os m
vs
s ml l
V g
A .
V g
= ~ ~ (6-51)
which obviously still exudes numerical predictability.
Yet another aspect of the amplifiers in Figures (6.12) and (6.13) is the apparent fact that
with the drain load resistance emulated actively by a diode-connected transistor, the load actually
driven by the amplifier is not connected in series with the drain circuit of transistor M. Instead,
the load is external to the amplifier and is connected, perhaps with capacitive coupling, from the
drain node of transistor M to ground. To this end, the amplifiers in either of the two aforemen-
tioned figures are decent voltage amplifiers because the output resistance, R
out
, seen looking back
toward the drain node of transistor M can be relatively small. This resistance is the parallel
combination of the resistance seen south of the drain node and that seen north of the load.
Specifically,
out os l
ml
1
R R R ,
g
= ~ (6-52)
where use is made of an earlier observation that R
os
in (6-47) is large and R
l
in (6-44) is approx-
imately the inverse of the forward transconductance associated with the load transistor. To the
+
V
gg

R
is
R
os
R
out
R
s
V
s
+V
dd
V
o
I
d
V
i
Ml
R
l
M

- 525 -
extent that the gate aspect ratio of the load device is large, and/or at least a moderate amount of
drain current is allowed to flow through transistor Ml, g
ml
is relatively large, whence a the
reasonably small output resistance that befits a practical voltage amplifier.
6.3.3.4. CMOS Amplifier
Yet another variant of the canonic common source amplifier is the complementary
MOSFET, or CMOS structure displayed in Figure (6.14a). This classic CMOS topology enjoys
widespread utility in operational amplifiers and in other applications that require very high open
loop (meaning prior to the incorporation of feedback) voltage gains. It is termed a complemen-
tary MOSFET stage because of the use of both an n-channel device (transistor Mn in the figure)
and a p-channel transistor (transistor Mp). No source degeneration is invoked since resistances
inserted in the source lead of the NMOS driver degenerate the available voltage gain of the stage.
This compromised gain defeats the primary purpose of CMOS signal processing, which is the
realization of very high I/O gain. We note that the PMOS gate terminal is connected to a con-
stant biasing voltage, V
bias
, which means that the gate of transistor Mp in Figure (6.14a) lies at
signal ground in the small signal equivalent circuit. Both the source and bulk terminals of Mp
are likewise signal grounded through the constant power bus voltage, V
dd
. We therefore recog-
nize that for small, low frequency signals, transistor Mp effectively functions as a straightfor-
ward resistive load imposed on the drain of transistor Mn. In effect, transistor Mp functions as
an active equivalent to the drain load resistance, R
l
, used in the amplifier of Figure (6.3a).

Figure (6.14). (a). CMOS common source amplifier. The amplifier utilizes a PMOS transistor to synthesize
the drain load resistance in which the NMOS transistor is terminated. (b). Low frequency, small
signal model of transistor Mp in the circuit of (a).
We can confirm, trough an inspection of the small signal model provided in Figure
(6.14b), that the value of effective load resistance R
l
is the channel resistance, r
op
, of transistor
Mp. We should once again take special note of the fact that the model for the PMOS transistor is
identical to the model used to analyze the small signal performance of NMOS devices. Since the
signal component, V
a
, of the gate-source voltage applied to Mp is zero by virtue of the fact that
the gate and source terminals of this transistor are incident with signal ground, g
mp
V
a
in this
+
V
gg

R
is
R
os
R
s
V
s
+V
dd
V
o
I
d
V
i
(a).
g V
mp a

bp mp b
g V r
op
V = 0
a
V = 0
b
R
l
V
bias
R
l
Mp Drain
Mp Source
Mp Bulk
Mp Gate
Mn
Mp
(b).

- 526 -
model is zero. Similarly, the bulk transconductance generator,
bp
g
mp
V
b
is zero because bulk-
source signal voltage V
b
is forced to zero by virtue of the fact that both the bulk and source
terminals are incident with signal ground. Resultantly, only the channel resistance, r
op
, remains
unscathed in the PMOS small signal model. This channel resistance is upwards of several thou-
sand to even several tens of thousands of ohms. Such a large resistance value for a passive ver-
sion of the drain load in Figure (6.3a) is impractical because of biasing constraints. To wit, if R
l

= 10 K, a mere 1 mA of Q-point drain current conducted by the NMOS device requires a power
line voltage, V
dd
, in excess of 10 volts since V
dd
must supply energy to both load resistance R
l
and
the NMOS device. But in the active PMOS load realization of Figure (6.14a), the voltage drop
across transistor Mp need only be slightly larger than the source saturation voltage, which for
small geometry transistors, is typically of the order of less than several tenths of a volt. In effect,
the CMOS amplifier lets us eat our cake, in the form of a very large load resistance, embellished
by that good chocolate icing spread over the cake as only a relatively small power line voltage.
A stipulation of the voltage gain provided by the CMOS amplifier involves little more
than a reinterpretation of (6-15), (6-21), and (6-23), which define basic common source perfor-
mance metrics in generalized terms. For example, since the source degeneration resistance, R
ss
,
is zero in the network of Figure (6.14a), (6-15) confirms an effective forward transconductance
that is identical to the transconductance, g
mn
, of the NMOS driver used in the basic CMOS stage.
Additionally, (6-21) shows that the low frequency resistance seen looking into the drain of a
common source amplifier that exploits no source degeneration is simply the channel resistance,
r
on
of the NMOS driver; that is, R
os
= r
on
. Then, from (6-23), the low frequency, small signal
voltage gain, A
vs
, of the CMOS stage follows as
( )
os
vs mn on op
s
V
A g r r .
V
= = (6-53)
where we have made use of the fact that the effective load resistance imposed by the PMOS
transistor on the drain of the n-channel driver is r
op
.
While the small signal analysis of the CMOS stage is straightforward, its biasing can
pose a daunting challenge. A necessary design condition under standby, or quiescent, operating
conditions is that transistor Mn operates in saturation. Accordingly, its static drain-source vol-
tage, which is V
oQ
, must be at least as large as its applied static gate-source voltage, which is V
gg
,
less an NMOS threshold potential, say V
hn
; that is,
oQ gg hn
V V V . > (6-54)
In order for the PMOS device to function in its saturation domain,
dd oQ dd bias hp
V V V V V , > (6-55)
where V
hp
represents the threshold voltage of transistor Mp. We note that (6-55) equates to the
inequality,
oQ bias hp
V V V . s + (6-56)
A comparison of (6-56) with (6-55) underscores the necessity of sustaining a Q-point voltage at
the output port that lies in the generally narrow range (particularly if V
gg
V
bias
) that spans one
NMOS threshold voltage below V
gg
to one PMOS threshold voltage above V
bias
. This range of
allowable Q-point voltage essentially brackets the maximum permissible dynamic range, or
swing, of the output signal response, V
os
.
Setting an output Q-point voltage reliably and predictably to an appropriate value that
satisfies both (6-55) and (6-56) is hardly a trivial design task. The problem stems from the fact

- 527 -
that to the extent that channel length modulation phenomena are negligible, the PMOS transistor
acts as an ideal quiescent source-drain current source that is placed in series with an ideal quies-
cent drain-source current sink postured by the n-channel transistor. Specifically, for the p-chan-
nel transistor,
( )
2
p
dQ p dd bias hp
K
I V V V ,
2
| |
=
|
\ .
(6-57)
while for the n-channel device,
( )
2
n
dQ n gg hn
K
I V V ,
2
| |
=
|
\ .
(6-58)
where
p
and
n
are the gate aspect ratios of transistor Mp and transistor Mn, respectively. We
observe that these two relationships are independent of the quiescent output voltage, V
oQ
, which
means that equating these two expressions fails to define a value of V
oQ
. Precisely the same
problem pervades the CMOS cell examined in Example #6.1. The problem at hand is akin to the
insoluble trickery that we abstract in Figure (6.15). In this problem, the neophyte circuits student
is directed to determine the voltage, V
oQ
, across an ideal current source (I
dQ
) that is placed in se-
ries with a second current source, necessarily having the same current value of I
dQ
. The series
connection of these two idealized current sources is driven by a known voltage source, V
dd
. Be-
fore the frustrated student striving to solve the problem contemplates something rash, we remind
him or her that since the current conducted by an ideal current source (or sink) is independent of
the voltage developed across the terminals of the source or sink, the problem assigned cannot be
solved. In other words, the values of the constant currents ideally has nothing to do with their
respective terminal voltages. From an algebraic perspective, insolubility derives from an
indeterminate voltage divider ratio. Since both of the ideal current sources in the network
representation of Figure (6.15) have infinitely large terminal resistances, the pertinent divider
relationship is V
oQ
= [/( + )]V
dd
, which is indeterminate and certainly not necessarily equal
to V
dd
/2.

Figure (6.15). Illustration of the output port biasing problem
in the CMOS amplifier of Figure (6.14a).
It is one thing to pull a nasty trick of an unsuspecting circuits student. It is quite
another thing to circumvent the problem pragmatically with circuit hardware. To this end, a
strategy involving the use of common mode feedback is typically exploited. In this design ap-
proach, a replica of the CMOS stage is incorporated as a means of monitoring a linear function
I
dQ
I
dQ
V
oQ
+V
dd
Drain Current of
p-Channel Transistor
Drain Current of
n-Channel Transistor
Mp & Mn Drain Node

- 528 -
of the desired Q-point output voltage. This measured voltage is compared to a reference voltage,
whose value is the desired Q-point output voltage. The response to the difference between moni-
tored and reference voltages is appropriately applied to the CMOS stage through a high loop gain
feedback topology to achieve the desired static output. We shall reserve the detailed discussion
of common mode and other relevant feedback issues for later in this text.
EXAMPLE #6.1:
A commonly used alternative to the classic CMOS common source
architecture is the network that appears in Figure (6.16). In this alternative
topology, we note that the source signal and the gate biasing voltage are
common to the gate terminals of both the PMOS and the NMOS
transistors. This means that only one voltage source, V
gg
, is required to
bias both transistor gates, as opposed to the two sources, V
bias
and V
gg
,
which are deployed in the circuit of Figure (6.14a).

Figure (6.16). An alternative form of the CMOS common
source amplifier shown in Figure (6.14a).
Derive expressions for the small signal voltage gain, A
vs
= V
os
/V
s
, and the
indicated output resistance, R
out
of the alternative CMOS circuit. Take the
source resistance as R
s
= 50 . In addition, give the general conditions
that confine both transistors in the CMOS network to their saturation do-
mains under static operating conditions. Finally, use Tables (6.1) and
(6.2), which delineate Level 49 SPICE parameters for complementary 180
nM technology CMOS transistors, to execute a static (low frequency)
SPICE simulation sweep of output voltage response V
o
-versus- input sig-
nal amplitude V
s
. Such a sweep is commonly referred to in the literature
as an I/O describing function. For this simulation, take V
dd
= 3.5 volts, as-
sume the gate aspect ratios of both transistors are 25, and set V
gg
to a vol-
tage value that is commensurate with maximum output voltage swing. Fi-
nally, adjust the gate aspect ratio of transistor Mp so that the static output
voltage is about V
dd
/2.
+
V
gg

R
is
R
os
R
s
V
s
+V
dd
V
o
I
d
V
i
R
l
Mn
Mp
R
out

- 529 -
.MODEL CMOSN NMOS (LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3627858
+K1 = 0.5873035 K2 = 4.793052m K3 = 1m
+K3B = 2.2736112 W0 = 1E-7 NLX = 1.675684E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.7838401 DVT1 = 0.5354277 DVT2 = -1.243646E-3
+U0 = 263.3294995 UA = -1.359749E-9 UB = 2.250116E-18
+UC = 5.204485E-11 VSAT = 1.083427E5 A0 = 2
+AGS = 0.4289385 B0 = -6.378671E-9 B1 = -1E-7
+KETA = -0.0127717 A1 = 5.347644E-4 A2 = 0.8370202
+RDSW = 150 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 1.798714E-9 LINT = 7.631769E-9
+XL = -2E-8 XW = -1E-8 DWG = -3.268901E-9
+DWB = 7.685893E-9 VOFF = -0.0882278 NFACTOR = 2.5
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.455162E-3 ETAB = 1
+DSUB = 0.0173531 PCLM = 0.7303352 PDIBLC1 = 0.2246297
+PDIBLC2 = 2.220529E-3 PDIBLCB = -0.1 DROUT = 0.7685422
+PSCBE1 = 8.697563E9 PSCBE2 = 5E-10 PVAG = 0
+DELTA = 0.01 RSH = 6.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.16E-10 CGSO = 7.16E-10 CGBO = 1E-12
+CJ = 9.725711E-4 PB = 0.7300537 MJ = 0.365507
+CJSW = 2.604808E-10 PBSW = 0.4 MJSW = 0.1
+CJSWG = 3.3E-10 PBSWG = 0.4 MJSWG = 0.1
+CF = 0 PVTH0 = 4.289276E-4 PRDSW = -4.2003751
+PK2 = -4.920718E-4 WKETA = 6.938214E-4 LKETA = -0.0118628
+PU0 = 24.2772783 PUA = 9.138642E-11 PUB = 0
+PVSAT = 1.680804E3 PETA0 = 2.44792E-6 PKETA = 4.537962E-5)
Table (6.1). SPICE Level 49 parameters for an NMOS MOSFET having a drawn channel
length of 180 nM. This transistor is nominally complementary to the PMOS
transistor whose parameters are given in Table (6.2).
.MODEL CMOSP PMOS (LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4064886
+K1 = 0.5499001 K2 = 0.0389453 K3 = 0
+K3B = 11.4951756 W0 = 1E-6 NLX = 9.143209E-8
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.5449299 DVT1 = 0.3160821 DVT2 = 0.1
+U0 = 117.9612996 UA = 1.64867E-9 UB = 1.165056E-21
+UC = -1E-10 VSAT = 2E5 A0 = 1.7833459
+AGS = 0.407511 B0 = 1.314603E-6 B1 = 5E-6
+KETA = 0.0137171 A1 = 0.4610527 A2 = 0.6597363
+RDSW = 364.9443889 PRWG = 0.5 PRWB = -0.1129203
+WR = 1 WINT = 0 LINT = 2.007556E-8
+XL = -2E-8 XW = -1E-8 DWG = -2.835566E-8
+DWB = 8.003075E-9 VOFF = -0.1064646 NFACTOR = 2
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0141703 ETAB = -0.0398356
+DSUB = 0.4441401 PCLM = 2.2364512 PDIBLC1 = 9.167645E-4
+PDIBLC2 = 0.0209189 PDIBLCB = -9.568266E-4 DROUT = 9.976778E-4
+PSCBE1 = 1.731161E9 PSCBE2 = 5E-10 PVAG = 14.337819
+DELTA = 0.01 RSH = 7.5 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9

- 530 -
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.79E-10 CGSO = 6.79E-10 CGBO = 1E-12
+CJ = 1.176396E-3 PB = 0.8607121 MJ = 0.4163285
+CJSW = 2.135953E-10 PBSW = 0.6430918 MJSW = 0.2654457
+CJSWG = 4.22E-10 PBSWG = 0.6430918 MJSWG = 0.2654457
+CF = 0 PVTH0 = 4.364418E-3 PRDSW = 4.4192048
+PK2 = 3.104478E-3 WKETA = 0.0270296 LKETA = 2.038008E-3
+PU0 = -2.3639825 PUA = -8.41675E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.444802E-3)
Table (6.2). SPICE Level 49 parameters for an NMOS MOSFET having a drawn channel
length of 180 nM. This transistor is nominally complementary to the PMOS
transistor whose parameters are given in Table (6.2).
SOLUTION #6.1:
(1). The common connection of the signal source to both gates means that the resultant output
signal response effectively reflects a superposition of the small signal dynamics associated
with two common source amplifiers. This superposition strategy is highlighted in Figure
(6.17a). In this diagram, we allow for two independent signal sources, V
s1
and V
s2
, although
the reality is that V
s1
= V
s2
= V
s
. And as we see in Figure (6.17b), superposition facilitates
our witnessing an NMOS common source amplifier loaded in an active p-channel load com-
bined with a PMOS common source amplifier terminated at its drain in an active n-channel
load. From Figure (6.17a), the contribution, V
osn
, of the NMOS device to the total output re-
sponse is
( ) ( ) osn mn 1 on op mn on op s1
V g V r r g r r V . = = (E1-1)
Analogously, we deduce for the PMOS component,
( ) ( ) osp mp 2 op on mn on op s2
V g V r r g r r V . = = (E1-2)
Since V
s1
= V
s2
= V
s
and the output voltage, V
os
, is the superposition of signal voltages V
osn

and V
osp
, we find that the voltage gain, A
vs
, of the alternative common source CMOS am-
plifier is
( )( )
os
vs mn mp on op
s
V
A g g r r .
V
= = +
(E1-3)
(2). An inspection of the schematic diagram in Figure (6.17a) indicates that the output resistance,
R
out
, is the shunt interconnection of effective resistance R
os
and effective resistance R
l
. From
Figure (6.17b), we observe that R
os
is the drain-source channel resistance, r
on
, of the NMOS
device, while R
l
is the PMOS counterpart, r
op
, to r
on
. We therefore have
out on op
R r r . =
(E1-4)
(3). Under quiescent operating conditions, the gates of both transistors conduct no current.
Accordingly, the standby gate-source voltage applied to transistor Mn is V
gg
, while the static
source-gate potential on transistor Mp is (V
dd
V
gg
). In order to enable conduction in each of
the two transistors, we require
gg hn
gg dd hp
V V for NMOS conduction
.
V V V for PMOS conduction
>
s
(E1-5)
These conduction requirements are generally easy to satisfy.

- 531 -

Figure (6.17). (a). Small signal partitioning of the CMOS amplifier in Figure (6.16), wherein independent sig-
nal sources, V
s1
and V
s2
are applied to the NMOS and PMOS gate terminals, respectively. Vol-
tages V
s1
and V
s2
are identical to the originally applied single signal voltage, V
s
in Figure (6.16).
(b). The low frequency small signal model of the network in (a), in which classic superposition
theory is exploited.
The saturation of both transistors comprises a potentially more significant challenge. If
transistor Mn is to operate in its saturation regime, we require V
oQ
(V
gg
V
hn
). On the other
hand, the saturation of transistor Mp requires (V
dd
V
oQ
) (V
dd
V
gg
V
hp
). Therefore, we
summarize by asserting that both transistors are saturated if
oQ gg hn
oQ gg hp
V V V , for transistor Mn
.
V V V , for transistor Mp
>
s +
(E1-6)
In effect, (E1-6) defines the allowable output voltage swing that confines both transistors to
their saturation domains. In particular, the largest permissible output voltage is V
omax
= (V
gg

+ V
hp
), while the smallest permissible output response is V
omin
= (V
gg
V
hn
). Thus, the
allowable peak-to-peak output signal swing is (V
omax
V
omin
) = (V
hp
+ V
hn
). In order to en-
sure that this output signal excursion is confined to a reasonably linear segment of the static
+
+
+

V
gg

R
is2
R
is1
R
os
R
os
R
is1
R
s
R
s
R
s
V
s
2
V
s
1
V
s
1
+V
dd
V
o
I
d
V
i2
V
i1
R
l
Mn
Mp
R
out
(a).
r
op
g V
mn 1
V
1
V
osn
R
l
R
is2 R
s
V
s
2
r
on
g V
mp 2
V
2
V
osp
+
V
os
(b).
r
on
r
op
R
out
+

- 532 -
I/O characteristic transfer, or describing function, V
oQ
, which is the quiescent, or zero signal,
value of the output voltage response, is commonly set to one-half of V
dd
. We note that the
allowable voltage swing at the output port is somewhat restricted since threshold potentials in
deep submicron transistors are of the order of a 500 mV or less.
(4). The SPICE simulation of the static I/O describing function is provided in Figure (6.18). Two
preliminary analytical steps have been exercised before finalizing this graphical display.

Figure (6.18). The simulated static I/O describing function for the CMOS am-
plifier diagrammed in Figure (6.16). The darkened segment of the
curve identifies the nominal range of I/O linearity.
(a). The simulated static sweep of output voltage V
o
versus applied gate voltage V
gg
was ex-
ecuted with the gate aspect ratios of both the PMOS device and the NMOS transistor set
to 25. The resultant, nominally linear, range of this V
o
versus V
gg
describing function was
found to reside in the gate voltage interval, 1.36 V V
gg
1.435 V, which is in one-to-one
correspondence to the output voltage range, 0.819 V V
oQ
2.011 V. We then deter-
mined the centroid of the gate voltage range to be V
gg
= 1.3975 V, which corresponds to a
static output voltage centroid of V
oQ
= 1.415 V.
(b). Since the quiescent output voltage corresponding to the linear operational range dis-
cerned in (a) is below the V
dd
/2 = 1.750 V target, we must adjust the gate aspect ratios of
one or both of the transistors in the modified CMOS common source amplifier. In accor-
dance with the problem statement, we elect to adjust the gate aspect ratio of PMOS de-
vice MP in Figure (6.16). An arguably systematic, but somewhat arbitrary, analytical
scheme, is to fix voltage V
gg
to the centroidal value, 1.3975 V deduced in the preceding
analytical step. After a few iterations, we find that a PMOS gate width of 4.681 M,
which corresponds to an MP gate aspect ratio of 26.01, delivers V
oQ
= 1.75V when V
gg
is
held fast at V
gg
= 1.3975 V.
The simulated static I/O describing function depicted in Figure (6.18) indeed invokes an
NMOS gate aspect ratio of 25 and a PMOS gate aspect ratio of 26.01; the channel lengths of
both transistors remains equal to 180 nM. The curve is significantly nonlinear, but nonethe-
less, we are able to identify an approximate interval of apparent linearity. We indicate this
region as the heavily lined segment for which the gate voltage range is 1.380 V V
gg
1.455
V, and the corresponding output voltage interval is 0.793 V V
oQ
1.987. The center of this
output voltage range is V
oQ
= 1.390 V, which clearly is not the established Q-point level of
Gate Bias Voltage, (volts) V
gg
S
t
a
t
i
c

O
u
t
p
u
t

V
o
l
t
a
g
e
,

(
v
o
l
t
s
)
V
o
Q
0
1
2
3
4
0 0.5 1.0 1.5 2.0 2.5 3.0
V = 1.380 V; V = 1.987 V
gg o
V = 1.455 V; V = 0.793 V
gg o
x
x

- 533 -
1.75 V. This disparity suggests that the segment we have indicated as linear is far from
reflecting perfect linearity. We can sustain the 1.75 V output level, which is realized with V
gg

1.398 V or, we can adjust V
gg
until V
oQ
drops to 1.390 V. We opt for the former, but in the
interest of completeness, we find that V
oQ
1.39 V if V
gg
1.419 V.
(5). At the operating point pinned by (V
gg
, V
oQ
) (1.398 V, 1.75 V), SPICE delivers the operating
point and small signal metrics itemized in Table (6.3). SPICE also delivers a low frequency
voltage gain of A
vs
= 15.07 volts/volt, and an approximate 3-dB bandwidth of 2.96 GHz. If
we insert the relevant tabularized data into (E1-3), we compute a small signal voltage gain of
15.08, which is in excellent agreement with the simulated gain result. The quoted band-
width is likely highly optimistic for we have not attempted to account for input and output
port parasitic capacitances.
DESCRIPTION SYMBOL VALUE UNITS
Q-Point Drain Current I
dQ

1.591 mA
Gate Bias V
gg

1.3975 V
Output Q-Point V
oQ

1.75 V
NMOS Threshold V
hn

511.3 mV
PMOS Threshold V
hp

486.7 mV
NMOS Forward Transconductance g
mn

2.160 mmho
PMOS Forward Transconductance g
mp

1.295 mmho
NMOS Drain-Source Channel Resistance r
on

9.643 K
PMOS Drain-Source Channel Resistance r
op

7.974 K

Table (6.3). Simulated values of the quiescent and small signal metrics for the CMOS amplifier given in
Figure (6.16).
ENGINEERING COMMENTARY:
This example offers several learning opportunities. The first of these is that the magnitude of
the low frequency voltage gain is doubtlessly larger than would be the gain magnitude if the
CMOS stage were biased in the conventional fashion depicted in Figure (6.14a). The reason
for this embellished gain is that in the current example, the gain postured at the amplifier out-
put port is effectively the superposition of two CMOS stages. In particular, the gain superim-
poses the gain of an NMOS unit driving a PMOS load with the gain of a PMOS device driv-
ing an NMOS load. This enhanced gain is a laudable attribute for deep submicron transistors
that unfortunately deliver anemic forward transconductances for reasonable quiescent drain
currents.
Recalling (E1-6), the output signal swing commensurate with maintaining both transistors in
saturation is (V
hn
+ V
hp
), which, by Table (6.3), computes as 998 mV. In contrast, the output
signal swing corresponding to the nominally linear range underscored in Figure (6.18) is
1.194 V. While this 19.6 % difference is sizeable, it is less than surprising for two reasons.
First, the signal swing computed analytically is predicated on maintaining both transistors in
saturation, while the highlighted segment in Figure (6.18) derives from only a qualitative
observation of reasonable linearity. Second, our analysis derives from a simple Schichman-
Hodges model, whose accuracy cannot match that of the Level 49 SPICE model, which ex-
ploits more than 100 parameters. Presumably, this explosion of largely curve fit model
parameters accounts for most, if not all, of the high order phenomena that Schichman-Hodges
throws under the proverbial bus in the interest of preserving manual analytical sanity.
We have already warned of the difficulty in biasing the CMOS structure without making
appropriate use of feedback or some other form of control strategy. Our adjustment of the

- 534 -
gate aspect ratio for the PMOS device to effect the proper output port Q-point attests to this
difficulty. In particular, the static output port voltage is V
oQ
= 1.415 V for V
gg
= 1.3975 V and
a PMOS gate aspect ratio of 25. By increasing this gate aspect ratio by a mere 4.02% to
26.01, while sustaining V
gg
= 1.3975 V, we succeed in raising the output voltage to 1.75 V,
which reflects an almost 23.7% increase. Clearly, only a small parametric change is required
to effect a significant change in observable performance. It is hardly a leap of proverbial
faith to rationalize that any parametric change in one of the two utilized transistors, as op-
posed to only a gate width alteration in the PMOS transistor, can result in analogous output
port sensitivities. Accordingly, design care must indeed be exercised if we are to experience
engineering satisfaction with the CMOS amplifier.
6.4.0. COMMON DRAIN AMPLIFIER
The foundational schematic diagram of an NMOS common drain amplifier, which is
also known as a source follower, is drawn in Figure (6.19a). Its PMOS counterpart appears in
Figure (6.15b). In the source follower, the input signal is applied to the gate terminal of the uti-
lized transistor, while the output response, which is traditionally a signal voltage, is extracted at
the transistor source terminal. As in the common source amplifier, the power line voltage, V
dd
,
and the gate biasing voltage, V
gg
, are selected to ensure that the transistor operates in its satura-
tion domain for all anticipated amplitudes of the signal voltage, V
s
. But unlike the common
source stage, the source follower is rarely advanced as a standalone amplifier. Instead, it is fre-
quently used in conjunction with a common source amplifier that is tasked to deliver gain to a
strongly capacitive load at high signal frequencies or more generally, any low impedance load.
As such, the source follower serves as a buffer inserted between the output port of a common
source amplifier and the load. In a buffering application, voltage V
gg
ordinarily derives from the
output Q-point voltage of the predecessor common source amplifier.

Figure (6.19). (a). Simplified schematic diagram of a common drain amplifier realized with an
NMOS transistor. (b). The PMOS counterpart to the NMOS source follower in (a).
We recall that an ideal voltage buffer boasts unity I/O voltage gain, infinitely large in-
put impedance, and zero output impedance. The source follower is hardly an ideal buffer, but it
does serve as a practical voltage buffer in a myriad of electronic systems. We can therefore infer
+
V
gg

R
id
R
od
R
od
R
l
R
s
V
s
+V
dd
V
o
V
o
V
i
(a).
+
V
gg

R
id
R
l
R
s
V
s
+V
dd
V
i
(b).

- 535 -
that the MOSFET source follower boasts near unity voltage gain, a large input impedance, and a
low output impedance. An inspection of either schematic diagram in Figure (6.19) confirms that
for low to moderately high frequencies, the input resistance, R
id
, of a common drain amplifier is
infinitely large, since the input port is the gate terminal of the utilized transistor. We might ha-
zard a guess that the output resistance, R
od
, is low at least at low signal frequencies, since the out-
put port is formed by the source terminal of the transistor and signal ground. We offer this
contention in light of our earlier work with diode-connected transistors, where we witnessed a
small resistance of approximately 1/g
m
presented at its source terminal. If a relatively small out-
put resistance prevails for the source follower, it makes sense to represent the follower output
port by a Thvenin equivalent circuit.
6.4.1. SMALL SIGNAL ANALYSIS
With load resistance, R
l
removed, as befits the development of a Thvenin equivalent
circuit, the low frequency, small signal model of either of the two source followers diagrammed
in Figure (6.19) appears as the network in Figure (6.20). For clarity, the transistor gate, drain,
source, and bulk nodes are labeled by the italicized boldface letters, G, D, S, and B, respectively.
Under the condition of an open circuited load termination, the response established at the source
terminal is not the signal component, V
os
, of the net output voltage, V
o
, but instead, it is the
Thvenin, or open circuit, output signal voltage, V
ot
. The Thvenin resistance established at the
source port is indeed the output resistance, R
od
, in which we are interested. We can succumb to a
crank and grind circuit analysis strategy to deduce expressions for V
ot
and R
od
. Or we can be a
bit more creative and reduce the model in question to a simplified topological structure that in-
spires insights of relevant circuit dynamics. Guess which approach we shall adopt. The creative
analytical strategy facilitates our ability to deduce first order electronic network responses
through mere engineering inspection that requires little, if any, algebraic effort.

Figure (6.20). Low frequency, small signal model of either of the source follower
networks appearing in Figure (6.19).
We begin by observing in Figure (6.20) that the gate-source signal voltage, V
1
, is the
signal voltage difference, (V
s
V
ot
). Our astuteness resultantly leads to
m 1 m s m ot
g V g V g V , = (6-58)
which implies that the controlled current, g
m
V
1
, flowing from the drain terminal of the transistor
to its source terminal, where voltage V
ot
is sustained, can be viewed as the shunt interconnection
of two controlled currents. One of these currents is g
m
V
s
, which flows from drain to source; that
is, in the same direction as does the original g
m
V
1
. Because of the minus sign on the right hand
+
g V
m 1

b m 2
g V r
o
R
s
V
s
V
1
V
2
V
ot
R
id
R
od
G
D
S
B

- 536 -
side of (6-58), the other current, g
m
V
ot
, is directed from source to drain, opposite to the flow of
g
m
V
1
. These observations are portrayed schematically as Step 1 in the modeling diagram of Fig-
ure (6.21a). But since voltage V
ot
appears directly across, and in associated reference polarity
with, the controlled current, g
m
V
ot
, current g
m
V
ot
can be supplanted, as suggested in Step 2 of Fig-
ure (6.21a), by a simple branch resistance of value 1/g
m
. We note that the current flowing though
this resistive branch is indeed g
m
V
ot
, identical to the current value of the controlled source it rep-
laces. In Step 3 of Figure (6.21a), we simply redraw the outcome of the preceding modeling step
to depict the source terminal at the top of the modeling topology. This source node supports
open circuit voltage V
ot
, which is established with respect to drain signal ground,

Figure (6.21). (a). Replacement of the voltage controlled current source, g
m
V
1
, in the model of Figure (6.20) by
a controlled source, g
m
V
s
shunted by a branch resistance of value 1/g
m
. (b). Replacement of the
controlled source,
b
g
m
V
2
, in the source follower model of Figure (6.20) by a branch resistance
of value 1/
b
g
m
. (c). Simplified model for the open circuited output port of the source follower
whose equivalent circuit appears in Figure (6.20).
Returning to Figure (6.20), we observe that the bulk-source signal voltage, V
2
, is pre-
cisely the negative of voltage V
ot
. Thus, the
b
g
m
V
2
source, whose current flows from drain to
source, is equivalent to a current,
b
g
m
V
ot
, directed from source to drain, as illustrated in Step 1 of
Figure (6.21b). Step 2 in this diagram is a trivial redraw of the result of Step 1, wherein we see
that voltage V
ot
appears directly across the subject generator. Step 3 follows naturally in that the
b
g
m
V
ot
generator in the outcome of modeling Step 2 can be represented electrically as a branch
resistance whose value is 1/
b
g
m
.
We can correlate the foregoing two disclosures with the output port of the general
model given in Figure (6.20) to arrive at the Thvenin representation of the follower output port
we give in Figure (6.21c). This diagram straightforwardly depicts the output resistance, R
od
, as
the parallel combination of the three resistances, 1/g
m
, 1/
b
g
m
, and r
o
; namely,
g V
m 1
r
o
V
ot
R
od
D
S
1
g V
m s
g V
m s
g V
m s
g V
m s
V
ot
V
ot
V
ot
V
ot
D D S
S
S S D
D
g V
m ot
g
m
1
g
m
1
g
m
1
(a).
2 3
b m 2
g V
V
ot
D
S
1
b m ot
g V
b m ot
g V
V
ot
V
ot
V
ot
D S S
S D D
b m
g
b m
g
1
1
(b).
2 3
(c).

- 537 -
( )
o
od
b m o m
r 1
R .
1 1 g r g
= ~
+ +
(6-59)
As we suspected, this resistance approaches 1/g
m
, but only if
b
<< 1 and g
m
r
o
>> 1. The con-
straint entailing the bulk transconductance factor,
b
, is reasonable for most properly biased
MOSFETs. The second requirement, g
m
r
o
>> 1 is somewhat problematic for deep submicron
devices, which deliver anemic forward transconductances and drain-source channel resistances
for routine gate aspect ratios and reasonable biasing. In view of (6-59), the Thvenin voltage
gain, A
td
= V
ot
/V
s
, projected by the simple model in Figure (6.21c) is
( )
ot m o
td m od
s b m o
V g r
A g R ,
V 1 1 g r
= = =
+ +
(6-60)
which is clearly less than one. We do see, however, that A
td
approaches unity for the same con-
straints that validate the approximation, R
od
1/g
m
. The foregoing two results produce the
equivalent circuit shown in Figure (6.22), which represents the terminated output port of the
source follower operated at relatively low signal frequencies. This structure highlights a termi-
nated voltage gain, A
vd
= V
os
/V
s
, of

Figure (6.22). The terminated output port model, which
exploits Thvenins theorem, for either
source follower depicted in Figure (6.19).
( )
os l m o l
vd td
s l od b m o l od
V R g r R
A A .
V R R 1 1 g r R R
( | | | |
= = =
( | |
+ + + +
\ . \ .
(6-61)
Although the terminated, or actual, I/O voltage gain is less than the observed Thvenin
gain, A
td
, we note that A
vd
approaches A
td
if R
l
>> R
od
, which, by (6-59), essentially requires g
m
R
l

>> 1. Thus, the near unity Thvenin voltage gain is sustained for relatively small R
l
only insofar
that R
l
is substantially larger than 1/g
m
. To the extent that near unity voltage gain for arbitrary
load terminations is a critical design requirement, we therefore require large g
m
, which relies on
large gate aspect ratio and/or large quiescent drain current. Note further that no phase inversion
prevails between the input and output ports of the source follower. Engineering credence is lent
to the last observation by returning to either amplifier in Figure (6.19). In the NMOS circuit of
Figure (6.19a), for example, we see that an increase in the source signal voltage, V
s
, manifests an
increase in the gate-source signal voltage. In turn, this increased signal voltage spawns an in-
crease in the drain current conducted by the transistor. The fact that the drain current is dumped
into load resistance R
l
across which the signal voltage response, V
os
, is extracted confirms that
V
os
rises with increasing V
s
(and vice versa).
The lack of phase inversion, together with an I/O gain that can approach one, argues for
terming the common drain amplifier a source follower. This is to say that the source follows
the gate in the sense of producing an output voltage response that almost mirrors the signal ap-
plied at the gate input port. It nonetheless bears underscoring that when realized in deep submi-
+
A V
td s
R
l
R
od
V
os

- 538 -
cron MOS technology, the relatively anemic nature of both the forward transconductance and the
drain-source channel resistance rarely allows a Thvenin voltage gain larger than 900 mV/volt.
Moreover, the output resistance for these configurations is not near zero; instead, it is typically in
the range of high tens to several hundreds of ohms.
6.4.2. SOURCE FOLLOWER WITH ACTIVE LOAD
In order to achieve a terminated source follower gain that approaches its open circuit
value, a sufficiently large load resistance, R
l
, is obliged. Unfortunately, too large of a load resis-
tance in either of the common drain units shown in Figure (6.19) requires a commensurately
large power line voltage, V
dd
, which must supply voltage to both the load resistance and the
transistor. One way of achieving large effective R
l
without requiring a significant increase in the
power line voltage is to replace the passive load resistance, R
l
, by an active load that functions as
an approximate ideal current source or sink. An NMOS example of such a variation to the basic
follower is provided in Figure (6.23), where the load resistance in the original schematic diagram
is replaced by transistor Ml. We see that the gate of this introduced device is biased by constant
voltage, thereby resulting in null gate-source signal voltage. For this zero gate-source signal vol-
tage and the connection of both the bulk and source transistor terminals to ground, the small sig-
nal model of transistor Ml consists solely of its channel resistance, say r
ol
, which can be substan-
tial for appropriate choices of gate aspect ratio and quiescent current. In other words, Ml
approximates a constant current generator that provides a current path to ground for the source
current conducted by the follower transistor, M. We say that Ml behaves as a current sink in that
it returns the current of transistor M to ground. As such, its function is similar to the active load
transistor Mp in the CMOS amplifier of Figure (6.14a), except that Mp therein sources current
(meaning it supplies current) to the common source transistor, Mn. The resultant terminated vol-
tage gain of the actively loaded source follower derives directly from (6-61), subject to the pro-
viso that resistance R
l
in that expression is replaced by the channel resistance, r
ol
, of transistor
Ml. Moreover, the reader should be able to confirm easily that the output resistance, R
od
, remains
given by (6-59).

Figure (6.23). The NMOS source follower of Figure (6.19a)
with the passive load resistance, R
l
, replaced
by an active, current sinking load formed of
transistor Ml.
6.4.3. BUFFERED COMMON SOURCE AMPLIFIER
A meaningful example of a source follower buffering application initiates with a
+
V
gg

R
id
R
od
R
l
R
s
V
s
+V
dd
V
o
V
i
V
bias
Ml
M

- 539 -
reconsideration of the actively loaded common source amplifier shown in Figure (6.14a). This
amplifier is redrawn in Figure (6.24a), subject to the incorporation of a capacitive load, C
l
, at the
output port. The subject load capacitance can represent the input impedance of a succeeding
common source amplifier. It can also represent the input port capacitance of a data converter,
signal processor, or some other form of dominantly capacitive loading that the base amplifier
comprised of transistors Mn and Mp is compelled to drive.

Figure (6.24). (a). Common source CMOS amplifier of Figure (6.14a) with capacitive load appended.
(b). Common source amplifier of (a) with source follower buffer inserted between the
output port of the common source unit and the capacitive load.
Aside from the biasing issues discussed earlier, the problem with this CMOS amplifier
is that the 3-dB bandwidth of the stage at hand is limited by the substantial output resistance,
+
V
gg

R
is
r
on
R
s
V
s
+V
dd
V
o
I
d
V
i
(a).
V
bias
r
op
Mn
Mp
C
l
+
V
gg

R
is
r
on
R
s
V
s
+V
dd
I
d
V
i
(b).
V
bias
r
op
Mn
Mp
C
l
R
od
V
o
V
i
V
bias
Ml
M
r
ol
R
out1
R
out1

- 540 -
R
out1
, which faces capacitance C
l
. This output resistance is the parallel combination of the chan-
nel resistances, r
on
and r
op
, of the NMOS and PMOS transistors, respectively. As a result, the
bandwidth, say B
1
of the stage is, assuming that no capacitances implicit to the transistor models
are significant at frequency B
1
,
( )
1
out1 l
on op l
1 1
B .
R C
r r C
= = (6-62)
This bandwidth is potentially deficient in light of the fact that both r
on
and r
op
are reasonably
large resistances. At frequencies that are below the 3-dB bandwidth and thus, for frequencies
within the passband of the amplifier, C
l
emulates an open circuit. Resultantly, the amplifier in
Figure (6.24a) reduces to the topological form of the network in Figure (6.14a). This means that
the low frequency gain of the amplifier at hand remains given by
( )
os
vs mn on op
s
V
A g r r ,
V
= = (6-63)
where model parameter g
mn
is recalled as the forward transconductance of the n-channel transis-
tor that serves as the driver device in Figure (6.24a). It follows that the gain-bandwidth product,
GBP
s
, of the topology under current scrutiny is
s vs 1 mn l
GBP A B g C . = = (6-64)
For a fixed load capacitance, we see that the gain-bandwidth product, which we should like to
have as large as possible so that a large magnitude of passband gain and a large bandwidth are
enabled, is controlled exclusively by the transconductance of the driver. We remember that the
transconductance can be increased through increases in the transistor gate aspect ratio and/or in-
creases in the Q-point drain current. But large gate aspect ratios run the risk of magnifying
transistor capacitances to levels that challenge the presumption of a clearly dominant load
capacitance. Accordingly, large gate aspect ratios potentially compromise the accuracy of the 3-
dB bandwidth relationship in (6-62). On the other hand, large quiescent drain currents imply
possibly unacceptably large circuit power dissipation.
In order to understand how the buffer introduced in Figure (6.20b) addresses the chal-
lenge of a targeted large circuit gain-bandwidth product, we note that the load capacitance is now
incident with the output port of the source follower formed by transistor M and its source lead
load, transistor Ml. Since channel resistance r
ol
is the resistance presented to this output port by
Ml and R
od
, as given by (6-59), is the resistance seen looking into the source of transistor M, the
time constant associated with load capacitance C
l
, is simply the product of C
l
and the parallel
combination of resistances r
ol
and R
od
. Assuming that C
l
remains the dominant capacitance in
the circuit, this means that the revised 3-dB bandwidth, B
2
, is
( )
m
2
od l l ol od l
g 1 1
B ,
R C C r R C
= ~ ~ (6-65)
where g
m
symbolizes the forward transconductance of transistor M. We arrive at the final form
on the right hand side of (6-65) by tacitly presuming large channel resistances in both transistors
and negligible body effect in the source follower device, M. Under these approximate operating
conditions, the small signal gain, V
os
/V
is
, in the buffered amplifier of Figure (6.24b) is, by (6-61),
very close to unity, which means that the overall gain, V
os
/V
s
, within the passband remains the
same as stipulated by (6-63); namely, A
vs
. This assertion follows from our observation that the
output signal voltage, V
is
, developed at the drain of transistor Mn in Figure (6.20b) is essentially
an open circuit voltage in that V
is
is applied to the gate terminal of transistor M. But signal vol-
tage V
os
in Figure (6.24a), to which (6-63) pertains, is also an open circuit voltage in that the load

- 541 -
capacitance in this schematic diagram behaves as an open circuit within the passband of the am-
plifier. Consequently, the buffered gain-bandwidth product, say GBP
b
, is
( ) ( )
m
b vs 2 mn on op m on op s
l
g
GBP A B g r r g r r GBP .
C
| |
(
~ ~ ~
|

\ .
(6-66)
Obviously, the buffered gain-bandwidth product exceeds its non-buffered counterpart if
g
m
(r
on
||r
op
) > 1. For routine source follower biasing currents, the satisfaction of this inequality is
all but guaranteed if for no other reason than resistances r
on
and r
op
, which remain unaffected by
source follower biasing, are reasonably large.
Before we decide to celebrate the significant increase in gain-bandwidth product pro-
jected by (6-66), we need to demonstrate a bit of engineering caution. In particular, the result in
question is predicated on the presumption that the load capacitance, C
l
, dominantly determines
the 3-dB bandwidth of the circuit. This is to say that the time constant associated with C
l
, which
is nominally the inverse of the 3-dB circuit bandwidth, is significantly larger than the sum of all
other capacitive time constants established by the entire network. Clearly, there are four transis-
tors in the network of Figure (6.24b). Each of these transistors embraces four capacitances: gate-
source, gate-drain overlap, bulk-drain, and bulk-source capacitances. To be sure, some of these
capacitances appear across short circuits and therefore establish no individual time constants.
For example, the bulk-source capacitances of transistors Mn, Mp, and Ml give rise to null time
constants because each of these devices have their bulk and source terminals incident with signal
ground. Additionally, the bulk-drain capacitance of transistor M establishes zero time constant
because its drain and bulk terminals are connected to signal ground. Yet another null time con-
stant is that which is associated with the gate-source capacitance of Mp. In this case, the subject
time constant is zero because the Mp drain and the Mp gate terminals are grounded, assuming
that voltage reference, V
bias
is ideal. Thus, ten (10) other transistor capacitances, when scruti-
nized one at a time, produce 10 time constants, each of which act to degrade, hopefully mini-
mally, the circuit 3-dB bandwidth. At some risk of oversimplification, which is a dilemma we
shall rectify when we consider broadband amplifier design strategies later in this text, (6-66) pre-
sumes that the time constant produced by load capacitance C
l
is significantly larger than the sum
of these 10, tacitly ignored capacitive time constants. It is certainly possible to satisfy this tight
design constraint. But such satisfaction is rendered increasingly more challenging if, as we wit-
nessed when we assessed the performance of our source follower, we encounter the need for
large geometry (large gate aspect ratio) transistors.
EXAMPLE #6.2:
In the simple source follower of Figure (6.25a), all transistors operate in
their saturation domains where they boast negligible CLM and negligible
BITM. Without executing an actual small signal analysis, deduce (largely
by inspection) the low frequency, small signal voltage gain, A
v
(0) = V
os
/V
s
,
and the indicated output resistance, R
out
. What is the 3-dB bandwidth, say
B, of the amplifier if capacitance C is the dominant energy storage element
in the network?

- 542 -

Figure (6.25). (a). A source follower terminated in the active, current sinking load forged by transis-
tor M2 and its constant gate voltage biasing. (b). The schematic diagram of (a) under
exclusively signal conditions. Note that the constant voltages, V
dd
, V
gg
, and V
bias
, are
supplanted by short circuits.
SOLUTION #6.2:
(1). Until we achieve a comfort level with first order assessments of electronic circuits by inspec-
tion, it is probably best to begin by sketching the so-called AC schematic diagram for the
electronic network of interest. This diagram is the given schematic, but drawn under exclu-
sively signal conditions. To this send, the present AC schematic is offered in Figure (6.25b).
In this figure, load capacitance C is removed because of our concentration on only low fre-
quency dynamics. This action exploits the fact that at low frequencies, capacitances present
high branch impedances and therefore, they emulate open circuited branch elements. Since
the signal values of the presumably ideal (meaning zero internal Thvenin impedances) con-
stant voltage sources, V
dd
, V
gg
, and V
bias
, are zero, these sources of static energy appear as
short circuits in the AC schematic.
(2). We are told to ignore channel length modulation (CLM) and bulk-induced threshold modula-
tion (BITM). Our mental image of the small signal model for each of the transistors in the
source follower before us resultantly collapses to a single branch element. In particular, the
small signal model of each transistor has but one voltage-controlled current source, g
m
V, di-
rected from drain to source, where we understand voltage V to be the signal voltage devel-
oped from gate to source for the transistor of interest.
(a). For transistor M2, the gate-source signal voltage, V
2
, is clamped at zero because both the
gate and the source terminals of M2 are incident with circuit ground. It follows that the
drain to source controlled current, g
m2
V
2
, is zero, which means that no signal current
flows through the drain of transistor M2. More precisely, the signal component of the net
drain current conducted by transistor M2 is zero.
(b). The drain current conducted by transistor M1 is g
m1
V
1
, with V
1
representing the gate-
source signal voltage developed on transistor M1. Because essentially no gate current
flows at low signal frequencies, V
1
= (V
s
V
os
), where V
os
is the signal component of the
net output voltage, V
o
.
(c). The signal current flowing into the drain of transistor M1 flows out of the M1 source ter-
minal and therefore into the M2 drain. But we have already concluded that the signal
drain current of M2 is null. Accordingly, this null current forces g
m1
V
1
= 0. This con-
straint mandates V
1
= 0 or equivalently, V
os
= V
s
. The low frequency gain of the follower
network correspondingly follows as
+
M1
M2
R
s
V
s

V
gg

V
bias
+V
dd
V
o
C
R
out
(a).
+
M1
M2
R
s
V
s
V
os
R
out
(b).
+
V
2
0
V
o
+
g V = 0
m2 2
+
V
1
g V
m1 1

- 543 -
v os s
A (0) V V 1 . = =
(E2-1)
(3). The resistance, R
out
, presented to the output port of the follower is, as an inspection of Figure
(6.25b) confirms, the parallel combination of the resistance seen looking south into the drain
of transistor M2 and the resistance seen looking north into the source of transistor M1. But
since M2 functions as a small signal open circuit, the resistance presented to the output port
by the drain of transistor M2 is infinitely large. This means that output resistance R
out
is
merely the resistance delivered to the follower output port by the source of transistor M1. In
view of our negligible CLM and BITM presumptions, this latter resistance is merely 1/g
m1
.
Thus,
out
m1
1
R .
g
=
(E2-2)
(4). The following issues should serve to test our comprehension of the basic circuit and system
concepts addressed in Chapter One. We are told that capacitance C establishes the dominant
network pole or equivalently, the only significant time constant of the circuit. This presump-
tion implies at least two things. First, all of the capacitances that are implicit to either
transistor in the network establish insignificantly minor constants and therefore, the sum of
these device time constants contribute negligibly to the dominant time constant of the net-
work. Accordingly, the transistor time constants negligibly impact the bandwidth of the net-
work. Second, because only one time constant is significant, the amplifier has but a single
pole in its I/O voltage transfer function. Moreover, the radial frequency of this lone pole is
precisely the radial 3-dB bandwidth, B. In particular, we have
v
v
A (0) 1
A (j) .
j j
1 1
B B
= =
+ +
(E2-3)
We should note that B in (E2-3) is indeed the 3-dB bandwidth in that
v
v
A (0) 1
A (jB) ,
1 j 2
= =
+
(E2-4)
which is a gain magnitude that is a factor of root two, or 3-dB, below the low frequency gain
of the amplifier. In this first order transfer relationship, B is the inverse of the dominant time
constant established by capacitance C. Since C faces a resistance of R
out
, as per (E2-2), we
conclude that
m1
out
g 1
B .
R C C
= =
(E2-5)
For a given load capacitance, a broadband amplifier response requires a large forward
transconductance, g
m1
, in transistor M1. But caution must be thrown to the proverbial wind,
for one way of achieving large g
m1
involves large gate aspect ratio. This tack increases
transistor capacitances to a point that may invalidate the alleged dominance of load capacit-
ance C. A second way of manifesting large g
m1
entails larger quiescent drain current in M1.
This strategy is equivalently unattractive because it results in increased static power dissipa-
tion.
The gain and bandwidth results generated herewith are of secondary importance to the me-
thod enlisted to delineate approximate expressions for these performance indices. In particu-
lar, we solved the problem before us largely by inspection and assuredly without resorting to
definitive circuit analyses. To be sure, the simplifying assumptions invoked at the outset
enabled our intuitive approach to problem solving. And while the performance results are in-
deed approximations that are fraught with varying degrees of computational errors, we must

- 544 -
remember three important points that philosophically surround first order analyses. The first
of these is that acceptable performance results predicated on a simplified, largely idealistic
framework is a prerequisite to achieving satisfactory performance under practical constraints.
In a word, if you cannot get the bloody thing to work under ideal conditions, you have little
hope for success in the real world. Second, manual analyses do not conclude a meaningful
circuit investigation. Instead, manual analyses are executed as a precursor to definitive com-
puter-aided and/or extended manual studies. They are largely intended to foster insightful
understanding and comprehension of foundational circuit dynamics, which are essential for
executing a rationale, detailed, and tractable computer-aided investigation and design. Third,
intuitive deductions also define engineering avenues that may result in improved circuit
performance. For example, our approximate work suggests an improved bandwidth when the
forward transconductance of transistor M1 is increased. It is a trivial matter to validate the
prudence of following this identified avenue and quantifying the engineering prices paid for
enhancing transconductance via increases in the gate aspect ratio and/or Q-point drain cur-
rent.
6.5.0. COMMON GATE AMPLIFIER
The last of the three canonic cells of analog MOSFET technology is the common gate
amplifier for which signal is applied at the source terminal and the response is extracted, often as
a current, at the drain terminal. We have already witnessed through our work with both diode-
connected transistors and the source follower that the resistance established at the source ter-
minal of a MOSFET is relatively low and of the order of only an inverse transconductance. We
have also seen that the resistance presented to a circuit by the drain terminal of a MOS technol-
ogy amplifier is at least as large as the relatively large channel resistance of the utilized device.
It is therefore logical (but not completely necessary) to apply an input current signal to a com-
mon gate unit and to extract the response associated with this input signal current as a current.
For these reasons, we choose to depict the NMOS common gate amplifier as the topological
form shown in Figure (6.26a). In this representation and in contrast to the common source and
common drain cases, the input signal is represented as a Norton equivalent circuit comprised of
signal current I
s
and shunt source resistance R
s
. The selection of a Norton input topology in Fig-
ure (6.26) makes it fair to presume that resistance R
s
is large. The output response to current I
s
is
the signal component, say I
os
, of the net output current, I
o
, flowing through load resistance R
l

and, of course, through the drain of the transistor. The gate of this transistor is biased at a con-
stant voltage, V
bias
. The constant, or static, current, I
Q
, together with the power line voltage, V
dd
,
and the biasing voltage, V
bias
, are selected to place the quiescent operating point of the transistor
in its saturated domain.
The low frequency, small signal equivalent circuit of the amplifier before us appears in
Figure (6.26b). For clarity, we have highlighted the transistor gate, drain, source, and bulk
terminals in this circuit model. Additionally, we have indicated that the signal current, I
os
, con-
ducted by the load resistance and the drain of the transistor is necessarily identical to the
transistor source signal current because zero current flows through the transistor gate at low sig-
nal frequencies.
6.5.1. SMALL SIGNAL METRICS
We commence our analysis of the common gate amplifier with an examination of the
input resistance, R
ig
, seen by the applied signal source. To this end, the model in Figure (6.27a)

- 545 -
allows us to evaluate R
ig
as the voltage to current ratio, V
x
/I
x
, of our mathematical ohmmeter vol-
tage and current variables, V
x
and I
x
. The subject model derives directly from Figure (6.26b),
which confirms the voltage identity, V
1
V
2
V
x
. These identities encourage adding the cur-
rents of the two voltage controlled current sources and flipping their directional flow. From Fig-
ure (6.27a), Kirchhoff delivers

Figure (6.26). (a). Basic schematic diagram of a common gate amplifier driven by an input current signal.
The output response is taken as the signal component, I
os
, of current I
o
. (b). The low frequency,
small signal equivalent circuit of the common gate configuration in (a).

Figure (6.27). (a). Low frequency, small signal model used in the evaluation of the input
resistance, R
ig
, for the common gate amplifier in Figure (6.26a). (b). Norton
representation of the input port of the common gate amplifier.
( )
x o x b m x l x
V r I 1 g V R I , ( = + +

(6-67)
from which we deduce readily that the input resistance is
g V
m 1

b m 2
g V r
o R
l
V
1
V
2
R
ig
R
ig
G
D
S
+V
dd
I
o
(a). (b).
V
bias
I
s
I
s
I
Q
R
s
R
s
R
l
R
og
R
og
B
I
os
I
os
(1+ )g V
b m x
r
o R
l
R
ig
D
S
(a).
I
x
B
I
x
I
os
+
V
x
I (1+ )g V
x b m x

I
s
R
s
R
ig
B
(b).
S

- 546 -
( )
x o l
ig
x b m o
V r R
R .
I 1 1 g r
+
= =
+ +
(6-68)
Three important observations bubble to the surface of (6-68). First, we note that for a
large channel resistance, r
o
, and negligible BITM (
b
0), R
ig
1/g
m
. This approximation echoes
expectations since the input port of a common gate amplifier is formed with respect to ground at
the device source terminal where we have observed, in the cases of a diode-connected transistor
and a source follower, a resistance of nominally an inverse forward transconductance. Second,
we see that for the special case of R
l
= 0, R
ig
is identical to R
od
, the output resistance of a source
follower, as per (6-59). Once again, we draw engineering comfort from this conclusion in that
the drain terminal of the transistor deployed in a traditional source follower has no resistance.
Finally, since the signal current, I
os
, conducted by the resistive load imposed on the common gate
unit also flows through the device source terminal, where we have deduced an input port resis-
tance of R
ig
, we are motivated to represent the amplifier input port by the simple Norton structure
shown in Figure (6.27b). As simplistic as it might appear, the resultant common gate current
gain, say A
ig
, derives as the elegantly simple current divider,
( )
os s s m s
ig
o l
s s ig m s
s
b m o
I R R g R
A .
r R
I R R 1 g R
R
1 1 g r
= = ~
+
+ +
+
+ +
(6-69)
The indicated approximation in (6-69) once again invokes the presumptions of large channel
resistance and negligible body effect.
In (6-69), we witness a common gate current gain that displays no phase inversion and
a magnitude that is always less than one. The absence of phase inversion between the input and
output currents supports the small signal dynamics implied by the model in Figure (6.26b). In
particular, the current response, I
os
, conducted by the load resistance necessarily flows into the
drain terminal of the transistor and then out of the source terminal, which is the indicated direc-
tional flow of the signal source current, I
s
. We also notice that A
ig
tends toward unity if R
s
>>
R
ig
, whose satisfaction likely presents no challenges. In fact, if R
s
is infinitely large, A
ig
is pre-
cisely one, which is gratifying in light of the fact that zero signal current in the gate lead of the
transistor forces an identity between the drain and source terminal signal currents. A final
important observation is that to the extent that r
o
is large and
b
is small in (6-69), the current
gain, A
ig
, is nominally invariant with the load resistance. This fact supports our earlier claim that
the common gate amplifier is characterized by an output resistance, R
og
, which is far larger than
the drain load resistance, R
l
.
The foregoing output resistance contention can be confirmed with the help of the basic
common gate model in Figure (6.26b). To this end, the subject model is redrawn in Figure
(6.28a), where the terminating load resistance, R
l
, is supplanted by our mathematical ohmmeter,
the signal source, I
s
, is set to zero, and use is once again made of the fact that the gate-source and
bulk-source signal voltages, V
1
and V
2
, respectively, are identical. Moreover, since the ohmme-
ter signal current, I
x
, enters the drain terminal of the transistor and exits its source terminal, V
1

V
2
R
s
I
x
. Thus, the two controlled generators, g
m
V
1
and
b
g
m
V
2
, can be supplanted by a single
controlled source of value (1+
b
)g
m
R
s
I
x
, the direction of which is opposite to either of the two
original current generators. These manipulations are reflected by the model in Figure (6.28a).
By inspection, we determine an output resistance, R
og
, of
( ) ( )
x
og s b m s o m o s
x
V
R R 1 1 g R r 1 g r R .
I
= = + + + ~ + (

(6-70)

- 547 -
Since the resistance, R
s
, of the signal source applied to the common gate amplifier is large for
most practical applications of the amplifier in question, (6-70) assures a very large output resis-
tance, R
og
.

Figure (6.28). (a). Low frequency, small signal model used to investigate the output resistance,
R
og
, of the common gate amplifier in Figure (6.26a). (b). Norton representation
of the output port of the common gate configuration.
A comparison of the performance metrics of a source follower with those of a common
gate amplifier manifests an interesting sidebar. Recall that a source follower, or common drain
amplifier, boasts essentially infinitely large input resistance, a relatively small output resistance,
and a voltage gain having less than unity magnitude and no phase inversion. In contrast, we
have just witnessed that a common gate amplifier delivers small input resistance, very large out-
put resistance, and a current gain projecting less than unity magnitude and no phase inversion. In
a word, the common gate amplifier is the network dual of the common drain unit. It is thus
understandable that whereas the common drain amplifier is known as a voltage buffer, the com-
mon gate amplifier is often referenced as a current buffer. Thus, just like a source follower buf-
fer can deliver reasonably large amplitude voltage responses to relatively low impedance loads, a
common gate current buffer can sustain nonzero current responses through relatively high
impedance load terminations.
With R
og
demonstrably a large resistance, prudence dictates wrapping up this phase of
our common gate amplifier interlude by formulating the Norton equivalent circuit for the output
port of the common gate cell, which we depict in Figure (6.28b). We need only determine the
Norton, or short circuit output current, I
N
. Since (6-69) defines the generalized common gate
current gain in terms of any load termination, R
l
, we readily deduce the Norton current gain, A
ng
,
by setting the load resistance in the subject expression to zero. Accordingly,
( )
l
N s m s
ng ig ig
R 0
o
s m s
s
b m o
I R g R
A A A .
r
I 1 g R
R
1 1 g r
=
= = ~ ~
+
+
+ +
(6-71)
Because g
m
r
o
is generally a large number and
b
is usually much smaller than one, the Norton
gain closely approximates the actual common gate current gain. The resultant Norton model in
Figure (6.28b) postures a terminated common gate amplifier current gain of
r
o
D
S
(a).
R
s
R
og
B
I
x
I
x
I
os
+
V
x
I (1+ )g R I
x b m s x
+
A I
ng s
R
og
R
l
B
(b).
D
(1+ )g R I
b m s x
I
N
R
og

- 548 -
( )
( )
( )
og
os
ig ng
s og l
s b m s o
s
o
s b m s o l
s
b m o
R
I
A A
I R R
R 1 1 g R r
R
.
r
R 1 1 g R r R
R
1 1 g r
| |
= |
|
+
\ .
(
(
( + + + (

( =
(
+ + + + ( (
(
+
(
+ +

(6-72)
While it may not be immediately apparent, this expression, upon appealing to (6-68), predicts
identically the same gain as does the more compact expression in (6-69). That which is imme-
diately evident is that both factors on the far right hand side of (6-72) are less than one. Accor-
dingly, the terminated current gain, A
ig
, of a common gate amplifier always satisfies the inequa-
lity, A
ig
< 1.
6.5.2. COMMON SOURCE-COMMON GATE CASCODE
Although the common gate amplifier can function as a standalone active cell, it is often
used in conjunction with a common source amplifier to improve certain performance metrics of
the latter. A typically exploited application is the common source-common gate cascode for
which a basic schematic diagram appears in Figure (6.29a). A source degeneration resistance,
R
ss
, is included in the common source component of the network at hand in the interest of
analytical generality. Its utilization is optional and dependent on the intended application of the
stage, the available standby voltage and power budget, and other factors that the design engineer
must weigh. Figure (6.29b) redraws the network in Figure (6.29a) as a signal schematic dia-
gram, which is to say that all constant voltages, which are used exclusively for biasing purposes,
are replaced by short circuits to signal ground. Additionally, all branch and node variables are
replaced by their small signal values. Most notably, the net drain current, I
d
, becomes small sig-
nal drain current I
ds
, while the net output voltage, V
o
, becomes its implicit signal component, V
os
.
These actions reflect the fact that the static voltages applied to the original circuit and which
have been reduced to zero in the signal schematic diagram, give rise to only quiescent branch
current and node voltage components, assuming that the biasing is judiciously implemented to
achieve relatively high network linearity in transistor saturation regimes. Finally, the output port
of the source-degenerated common source amplifier formed of transistor M1, which drives the
input port of the common gate unit comprised of M2, has been supplanted by its Norton equiva-
lent circuit. To the latter end, we have relied on Figure (6.5), where from (6-15), the effective
forward transconductance, g
me
, of the common source cell is
( ) ( )
o1
m1
o1 ss m1
me
m1 ss b1 m1 o1 ss
r
g
r R g
g .
1 g R 1 1 g r R
| |
|
+
\ .
= ~
+ + +
(6-73)
In this expression, we recognize parameter g
m1
as the forward transconductance of transistor M1
at the quiescent operating point at which M1 operates. Naturally, parameter
b1
represents the
bulk transconductance factor of transistor M1. Moreover, resistance R
os
in the Norton model in-
voked in Figure (6.29b) is, by (6-21),
( ) ( )
os ss b1 m1 ss o1 m1 ss o1
R R 1 1 g R r 1 g R r . ( = + + + ~ +

(6-74)
When we study the diagram in Figure (6.29b), it is important to compare judiciously
the subject network with the basic common gate amplifier in Figure (6.26a). In particular, the

- 549 -
signal current applied to the common gate amplifier in Figure (6.26a), which is generically
symbolized as I
s,
is now seen to be the current, g
me
V
s
, applied to the common gate input port of
the cascode in Figure (6.29b). Moreover, the generalized signal source resistance in Figure
(6.26a) is now R
os
, the output resistance of the common source amplifier whose output port is
coupled directly to the common gate unit under present consideration. These circuit level
interpretations, when viewed in the context of the Norton common gate model for the output port
in Figure (6.28b), enable the Norton embodiment for the output port of the cascode amplifier
delivered in Figure (6.29c). In the latter diagram, the indicated Norton gain, is, using (6-71),

Figure (6.29). (a). Basic schematic diagram of a common source-common gate cascode amplifier. (b).
Small signal schematic diagram of the amplifier in (a). The small signal model of the out-
put port for the common source amplifier formed of transistor M1 is represented by its
Norton equivalent circuit. (c). Small signal Norton equivalent circuit of the output port
formed of signal ground and the drain terminal of the common gate transistor, M2.
( )
os m2 os
ng
o2
m2 os
os
b2 m2 o2
R g R
A 1 ,
r
1 g R
R
1 1 g r
= ~ ~
+
+
+ +
(6-75)
where we have replaced source resistance R
s
in (6-71) by the effective source resistance, R
os
,
seen by the common gate device in Figure (6.29a). We have additionally taken the liberty of
presuming that g
m2
R
os
>> 1 in (6-75).
Continuing with the Norton output port depiction in Figure (6.29c), shunt resistance R
og

derives directly from (6-70); namely,
( ) ( )
og os b2 m2 os o2 m2 o2 os
R R 1 1 g R r 1 g r R . = + + + ~ + (

(6-76)
+
V
gg

R
ss
R
is
R
os
R
l
R
s
V
s
+V
dd
V
o
I
d
V
i
(a).
g V
me s
R
os
R
ig
I
d
V
bias
R
og
R
l
V
os
V
os
I
ds
I
ds
R
ig
R
og
M1
M2
M2
(b).
I
ds
A g V
ng me s
R
og
R
l
(c).
R
og

- 550 -
This output resistance is very large in that it multiplies R
os
, which is a resistance greater, and
likely much greater than r
o1
, the channel resistance of the common source driver, M1, by the
large factor, (1 + g
m2
r
o2
). As a result, we surmise a load resistance that is significantly smaller
than R
og
, and we resultantly conclude a signal output voltage, V
os
, in Figure (6.29c) of
( )
os ng me og l s me l s
V A g R R V g RV . = ~ (6-77)
It follows that the I/O voltage gain, A
vc
, of the common source-common gate cascode amplifier is
( )
os m1 l
vc ng me og l me l
s m1 ss
V g R
A A g R R g R .
V 1 g R
= = ~ ~
+
(6-78)
Although the foregoing investigations systematically exploit straightforward circuit
analysis procedures, it may prove instructive to execute an approximate study predicated on the
simplifying assumptions of infinitely large channel resistances and null bulk transconductance
factors. To begin, the signal voltage, V
s
, applied to the amplifier in Figure (6.29a) does not ap-
pear directly across the gate-source terminals of transistor M1 because of the source degeneration
resistance, R
ss
. Accordingly, the signal current, I
ds
, conducted by the drain of M1 is not g
m1
V
s

(which it would if R
ss
= 0) but is instead degraded, or degenerated, by the factor, (1 + g
m1
R
ss
). In
other words,
m1 s
ds
m1 ss
g V
I .
1 g R
~
+
(6-79)
To the extent that channel resistances are large, this signal current rolls through the source and
drain terminals of transistor M2 in Figure (6.29a) and ultimately through the terminating load
resistance, R
l
. The signal voltage response, V
os
, therefore follows as
m1 l s
os l ds
m1 ss
g RV
V R I ,
1 g R
= ~
+
(6-80)
whence the approximate voltage gain result in (6-78) is evident.
A comparison of the cascode gain result in (6-78) with the common source gain disclo-
sure in (6-24), which applies to both of the single transistor common source amplifiers depicted
in Figure (6.3), suggests that the two voltage gains are virtually identical. Indeed, the two gains
are identical if the utilized transistors boast very large channel resistances and negligible bulk
transconductance factors. This gain observation logically begets questions as to what purposes
are actually served by appending the common gate cell to the common source amplifier to forge
the cascode system of Figure (6.29b). The truth is that no gain advantages accrue from conven-
tional cacoding. In a sense, a penalty arguably accrues with the common gate cascode in that in
the cascode configuration, the standby power dissipation must supply energy to two transistors as
opposed to only one in the traditional common source cell.
While the gain of the common source and common source-common gate cascode struc-
tures are virtually identical, the output resistance, as seen by the terminating load resistance, R
l
,
is enhanced by the insertion of the cascode stage. Equation (6-76) suggests that the factor by
which the cascode topology increases the traditional common source output resistance is approx-
imately given by
og
m2 o2
os
R
1 g r .
R
~ + (6-81)
This factor can be large, particularly if transistor M2 has a large gate aspect ratio and/or the
quiescent drain current conducted by both M2 and M1 in Figure (6.29a) is relatively low.

- 551 -
We should interject that high output resistance is an important performance metric in
the design of transconductance amplifiers, which ideally have infinitely large output resistances.
In turn, transconductance cells are vital active components of a class of high performance filters
known as operational transconductance-capacitance (OTA-C) filters
[1]-[2]
. Transconductance
cells also comprise the foundation of a class of impedance converters known as gyrators, which,
among other attributes, boast the ability of transforming a capacitive load termination into an
effective input port inductance. Such an impedance transformation is laudable because of the
challenges implicit to realizing high quality inductances on chip. With gyrators, tuned circuits
comprised only of resistances and capacitances can be forged to realize fixed frequency and vol-
tage controlled oscillators, tuned bandpass filters, and broadband lowpass amplifiers
[3]-[7]
.
6.5.2.1. Miller Capacitance
Cascode topologies potentially offer circuit broadbanding attributes. Broadbanding is
the task of increasing the 3-dB bandwidth of an amplifier to a desired value without significantly
deteriorating the gain and other key performance metrics presented by the amplifier in the net-
work passband. The bandwidth of a circuit is related (but not precisely equal) to the inverse sum
of the individual time constants (taken one at a time) associated with the energy storage elements
implicit to both the layout of the circuit and the models of the active devices embedded therein.
While numerous design challenges and issues accompany the bandwidth enhancement problem,
it is generally true that progressively smaller network time constants engender correspondingly
larger bandwidths. The common gate cascode attacks but one of the time constants evidenced in
a common source amplifier; namely, the time constant associated with the gate-drain capacit-
ance, C
gd
, of the common source, or driver, transistor. It has no effect on the time constants
established by gate-source, bulk-drain, and bulk-source transistor capacitances.
In order to garner an appreciation of the effect that a common gate cascode has on cir-
cuit 3-dB bandwidth, we return to the basic common source amplifier of Figure (6.3a) for the
purpose of focusing on the gate-drain capacitance. We choose to depict the latter device model
element by the partially dashed external branch capacitance in Figure (6.30a). The correspond-
ing small signal model appears in Figure (6.30b). In the interest of analytical convenience, we
show capacitance C
gd
as a gate to drain circuit element by partitioning the intrinsic gate-drain
capacitance, C
gd
, out of the transistor model. Because of our present focus on only the gate-drain
capacitance of the driver, the gate-source, bulk-drain, and bulk-source capacitances of the subject
transistor are not shown. It should be understood that we are not implying herewith that these
latter three capacitances are insignificant at signal frequencies in the neighborhood of the circuit
3-dB bandwidth. Instead, we are directing our analytical attention to only the gate-drain capacit-
ance to demonstrate that its impact on high frequency circuit performance effects is ostensibly
mitigated by the incorporation of a cascode stage in tandem with the common source driver.
Before diving into the obligatory sea of mathematics, we should note in Figure (6.30b)
that the gate-drain capacitance, C
gd
, can be expected to conduct a high frequency signal current,
I
gd
. This current must be supplied by the source of applied signal energy. In the steady state, this
capacitive current can be large at very high frequencies, since in terms of the voltage variables
delineated in Figure (6.30b),
( )
gd gd i os
I jC V V . = (6-82)
In addition to the direct proportionality of capacitive current I
gd
on radial signal frequency , we
can postulate a potentially significant voltage difference, (V
i
V
os
), which can further increase
the magnitude of the current conducted by capacitance C
gd
. This postulate derives from the fact

- 552 -
that a common source amplifier is typically designed for larger than unity I/O voltage gain.
Moreover, a common source amplifier exhibits 180 of I/O phase inversion, at least at low to
moderately high signal frequencies lying within the network passband. Consequently, and to
crude first order, V
os
is proportional to input port voltage V
i
by some negative, gain-related con-
stant, say (K). It follows that

Figure (6.30). (a). Common source amplifier of Figure (6.3a) with due
consideration given to the gate-drain capacitance, C
gd
,
implicit to the utilized transistor. (b). Small signal model of
the amplifier in (a). The only capacitance addressed by this
model is the gate-drain capacitance of the transistor in (a).
( ) ( )
gd gd i os gd i
I jC V V jC 1 K V , = = + (6-83)
+
V
gg

R
ss
R
l
R
s
V
s
+V
dd
V
o
I
d
V
i
V
i
(a).
+
g V
m 1
R
ss
R
s
V
s
V
1
R
l
V
os
I
ds
C
gd
C
gd
I
gd
I
gd
(b).

- 553 -
which is certainly sizeable for a large gain magnitude, K. Because the current predicted by (6-
83) is necessarily supplied by the signal source, a potentially appreciable fraction of the
Thvenin signal voltage, V
s,
is resultantly lost as a high frequency voltage drop across the inter-
nal resistance, R
s
, of the source. This signal voltage loss diminishes the input port signal, V
i
,
which in turn, proportionately decreases the magnitude of the output voltage response, V
os
. If the
stage at hand indeed exhibits voltage gain, as is commonly the case, the magnitude of V
os
de-
creases at a rate that is K-fold larger than the rate at which input port signal voltage V
i
increases.
As we learned earlier, a measure of this gain degradation is the 3-dB bandwidth, which is the sig-
nal frequency at which the magnitude response has degraded by 3 decibels with respect to the
gain provided at low to moderate signal frequencies. Of course the currents conducted by all cir-
cuit capacitances are negligible at these lower signal frequencies.

Figure (6.31). (a). Circuit model for computing the resistance faced by
capacitance C
gd
in the equivalent circuit of Figure (6.30b).
(b). Alternative equivalent circuit for the model in Figure
(6.30b). The structure provides the same low frequency vol-
tage gain predicted by the original model, and the sum of the
time constants associated with capacitances C
m
and C
gd
is
identical to the time constant established by capacitance C
gd

alone in the former model.
As inferred earlier, the circuit bandwidth is inversely related to the sum of the individ-
ual time constants associated with the energy storage elements that are implicit to the circuit
undergoing investigation. In order to compute the time constant of capacitance C
gd
in Figure
(6.30b), we must first evaluate the resistance, say R
gd
, which electrically faces C
gd
. To this end,
V
i
g V
m 1
g V
m 1
I
x
R
ss
R
s
V
1
R
l
I +g V
x m 1
I
x
(a).
V
i
+
g V
m 1
R
ss
R
s
V
s
V
1
R
l
V
os
C
m
(b).
V
x
+
C
gd

- 554 -
we apply our mathematical ohmmeter between the gate and drain terminals, where C
gd
is inci-
dent, as we demonstrate in Figure (6.31a). In this model, which tacitly neglects CLM and BITM,
signal source V
s
is set to zero. Setting the independent signal to zero is appropriate for the
computation of gate-drain resistance R
gd
as the ohmmeter voltage to current ratio, V
x
/I
x
. The
model in question stipulates
( )
x s x l x m 1
1 s x m ss 1
V R I R I g V
.
V R I g R V
= + +
=
(6-84)
Upon eliminating voltage V
1
in these two relationships, we find that
x m l
gd l s
x m ss
V g R
R R 1 R .
I 1 g R
| |
= = + +
|
+
\ .
(6-85)
It follows that the time constant,
gd
, associated with capacitance C
gd
is of the form,
gd gd gd l gd s m
R C R C R C = = + (6-86)
where
m l
m gd
m ss
g R
C 1 C .
1 g R
| |
= +
|
+
\ .
(6-87)
Equation (6-86) gives rise to the alternative high frequency model we depict in Figure (6.31b).
This alternative structure is equivalent to that of Figure (6.30a) in only two senses. First, both
models predict the same voltage gain at low signal frequencies where the effects of capacitance
C
gd
can be ignored. Second, the sum of the two time constants (one due to C
gd
and one due to
C
m
) evoked in Figure (6.31b) is identical to the time constant,
gd
, predicted by the schematic dia-
gram in Figure (6.30a). However, it should be underscored that the latter model is not strictly
correct in a physical sense because it predicts two finite frequency poles (one due to each of the
two capacitors) and no finite frequency zeros. In contrast, the model in Figure (6.30a) estab-
lishes a single finite frequency pole and, as detailed analyses reveal, a finite frequency zero lying
in the right half plane.
The most notable aspect of (6-86) and (6-87) is that the gate-drain capacitance mani-
fests a time constant component, R
s
C
m
, which implies an effective capacitance, C
m
, placed in
parallel with the input port to the common source amplifier. It therefore imposes a high fre-
quency load on the signal source that is not evident at low to moderately high signal frequencies.
For that matter, this load is less than transparent at high signal frequencies. From (6-87), the
high frequency load in question can be significant because capacitance C
m
can substantively ex-
ceed the original gate-drain capacitance. Indeed, (6-24) reveals that the factor by which C
m
ex-
ceeds C
gd
is intimately related to the magnitude of common source voltage gain. In particular,
for large channel resistance and negligible bulk transconductance,
( )
m l
m gd vs gd
m ss
g R
C 1 C 1 A C .
1 g R
| |
= + ~ +
|
+
\ .
(6-88)
Capacitance C
m
is often referenced in the literature as the Miller capacitance, and the
approximate multiplier of C
gd
by one plus the common source gain magnitude, is traditionally
termed the Miller multiplication factor. Pardon the pun, but it may be natural to refer to the time
constant,
gd
, in (6-86) as the Miller time (constant). It is interesting to note that a progres-
sively larger magnitude of circuit gain results in a larger Miller capacitance and consequently, a
larger Miller time constant that can degrade the bandwidth of the network. This observation is

- 555 -
important because generally, high gain and large bandwidth are diametrically opposed perfor-
mance metrics.
If we now turn our attention to the basic form of the common source-common gate cas-
code of Figure (6.29a), we see that the effective load resistance imposed on the drain of common
source transistor M1 is no longer the actual load resistance, R
l
. Instead, it is R
ig
, the input resis-
tance to the common gate cell formed of transistor M2. This means that the Miller capacitance,
say C
mc
, evidenced implicitly at the input port of the cascode amplifier in Figure (6.29a) is given
by
m ig
mc gd
m ss
g R
C 1 C ,
1 g R
| |
= +
|
+
\ .
(6-89)
where g
m
and C
gd
respectively denote the forward transconductance and gate-drain capacitance
of transistor M1. Recalling (64),
( )
o2 l
ig
b2 m2 o2 m2
r R 1
R .
1 1 g r g
+
= ~
+ +
(6-90)
The indicated approximation reflects the reasonable presumptions that the channel resistance, r
o2
,
of M2 is much larger than the actual load resistance, R
l
, and the bulk transconductance factor,
b2
,
of M2 is negligibly small. Accordingly,
m m2
mc gd
m ss
g g
C 1 C .
1 g R
| |
~ +
|
+
\ .
(6-91)
To the extent that
ig l
m2
1
R R ,
g
~ < (6-92)
we observe a cascode version of the Miller capacitance, C
mc
, which is smaller than the basic
common source Miller capacitance, C
m
. This is to say that the gate-drain capacitance in the cas-
code configuration establishes a smaller time constant, and hence a diminished high frequency
load on the input signal source, than does the gate-drain capacitance of the original common
source amplifier. In a word, the cascode addendum to the common source amplifier ostensibly
improves the 3-dB bandwidth of the common source amplifier.
Before texting home to set up a party in celebration of our ability to reduce Miller time,
we should view these disclosures in a guardedly optimistic fashion. The first issue inherently
underpinning design trepidation is that in a common source amplifier, the gate-drain capacitance
may not establish a dominant percentage of the net sum of time constants established by the am-
plifier. For minimal geometry transistors processed in a self-aligning gate technology, which
ideally reduces the gate-drain capacitance to nearly zero, it is, in fact, likely that the gate-drain
capacitance does not establish time constant dominance or significance. A common source am-
plifier implicitly has gate-source, bulk-source, and bulk-drain capacitances. Moreover, the am-
plifier itself may be plagued by parasitic nodal capacitances associated with its layout and
packaging. Additionally, the amplifier may be called upon to drive a strongly capacitive (or
even inductive) external load termination. Any one or more of these energy storage elements
may give rise to time constants that are respectively many times larger than the time constant
attributed to the gate-drain capacitance. In such a circumstance, a cascode-related decrease in
Miller time may result in no observable improvement in the measured 3-dB bandwidth of the
amplifier.
The foregoing plausible dilemma is exacerbated by the fact that the deployment of a

- 556 -
common gate cascode does not eliminate the gate-drain capacitive time constant. To the extent
that (6-91) is valid, we see that it merely diminishes said time constant. But in the process of
such time constant attenuation, a second transistor, M2, replete with its own gate-drain, gate-
source, bulk-source, and bulk-drain capacitances, adds time constants to those that already pre-
vail in the simple common source amplifier. Therefore, the question that naturally arises is
whether the time constant reduction afforded by the common gate cascode is larger or smaller
than the additional time constants added to those that already prevail in the simple form of the
amplifier. If such reduction is larger, the bandwidth can be expected to improve. Otherwise, the
bandwidth may actually be smaller than that observed prior to deploying the cascode unit.
Whether we win or lose the cascode compensation game is strongly dependent on the size of the
utilized transistors, the biasing applied to these devices, the high frequency capabilities of these
transistors, and the intended system application of the final form amplifier.
6.5.2.2. Folded Cascode
The folded cascode, which is shown in Figure (6.32), uses an NMOS common source
amplifier (M1), a PMOS common gate stage (M2), and a PMOS current source (M3) to achieve
nominally the performance characteristics that are indigenous to the traditional common source-
common gate cascode amplifier of Figure (6.29a). An advantage of the folded topology is that
the biasing current, say I
d2Q
, which flows through the PMOS common gate stage and which is set
by the indicated biasing potential, V
bias1
, need not be the same as the standby current, I
d1Q
, con-
ducted by the common source transistor, M1. Among other things, this means that the forward
transconductance, g
m2
, of transistor M2 can be increased with respect to the forward transconduc-
tance, g
m1
, of M1 through biasing means alone, without risking the potentially deleterious band-
width consequences associated with increasing the gate aspect ratio of M2. Increased g
m2
is
desirable in that it results in a decreased input resistance to the common gate amplifier, thereby
making this amplifier behave as a better emulation of a current amplifier. Of course, if M1 con-
ducts I
d1Q
and M2 conducts I
d2Q
at the quiescent operating point of the circuit, the biasing vol-
tage, V
bias2
, which is applied to the gate of the current source transistor, M3, must be adjusted so
that the standby current flowing through M3 is the quiescent current sum, (I
d1Q
+ I
d2Q
). We
should also understand that the three indicated static voltages, V
dd
, V
bias1
, and V
bias2
, must be se-
lected to ensure the saturation domain operation of all three active devices in the subject circuit.
A second advantage of the folded cascode is that the static output voltage, V
oQ
, in the
circuit of Figure (6.32) is rendered less vulnerable to variations in the power line voltage, V
dd
,
than is the corresponding static output voltage of the traditional cascode. In particular, V
oQ
in
Figure (6.32) is merely I
d2Q
R
l
. To the extent that CLM in both M2 and M3 is minimal, this vol-
tage is independent of the source-drain Q-point voltages of M3 and M2, and is therefore nomi-
nally insensitive to the power line voltage, V
dd
(as long as V
dd
is big enough to maintain satura-
tion of all transistors). Depending on the system into which the folded cascode is embedded,
there may even be an additional system level advantage precipitated by the fact that the static
output voltage of I
d2Q
R
l
in Figure (6.27) lies closer to system ground than does the static output
voltage, (V
dd
I
dQ
R
l
), evidenced in the network of Figure (6.29a).
We shall commence our small signal investigation of the folded cascode by first adopt-
ing the simplifying approximations that all transistors in the network of Figure (6.32) have infi-
nitely large channel resistances and negligibly small bulk transconductances. Accordingly and in
light of the source degeneration resistance, R
ss
, the signal current, I
1s
, conducted by M1 is

- 557 -

Figure (6.32). Schematic diagram of a folded common source-common gate
cascode amplifier.
m1 s
d1s
m1 ss
g V
I .
1 g R
=
+
(6-93)
Since the source-gate voltage applied to transistor M3 is the constant, (V
dd
V
bias2
), its drain cur-
rent is signal invariant, at least to the extent that our presumption of infinite channel resistance is
reasonable. This means that zero signal current flows through M3, and in turn, signal current I
d1s

must be supplied exclusively by transistor M2. With reference to the subject schematic diagram,
it follows that
m1 s
d2s d1s me s
m1 ss
g V
I I g V ,
1 g R
= = =
+
(6-94)
where we have exploited (6-73). It follows that the signal output voltage, V
os
, is
m1 l s
os d2s l me l s
m1 ss
g RV
V I R g RV ,
1 g R
= = =
+
(6-95)
from which we uncover a small signal voltage gain of
os m1 l
me l
s m1 ss
V g R
g R .
V 1 g R
= =
+
(6-96)
We note by (6-78) that this voltage gain is identical to the approximate voltage gain, A
vc
, of the
traditional common source-common gate cascode, thereby lending credence to a previous
declaration that the folded cascode performs similarly to the traditional cascode.
For the purists among the readership, we can execute a more definitive small signal
analysis of the folded configuration by relying once again on the unimpeachable Mr. Norton. To
this end, we replace the circuit lying to the left of the source terminal of transistor M2 in Figure
(6.32) by its Norton equivalent. If we appeal to Figure (6.29b) we have most of this circuit
equivalence at hand, the only difference being that transistor M3 in Figure (6.32) imposes an
additional load comprised of its channel resistance, r
o3
, on the source terminal of the present
+
V
gg

R
ss
R
is
R
os
R
l
R
s
V
s
+V
dd
V
o
I
d1
V
i
R
ig
I
d2
V
bias2
V
bias1
R
og
M1
M3
M2

- 558 -
PMOS cascode device. This load is indeed a simple channel resistance because both the bulk
and source terminals of M3 are connected together at the power line, thereby rendering no bulk
transconductance phenomena. Accordingly, the pertinent small signal schematic diagram is the
structure shown in Figure (6.33), where relevant currents and node voltages have been replaced
by their signal components. In this structure, the effective transconductance, g
me
, which is mani-
fested by the M1 common source driver and its source degeneration resistance, R
ss
, remains
given by (6-73). Moreover, the resistance, R
os
, which is now shunted by resistance r
o3
, is still
defined by (6-74). On the other hand, resistance R
ig
, which represents the input resistance at the
source terminal of the grounded gate transistor, M2, remains stipulated by (6-68). The load resis-
tance, R
og
, or cascode output resistance facing the drain load resistance of R
l
, is, recalling (6-76),

Figure (6.33). AC/small signal schematic diagram of the folded cas-
code amplifier in Figure (6.32). The output port of
transistor M1 is modeled by its Norton equivalent, which
includes the shunting resistance effect of channel
resistance r
o3
for transistor M3.
( ) ( ) ( ) ( )
og os o3 b2 m2 os o3 o2 m2 o2 os o3
R R r 1 1 g R r r 1 g r R r .
(
= + + + ~ +

(6-97)
Armed with this slightly modified resistance and the foregoing observations, the voltage gain of
the folded common source-common gate cascode amplifier derives directly from (6-78), with the
understanding that the Norton current gain, A
ng
, in (6-75) is now given by
( )
( )
( )
m2 os o3 os o3
ng
o2
m2 os o3
os o3
b2 m2 o2
g R r R r
A 1 ,
r
1 g R r
R r
1 1 g r
= ~ ~
+
+
+ +
(6-98)
From a simplistic, but nonetheless accurate, perspective, we can state that the small sig-
nal metrics deduced in the course of analyzing the conventional common source-common gate
cascode configuration are applicable to its folded counterpart. The only requirement in support
of such similarity is that resistance R
os
in the former expressions must be replaced by the slightly
reduced resistance value, (R
os
||r
o3
).
6.5.2.3. Regulated Cascode
In yet another variation of the basic common source-common gate cascode thematic
option, the regulated cascode amplifier depicted in Figure (6.34) deploys a common source
transistor, M3, to establish local feedback from the source terminal to the gate terminal of the
common gate device, M2. The circuit cell comprised of transistors M2 and M3 and the resis-
R
l
V
os
I
d1s
R
ig
I
d2s
R
og
M2
g V
me s
R
os
r
o3

- 559 -
tances, R and R
l
, is often referred to in the literature as a regulated common gate amplifier. As is
the case in the standard, or unregulated, common source-common gate amplifier of Figure
(6.29a), transistor M1 is the common source driver to which signal is applied in the form of a
voltage source. We shall learn that the forward transconductance of feedback transistor M3 en-
sures a dramatically small effective load resistance, R
ir
, imposed on the common source driver.
This resistance also represents the input resistance to the regulated common gate topology, dri-
ven by the common source input stage. Transistor M3 also dramatically increases the output
resistance, R
or
of the regulated cascode. Combined with its affect on resistance R
ir
, M3 postures
the regulated common gate stage as an excellent emulation of an ideal, unity gain, current am-
plifier.

Figure (6.34). Schematic diagram of a regulated common
source-common gate cascode amplifier.
Prior to formulating the small signal model of the regulated cascode, we observe that
transistor M3 in Figure (6.34) functions as a simple common source amplifier. The external load
imposed on the drain of M3 is solely resistance R since the gate of transistor M2 conducts no sig-
nal current at low to moderate signal frequencies. Accordingly, the ratio, V
3s
/V
2s
, of the signal
components of the indicated voltages, V
3
and V
2
, is predicated on the expression in (6-23). In
particular,
( )
3s
vf m3 o3 m3
2s
V
A g r R g R ,
V
= ~ (6-99)
where we have elected to write gain parameter A
vf
as a positive number. Recalling (6-16) and (6-
18), we have additionally capitalized on the fact that M3 utilizes no source degeneration.
Additionally, because both the bulk and source terminals of this transistor are grounded, no
BITM is evoked. Consequently, the small signal model of interest can be couched in the form of
+
V
gg

R
ss
R
is
R
os
R
l
R
R
s
V
s
+V
dd
V
o
I
d
V
i
R
ir
V
2
V
3
I
d
R
or
M1
M2
M3

- 560 -
the architecture displayed in Figure (6.35). In the interest of academic completeness, we have
included the Thvenin resistance, (r
o3
||R), associated with the dependent voltage source,
(A
vf
V
2s
), that drives the gate of feedback transistor M3. Of course, this resistance is
inconsequential at the low to even moderately high signal frequencies for which no observable
gate current flows. Recalling the modeling developments that precipitate Figure (6.5), we have
proceeded to represent the output port of the source-degenerated common source transistor, M1,
in the regulated cascode network by its Norton equivalent circuit. It should therefore be unders-
tood that transconductance g
me
and shunt resistance R
os
in this Norton model are given respec-
tively by (6-15) and (6-21), respectively. Upon adapting these two expressions to the amplifier
under present consideration, we have

Figure (6.35). Low frequency, small signal model of the regulated cascode network in Fig-
ure (6.30). The output port of the common source subcircuit formed of
transistor M1 and resistance R
ss
is represented as a Norton equivalent circuit.
( ) ( )
o1
m1
o1 ss m1
me
m1 ss b1 m1 o1 ss
r
g
r R g
g ,
1 g R 1 1 g r R
| |
|
+
\ .
= ~
+ + +
(6-100)
and
( ) ( )
os ss b1 m1 ss o1 m1 ss o1
R R 1 1 g R r 1 g R r . = + + + ~ + (

(6-101)
We now begin our investigation by determining the input resistance, R
ir
, seen looking
into the input port of the regulated cascode structure. To this end, the pertinent model is given in
Figure (6.36a), where we observe
2s b x
V V V , = = (6-102)
( )
a vf 2s 2s vf x
V A V V A 1 V , = = + (6-103)
and
( )
x o2 x m2 a b2 m2 b l x
V r I g V g V R I . = + + + (6-104)
Upon inserting (6-102) and (6-103) into (6-104), we arrive at our resistance expression goal:
( ) ( )
( )
x o2 l
ir
x m3 m2
b2 vf m2 o2 vf m2
V r R 1 1
R .
I 1 g R g
1 1 A g r 1 A g
+
= = ~ ~
+
+ + + +
(6-105)
R
ir
g V
me s
R
os
I
ds
+
g V
m2 a

b2 m2 b
g V r
o2
r ||R
o3
A V
vf 2s
V
a
V
b
R
l
V
os
I
ds
R
or
V
3s
V
2s

- 561 -

Figure (6.36). (a). Small signal model used to evaluate the low frequency, short circuit current, I
ns
, evi-
denced at the output port of the regulated common gate amplifier. (b). The Norton equiva-
lent circuit for the output port of the regulated cascode configuration.
The indicated approximations in this expression reflect the presumptions of large channel resis-
tances and small bulk transconductance in transistor M2. We remember that the input resistance
of the classic form of a common gate amplifier is nominally 1/g
m2
. The result at hand suggests
an input resistance for the regulated common gate amplifier that is significantly smaller than
1/g
m2
. In particular, we see that the effect of the feedback common source amplifier comprised
of transistor M3 and resistance R is to multiply the transconductance, g
m2
of the common gate
transistor, M2, by a factor of one plus the voltage gain magnitude afforded by the M3-R subcir-
cuit.
The aforementioned reduction in the input resistance can be understood qualitatively by
noting in Figure (6.34) that squirting a mathematical ohmmeter current, I
x
, into the source ter-
minal of transistor M2 increases the signal voltage, V
2s
, which is also the ohmmeter voltage, V
x
,
established at this source node. But the gate of the common source transistor, M3, is also con-
nected to the M2 source terminal, whence an increase in V
2s
results in the establishment of a sig-
nal voltage, V
3s
, at the drain of M3. This voltage response is a phase inverted and amplified ver-
sion of V
2s
. In other words, the indicated signal voltage, V
3s
, developed at the drain node of
transistor M3 is larger in magnitude than is signal voltage V
2s
, and, in relationship to a positive
signal voltage, V
2s
, it is a negative voltage signal response. Since the drain of M3 is connected to
the gate of M2, and the voltage at the source of M2, where ohmmeter current I
x
is originally ap-
plied, follows the gate, the resultant signal voltage response at the ohmmeter site counteracts the
original rise in voltage caused there by current I
x
. Consequently, the V
x
/I
x
ratio is small by a fac-
tor of roughly g
m3
R. Of course, small V
x
/I
x
is indicative of a small input resistance.
Figure (6.36b) is the low frequency, small signal model pertinent to the evaluation of
or
, seen by the drain load resistance, R
l
, imposed on the regulated com-
mon source-common gate cascode amplifier of Figure (6.34). An analysis similar to the one ex-
ecuted to discern the input resistance, R
ir
, seen by the common source driver reveals
( )
( )( )
x
or o2 b2 vf m2 o2 os m3 m2 o2 os
x
V
R r 1 1 A g r R 1 g R g r R .
I
(
= = + + + + ~ +

(6-106)
As in the case of the expression for R
ir
in (6-105), we see that the effect of the feedback common
source amplifier comprised of transistor M3 and resistance R is to multiply the forward
transconductance of the common gate transistor by a factor of one plus the magnitude of the volt-
g V
me s
R
os
I
ns
+
g V
m2 a

b2 m2 b
g V r
o2 r ||R
o3
A V
vf 2s
V
a
V
b
V
os
I
ns
I
ns
V
3s
V
2s
(a).
G V
nr s
R
or
R
l
(b).

- 562 -
age gain projected by said feedback amplifier. Because of this multiplicative effect, resistance
R
or
is invariably huge (likely into the meg-ohm range) even for deep submicron transistors that
offer only relatively anemic channel resistances.
Since the output resistance of the regulated cascode is very large, it makes sense to
model the output port of the amplifier by a Norton equivalent circuit, as is suggested by Figure
(6.36a), where signal current I
ns
is the Norton, or short circuit output port current. And in light of
the fact that the regulated amplifier is driven by a voltage signal, V
s
, the Norton current generator
for the output port is sensibly cast into the form of a voltage controlled current source whose
Norton transconductance, say G
nr
, is simply the ratio of Norton signal current I
ns
to input signal
voltage V
s
. The resultant Norton equivalent circuit is symbolically portrayed in Figure (6.36b).
In Figure (6.36a), we note
( )
o2 ns m2 a b2 m2 b b
0 r I g V g V V , = (6-107)
where
( )
a vf 2s 2s vf b
V A V V A 1 V , = = + (6-108)
and
( )
b os ns me s
V R I g V , = (6-109)
The substitution of the last two relationships into (6-107) leads to a Norton output port
transconductance of
( )
( )( )
ns me me
nr
o2
s
m3 m2 os
b2 vf m2 o2 os
I g g
G .
r 1
V
1 1
1 g R g R
1 1 A g r R
= ~
+ +
+ (
+ + +

(6-110)
As witnessed for both the input and the output resistances, the multiplicative impact on
transconductance g
m2
by the feedback common source amplifier is evident even for the Norton
output port transconductance. However, the effect of this multiplication factor on the observable
transconductance of the input stage common source driver is minimal because (1+g
m3
R)(g
m2
R
os
)
is invariably much larger than one. It therefore follows from (6-110) that
( )( )
me
nr me
m3 m2 os
g
G g ,
1
1
1 g R g R
~ ~
+
+
(6-111)
which is to say that the regulated common gate amplifier comprised of transistors M2 and M3
and resistance R in Figure (6.34) delivers essentially unity I/O current gain. In view of this fact,
the very low input resistance, and its very high output resistance, the regulated common gate
stage can be promoted as an excellent approximation of an ideal current buffer. Of particular
significance is the fact that the regulated cascode effectively compensates for small channel
resistances in deep submicron CMOS transistors.
6.6.0. WILSON CURRENT AMPLIFIER
Of the three standard cells of analog MOSFET technology that are currently book-
marked in our design notebook, only the common gate unit functions as a current amplifier in at
least the senses that it offers a relatively low input resistance and a very high output resistance.
Unfortunately, the actual current gain afforded by the traditional common gate topology is at
most one and in practice is slightly less than one owing to the presence of a finite signal source

- 563 -
resistance.
The Wilson amplifier, whose basic schematic diagram appears in Figure (6.37), im-
proves on the current signal processing capability of a common gate stage by offering an I/O cur-
rent gain that can be rendered a highly predictable, greater than unity value. In the subject dia-
gram, transistors M1, M2, and M3 operate in their conventional saturation modes and are similar
devices, save for designable differences in their respective gate aspect ratios. In particular, the
gate aspect ratio of transistor M3 is generally selected to be the same as that of M2 in order to
equalize the current densities in these two transistors. But the gate aspect ratio of transistor M2
is chosen to be a factor of larger than that of transistor M1. Note then from (6-1) that if I
2Q
is
the quiescent drain current flowing through M2 and if I
1Q
symbolizes the standby drain current of
transistor M1, the forward transconductances, g
m1
and g
m2
, of M1 and M2, respectively, are

Figure (6.37). The basic schematic diagram of the Wilson current amplifier.
The output response to the input excitation to the amplifier,
which consists of a quiescent current, I
Q
, and a signal current
component, I
s
, is the indicated current I
o
, which itself is the
superposition of a Q-point current, I
oQ
, and a signal response, I
os
.
1
m1 n 1Q
1
2
m2 n 2Q
2
W
g 2K I
L
.
W
g 2K I
L
| |
~
|
\ .
| |
~
|
\ .
(6-112)
In (6-112), we have ignored possible differences incurred in transconductance coefficient, K
n
, by
carrier mobility degradation. It now follows that
M3
M2
M1
I
1
V
1
V
2
I
2
I
2
I
o
+V
dd
R
l
R
s
I + I
Q s
R
iw
R
ow

- 564 -
2
2Q
2Q
2 m2
m1 1Q 1
1Q
1
W
I
I
L g
,
g I W
I
L
| |
|
| |
\ .
= = |
|
| |
\ .
|
\ .
(6-113)
where we have made use of the stipulation that the gate aspect ratio, W
2
/L
2
, of transistor M2 is -
times larger than W
1
/L
1
, the gate aspect ratio of transistor M1. But transistors M1 and M2 form a
classic current mirror. Specifically, we note that the gate-source voltages of M1 and M2 are
identical, which means that to the extent that CLM phenomena are negligible in both devices
and/or the difference between the quiescent drain-source voltages, V
1Q
and V
2Q
, and the respec-
tive drain saturation voltages of the two transistors are not significantly different,
( )
( )
2
n 1
1Q gs1Q h
1
2
n 2
2Q gs2Q h
2
K W
I V V
2 L
,
K W
I V V
2 L
| |
~
|
\ .
| |
~
|
\ .
(6-114)
where V
h
represents the threshold potential of the MOSFETs. Since the quiescent gate-source
voltage, V
gs1Q
, applied to transistor M1 is the same as V
gs2Q
, the Q-point gate-source voltage deli-
vered to M2, and since (W
2
/L
2
) = (W
1
/L
1
),
2Q
1Q
I
.
I
= (6-115)
Although this relationship is couched expressly in terms of quiescent currents, it applies equally
well to steady state instantaneous and signal component currents flowing through transistors M2
and M3. This assertion follows from the fact that the square law expressions in (6-114) apply to
static conditions, as well as to dynamic circumstances that embrace signals whose frequency
spectra are confined to low through moderately high signal frequencies. In a word, the static,
signal components, and net instantaneous currents conducted by M1 and M2 are geometrically
scaled mirror images of one another. The immediate impact of this disclosure is that it reduces
(6-113) to
2Q
m2
m1 1Q
I
g
.
g I
| |
= = |
|
\ .
(6-116)
In other words, just as the M1 and M2 transistor currents scale by a factor of , the forward
transconductances of these devices also scale by the same geometric factor. It is worthwhile
mentioning that because parameter represents a ratio of geometric dimensions, the numerical
value of is predictable and accurately controllable in monolithic processes.
There is another, even more important, aspect to (6-115). In particular, we observe in
Figure (6.37) that the net input current, (I
Q
+ I
s
), is the drain current, I
1
, conducted by transistor
M1 if the effective source resistance, R
s
, is much larger than the indicated input resistance, R
iw
.
But with I
1
= (I
Q
+ I
s
), the current, I
2
, conducted by M2 is, by (6-115), I
2
= I
1
= (I
Q
+ I
s
). In
turn, current I
2
rolls through transistor M3 so that the output current, I
o
, is I
o
= I
2
= (I
Q
+ I
s
).
We conclude, recalling the proviso, R
s
>> R
iw
, that the approximate current gain, say A
iw
, of the
Wilson amplifier is

- 565 -
os s
iw
s s
I I
A .
I I
= ~ = (6-117)
which suggests that the current gain of the Wilson stage is determined almost exclusively by a
ratio of transistor gate aspect ratios. Although the realization of a predictable current gain that
can be greater than one is a laudable characteristic of the Wilson architecture, its depressing
downside is that the standby, or Q-point, current conducted by transistors M2 and M3 is likewise
a factor of larger than the quiescent current flowing in transistor M1. Thus, we are forced to
temper a desire for a large current gain with a concern over proportionately escalating standby
power dissipation. In a word, the Wilson current amplifier is fully capable of delivering an I/O
current gain greater than one, but too much greater one gain incurs a significant standby power
dissipation penalty.
In arriving at (6-117), we tacitly presume an input resistance that is significantly
smaller than the signal source resistance. A first blush inspection of the circuit in Figure (6.37)
seemingly contradicts this presumption because it would appear that the input resistance is the
parallel combination of the ostensibly large resistances presented to the signal source by the
drain of M1 and the gate of M3. This tacit observation is incomplete and indeed, it is flat out
wrong! Consider our infamous ohmmeter, which we can use to squirt a figurative current into
the input port where the drain of M1 and the gate of M3 are incident. This current raises the in-
put port voltage, V
1
, which in turn increases (to a slightly lesser extent) the voltage, V
2
, at the
source terminal of M3. This declaration stems from the fact that the source of a MOSFET
closely follows the voltage established at its gate. We see that the source of M3 is pinned to the
gate of M1, which operates as a common source amplifier. Because a common source stage of-
fers voltage gain with phase inversion, the effect of a rising gate voltage is a potentially substan-
tial decrease in the signal voltage, V
1
, established at the drain node of M1. To be sure, M1 is a
common source unit. Even more significantly, it is a common source amplifier that functions as
a feedback element in the Wilson configuration. This is to say that M1 feeds back to the input
node an amplified and phase inverted version of the signal generated at its gate. The signal vol-
tage fed back to the drain of M1 opposes the original increase in voltage at this input node that is
spawned by our mathematical ohmmeter current. We therefore contend that the voltage to cur-
rent ratio at the drain of M1, which in fact is the input resistance, R
iw
, is smaller than the voltage
to current ratio caused solely by the ohmmeter current. The implication herewith, without rigor-
ous proof, is that the input resistance is small.
The feedback manifested by transistor M1 can also be used to suggest a potentially
large output resistance, R
ow
, in Figure (6.37). To this end, let us now imagine our ohmmeter
squirting a current into the drain of transistor M3. This current flows out of the source of M3 and
into the diode-connected transistor, M2, thereby increasing the signal voltage, V
2
, at the M1 gate
to which transistor M2 is incident. Because of the common source nature of M1, the rise in vol-
tage V
2
results in a decrease in the voltage at the gate of M3 to which the drain of M1 is incident.
Since M3 operates as a phase inverting common source amplifier, the decrease in M3 gate vol-
tage produces an amplified increasing signal voltage at the drain of M3, to which our ohmmeter
is attached. Thus, the response to the original ohmmeter-induced increase of the signal voltage
at the output node is a further increase in output node voltage. For a fixed level of ohmmeter
current, we therefore surmise a potentially large output resistance.
The preceding discourse implies that the Wilson amplifier of Figure (6.37) is characte-
rized by a small input resistance, R
iw
, and a large output resistance, R
ow
. The large output resis-
tance suggests the propriety of a Norton equivalent small signal model for the Wilson output

- 566 -
port. At a minimum, a detailed small signal analysis is appropriate if for no other reason than to
lend credence to the intuitive disclosures advanced in the preceding subsection. To this end, we
shall begin by developing a tractable model for the feedback current mirror comprised of transis-
tors M1 and M2. We shall then use this model in conjunction with the small signal equivalent
circuit for transistor M3 to execute a definitive small signal performance investigation of the
Wilson topology.
6.6.1. FEEDBACK CURRENT MIRROR
Figure (6.38a) highlights, for the case of small signal inputs, the feedback current mir-
ror embedded in the Wilson amplifier. Figure (6.38b), represents this current mirror by its low
frequency, small signal equivalent circuit. In the course of formulating this model, we note that
voltage V
2s
, which is the signal potential established across diode-connected transistor M2, is also
the signal voltage appearing across the gate-source terminals of transistor M1. We have
additionally exploited the fact that no bulk transconductance effects prevail in either M1 or M2,
since the bulk and source terminals of both of these devices are grounded, thereby ensuring zero
bulk-source signal potential.

Figure (6.38). (a). Wilson amplifier with the current mirror subcircuit comprised of transistors M1 and M2 ex-
tracted for small signal analysis purposes. (b). The low frequency, small signal model of the
current mirror subcircuit. (c). Equivalent model of the network in (b) with the voltage con-
trolled current source, g
m2
V
2s
, replaced by a current controlled source, f
w
I
2s
.
M3
M2
M1
I
1
V
1
V
2
I
2
I
2
I
o
+V
dd
R
l
R
s
I + I
Q s
R
iw
R
ow
M2
M1
I
1s
V
1s
V
1s
V
2s
I
1s
I
2s
I
2s
V
2s
(a).
(b).
g V
m1 2s
r
o1
r
m2
V
1s
I
1s
(c).
f I
w 2s
r
o1
V
2s
I
2s
r
m2

- 567 -
Because transistor M2 is configured as a diode-connected transistor, we have replaced
it by a simple two-terminal resistance, r
m2
, which derives from earlier considerations that en-
gender (6-44). In particular and in light of the absence of bulk transconductance phenomena,
o2
m2 o2
m2 m2 o2 m2
r 1 1
r r ,
g 1 g r g
= = ~
+
(6-118)
where, of course, r
o2
and g
m2
respectively denote the drain-source channel resistance and forward
transconductance of transistor M2. The indicated approximation reflects the presumption that
g
m2
r
o2
>> 1. The model in Figure (6.38c) is electrically identical to that of Figure (6.38b) in that
the drain-source signal voltage developed across M2 relates to the signal current, I
2s
, conducted
by M2 as
2s m2 2s
V r I . = (6-119)
It follows that the dependent current source, g
m1
V
2s
, in Figure (6.38b) is expressible as
m1 2s m1 m2 2s w 2s
g V g r I f I , = = (6-120)
where
m1 o2 m1
w m1 m2
m2 o2 m2
g r g 1
f g r ,
1 g r g
= ~ =
+
(6-121)
and (6-116) and (6-128) have been recalled. Armed with Figure (6.38c), the complete low fre-
quency, small signal model of the Wilson current amplifier is the structure in Figure (6.39). In
the latter equivalent circuit, we have made use of the fact that the signal current, I
2s
, is identical
to the output current, I
os
, which flows through the terminating load resistance, R
l
. Thus, the cur-
rent controlled current source, f
w
I
2s
, in Figure (6.38b) is replaced by f
w
I
os
, which obviously re-
flects a dependent current that is directly proportional to the output signal current.

Figure (6.39). Low frequency, small signal equivalent circuit of the Wilson current amplifier shown in
Figure (6.37). The model makes use of the current mirror representation in Figure (6.38c).
The parameter, f
w
, is a critical metric that, as we shall shortly demonstrate, determines
the current gain and dramatically influences the driving point input and output resistances (as
well as several other performance barometers) of the Wilson configuration. It is referred to as
the global feedback factor of the Wilson current cell in that it measures the amount of signal cur-
rent that is fed back from the output port to the input port where input signal current I
s
is ap-
g V
m3 a
r
o3
V
1s
V
2s
I
1s
I
2s
I
os
f I
w os
r
o1
r
m2
R
ow
b3 m3 b
g V R
l
+ V
a
+
R
s
I
s
R
iw
+ V
b

- 568 -
plied.
2
. We note in Figure (6.39) that in the presence of this feedback generator, the net signal
current exciting the input port of the subject amplifier is the current difference,
i s w os
I I f I . = (6-122)
which in the jargon of feedback amplifiers is termed the input current error. If this current error
were to be magically reduced to zero by the Wilson circuit, (6-122) implies
i
os
s w
I 0
I 1
;
I f
=
= (6-123)
that is, the current gain becomes merely the inverse of the feedback factor. By (6-121), this in-
verse feedback factor is the ratio, , of the gate aspect ratio of transistor M2 to that of M1, which
we previously demonstrated, per (6-117), as the approximate current gain of the Wilson am-
plifier. We are therefore moved to advise that forcing the input current error to zero in a Wilson
amplifier is foundational to a current gain that is locked to a predictable ratio of device gate as-
pect ratios.
6.6.2. WILSON ANALYSIS --- INTRODUCTORY FEEDBACK
Let us begin to quantify the small signal characteristics of the Wilson current amplifier
by returning to the model in Figure (6.39) to write
( )( )
1s s o1 s w os
V R r I f I , = (6-124)
2s m2 2s m2 os
V r I r I , = = (6-125)
and
( ) ( )
a 1s 2s s o1 s w s o1 m2 os
V V V R r I f R r r I . ( = = +

(6-126)
Moreover,
l os 2s
os m3 a b3 m3 b
o3
R I V
I g V g V ,
r
+
= + (6-127)
where the bulk-source signal voltage, V
b
, applied to transistor M3 is related to signal voltage V
2s

and output signal current I
os
through
b 2s m2 os
V V r I . = = (6-128)
If we put (6-126) and (6-128) into (6-127), we arrive at a Wilson amplifier current gain, A
iw
, of
( )
( ) ( )
m3 s o1
os
iw
l m2
s
b3 m3 m2 w m3 s o1
o3
g R r
I
A .
R r
I
1 1 g r f g R r
r
= =
+
+ + + +
(6-129)
An equation that is as algebraically sloppy as (6-129) is either useless for design or is an eager
candidate for a design-oriented, insightful interpretation. Let us assume the latter if for no other
reason than Mr. Wilson knew what he was doing when he engineered his amplifier topology.
Consider first the special case of no feedback; that is, f
w
= 0. From (6-121), f
w
= 0
materializes if resistance r
m2
in (6-118) is zero or if the transconductance, g
m1
, of transistor M1 is
null. Since r
m2
represents the small signal resistance of the diode-connected transistor, M2, it is
impractical to presume r
m2
can be zero, for such a constraint mandates the silliness of either an

2
The term, global, is used in conjunction with the phrase, feedback factor, to denote that the feedback path
proceeds directly from the output port of the amplifier to the input port; in other words, global encompasses the
entire amplifier from output port to input port. In contrast, local feedback refers to feedback executed between
internal amplifier nodes, at least one of which is neither the output port node nor the input port node.

- 569 -
M2 channel resistance of zero or an M2 transconductance that is infinitely large. Thus, the only
recourse supportive of the zero feedback condition is g
m1
= 0, which is tantamount to zero drain
current flowing in transistor M1. In turn, if M1 conducts no drain current, it behaves as an open
circuit, which is to say that the feedback precipitated by transistor M1 from the source terminal
of M3 to the gate of M3 is disabled. In the lexicon of the feedback literature, this zero feedback
state is referred to as the open loop condition. We may therefore assert with engineering traction
that the open loop gain, say A
ow
, of the Wilson amplifier is
( )
( )
w
w
m3 s o1
os
ow iw
f 0
l m2
s
f 0
b3 m3 m2
o3
g R r
I
A A .
R r
I
1 1 g r
r
=
=
= = =
+
+ + +
(6-130)
which is certainly larger than the actual current gain, A
iw
. Parameter A
ow
is literally the low fre-
quency, small signal gain of the Wilson unit if transistor M1 is either removed from the circuit or
is biased in cutoff.
An appreciation of the utility of the open loop gain metric is sparked by an algebraic
reconsideration of (6-129), from which we deduce the considerably simpler algebraic expression,
os ow
iw
s w ow
I A
A .
I 1 f A
= =
+
(6-131)
This transfer function result is typified by the classic block diagram shown in Figure (6.40). In
this abstraction, we observe that the two signal currents, I
s
and f
w
I
os
, applied to the indicated alge-
braic summer are precisely the two anti-phase currents that activate the input port of the am-
plifier model in Figure (6.39). It therefore follows that the summing operation in Figure (6.40) is
a mathematical representation of current summing at the input port node in the small signal
equivalent circuit of the amplifier. We observe further that the response of the summer in the
block diagram before us is precisely the input current error defined by (6-122). This error cur-
rent activates the open loop gain block to produce an output current response, I
os
, of

Figure (6.40). System level block diagram model of the Wilson current
amplifier. The transfer function parameter, A
ow
is the
open loop, or zero feedback, small signal current gain of
the amplifier in Figure (6.37), where it is understood that
zero feedback connotes f
w
= 0. This directive is equiva-
lent to open circuiting the drain of transistor M1.
( )
os ow i
I A I . = (6-132)
If we determine the current ratio, I
os
/I
s
, from the expression that results when (6-122) is substi-
tuted into (6-132), we reassuringly find that this ratio is identical to that given by (6-131). In
other words, the block diagram in Figure (6.40) mirrors the circuit level analyses that produce
the algebraic gain result in (6-131).
The block diagram representation in Figure (6.40) provides us with a mathematical pic-
ture that proves useful in developing an insightful engineering interpretation of the nomenclature
commonly invoked in the study of feedback networks. For example, (6-131) clearly demon-
A
ow
I
i
I
os
f
w
f I
w os
I
s
+

- 570 -
strates an amplifier gain that is identical to the metric, A
ow
, if parameter f
w
is null. Referring to
A
ow
as an open loop gain is now grasped intuitively in that forcing f
w
to zero is tantamount to
breaking, or opening, the signal processing loop forged by gain blocks A
ow
and f
w
. We note that
this loop is formed between the input current error variable, AI
i
, and the fed back current metric,
f
w
I
os
, of the feedback (f
w
) block. Because a loop is indeed formed by the open loop block and the
feedback block in Figure (6.40), it is additionally sensible to call the product, f
w
A
ow
, the loop
gain, say T
w
, of the Wilson amplifier. With
w w ow
T f A , (6-133)
(6-131) becomes
os ow ow
iw
s w ow w
I A A
A .
I 1 f A 1 T
= = =
+ +
(6-134)
And since the loop in question is effectively closed when neither the feedback factor, f
w
, nor the
open loop gain, A
ow
, are zero, the current gain, A
iw
, which we have thus far referenced mundanely
as actual current gain, is more commonly and more meaningfully codified as the closed loop
gain of the current amplifier.
The loop gain of a feedback network is a critically important measure of feedback am-
plifier quality. For example, if high frequency phenomena are addressed in the model utilized to
characterize the performance of the amplifier before us, the loop gain leads to establishing the
frequency domain locations of closed loop pole and zero locations in terms of the critical
frequencies of the open loop gain function. As such, it determines the overall quality of the
closed loop frequency and transient step responses, and it additionally quantifies the degree of
stability of the considered network
[8]
. These and other important issues are beyond the scope of
this chapter. We must therefore be at least temporarily content to examine the effect that the
loop gain, T
w
, has on the input current error response, AI
i
, to the applied signal current excitation,
I
s
. To this end, (6-122) and (6-131) combine to yield
i s w os w ow
s s w ow w ow w
I I f I f A 1 1
1 .
I I 1 f A 1 f A 1 T
= = = =
+ + +
(6-135)
This outcome suggests that for a given input excitation, the input current error, AI
i
approaches
zero in the limit as loop gain T
w
tends toward infinity. Recall that (6-123) portends a closed loop
gain of inverse f
w
if indeed, the input current error is magically forced to zero. In truth, we
learn that magic is in short supply in a practical Wilson amplifier in that its input current error
can never be made to disappear. But this error current can be made small if the adopted circuit
design strategy focuses on achieving a large loop gain. For the large loop gain circumstance, we
observe in (6-134) that since large T
w
implies f
w
A
ow
>> 1, A
iw
collapses to A
iw
1/f
w
, which hap-
pily agrees with our earlier disclosures surrounding (6-122).
It is only natural to investigate if a large loop gain is practicable in a Wilson current
amplifier. Since the loop gain, T
w
, is the product of the feedback factor, f
w
, and the open loop
gain, A
ow
, a large loop gain mandates a very large open loop gain. This logic derives from our
understanding that in light of a closed loop gain that is approximately 1/f
w
, f
w
is necessarily
smaller than one if we are to achieve a closed loop gain greater than one. If we do not achieve
greater than one gain, we might just as well abandon our Wilson topology in favor of a
considerably simpler common gate standard cell. In (6-130), the body effect factor,
b3
, for
transistor M3 is invariably much smaller than one. Moreover, for reasonable values of the
terminating load resistance, R
l
, we can expect the M3 channel resistance, r
o3
, to be significantly
larger than the resistance sum, (R
l
+ r
m2
). Accordingly,

- 571 -
( )
m3 s o1
ow
m3 m2
g R r
A .
1 g r
~
+
(6-136)
In this approximate relationship, r
m2
, which is given by (6-118) is likely comparable to the in-
verse of the transistor M3 transconductance, g
m3
, especially if transistors M3 and M2 have nomi-
nally the same gate aspect ratios. Thus, it is unreasonable to force g
m3
r
m2
<< 1, thereby render-
ing an attempt to increase A
ow
through increases in parameter g
m3
potentially counterproductive.
We conclude that a very large A
ow
can be realized only if the source resistance, R
s
, is large and
the channel resistance, r
o1
, of transistor M1 is likewise large. A large source resistance is likely
since the Wilson stage is explicitly contrived to be driven by a current signal. On the other hand,
large r
o1
can be accomplished, at some risk of circuit bandwidth deterioration, by laying out
transistor M1 as a relatively long channel device. Additionally, r
o1
can be made large if the drain
biasing current through M1 is small. Caution must accompany the latter design tack in that a
small M1 bias current also reduces its transconductance, g
m1
. Recalling (117), a small g
m1
, in
turn, may reduce the feedback factor to a level where the corresponding loop gain, f
w
A
ow
, is
anemic. We conclude that a large loop gain in the Wilson current amplifier is possible only if a
large signal source resistance prevails and a large M1 channel resistance can be achieved without
incurring undue compromises in other performance metrics indigenous to the Wilson stage.
6.6.3. NORTON MODEL OF AMPLIFIER OUTPUT PORT
The Norton equivalent circuit for the output port of the Wilson amplifier assumes the
traditional topological form depicted in Figure (6.41). In this representation, R
ow
symbolizes the
output resistance seen by the load resistance, R
l
, while A
nw
is the short circuit, or Norton, small
signal, I/O current gain. Specifically, A
nw
is the closed loop current gain under the condition of a
short circuited load resistance; that is, R
l
= 0. Recalling (6-129)

Figure (6.41). Norton equivalent, low frequency, small signal
representation of the output port of the Wilson
amplifier in Figure (6.37).
( )
( ) ( )
l
l
m3 s o1
os
nw iw
R 0
m2
s
R 0
m3 b3 m2 w s o1
o3
g R r
I
A A ,
r
I
1 g 1 r f R r
r
=
=
= = =
( + + + +

(6-137)
where we recognize that the feedback factor, f
w
, in (6-121) is independent of load resistance R
l
.
A comparison of this result with (6-129) allows expressing the closed loop current gain, A
iw
, in
the form
( ) ( ) { }
os nw
iw
l
s
m3 b3 m2 w s o1 o3 m2
I A
A .
R
I
1
1 g 1 r f R r r r
= =
+
( + + + +

(6-138)
In turn, however, the Norton model in Figure (6.41) predicts a closed loop current gain of
A I
nw s
R
ow
R
l
I
os

- 572 -
os ow nw
iw nw
l
s ow l
ow
I R A
A A .
R
I R R
1
R
| |
= = =
|
+
\ .
+
(6-139)
Upon comparing the denominators on the far right hand sides of the preceding two expressions,
we conclude that the closed loop output resistance of the Wilson current amplifier is
( ) ( ) { } ow m3 b3 m2 w s o1 o3 m2
R 1 g 1 r f R r r r , ( = + + + +

(6-140)
which is larger potentially much larger than the channel resistance, r
o3
, of transistor M3. For a
large signal source resistance, R
s
, and a large M1 channel resistance, r
o1
,
( )( )
( )( )
m3 o3 s o1
ow w m3 o3 s o1
iw
g r R r
R f g r R r .
A
~ ~ (6-141)
We observe that a large closed loop current gain, A
iw
, tempers the otherwise large output resis-
tance. In particular, this output resistance is directly proportional to the product of two numeri-
cally large factors: the parallel combination of the signal source resistance (R
s
) and the M1 chan-
nel resistance (r
o1
), and the product of M3 transconductance and M3 channel resistance. But it is
also inversely proportional to the closed loop current gain. Aside from aggravating the static
power dissipation of the Wilson circuit, there is thus another reason to obviate large current gain.
In a word, a large closed loop current gain compromises the ideal properties of the current am-
plifier by diminishing its driving point output resistance.
6.6.4. AMPLIFIER OUTPUT RESISTANCE
In order to evaluate the input port resistance, R
iw
, presented by the Wilson amplifier to
the signal source, we once again play the ohmmeter game. As is implied by the equivalent cir-
cuit in Figure (6.42), this input resistance is simply the voltage to current ratio, V
x
/I
x
. But rather
than execute yet another detailed circuit analysis, we observe that the subject voltage to current
ratio is identical to the ratio, V
1s
/I
s
, in Figure (6.39), subject to proviso that source resistance R
s
is
set to infinity (since we want only the resistance seen by R
s
). We therefore have from (6-124),

Figure (6.42). Equivalent circuit for computing the input resistance, R
iw
, of the Wilson current mirror.
s s
1s os
iw w o1
s s
R R
V I
R 1 f r .
I I
= =
| |
|
= =
|
\ .
(6-142)
Using (6-129) under the infinitely large source resistance constraint, (6-142) can be shown to be
g V
m3 a
r
o3
V
x
V
2s
I
1s
I
2s
I
os
f I
w os
r
o1
r
m2
b3 m3 b
g V R
l
+ V
a
+
I
x
R
iw
+ V
b

- 573 -
( )
l m2
b3 m3 m2
o3
iw o1
w m3
R r
1 1 g r
r
R r ,
f g
+
(
+ + +
(
= (
(
(

(6-143)
which reflects the clarion fact that the input resistance is the parallel combination of channel
resistance r
o1
and the effective resistance established across the input port by the controlled feed-
back source, f
w
I
os
. Despite the fact that this feedback generator is a current source, it does not
emulate an infinitely large resistance because as the signal source current, I
s
, increases, so does
the output current I
os
(in direct proportion to I
s
). Because feedback factor f
w
is a positive number,
this increase in I
os
imposes an additional current load on input current I
s
, thereby reducing the
effective resistance seen by I
s
.
For large channel resistances in transistors M1 and M3 and negligible bulk-induced
threshold modulation in M3, (6-143) reduces to
iw m2 iw m2
w m3 m3
1 1 1
R r A r .
f g g
| | | |
~ + ~ +
| |
\ . \ .
(6-144)
Since r
m2
is the small signal resistance associated with diode-connected transistor M2 and
transconductance g
m3
can be relatively large for appropriate bias current and gate aspect ratio in
transistor M3, R
iw
is noted as the reasonably small input resistance that we strive to achieve in a
current amplifier. But just as I/O current gain compromises the desirably large output resistance
of the Wilson structure, large current gain is seen to elevate the input resistance.
XEXAMPLE #6.3:
The Wilson current amplifier is a viable candidate for a CMOS common
source-Wilson cascode, as is suggested by the buffered cascode configura-
tion illustrated in Figure (6.43). In this schematic diagram, all six transis-
tors are biased in their saturation regimes. All transistors can be presumed
to abide by the Schichman-Hodges, long channel model. Specifically, all
transistors display negligible CLM, BITM, and other high order modeling
effects. As is noted in the schematic diagram, the gate aspect ratios of
transistors M2 and M3 are each a factor of k larger than the gate aspect ra-
tio of transistor M1. Perform a simplified engineering analysis of the
amplifier to deduce the voltage gain, A
v
(0) = V
out
/V
s
, at low signal
frequencies. In addition, deduce the gain-bandwidth product, say GBP, of
the amplifier if the load capacitance, C
l
, which is driven by the buffered
cascode, is the dominant energy storage element in the network.
SOLUTION #6.3:
(1). Before initiating our engineering analysis, it is fruitful to stand back and acquire an adequate
understanding of the various subcircuit cells within the buffered cascode.
(a). The input signal, V
s
, is applied to the gate of PMOS transistor M4, which functions as a
common source amplifier whose source is degenerated in resistance R
ss
. This degenera-
tion resistance reduces the sensitivity of the amplifier gain to the forward transconduc-
tance, g
m4
, of transistor M4.

- 574 -

Figure (6.43) Schematic diagram of a CMOS common source-Wilson cascode amplifier.
(b). The drain of M4 is connected in cascode with a Wilson current amplifier comprised of
transistors M1, M2, and M3. Given that the gate aspect ratio of transistor M2 is k-times
that of transistor M1, and given the stipulated simplifying approximations we are allowed
to adopt, current I
2
in the diagram is kI
1
. At low signal frequencies no gate currents are
conducted, thereby making I
3
= I
2
= kI
1
.
(c). Resistance R
l
conducts current I
3
. Accordingly, the signal component, say V
3s
, of the vol-
tage, V
3
, developed at the drain of transistor M3 bears an Ohms law relationship to the
signal component of current I
3
. Specifically, V
3s
= R
l
I
3s
.
(d). Transistor M5 operates as a source follower that buffers the signal voltage developed at
the M3 drain. At low frequencies, M5 is loaded in transistor M6, while load capacitance
C
l
acts as an open circuit. Because of the constant gate-source voltage, V
bias
, applied to it
and the stipulated approximations, M6 acts as an ideal, infinite resistance, current sink.
Thus, the source terminal of transistor M5 is connected to an open circuit at low frequen-
cies.
(e). The fact that M6 is an effective open circuit for low frequency signals precludes the flow
of signal current through transistor M5. Since this signal current, g
m5
V
5s
, is proportional
to the gate-source signal voltage, V
5s
, applied to M5, it follows that V
5s
is null. Of course,
the appended subscript, s, designates a signal component of a circuit variable. But this
means that the signal component, V
outs
, of the net output voltage, V
out
, is identical to the
signal component, V
3s
, of voltage V
3
. In other words, V
outs
= V
3s
.
(f). Although V
outs
= V
3s
, the output port resistance, R
out
, is likely to be considerably smaller
than the resistance established at the node supporting signal voltage V
3s
. In particular,
R
out
is formally the parallel combination of the resistance seen looking into the drain of
transistor M6 (which is infinitely large) and the resistance observed at the source terminal
of transistor M5 (simply 1/g
m5
). Accordingly, R
out
= 1/g
m5
, which is presumably much
smaller than the shunt combination of the M3 drain terminal resistance, R
l
, and the
Wilson output port resistance seen looking into the drain of M3.

V
gg

M5
M6
M4
M2
M1
I
1
V
1
I
2
V
3
+V
dd
R
l
R
ss
R
s
+
V
s
I
4
V
bias
M3
V
2
I
2
I
3
C
l
R
out
V
out
x 1
x k
x k

V

5

- 575 -
(2). The AC schematic version of the Wilson cascode appears in Figure (6.44). In addition to set-
ting all constant voltages to their null small signal values, the following information is rele-
vant to computing the low frequency gain and gain-bandwidth product. Keep in mind that at
low signal frequencies, all transistor capacitances (which we are nevertheless ignoring) and
the load capacitance, C
l
, emulate open circuits.

Figure (6.44). AC schematic diagram of the CMOS common source-Wilson cascode amplifier in
Figure (6.43). In the interest of computational ease, the signal components of relevant
branch currents and circuit voltages are explicated.
(a). Because of the resistive source degeneration of transistor M4, the effective transconduc-
tance, g
me4
of M4 is
m4
me4
m4 ss
g
g .
1 g R
=
+
(E3-1)
This means that the M4 signal drain current, I
4s
, which is directed from drain to source
when the signal voltage is applied from the gate to source, is
m4 s
4s
m4 ss
g V
I .
1 g R
=
+
(E3-2)
We show this current in Figure (6.44) as a current,
m4 s
m4 ss
g V
,
1 g R +

flowing into the M4 drain, opposite the direction delineated for the net drain current, I
4
,
in Figure (6.43). At first blush, this current direction may appear erroneous for the
PMOS device. But we must remember that (E3-2) defines only the signal component of,
and not the net, drain current conducted by transistor M4.
(b). Since no gate currents flow at low to moderate signal frequencies, we have
m4 s
1s 4s
m4 ss
g V
I I .
1 g R
= =
+
(E3-3)
The Wilson circuit and the stipulated gate aspect ratios of transistors M2 and M1 yield
M5
M6
M4
M2
M1
V
1
I
2
V
3s
R
l
R
ss
R
s
+
V
s
M3
V
2
C
l
R
out
V
outs
x 1
x k
x k
g V
m4 s
1 + g R
m4 ss
g V
m4 s
1 + g R
m4 ss
kg V
m4 s
1 + g R
m4 ss
kg V
m4 s
1 + g R
m4 ss
0
0
kg V
m4 s
1 + g R
m4 ss
+
0

- 576 -
m4 s
2s 3s
m4 ss
k g V
I I .
1 g R
= =
+
(E3-4)
The four currents defined collectively by (E3-3) and (E3-4) are annotated in the sche-
matic diagram of Figure (6.44). Note that an account of the minus signs associated with
these signal currents is made simply by reversing their respective current directions with
respect to the direction of the net currents, I
1
, I
4
, I
2
, and I
3
.
(c). In Figure (6.44), we see that the signal voltage, V
3s
, developed at the gate of transistor
M3, is
m4 l s
3s
m4 ss
k g R V
V .
1 g R
=
+
(E3-5)
In accordance with our earlier musings,
m4 l s
outs 3s
m4 ss
k g R V
V V ,
1 g R
= =
+
(E3-6)
which gives rise to a low frequency voltage gain, A
v
(0), of
m4 l
outs
v
s m4 ss
k g R
V
A (0) .
V 1 g R
= =
+
(E3-7)
(3). We have already concluded that the driving point output resistance, R
out
, is R
out
= 1/g
m5
. In
view of the facts that capacitance C
l
is dominant and C
l
establishes an ostensibly dominant
time constant of R
out
C
l
, we conclude that the 3-dB bandwidth, B, of the amplifier is
m5
out l l
g 1
B .
R C C
= = (E3-8)
It follows that the gain-bandwidth product, GBP, is
( )
m4 m5 l
v
m4 ss l
k g g R
GBP A (0) B .
1 g R C
= =
+
(E3-9)
There is no arguing that the amplifier diagrammed in Figure (6.43) is non-trivial. But armed
with the insights that have accrued from our definitive modeling and detailed circuit
investigations, we have arrived at gain and gain-bandwidth results without the need of
mathematical analyses. To be sure, the results we have gleaned are only approximations.
But they are sufficiently germane to establishing the foundation for definitive computer-aided
studies that can lead to a more accurate or even an optimal design. Moreover, they establish
the fundamental propriety of the circuit architecture, for if the desired performance cannot be
attained under simplified, but nonetheless meaningful and realistic, approximations, there is
little hope for proper circuit functionality in real environments that are plagued with high
order physical phenomena, energy storage parasitics, and so forth.
The simplified analysis serves to highlight very clearly two advantages of the Wilson cas-
code. The first of these advantages derives from an inspection of the gain relationship in (E3-
7). In particular, this expression indicates that the gain is directly proportional to kR
l
, as op-
posed to only the load resistance value, R
l
. If a required or desired gain with k = 1 (indicative
of the use of a conventional common gate, as opposed to a Wilson, cascode) requires a cer-
tain value of R
l
, the deployment of a Wilson cascode boasting k > 1 allows resistance R
l
to be
decreased by a factor of k. In turn, this decreased load resistance serves the designer in two
respects. First, it decreases power losses in the circuit. Second, the time constant established
by parasitic capacitances incident at the drain of transistor M3 is reduced (by a factor of k),
thereby supporting the presumption of a dominant capacitance at the output port. In other
words, the bandwidth is controlled more fully and distinctly by the output load capacitance.

- 577 -
The second advantage of the Wilson architecture is projected by (E3-9). In particular, the
gain-bandwidth product is enhanced by the current gain, k, of the Wilson amplifier. Interes-
tingly, increasing k not only improves the GBP, but it also enhances the low frequency vol-
tage gain of the amplifier. This attribute suggests that the circuit bandwidth is not a function
of circuit gain, as (E3-9) indeed confirms.
As a sidebar, we note that both the bandwidth and the gain-bandwidth product are propor-
tional to the transconductance, g
m5
of transistor M5. Parameter g
m5
, and therefore the gain
and gain-bandwidth product of the network, can be increased by increasing the quiescent cur-
rent flowing through M5. In turn, this quiescent current is conveniently controlled by the
bias voltage, V
bias
, which activates the gate of the current sinking transistor, M6.
6.7.0. BALANCED DIFFERENTIAL AMPLIFIER
The balanced differential amplifier, whose system level abstraction is Figure (6.45), is
not a new analog canonic cell. Rather, it is an interconnection of a matched pair of generally
recognizable analog cells and their associated subcircuits. The pair of amplifier cells embedded
within a balanced differential architecture allow for the application of two input signals one of
which is allowed to be zero, and the generation of multiple output responses. Although the ap-
plied inputs are delineated as the signal voltage sources, V
s1
and V
s2
, in the subject diagram, cur-
rent source inputs, while somewhat unusual are not precluded. The output responses can be
taken as currents or voltages almost anywhere in the system. In this exercise, we shall initially
focus on output voltage responses. To this end, the three outputs of immediate interest are the
single ended voltages, V
o1
and V
o2
, and the indicated differential voltage, V
do
. By a single ended
voltage is meant a voltage measured at a circuit node with respect to signal ground. In truth, all
of the output and other node voltages addressed in our earlier discussions are single ended vol-
tages. In contrast, the indicated differential voltage is not referred to signal ground. In an at-
tempt to keep Dr. Gustav Kirchhoff happy, it is merely the difference between the single ended
output voltages, V
o1
and V
o2
; that is,
do o1 o2
V V V . = (6-145)
The diagram of Figure (6.45) clearly incorporates two amplifier modules. Each of
these modules can be a common source unit, a common drain cell, a common gate structure, any
of the other more intricate topologies we addressed in preceding sections of material, or any
other configuration innovated by the circuit designer. These amplifiers need not be realized in
MOS technology. They can be implemented with bipolar junction transistors, a mixture of MOS
and bipolar devices (commonly referred to in the literature as BiCMOS technology), or with III-
V compound devices (e.g. gallium arsenide transistors, indium phosphide devices, etc.). The
pivotally important key to a balanced differential system is that the topology and the device
technology exploited in the individual amplifiers must be identical; in short, the amplifier mod-
ules must be mirror images of one another. Although biasing is not explicitly shown in the
differential network at hand, this matching requirement subsumes identical biasing of each am-
plifier. With identical topological structures that are biased identically for presumably linear sig-
nal processing purposes, the necessary conditions that enable each amplifier to exhibit the same
performance characteristics are satisfied. Sufficiency complements necessity with respect to the
realization of matched amplifier performance traits when we additionally require that the input
and output ports of both amplifiers be terminated in the same signal source resistances (R
s
) and
the same single ended loads, R
l
, respectively. Moreover, the resistances, R
gg
, in the third am-
plifier terminal, which is normally the signal ground lead of the amplifier in its single ended

- 578 -
embodiment (e.g. the source terminal in a common source amplifier) must be matched. The
same statement applies to any input port biasing resistances, R
b
, which may be required. Iden-
tical topologies that are identically biased and input and output ports that are terminated in
respectively identical impedances guarantee that the two amplifiers deliver equivalent I/O gains
and identical I/O port driving point resistances or impedances. Moreover, these matched am-
plifier cells yield the same 3-dB bandwidths, identical transient responses, and in general,
correspondingly identical performance metrics that serve to establish their I/O engineering
properties.

Figure (6.45). System level portrayal of a balanced differential amplifier. Amplifiers #1 and #2 are
identical active networks that are biased identically for linear signal processing purposes.
Because no biasing subcircuits are delineated, all indicated voltage and current variables
represent only signal components thereof.
Before proceeding with our analytical investigation of the balanced differential am-
plifier, it is illuminating to point out while differential technology has existed for decades, the
technology did not rise to prominence until the advent of the modern monolithic age
[9]
. Prior to
the integrated circuit revolution, the circuit designer had no option but to realize differential
topologies with discrete, off the shelf components. The inherent problem plaguing discrete
components is that matching of presumably like devices and circuit elements is a daunting chal-
lenge. This challenge can be offset through time-consuming, and therefore costly, individual
component testing and selection or through circuit design heroics that often compromise overall
system performance and integrity. The matching challenge is far from superficial. For example,
threshold voltages of same type discrete component MOSFETs can differ by at least tens of per-
cent, and transconductance coefficients (K
n
) can be at variance by many tens of percent. To be
+
Amplifier
#1
I
1
I
b1
I
o1
I +I
1 2
I +I
b1 b2
R
gg
R
s
R
s
R
b
I
2
I
b2
I
o2
R
gg
R
b
Amplifier
#2
R
kk
R
l
R
l
R
bb
V
s1
V
s2
V
o2
V
o1
R
ll
R
ll
V
b
V
k
V
l
V
do
V
i1
V
i2
I
ll
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Output Node:
Amplifier #2
Output Node:
Amplifier #2

- 579 -
sure, we can offset these effects, perhaps by implementing the two resistive branch elements, R
gg
,
as judiciously adjusted, non-equivalent resistances. But such a tack invariably engenders in-
creased power dissipation, increased noise levels, compromised system reproducibility, and other
issues. Even simple, resistors rated for the same resistance values have their resistance values
stipulated to within error tolerances of at least 10%. It follows that the likelihood of realizing,
straightforwardly and repeatedly, two identical resistances, yet alone two identical amplifiers,
with discrete, off-the-shelf components, is virtually nil. But when implemented in an integrated
circuit, matching among like circuit devices and components, though still strictly imperfect,
comes au gratis. Indeed, implicit mismatches between two similar components laid out in close
proximity to one another on an integrated circuit chip are virtually imperceptible.
One caveat to the matching attribute of integrated circuits must be flagged when one of
the two input signals, say V
s2
, applied to the balanced amplifier is zero. In this case, the source
resistance, R
s
, associated with the nonzero input signal voltage, V
s1
, is the internal resistance of
said source. This signal source may be an antenna, a CD player, or the output resistance of a
preceding stage of amplification. With V
s2
equal to zero, the terminating resistance, R
s
, at the
input port of the second amplifier, is necessarily implemented as a two terminal, passive resistor
that is physically synthesized on chip. In this circumstance, component matching between the
two R
s
resistances is problematic, particular since the internal resistance associated with an actual
signal source is generally neither precisely known nor strictly independent of signal source vol-
tage and current levels. The problem at hand is not severe in MOS technology realizations that
feature either a common source or a source follower amplifier input stage for which input port
biasing resistances (R
b
= ) are not essential. In these embodiments, the gate of the input stage,
which comprises the input port of each amplifier, conducts no current, at least at low to mod-
erately high signal frequencies. As a result, no signal voltage is established across either resis-
tance, R
s
, which is to say that resistances R
s
and their unavoidable mismatches are inconsequen-
tial when dealing with MOSFETs.
6.7.1. DIFFERENTIAL AND COMMON MODE SIGNALS
Because the amplifiers utilized in the differential system of Figure (6.45) are biased to
support linear signal processing of sufficiently small input signals, we can exploit superposition
theory to formulate general expressions that link the single ended output voltages, V
o1
and V
o2
, to
voltages V
s1
and V
s2
. In particular,
o1 11 s1 12 s2
o2 21 s1 22 s2
V A V A V
,
V A V A V
= +
= +
(6-146)
where the A
ij
are constants that are independent of all signal voltages and signal currents indigen-
ous to the differential network. We note that A
11
is the voltage gain, V
o1
/V
s1
, under the condition
of V
s2
= 0, while A
22
denotes the gain, V
o2
/V
s2
, with V
s1
= 0. In other words, A
11
is the voltage
transfer function of Amplifier #1 with Amplifier #2 and its associated subcircuit serving as a
kind of dummy load on #1 in that no input signal is externally applied to its input port. Simi-
larly, A
22
is the gain of Amplifier #2 when Amplifier #1 and its peripheral circuit functions as the
dummy load imposed on #2. But since the two amplifiers in question are matched and the ba-
lanced network at hand is electrically symmetrical, these two voltage gains are identical. Accor-
dingly, we assert
11 22 i
A A A . (6-147)
We can offer precisely the same stipulation as regards gain parameters A
12
and A
21
; that is,

- 580 -
12 21 f
A A A . (6-148)
This stipulation merely asserts that in a balanced differential pair, the sensitivity of output re-
sponse V
o1
to input signal V
s2
(with V
s1
= 0) is the same as the sensitivity of V
o2
to V
s1
(with V
s2
=
0). In other words, the cross-correlated voltage gains of the two amplifiers are identical in a ba-
lanced differential architecture. The preceding two results allow us to simplify (6-146) as
o1 i s1 f s2
o2 f s1 i s2
V AV A V
,
V A V AV
= +
= +
(6-149)
where we witness a need for only two parametric gains, A
i
and A
f
, to relate the single ended out-
put responses to the single ended input voltages applied to the balanced differential system.
In the process of analyzing the differential network in Figure (6.45), we shall find it
profitable to introduce the concepts of differential and common mode voltage and current sig-
nals. To this end, let the differential mode input signal voltage, say V
di
, be defined as the differ-
ence between the two applied input signal voltages; namely,
di s1 s2
V V V . (6-150)
In (6-150) we note an unmistakable algebraic similarity to the differential output voltage, V
do
,
defined by (6-145). On the other hand, the common mode input signal, V
ci
, is
s1 s2
ci
V V
V ,
2
+
(6-151)
which represents little more than the average of the two inputs. If we simultaneously solve (6-
150) and (6-151) for voltages V
s1
and V
s2
, we get
di
s1 ci
di
s2 ci
V
V V
2
.
V
V V
2
= +
=
(6-152)
Our ninth grade mathematics teachers would be proud of our algebraic skills. Teacher pride
notwithstanding, the design-oriented interpretation and implications of (6-152) are vital to
assimilating an insightful understanding of both the operation and utility of a balanced differen-
tial amplifier.
An important first implication of (6-152) is that the system in Figure (6.45) can be dia-
grammed as the circuit in Figure (6.46), where input signals V
s1
and V
s2
have been replaced by
the superposition of differential and common mode input voltages, as per (6-152). The latter
illustration highlights the fact that the common mode input signal is foundational to both V
s1
and
V
s2
, which activate the input ports of both of the matched amplifiers. As such, V
ci
might be
indicative of electrical noise radiated by lighting fixtures, nearby electrical appliances, or prox-
imately located electronics. Of course, the feasibility of both input ports witnessing precisely the
same unwanted electrical interference assumes that these ports are physically laid out closely to
one another on chip. The common mode input can also reflect fluctuations in biasing applied
commonly to both input ports. Such fluctuations might be incurred by electrical noise coupled to
the biasing line from which the input port biasing level is derived, temperature-induced changes
in device or circuit parameters, routine battery degradation, and other environmental phenomena.
As long as these network parasitic effects induce small changes in the common mode input vol-
tage level, the differential system continues to respond linearly to common mode signal fluctua-
tions, which is an underlying requirement of (6-149).

- 581 -

Figure (6.46). Alternative representation of the balanced differential architecture in Figure (6.45).
A laudable design goal that the foregoing arguments encourage is a differential network
that is disabled from responding to V
ci
and is therefore impervious to common mode signal
changes. A clue that we might be able to achieve, or at least to approximate, this design outcome
is offered by (6-152) and Figure (6.46) in that the differential input signal, V
di
= (V
s1
V
s2
), is
independent of the common mode input. It indeed stands to reason that if a signal parasitic or
otherwise is applied simultaneously (or commonly) to both of the amplifier inputs, the differ-
ence signal between these two input port voltages automatically cancels the common mode
excitation. Thus, if the balanced differential network can be designed in such a way as to re-
spond only to differential inputs, the output responses of the system are divorced of any
ramifications attributed to common mode excitations.
A second implication of the differential and common mode concepts is that the
superposition equations in (6-149) can be rewritten as
( )
( )
i f
o1 i f ci di
i f
o2 i f ci di
A A
V A A V V
2
;
A A
V A A V V
2
| |
= + +
|
\ .
| |
= +
|
\ .
(6-153)
that is, the single ended output responses, V
o1
and V
o2
, are individually a superposition of
differential and common mode inputs. This discovery is hardly worth texting home about since
the outputs are inherently a superposition of the effects of V
s1
and V
s2
. In turn, V
s1
and V
s2
are
+
+
+
Amplifier
#1
I
1
I
ll
I
b1
I
o1
I +I
1 2
I +I
b1 b2
R
gg
R
s
R
s
R
b
I
2
I
b2
I
o2
R
gg
R
b
Amplifier
#2
R
kk
R
l
R
l
R
bb
V
di
V
o2
V
o1
R
ll
R
ll
V
b
V
k
V
l
V
do
V
i1
V
i2
2
V
di
2
+
V
c
i
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Output Node:
Amplifier #2
Output Node:
Amplifier #2

- 582 -
linear functions of V
di
and V
ci
. Transparency notwithstanding, (6-153) serves to define three
traditionally adopted performance metrics of a balanced differential amplifier.
The first of these metrics is the differential voltage gain, say A
d
, which is the ratio of
the differential output voltage to the differential input voltage under the condition of a common
mode input voltage constrained to zero. Recalling (6-145),
ci ci
do o1 o2
d i f
di s1 s2
V 0 V 0
V V V
A A A .
V V V
= =
= =
(6-154)
In the course of formulating (6-154), we observe that the differential output response of a per-
fectly balanced differential pair is invariant with common mode input excitation, which is to say
that there is no common mode signal component to the differential output voltage response. If
we accept our view of a common mode input as reflecting undesirable electrical phenomena, this
independence of differential output voltage to common mode input voltage in a balanced pair is
commendable. The downside, however, is that since V
do
is not a single ended voltage response,
it is impossible to maintain a common signal ground between single ended input signals and
differential output response. This shortfall is troublesome in most electronic systems, but it can
be circumvented through the incorporation of a differential to single ended converter, which we
address later in this chapter.
The second relevant performance metric is the common mode voltage gain, A
c
, which is
the ratio of the common mode output voltage to the common mode input voltage when the
differential input signal is held at zero. A null differential input signal requires V
s1
= V
s2
and
therefore equal signal excitations are resultantly applied to both of the amplifier input ports.
Borrowing from (6-151), the common mode output voltage, V
co
, is defined as
o1 o2
co
V V
V .
2
+
(6-155)
This definition and (6-153) combine to evolve
( )
( )
di di
o1 o2 co
c i f
ci s1 s2
V 0 V 0
V V 2 V
A A A .
V V V 2
= =
+
= = +
+
(6-156)
In the idealized situation of a zero common mode gain, we see that gain parameter A
f
must be the
negative of gain parameter A
i
, which, by (6-154), gives a differential voltage gain of A
d
= 2A
i
or
equivalently, (2A
f
).
The final performance metric of interest in a differential amplifier is the common mode
rejection ratio, , which is simply the ratio of differential mode to common mode gains. From
(6-154) and (6-156),
i f
d
c i f
A A
A
.
A A A
=
+
(6-157)
The common mode rejection ratio, as its name implies, is a measure of the ability of a differen-
tial network to reject, or at least substantively attenuate, the network responses to common mode
input signals. Since A
c
is zero for complete rejection of applied common mode signals, the idea-
lized value of the common mode rejection ratio is = .
Equations (6-154), (6-156), and (6-157) can be used to express the output responses in
(6-153) in the form,

- 583 -
d d ci
o1 c ci di di
di
d d ci
o2 c ci di di
di
A A 2V
V A V V 1 V
2 2 V
.
A A 2V
V A V V 1 V
2 2 V
| |
| |
= + = +
| |
\ .
\ .
| |
| |
= =
| |
\ .
\ .
(6-158)
We have already seen, as is confirmed by the foregoing result, that the differential output re-
sponse, V
do
= (V
o1
V
o2
), in a balanced differential network is divorced of a common mode sig-
nal component. But interestingly, we now gather that
d d ci d
o1 c ci di di di
di
d d ci d
o2 c ci di di di
di
A A 2V A
V A V V 1 V V
2 2 V 2
,
A A 2V A
V A V V 1 V V
2 2 V 2
| |
| | | |
= + = + ~
| | |
\ . \ .
\ .
| |
| | | |
= = ~
| | |
\ . \ .
\ .
(6-159)
which is approximately independent of the common mode input signal, provided that
di
ci
V
V .
2
| |
>>
|
\ .
(6-160)
Absolute value signs are incorporated in the last expression to allow for the possibility that V
di
,
V
ci
, and/or may be negative in an application. In short, the individual single ended output res-
ponses show no significant common mode deterioration if either the common mode rejection ra-
tio is large and/or the common mode input signal is small. For this special, yet recurring, case,
we note that the magnitude of the single ended to differential input voltage gains, V
o1
/V
di
and
V
o2
/V
di
, are identical and equal to one-half of the differential gain of the of the entire differential
amplifier. Moreover, the individual single ended output responses are 180 out of phase with
one another, which gives the circuit designer flexibility over choosing V
o1
or V
o2
as the preferred
single ended output response. Note, however, that the price paid for selecting either of the two
single ended output voltages as the network response, as opposed to choosing the differential
output voltage as the response, is a factor of two attenuation in the observable I/O gain.
Although we have focused herewith on only the output voltage responses of the ba-
lanced differential amplifier, any network voltage or current variable is comprised of common
mode and differential mode components that abide by the general form of (6-159). In short,
Circuit Variable Common Mode Component
Half Differential Mode Component ,
=
(6-161)
where it is understood that the plus (+) sign applies when the circuit variable of interest is asso-
ciated with that part of the network that is driven by +V
di
/2, and the minus () sign applies to
that part of the system that is driven by V
di
/2. For example, consider currents I
1
and I
2
in Figure
(6.46), where I
1
flows out of Amplifier #1. It is important that we observe that this amplifier is
excited at its input port by a signal voltage whose differential component is couched as +V
di
/2.
On the other hand, current I
2
flows out of Amplifier #2, whose input differential signal is V
di
/2.
In accord with the defining nature of common mode signals, both amplifiers are excited by a
common mode signal component, V
ci
. Letting subscript d designate differential mode re-
sponse and subscript c denote common mode response, we use (6-161) to write for currents I
1

and I
2
,

- 584 -
d1
1 c1
d1
2 c1
I
I I
2
.
I
I I
2
= +
=
(6-162)
Because of circuit linearity, current I
c1
is linearly related to the common mode input voltage, V
ci
,
while differential current I
d1
is directly proportional to the differential input voltage, V
di
. Al-
though currents I
1
and I
2
have different values because of the phase inversion ascribed to their
differential components, both currents share the same common mode part and the same magni-
tude of differential component. This observation synergizes with our perception of a balanced
amplifier. Its propriety can be confirmed qualitatively by mentally applying superposition theory
to the network in Figure (6.46). To wit, if V
di
is set to zero, thereby constraining the differential
components of all circuit variables to zero, voltage V
ci
is the only voltage applied to the input
ports of each amplifier. But because each amplifier and its terminations are identical in all elec-
trical respects, a current of I
1
= I
c1
generated by V
ci
applied to Amplifier #1 mirrors the common
mode component of current I
2
produced by V
ci
, which is simultaneously applied to Amplifier #2.
With V
ci
set to zero, the common mode components of all network variables are vanquished, and
+V
di
/2 is applied to Amplifier #1, while the negative of this voltage excites the input port of Am-
plifier #2. Once again, linearity allows us to state that if +V
di
/2 causes a current of I
d1
/2 to flow
out of the third lead of Amplifier #1, the corresponding lead of Amplifier #2 necessarily con-
ducts an outward current of I
d1
/2. Yes, a negative differential current is produced. We must
remember that all of these currents represent only signal components of corresponding net cur-
rents.
An apparent dilemma with the foregoing abstractions occurs with respect to the vol-
tages, V
b
, V
k
, and V
l
, which are established at circuit nodes lying on the electrical centroid of the
network. In other words, are the differential components of these centroidal variables associated
with +V
di
/2 or with V
di
/2? There are two ways to address this dilemma, which we shall
exemplify with voltage V
k
. The first way entails blindly writing
dk
k ck
dk
k ck
V
V V
2
.
V
V V
2
= +
=
(6-163)
Clearly, (6-163) makes engineering sense only if the presumed differential part, V
dk
, of voltage
V
k
is zero. This postulate infers that V
k
contains no differential component and therefore only a
common mode component, V
ck
. Our argument is reasonable in that if the indicated +V
di
/2 incurs
a rise in voltage V
k
, the corresponding V
di
/2 applied to the second amplifier causes a decrease in
V
k
by precisely the same amount as the observed initial increase. Hence, no net change is mani-
fested in voltage V
k
if only a differential input signal is applied to the overall configuration.
The situation just described is reminiscent of the seesaws we enjoyed with our child-
hood friends. Upon mounting the seesaw, a push downward by our friend sitting at one end of
this playground equipment is matched by our swinging upward by precisely the same amount as
the initial downward travel at the other end, and vice versa. Accordingly, there is differential
swing in that the motion downward (upward) at one end of the equipment is mirrored at the
other end of the seesaw by upward (downward) displacement. But despite the amount of
differential swing, the fulcrum of the seesaw, which is effectively the centroid of the equip-
ment, moves neither upward nor downward. In other words, there is no differential displacement

- 585 -
at the seesaw centroid. In effect, the fulcrum is grounded, thereby allowing us to measure the
amount of displacement at either end of the seesaw with respect to the fulcrum, or common
mode ground. And note, in concert with (6-161), that the displacement of either end of the see-
saw, measured with respect to the common mode fulcrum, is one-half of the net, end to end,
differential swing.
An alternative way of addressing the problem at hand is to compute voltage V
k
in terms
of the currents, I
1
and I
2
, disclosed in (6-162). We glimpse in Figure (6.46) that the current flow-
ing through resistance R
kk
, which returns to ground the circuit node at which voltage V
k
is estab-
lished, is (I
1
+ I
2
). But from (6-162), we see that (I
1
+ I
2
) has only a common mode constituent
(actually twice the common mode current indigenous to either current I
1
or current I
2
). If there is
no differential current implicit to (I
1
+ I
2
), there can be, if Ohm is to promoted, no differential
part to voltage V
k
, which appears directly across resistance R
kk
.
6.7.2. HALF CIRCUIT ANALYSIS
The straightforward, but annoyingly cumbersome, way to assess the small signal
performance of the differential pair diagrammed in Figures (6.45) and (6.46) entails chasing the
solutions to the Kirchhoff equations written subsequent to replacing each amplifier by its
appropriate small signal model. This tack can prove formidable, particularly if the individual
amplifiers are complex architectures. Unfortunately, complex analyses invariably foster compli-
cated, if not intractable, disclosures that inhibit an insightful understanding of circuit operation.
A better analytical approach is predicated on exploiting the architectural symmetry inherent in a
balanced differential network.
6.7.2.1. Differential Mode Half Circuit
With superposition in mind, consider first the case of zero common mode input voltage,
which fosters zero common mode components to all network branch currents and node voltages.
As indicated in Figure (6.47a), voltage V
o1
sits at +V
do
/2, V
o2
= V
do
/2, and V
i1
= V
i2
= +V
d1
/2,
where V
d1
is the voltage difference, V
d1
= (V
i1
V
i2
). For reasons that we articulated in the
preceding subsection, voltage V
k
in Figure (6.46), which can assume only a common mode sta-
ture, is zero when the common mode input signal is null. In effect, the node at which voltage V
k

is established acts as a virtual signal ground when the only prevailing input signal is differential
in nature. Voltage V
b
in the same diagram is analogous to V
k
, and the node that supports this vol-
tage, like the node supporting voltage V
k
, also lies at signal ground potential. Let us now ex-
amine voltage V
l
. An inspection of the current, I
ll
, conducted by the series interconnection of the
two resistances labeled R
ll
reveals
do
l
do
ll
ll ll
V
V
V
2
I ,
2R R
= = (6-164)
which immediately forces V
l
= 0. Like the nodes at which voltages V
k
and V
b
are sustained, the
junction supporting voltage V
l
with respect to ground is a virtual signal ground. These discove-
ries allow us to replace, for exclusively differential input excitation, the entire differential
architecture in Figure (6.46) by the half circuit offered in Figure (6.47b). Either the top half or
the bottom half of the circuit can form the basis of this differential mode half circuit topology.
We have chosen the top half. If we had opted for the bottom half, the only significant changes
would be an input signal of V
di
/2 and a resultant output response of V
do
/2.

- 586 -

Figure (6.47). (a). The balanced differential architecture of Figure (6.46) under the condition of zero common
mode input voltage. (b). The differential mode half circuit model of the network in (a).
In the half circuit of Figure (6.47b), the I/O voltage gain, which is the ratio of output
signal voltage V
do
/2 to applied input signal voltage V
di
/2, is equal to the differential voltage gain,
A
d
, defined by (6-154) of the entire balanced differential amplifier shown in Figure (6.45). We
enthusiastically note that this gain metric is obtainable through consideration of only one-half of
the original balanced network. The analytical simplifications that ensue from an investigation of
a compressed architecture are likely to be enhanced further in that there is a distinct likelihood
that Amplifier #1 in Figure (6.47b) is a familiar or otherwise recognizable circuit architecture.
For example, Amplifier #1 may be one of the networks we have already studied in depth, or it
+
Amplifier
#1
I /2
d1
I
ll
I /2
db
0 0
R
gg
R
s
R
s
R
b
I /2
d1
I /2
db
R
gg
R
b
Amplifier
#2
R
kk
R
l
R
l
R
bb
V
di
R
ll
R
ll
V = 0
b
V = 0
k
V = 0
l
V
do
V /2
d1
2
V
di
2
+
V /2
d1
V /2
do
V /2
do
(a).
+
Amplifier
#1
I /2
d1
I /2
db
R
gg
R
s
R
b
R
l
V
di
R
ll
V /2
d1
2
V /2
do
R /2
di
R /2
do
(b).

- 587 -
could be a combination of two or more of these previously investigated active structures. In this
event, an evaluation of the differential gain amounts to little more than adapting previously de-
rived circuit performance results to the half circuit model at hand.
The foregoing gain assertions apply to the task of evaluating the input and output resis-
tances. But we must exercise care when interpreting these resistance results. To wit, the input
resistance seen by the signal source in the differential mode half circuit model is delineated as
R
di
/2 in Figure (6.47b). Parameter R
di
denoted the differential mode input resistance, which is to
say that it is the net effective resistance seen by the net differential input voltage, V
di
, under the
condition of zero source resistance; that is, R
s
= 0. In other words, R
di
is the input resistance seen
across the two amplifier input nodes that support voltages V
i1
and V
i2
in Figure (6.46). But since
the network in Figure (6.47b) is only one-half of the original balanced configuration, wherein all
centroid nodes are returned to signal ground, the input resistance actually evaluated in the subject
half circuit diagram is one-half of the true differential input resistance of the entire amplifier. An
analogous situation prevails for the differential mode output resistance, R
do
, where in the present
case, we have elected to include resistances R
l
and R
ll
in the calculation. The schematic diagram
in Figure (6.47b) correctly shows that a resistance evaluation pursued at the output port of the
half circuit results in only one-half of the net differential output resistance for the original circuit.
6.7.2.2. Common Mode Half Circuit
Having studied the balanced differential amplifier for the differential mode case in
which the common mode input signal, V
ci
, is held to zero, let us now turn our attention to the
common mode situation for which the input differential signal, V
di
, is set to zero. The electrical
conditions corresponding to exclusively common mode signal excitation are highlighted in Fig-
ure (6.48a), where all branch currents and node voltages assume their common mode values.
The corresponding common mode half circuit appears in Figure (6.48b). Several differences are
apparent when we compare this model to its differential mode counterpart in Figure (6.47b). We
can begin to underscore these differences by first examining the common mode voltage, V
cb
,
which is developed at the node to which the two resistances of value R
b
and the resistance, R
bb
,
are incident. Unlike the differential value, V
db
, of voltage established at the subject circuit node
when the common mode signal is set to zero, voltage V
cb
is not zero in that it must support the
flow of current through R
bb
. This current is twice the common mode current, I
cb
, conducted by
each of the two resistances, R
b
, whence V
cb
= 2I
cb
R
bb
. The common mode half circuit, which we
arbitrarily choose to construct from the top half of the network in Figure (6.48a), must be faithful
to the current conducted by resistance R
b
, as well as to the voltage, V
cb
. Since a current of (2I
cb
)
rattling through a resistance of R
bb
develops the same voltage that does a current of I
cb
conducted
by an effective resistance of (2R
bb
), we place a resistance of (2R
bb
) in series with the resistance,
R
b
. An analogous situation pervades resistances R
k
and R
kk
, whence (2R
kk
) appears in series with
R
k
in the common mode half circuit. Resistances R
ll
in Figure (6.48a) are not embedded in Fig-
ure (6.48b) for the simple reason that neither of the R
ll
resistances conducts any current. This
null value of current is caused by the fact that the voltages appearing with respect to signal
ground at both of the single ended amplifier output ports are identical and, in fact, equal to the
common mode voltage response, V
co
. It follows that the differential voltage generated between
these two ports, and which appears across the series interconnection of the two circuit resis-
tances, R
ll
, is zero, which harmonizes with the zero differential signal input state on which we are
presently focused. If no current flows through a branch, no electrical purpose is served by the
branch. We are therefore afforded the simplification luxury of trashing this non-conductive
branch.

- 588 -

Figure (6.48). (a). The balanced differential architecture of Figure (6.46) under the condition of
null differential mode input excitation. (b). The common mode half circuit model
of the network in (a).
We now see that the voltage gain, V
co
/V
ci
, of the common mode half circuit in Figure
(6.48b) is precisely the common mode voltage gain, A
c
, of the entire balanced differential am-
plifier. As in the case of the differential voltage gain, which derives as the voltage gain of the
differential mode half circuit, this gain can usually be evaluated either by inspection or with the
(a).
+
V
c
i
+
Amplifier
#1
I
c1
I = 0
ll
I
cb
2I
cb
R
gg
R
s
R
s
R
b
I
c1
I
cb
R
gg
R
b
Amplifier
#2
R
kk
R
l
R
l
R
bb
R
ll
R
ll
V
cb
V
cb
V
ck
0
V
c1
V
c1
V
co
V
co
+
Amplifier
#1
I
c1
I
cb
R
gg
R
s
R
b
2R
bb
2R
kk
R
l
V
ci
V
c1
V
co
R
ci
R
co
(b).
2I
c1
V
ck

- 589 -
minimal amount of analysis that our previous circuit analysis experiences foster. The input resis-
tance of the common mode half circuit is denoted as R
ci
and is termed the common mode input
resistance. It represents the net resistance with respect to signal ground established at both of the
two amplifier input port nodes, where signal voltages V
i1
and V
i2
respectively appear in the sys-
tem of Figure (6.45). Similarly, the common mode output resistance, R
co
, of the balanced
differential network is identical to the output resistance witnessed in the common mode half cir-
cuit. It is the resistance with respect to signal ground at either of the two output port nodes of the
original balanced network.
6.7.2.3. Utility of the Half Circuit Models
In the interest of clarity, it is worthwhile placing the analytical issues deriving from the
half circuit models of a balanced differential pair into perspective. Let us start with I/O gain is-
sues. The differential gain, A
d
, which is literally the voltage transfer function of the differential
mode half circuit in Figure (6.47b), is the ratio of the differential output voltage to the difference
between the two applied signals in the balanced pair of Figure (6.45). Specifically,
do o1 o2
d
di s1 s2
V V V
A ,
V V V
= =
(6-165)
where we understand that all stipulated voltages are small signal components that are divorced of
any biasing levels. In contrast, the common mode gain, A
c
, which derives as the voltage transfer
function, V
co
/V
ci
, of the common mode half circuit in Figure (6.4b8), is
( )
( )
o1 o2 co o1 o2
c
ci s1 s2 s1 s2
V V 2 V V V
A .
V V V 2 V V
+ +
= = =
+ +
(6-166)
At least four single ended gain relationships may be of interest to the circuit designer.
The first of these is the ratio of the single ended voltage, V
o1
, in Figure (6.45) to the applied input
signal, V
s1
, under the condition that input signal V
s2
is held to zero. Using (6-150), (6-151), and
(6-158),
s2
s2
do c s1 d s1
co
o1 d c
11
s1 s1 s1
V 0
V 0
V A V A V
V
V A A
2 2 2
A ,
V V V 2
=
=
+ +
+
= = = (6-167)
where we introduced constant A
11
in the fundamental equilibrium relationship of (6-146). Be-
cause of the balanced nature of the differential amplifier undergoing scrutiny, this is the same as
the ratio of the second of the two available single ended output voltages, V
o2
, to the second ap-
plied input signal, V
s2
, under the constraint of V
s1
= 0. In short,
s1 s2
o2 o1 d c
22 11 i
s2 s1
V 0 V 0
V V A A
A A A ,
V V 2
= =
+
= (6-168)
The voltage gain from the second input signal to the first single ended output, for the case of V
s1

= 0, is
( )
s1
s1
d s2
do c s2
co
o1 d c
12
s2 s2 s2
V 0
V 0
A V
V A V
V
V A A
2 2 2
A .
V V V 2
=
=
+ +

= = = (6-169)

- 590 -
Finally, the voltage gain from the first input signal to the second single ended output with V
s2
= 0
is the same as the gain just disclosed. In other words, the balanced nature of the amplifier at
hand delivers
s2 s1
o2 o1 d c
21 12 f
s1 s2
V 0 V 0
V V A A
A A A .
V V 2
= =
= (6-170)
We observe that if |A
c
| << |A
d
|, which implies a large common mode rejection ratio, , all of the
gains in (6-167) through (6-168) are nominally independent of the network common mode gain
and given quite simply as A
d
/2.
The interpretation of the differential mode and common mode input and output resis-
tances is facilitated by the conceptual port models advanced in Figure (6.49)
[10]
. We begin with
the input port model shown in Figure (6.49a). There is little to argue about the fact that the com-
mon mode input resistance, R
ci
, terminates each input port of the balanced differential amplifier
to ground. However, a potential argument surfaces concerning the resistance, R
xi
, which is
shown connecting together the subject two input ports. It seems almost natural to view this resis-
tance as the differential input resistance. But natural inclinations can be fallacious, and the
present case is no exception to this problematic view. In particular, we must remember that R
di

represents the net resistance established differentially across the two amplifier input ports. As
such, we recognize that R
di
must take due account of the port loading effected by the two com-
mon mode input resistances, R
ci
. Thus, we must select resistance R
xi
in such a manner that the
net resistance seen between input ports 1 and 2 is the differential input resistance, R
di
, computed
from the differential mode half circuit. In particular,

Figure (6.49). (a). Conceptual circuit model for the input ports of the balanced differential amplifier in
Figure (6.45). (b). Conceptual circuit model for the output ports of the balanced differen-
tial amplifier in Figure (6.45).
( )
di xi ci
R R 2R . = (6-171)
We can compute R
di
from the differential mode half circuit model, while R
ci
derives from an
examination of the common mode half circuit model. Armed with values for both R
di
and R
ci
,
(6-171) straightforwardly delivers
ci di
xi
ci di
2R R
R .
2R R
=
(6-172)
As expected, large R
ci
, which implies minimal common mode loading of the two amplifier input
ports, promotes R
xi
R
di
.
The situation at the output ports, which is abstracted in Figure (6.49b), is the same as
that considered for the input ports. Thus, we offer without analytical fanfare,
R
ci
R
xi
R
ci
V
i2
V
i1
R
di
(a).
R
co
R
xo
R
co
V
o2
V
o1
R
do
(b).
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Output Node:
Amplifier #1
Output Node:
Amplifier #2

- 591 -
co do
xo
co do
2R R
R .
2R R
=
(6-173)
In order to demonstrate the utility of the port resistance models, let us suppose that the
balanced differential pair of Figure (6.45) is operated with signal voltage V
s2
equal to zero. We
wish to determine the input resistance, say R
in
, seen by the signal applied to input port 1. The
applicable macromodel is the resistive network of Figure (6.50a), where we have terminated in-
put port 2 to ground in the physical resistance, R
s
, which, of course, is matched to the internal
resistance implicit to signal source V
s1
. By inspection of the subject model, we see that

Figure (6.50). (a). Model used to evaluate the input resistance, R
in
, seen at port 1 of the balanced differential
amplifier in Figure (6.45) under the condition that signal source V
s2
is zero. (b). Model used to
compute the output resistance, R
out
, at either output port of the balanced differential amplifier in
Figure (6.45).
( ) ( )
ci di
in ci xi ci s ci ci s
ci di
2R R
R R R R R R R R .
2R R
(
( = + = +
(

(6-174)
We note that this input resistance is dependent on resistance R
s
. But once again, this particular
R
s
is not the source resistance associated with the first signal voltage, V
s1
. Instead, it is the port 2
physical resistance required to match both of the input ports of the differential configuration.
Figure (6.50b) is the model pertinent to computing the output port resistance, R
out
,
which, because of amplifier symmetry, is identical for both output ports. By inspection of this
model and with (6-173) in mind, we find that the output resistance is
| |
co do
out co xo co co co
co do
co do
co co
co do
2R R
R R R R R R
2R R
2R R
R R .
2R R
(
= + = +
(

( | | +
=
( |
(
\ .
(6-175)
Equation (6-175) projects a net output resistance that is larger than R
co
/2 for given common
mode and differential mode output resistances. We see, however, that R
out
R
co
if R
do
= 2R
co
,
which, by (6-173), is tantamount to an infinitely large output port coupling resistance, R
xo
.
EXAMPLE #6.4:
A specific example of a balanced differential amplifier one that exploits
standard cell networks that we have already encountered is the somewhat
imposing structure in Figure (6.51). For this amplifier, we wish to deter-
mine approximate expressions for the low frequency, single ended, small
signal voltage gain, A
v
= V
o2s
/V
s
, the input resistance, R
in
, seen by the sig-
R
ci
R
in
R
out
R
xi
R
ci
R
s
V
i2
V
i1
(a).
R
co
R
xo
R
co
V
o2
V
o1
(b).
R
out
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Output Node:
Amplifier #1
Output Node:
Amplifier #2

- 592 -
nal source comprised of the series interconnection of Thvenin signal vol-
tage V
s
and Thvenin source resistance R
s
, and the driving point output
resistance, R
out
. Finally, we wish to determine the common mode
rejection ratio and explore means to maximize this performance ratio. Al-
though we can determine these and other amplifier metrics by considering
the effects of all device channel resistances, device bulk transconduc-
tances, and other second order circuit and layout phenomena, we shall
adopt herewith a simplified analytical strategy that is premised on several
operating presumptions and stipulations. It should be painfully obvious
that an analysis executed by replacing each transistor by its small signal
model (with due account made of channel resistance and body effect) is
not a viable option.
SOLUTION #6.4:
(1). The constraints and presumptions for which we shall weave our approximate analysis are ite-
mized herewith.
(a). We shall assume that all transistors are biased in their saturation regimes where they are
presumed to have very large drain-source channel resistances and negligibly small bulk
transconductances. Obviously, all diode-connected transistors are automatically satu-
rated. It follows that the low frequency, small signal model of every transistor consists
merely of a voltage controlled current source, g
m
V, directed from drain terminal to source
terminal. Of course, g
m
is the forward transconductance of a transistor, and V symbolizes
the signal component of the net gate to source voltage imposed on the device whose
transconductance is g
m
.
(b). Implicit to the foregoing transistor modeling assumption is the presumption that the sig-
nal frequencies implicit to signal source V
s
are not so high as to require a consideration of
intrinsic transistor capacitances.
(c). Circuit capacitances C
1
and C
2
are chosen to behave as short circuited branch elements
for all radial signal frequencies above a proscribed minimum, say
l
. Thus, while we
shall be cavalier in referring to the amplifier as a lowpass entity, in truth, the network
operates acceptably only for frequencies above
l
. Our reference stance is tolerable if
the 3-dB bandwidth is significantly larger than the low cutoff frequency,
l
.
(d). We are advised that the amplifier is a balanced configuration. This balance requires that
transistor Mi be geometrically and electrically matched to transistor Mia for i = 1, 2, 3, 4.
Note that transistor Mj or Mja need not be respectively matched to transistor Mi or Mia in
order for operational balance to be effected. Thus, for example, transistors M2 and M2a
must be identical, inclusive of gate aspect ratios. But transistors M1 and M1a, which
must be a matched pair, need not have the same gate aspect ratios as do M2 and M2a.
(2). Confronting any intricate circuit schematic for the first time can be an imposing ordeal for
even the more venerable of circuit design engineers. This taxing experience is all too often
exacerbated by an inclination to initiate mathematical analysis without an adequate apprecia-
tion of the design targets for the circuit at hand. Moreover, the experience is aggravated by
the absence of a strategy supportive of streamlined analytical procedures that produce re-
sponse disclosures couched to maximize engineering insights. An impressively precise and
definitive analysis that illuminates no results that are transparently applicable to circuit de-
sign is a moot accomplishment in the electronic circuits and systems discipline. But
approximate disclosures whose sources of error are clearly understood, quantified, and
understandable are priceless assets when we profit from them in the course of successfully
navigating a design challenge.

- 593 -

Figure (6.51). An example of a balanced differential pair. Although not explicitly shown, the bulk terminals of
all transistors are connected to circuit ground, which in this case is the minimum static potential
to which the circuit is exposed. The low frequency, small signal analysis of the amplifier is car-
ried out in the text for the simplifying approximations of very large device channel resistances
and negligible bulk transconductances in all transistors.
We therefore argue that the best first step to conducting a meaningful analysis of a practical
circuit is to lose the pencil and paper and to turn away from the computer. Instead, we begin
by studying the circuit schematic provided us albeit in only qualitative or visceral senses to
ascertain the functionality of the various active and passive circuit components implicit to the
network. If we execute this type of investigation with care and without violating any of the
fundamental precepts of circuit analysis, we just might quickly deduce first order response
results that can form an engineering basis for more definitive computer-aided follow-up.
Practicing this analytical tack for a variety of circuit structures has long-term benefits in that
it increases our intuitive abilities to gauge and estimate circuit dynamics. In the process, our
design skills are invariably honed.
Let us therefore return to the circuit schematic diagram in Figure (6.51) to deduce the basic
functionality and purposes of the various components therein. We might interject here that if
we ultimately find that our qualitative circuit overview fails to synergize with our approx-
imate analytical results, we need rush to call 911, in the hope of averting a design tragedy.
A poor meshing of qualitative observations and analytical disclosures means that we made an
analytical error, we made an inappropriate qualitative conclusion, or perhaps we messed up
on both accounts. Regardless, poor meshing of independently deduced observations offers an
excellent learning opportunity. If we act responsibly, we will admit the error and then work
diligently to uncover and mitigate it. And in the process, we just might learn something new
that will minimize the likelihood of similar future errors.
(a). We know that a balanced differential amplifier exploits two amplifiers whose architec-
tures, biasing, I/O terminations, and other electrical properties at circuit nodes and within
circuit branches are matched. We see that one of the requisite amplifiers in the balanced
configuration of Figure (6.51) is forged by transistors M1, M2, M3, and M4. The other
(matched) amplifier is forged by transistors M1a, M2a, M3a, and M4a.
(b). We recognize transistors M1 and M1a as common source amplifiers in that signal is ap-
plied to the gate terminal of M1, with the understanding that a zero amplitude signal is
+
M2
M7
M2a
M1 M1a
R
l
R
ss
R
b
R
s
R
s
V
s
R
b
R
ss
R
l
R
kk
M8
C
1
C
1
C
2
M4a
M3a
V
o2
V
bias1
M4
M3
V
o1
M5
M6
+V
dd
R
V
y1
V
y2
R
in
R
out

- 594 -
applied to the gate of transistor M1a. The outputs of these transistors are extracted at
their respective drain terminals. The common source amplifiers at hand are source
degenerated via resistances R
ss
. We recall from our earlier travels that this source
degeneration resistance desensitizes the gain of the amplifier with respect to the forward
transconductances of its embedded active elements. Resistance R
kk
, is required to
provide a current path to ground for the source currents conducted by transistors M1 and
M1a. Without R
kk
, the source current of one of these two transistors would be inappro-
priately constrained to be the negative of the net source current of the other transistor.
(c). The drain current outputs of the M1-M1a pair are applied to common gate transistors M2
and M2a, ostensibly for the purpose of mitigating Miller time for the gate-drain capacit-
ances of transistors M1 and M1a. We note that the gates of M2 and M2a are grounded,
via capacitance C
2
, for all signal frequencies of immediate interest. This capacitive
termination leaves only the source terminals of the common gate units as input ports and
their drains as output ports. The gates of these two common gate transistors are biased
by the power line active divider comprised of diode-connected transistors M7 and M8. It
is notable that neither of these latter two devices plays a role in the small signal perfor-
mance of the amplifier. In particular, transistor M8 is shorted (above frequency
l
) to
ground through capacitance C
2
. Recall that C
2
, like all other indicated circuit capacit-
ances, is chosen to emulate a short circuit for frequencies of interest, presumably for both
differential and common mode circumstances. On the other hand, the gate and drain
terminals of transistor M7 lie at signal ground, assuming that the power line is driven by
an essentially ideal voltage source, V
dd
. Moreover, the source terminal of M7 is returned
to ground via capacitance C
2
. It follows that for small signals, M7 is connected between
ground and ground; that is, it is incident with ground.
(d). A similar divider this one formed of transistors M5 and M6 powers the gate terminals
of the common source transistors, M1 and M1a. Because no static current is conducted
by transistor gates and no static current flows through the coupling capacitances, C
1
, no
static current flows through the bias resistances R
b
. Accordingly, the static voltage devel-
oped at the source terminal of transistor M5 in the divider topology is the static voltage
manifested at the gates of transistors M1 and M1a. Unlike transistors M7 and M8, M5
and M6 are not bypassed to ground and therefore, they do influence the small signal
performance of the entire amplifier.
(e). The load imposed on the common source-common gate cascode formed of transistor
pairs M1-M1a and M2-M2a consists of the interconnection of the single ended resis-
tances, R
l
, and the resistance, R, which is connected differentially between the two am-
plifier output ports. The voltages, V
y1
and V
y2
, developed across this terminating load
structure are coupled to the amplifier output ports through the balanced source follower
comprised of the transistor pair, M3-M3a. We see that each of these two source follower
transistors is terminated in active loads formed of the matched transistor pair, M4-M4a.
Because only a constant bias voltage, V
bias1
, is applied to the gates of the latter two
transistors, no signal voltage prevails across the gate-source terminals of either M4 or
M4a. As a result, the g
m
V dependent sources in the small signal models of M4 and M4a
are zero, thereby leaving, in view of the presumed negligible body effect, only drain-
source channel resistances in these models. But since all device channel resistances are
taken as very large, the small signal models of M4 and M4a reduce to effective open cir-
cuits at their respective drain sites. This state of affairs is indicative of the fact that M4
and M4a conduct only constant currents that necessarily have no signal-induced change
and therefore, zero small signal current value. In short, M4 and M4a behave as open cir-
cuits for the signals applied to the differential amplifier.
(2). The foregoing observations encourage us to simplify the given schematic diagram expressly
for the purpose of small signal analysis. The specific simplification that supports efficient

- 595 -
small signal analysis is the AC signal schematic diagram provided in Figure (6.52). This
diagram crops all independent biasing sources from the schematic picture. Accordingly, the
V
dd
power line appears now as a signal short circuit to ground. More formally, the battery
voltage, V
dd
, has been replaced by its small signal value, which is zero, if V
dd
emulates a con-
stant voltage source. With the line voltage removed, all variables in the circuit assume their
respective small signal values. Thus, voltage V
y1
in Figure (6.51) becomes signal voltage V
y1s

in Figure (6.51), voltage V
o1
is supplanted by V
o1s
, and so forth, where as usual the subscript,
s, is understood to identify a small signal value of a branch current or a node voltage. Be-
cause of the signal short circuit natures of V
dd
and capacitance C
2
, transistors M7 and M8 in
Figure (6.51) do not appear in the signal schematic version of the amplifier because these de-
vices are shorted for the signal frequencies of interest. In concert with the discussion above,
transistors M4 and M4a in Figure (6.51) become open circuits in Figure (6.52). Because
transistors M5 and M6 are diode-connected two terminal branch elements, these transistors
are replaced by their small signal resistance values, which, in consideration of the approxima-
tions invoked, are 1/g
m5
and 1/g
m6
, respectively. Finally, all circuit capacitances are replaced
by short circuits on the presumption that we are currently focused on the signal processing
characteristics of the differential amplifier for frequencies above the lowest frequency,
l
, of
interest.

Figure (6.52). The AC schematic equivalent of the balanced differential amplifier shown in
Figure (6.51).
(3). Before turning to the actual analysis of the circuit in Figure (6.52), we should also note that
since the source follower transistors, M3 and M3a, are terminated in open circuits, their
individual voltage gains are unity, owing to the assumptions of large channel resistances and
negligible bulk transconductances (negligible CLM and BITM). This fact follows from the
disclosures in Section (6.4.0). Consequently, V
y1s
= V
o1s
and V
y2s
= V
o2s
. More definitively,
do dv di
o1s co cv ci y1s
do dv di
o2s co cv ci y2s
V A V
V V A V V
2 2
,
V A V
V V A V V
2 2
= + = + =
= = =
(E4-1)
+
M2 M2a
M1
R
l
R
ss
R
b
R
s
R
s
V
s
R
l
M3a
V
o2s
M3
V
o1s
M1a
R
b
R
ss
R
kk
R
V
y1s
V
y2s
g
m5
1
g
m6
1
R
in
R
out

- 596 -
where A
dv
denotes the differential mode voltage gain of the balanced amplifier, and A
cv
is its
common mode voltage gain. From (6-150) and (6-151), the differential input voltage, V
di
, ap-
plied to the balanced pair is
di s
V V , = (E4-2)
while the common mode input signal voltage, V
ci
, is
s
ci
V
V .
2
= (E4-3)
It follows by (6-170) that the desired overall voltage gain, A
v
, of the network undergoing
investigation is
o2s dv cv
v
s
V A A
A .
V 2
= = (E4-4)
which underscores our need to evaluate both the differential and common mode gains in or-
der to determine the overall single ended voltage gain of the balanced differential amplifier.

Figure (6.53). (a). Differential mode, small signal, half circuit schematic diagram of the balanced differential
amplifier in Figure (6.51). (b). Common mode, small signal, half circuit schematic diagram
of the balanced differential pair in Figure (6.51).
(4). Figure (6.53a) delineates the AC differential mode half circuit for the amplifier diagrammed
in Figure (6.52). In concert with our earlier discussions, the circuit node to which resistance
R
kk
is connected, the node to which the resistances, 1/g
m5
and 1/g
m6
, are incident, and the mid-
point of resistance R are all grounded. Since the half model in question applies only to
differential mode, all circuit node voltages, as well as all branch currents, are divorced of
common mode components and have only half amplitude differential mode signal
components. The input signal applied to the half circuit is now V
di
/2. At the output port, we
have made use of the fact that the source follower transistor, M3, delivers unity gain, whence
its output signal voltage, V
do/
2, is identical to the signal voltage that prevails at its gate ter-
minal.
+
M1
R
l
R
ss
R
b
R
s
V
di
M3
V /2
do
V /2
do
R/2
R /2
di
R /2
do
V /2
dii
I /2
d1
M2
I /2
d1
I /2
d1
(a).
2
+
M2
R
l
R
s
V
ci
M3
V
co
V
co
R
co
I
c1
2R
kk
M1
R
ss
R
b
R
ci
V
cii
I
c1
I
c1
g +g
m5 m6
2
(b).

- 597 -
We observe further that the indicated input resistance is R
di
/2; that is, it is one-half of the
differential input resistance of the entire balanced amplifier. Given that the gate of transistor
M1 conducts no current at low to moderately high signal frequencies, a casual inspection of
the diagram in Figure (6.53a) produces
di
b
R
R .
2
= (E4-5)
Recalling our work with source followers, the indicated half differential output resistance,
R
do
/2, is simply the resistance presented by transistor M3 at its source terminal. Within the
framework of our approximations, this resistance is 1/g
m3
. Specifically,
do
m3
R 1
.
2 g
= (E4-6)
We now turn to the calculation of the differential voltage gain, A
dv
. In Figure (6.53a), the sig-
nal voltage, V
dii
/2, established at the gate of transistor M1 is a voltage divider function of the
input signal, V
di
/2. This is to say that
dii b di b1 di
b s
V R V k V
,
2 R R 2 2
| |
= =
|
+
\ .
(E4-7)
where
b
b1
b s
R
k
R R
=
+
(E4-8)
is the divider function for the input port. Because signal voltage V
dii
/2 is established at the
gate of transistor M1, whose source is degenerated by resistance R
ss
, the signal drain current
of M1 is
d1s m1 b1 di
m1 ss
I g k V
.
2 1 g R 2
| |
=
|
+
\ .
(E4-9)
As is indicated in the diagram of Figure (6.53a), this current cruises through common gate
device M2 and thence into the net load resistance, which is comprised of the shunt
interconnection of resistances R
l
and R/2. It follows that the half differential output voltage,
V
do
/2, is
do d1s m1 b1 di
l l
m1 ss
V I g k V R R
R R ,
2 2 2 1 g R 2 2
| | | | | |
= =
| | |
+
\ . \ . \ .
(E4-10)
which gives a small signal, low frequency (but at frequencies larger than
l
), differential
mode voltage gain, A
dv
, of
ci
do b1 m1
dv l
di m1 ss
V 0
b m1
l
b s m1 ss
V k g R
A R
V 1 g R 2
R g R
R .
R R 1 g R 2
=
| || |
= =
| |
+
\ . \ .
| || || |
=
| | |
+ +
\ . \ .\ .
(E4-11)
We should be clear about the fact that the proviso, V
ci
= 0, which is appended as a subscript
to this voltage gain expression, is automatically satisfied in the differential mode half circuit
of Figure (6.53a). In particular, Figure (6.53a) applies exclusively to differential mode
excitation, which means that the common mode component, V
ci
, of the applied signal source
is constrained to zero.
(5). Figure (6.53b) is the AC small signal, common mode half circuit schematic for the subject
balanced differential amplifier. In this model, the signal source is the common mode input
voltage, V
ci
. All node voltage and branch currents, inclusive of the output voltage variables,
resultantly assume their respective common mode signal values. No differential mode

- 598 -
voltage or current components prevail in this model because the differential part, V
di
, of the
applied input signal is set to zero. Three topological differences prevail between the common
mode half circuit and its differential mode brethren. First, the node to which resistances R
b
,
1/g
m5
, and 1/g
m6
are incident in Figure (6.52) is not grounded for common mode excitation.
The amplifier at hand operates with common mode signals applied to both input ports. Thus,
the current conducted by the resistance whose conductance sum is (g
m5
+ g
m6
) is necessarily
twice the signal current that flows through either resistance labeled as R
b
. It follows that the
common mode model incorporates a resistance of 2/(g
m5
+ g
m6
) in series with biasing resis-
tance R
b
, as shown in Figure (6.53b). For the second topological difference, the argument
just invoked applies equally well to resistance R
kk
in Figure (6.52), whence we place a resis-
tance of 2R
kk
in series with the source degeneration element, R
ss
. Finally, resistance R/2 no
longer shunts the drain load resistance, R
l
. In Figure (6.52), we witness R as connected be-
tween the two output ports. Since both of these output nodes support the same common
mode signal response, V
co
, no current flows through R, thereby allowing resistance R to be re-
moved from the circuit.
By inspection of the AC common mode half circuit in Figure (6.53b), the indicated common
mode input resistance, R
ci
, is
di
ci b
m5 m6 m5 m6
R 2 2
R R ,
g g 2 g g
= + = +
+ +
(E4-12)
where we have appealed to (E4-5). The effective input resistance, R
in
, can now be deter-
mined through a direct substitution of (E4-12) and (E4-5) into (6-174). This substitution
exercise is a task best left to the reader. But for the generally practical case of a large biasing
resistance, R
b
, which satisfies the inequality,
( )
m5 m6 b
g g R 2 , + >> (E4-13)
it is a straightforward matter to confirm
in b
R R . ~
(E4-14)
This disclosure supports our intuitive view of the input port in the amplifier of Figure (6.52).
In particular, if either transconductance g
m5
and/or transconductance g
m6
is large, which con-
flates with the requirement projected by (E4-13), resistance R
b
approximates a resistive
branch connection from the input port to ground.
An inspection of the output port in Figure (6.53b) reveals a common mode output resistance,
R
co
, of
do
co
m3
R 1
R ,
g 2
= = (E4-15)
where (E4-6) is exploited. Using (6-175), (E4-15) and (E4-6) deliver a net output resistance,
R
out
, of
out co
m3
1
R R .
g
= =
(E4-16)
This result is self-evident in that in Figure (6.52), the M3a gate, which conducts essentially
no signal current, isolates transistor M3a from the rest of the circuit. This isolation leaves
only the resistance, 1/g
m3
, seen looking into the source of M3a as the observable output resis-
tance.
The only major task remaining is the derivation of the common mode gain of the differential
network. In Figure (6.53b), the common mode signal voltage, V
cii
, developed at the gate of
transistor M1 is

- 599 -
b
m5 m6
cii ci b2 ci
b s
m5 m6
2
R
g g
V V k V ,
2
R R
g g
| |
+
|
+
|
= =
|
+ +
|
+
\ .
(E4-17)
where
( )
( )( )
b
m5 m6 b m5 m6
b2
m5 m6 b s
b s
m5 m6
2
R
2 g g R g g
k .
2
2 g g R R
R R
g g
+
+ + +
= =
+ + +
+ +
+
(E4-18)
Noting an effective source degeneration resistance of (R
ss
+ 2R
kk
), the small signal, common
mode signal drain current, I
c1s
, conducted by transistor M1 is
( )
m1
c1s b2 ci
m1 ss kk
g
I k V .
1 g R 2R
(
=
(
+ +
(

(E4-19)
This current flows through common gate transistor M2 and load resistance R
l
so that the com-
mon mode output response, V
co
, is
( )
m1 l
co c1s l b2 ci
m1 ss kk
g R
V I R k V .
1 g R 2R
(
= =
(
+ +
(

(E4-20)
We can now see that the common mode voltage gain, A
cv
, is
( )
( )
( )( ) ( )
di
co b2 m1 l
cv
ci m1 ss kk
V 0
m5 m6 b m1 l
m5 m6 b s m1 ss kk
V k g R
A
V 1 g R 2R
2 g g R g R
.
2 g g R R 1 g R 2R
=
= =
+ +
( + +
=
(
+ + + + +
(

(E4-21)
(6). The low frequency, small signal, single ended voltage gain, A
v
= V
o2s
/V
s
, delivered by the ba-
lanced network in Figure (6.51) can now be determined by plugging (E4-21) and (E4-11) into
(E4-3). The delineation of the resultant exact gain expression is left as an exercise for the
reader. But we can formulate a useful approximate gain relationship by observing that if the
biasing resistance, R
b
, satisfies (E4-13), the divider constant, k
b2
, in (E4-18) closely approx-
imates k
b1
in (E4-8). Additionally, if R
l
is implemented as a resistance that is significantly
smaller than R/2, which is likely owing to circuit biasing requirements, the resultant (approx-
imate) single ended voltage gain, A
dv
, is
( )
( )
o2s b1 m1 l m1 kk
v
s m1 ss m1 ss kk
b m1 l m1 kk
b s m1 ss m1 ss kk
V k g R g R
A
V 1 g R 1 g R 2R
R g R g R
.
R R 1 g R 1 g R 2R
( | |
= ~
( |
+ + +
( \ .
( | || |
=
( | |
+ + + +
( \ .\ .
(E4-22)
We note that because of resistance R
kk
and to the extent that R
l
<< R/2, the approximate sin-
gle ended gain is slightly less than one-half the magnitude of the differential gain of the cir-
cuit.
(7). The design-oriented issues surrounding resistance R
kk
, whose primary purpose in the balanced
pair is to route the source currents of transistors M1 and M1a to ground, deserve further
exploration. We note in (E4-21), for example, that large R
kk
, engenders a small common
mode gain, which we have stipulated as a desirable design target. Recall that a small com-
mon mode gain is tantamount to an appreciable rejection of common mode inputs, which is
especially laudable when such inputs derive from undesirable parasitic signals or other elec-

- 600 -
trical phenomena. We are therefore led to believe that in light of the fact that the differential
mode gain is independent of R
kk
, the common mode rejection ratio is rendered large if R
kk
is
large. We can easily confirm this contention by combining (E4-11) and (E4-21) with (6-157)
to arrive at a common mode rejection ratio, , of
dv b1 m1 kk
cv b2 l m1 ss
A k 2g R R 2
1 ,
A k R R 2 1 g R
| || || |
= = +
| | |
+ +
\ .\ .\ .
(E4-23)
which advances rejection ratio that rises linearly with R
kk
.
Unfortunately, there are practical limits as to how large resistance R
kk
can be in the circuit at
hand. Specifically, a large R
kk
burdens the supply voltage, V
dd
, in that independent of its
resistance value, R
kk
must conduct the sum of currents flowing through transistors M1 and
M1a. For large R
kk
, Georgey O. warns that the resultant potential drop across R
kk
, which must
be supplied by voltage V
dd
, is correspondingly large.

Figure (6.54). Modified version of the balanced differential amplifier in Figure (6.51). In this embodi-
ment, resistance R
kk
in Figure (6.51) is replaced by an active current sink formed by
transistor M9 and its gate source bias voltage, V
bias2
.
We can, however, get our proverbial cake (large R
kk
) and be allowed to eat it too (no exces-
sive burden imposed on V
dd
), by replacing R
kk
with an active current sink, as is suggested in
the modified schematic diagram of Figure (6.54). The active current sink in question is
forged by transistor M9, whose gate-source potential is supplied by a constant, and thus sig-
nal invariant, voltage, V
bias2
. Because the gate-source voltage of transistor M9 is constant, no
g
m
V controlled signal source prevails in the small signal model of M9. Indeed, said model is
comprised solely of a drain-source channel resistance, say r
o9
. This means that in (E4-23),
resistance R
kk
is supplanted by r
o9
, which, depending on the channel length selected for M9,
can be several tens of thousands of ohms. It follows that the common mode rejection ratio, ,
can be made large. Indeed, if we continue our previously established precedent of very large
channel resistances in the modified amplifier of Figure (6.54), tends toward its idealized
value of infinity. Intuitive support for this contention derives from a casual re-inspection of
the common mode half model in Figure (6.53b). If in this structure, resistance R
kk
, which is
presently replaced by r
o9
, tends toward infinity, the source terminal of transistor M1 is left
open circuited, which obviously precludes any signal current flow through M1, M2, and the
M9 V
bias2
+
M2
M7
M2a
M1 M1a
R
l
R
ss
R
b
R
s
R
s
V
s
R
b
R
ss
R
l
M8
C
1
C
1
C
2
M4a
M3a
V
o2
V
bias1
M4
M3
V
o1
M5
M6
+V
dd
R
V
y1
V
y2
R
in
R
out

- 601 -
load termination, R
l
. With zero current conducted by R
l
, the common mode output response,
V
co
, is forced to zero, whence zero common mode gain and correspondingly infinitely large
common mode rejection ratio result.
In the preceding paragraph, we suggest that channel resistance r
o9
can be rendered signifi-
cantly larger than the previously utilized passive resistance, R
kk
. For reasonable drain cur-
rents, a large channel resistance invariably requires a proportionately large channel length,
which automatically flags potential frequency response issues. But the frequency response
capabilities of transistor M9 are almost immaterial since for differential mode, the circuit
node to which the drain of M9 is connected is a virtual ground. And it should be noted from
(6-159) that for the very large common mode rejection ratio bred by the presumably large
channel resistance of M9, differential operation is the only operational mode of consequence.
A final noteworthy point is that unlike the electrical ramifications of a large passive resis-
tance, R
kk
, a large r
o9
does not require a large drain to source voltage on M9. To be sure, we
require M9 to operate in saturation in order to achieve large channel resistance. But satura-
tion requires only that the drain-source voltage of transistor M9, which effectively replaces
the original potential drop across R
kk
, be slightly larger than its drain saturation level. This
saturation voltage is nominally the difference between voltage V
bias2
and the M9 threshold
potential. It can be small, especially if the gate aspect ratio of transistor M9 is chosen large.
While the simplified analytical procedure invoked in this admittedly lengthy discourse may
be distasteful to the analytical purist, it is justifiable from a design-oriented perspective.
Moreover, acceptable or desirable responses deduced from analyses predicated on simplified
approximations can be viewed as a necessary condition that underpins a successful design
initiative. Stated bluntly, a circuit that does not evoke proper I/O functionality under
simplified perhaps almost idealized conditions has little, if any, hope for functionality with
realistic device models and due consideration given to all circuit and system second order
phenomena and energy storage parasitics. To be sure, performance estimates derived under
approximate operating circumstances constitute only design necessity, sans design
sufficiency, which can only be satisfied by definitive manual and computer-based analyses
and possibly, prototype testing.
The input port biasing exploited in the balanced differential pair of Figure (6.51) is a simple
active divider from the power line voltage, V
dd
. As such, appropriate care must be exercised
to ensure that the power line is well regulated and relatively immune to parasitic signal coupl-
ing from proximate sources of electrical noise, radio frequency interference, and other
contamination.
We should note that coupling capacitors are used at both of the input ports. These capacit-
ances establish a low cutoff frequency, which in this case is
l
. If
l
is small (say, at most 2
x tens of KHz), the coupling capacitances are large enough to force their implementation as
off chip circuit elements. If the coupling capacitances provide a low cutoff frequency of
l
,
the signal frequency passband of the amplifier does not extend from zero frequency to the
network 3-dB bandwidth, B. Instead the radial width of this passband is (B
l
). It is gener-
ally desirable to keep this width as small as the frequency spectra of applied signals permit.
The reason for a desirably constrained passband width is that the total integrated output noise
of an amplifier is nominally proportional to passband width. The logic here is that it makes
no sense to endure the large output noise that accompanies a wide passband when the fre-
quency spectrum of the signals identified for processing are confined to a relatively narrow
frequency interval.
As expected, we see in (E4-11) that the source degeneration resistance, R
ss
, reduces the
differential gain sensitivity to transistor transconductance g
m1
. Of course, the prices paid for
this reduced sensitivity is reduced gain, increased static power dissipation, and possibly in-

- 602 -
creased power line voltage.
Finally, we notice that since the divider constant, k
b1
, is obviously less than one, k
b1
contri-
butes to gain magnitude degradation. Such degradation is kept minimal if the biasing resis-
tance, R
b
, in (E4-11) is chosen to be significantly larger than signal source resistance R
s
. This
latter requirement generally poses no engineering dilemma.
6.7.3. DIFFERENTIAL TO SINGLE ENDED CONVERTER
In Section (6.7.1), we pointed out that the differential output response of a balanced
differential amplifier is divorced of a common mode signal component, regardless of the magni-
tude of the common mode rejection ratio of the amplifier and independent of the amplitude of the
common mode input signal. Extracting an amplifier output response in differential form is there-
fore appealing from the standpoint of obliterating the effects of undesirable common mode elec-
trical phenomena that couple to the input ports of a balanced pair. But in communication circuits
and many other applications, the inability of a differential output response to sustain a common
ground between amplifier input and output ports is a quandary. The differential to single ended
converter, or DSEC, which we abstract in Figure (6.55), addresses this issue by converting the
ungrounded differential output signal of a balanced pair to a single ended output signal response.
The ungrounded differential output, A
d
V
di
, of the balanced pair serves as the input to the DSEC.
In addition to a common mode signal component, we have allowed for a single ended, common
mode quiescent voltage, V
Q
, generated by the balanced pair, to serve as biasing for the DSEC.
The DSEC processes its differential signal input, A
d
V
di
, to generate a single ended output re-
sponse, V
ods
. We indicate this output in Figure (6.55) as proportional to V
di
, by a factor of A
ds
A
d
,
thereby implying that A
ds
represents the voltage gain of the DSEC. It is understood that the
magnitude of A
ds
can be one, less than one, or greater than one. In most cases, we opt for a
DSEC gain magnitude that is near one in order to restrain the DSEC from significantly impairing
the 3-dB bandwidth of the balanced differential amplifier. In the subject diagram, voltages V
di
,
V
ci
, and parameters A
d
, A
c
have their usual differential network connotations.

Figure (6.55). System abstraction of the use of a differential to single ended converter (DSEC) in conjunc-
tion with a balanced differential amplifier.
Figure (6.56) complements the system abstraction in Figure (6.55) by offering a rela-
tively simple CMOS realization of a differential to single ended converter. All transistors in the
Balanced
Differential
Amplifier
+
+
R
s
R
s
V
di
V
c
i
V
di
2 2
V +A V +
Q c ci
A V
d di
2
V +A V
Q c ci
A V
d di
V
= A A V
ods
ds d di
2
+
A V
d di

- 603 -
DSEC operate in their saturation domains, M1 and M1a are matched pairs, and M2-M2a are
matched transistors. Although not shown explicitly, the bulk terminals of all NMOS transistors
are returned to signal ground, while the bulk terminals of all PMOS devices are connected di-
rectly to the power line voltage, +V
dd
. The DSEC input signal voltage, (A
c
V
ci
+A
d
V
di
/2), which is
applied to the gate of transistor M1, and (A
c
V
ci
A
d
V
di
/2), which activates the gate terminal of
transistor M1a, are the single ended Thvenin output signal components of the predecessor ba-
lanced amplifier. The source resistances, R
s
, in Figure (6.56), represent the single ended output
port resistances of the differential driver, whose ungrounded differential voltage response is to be
converted to a single ended output response. During this conversion process, it is crucial that
linearity be sustained. The output response is denoted as the voltage, V
ods
, which appears across
load resistance R
l
. Since the load resistance is capacitively coupled to the DSEC output port, no
static voltage is supported across resistance R
l
, whence the output response contains only a signal
component in the steady state. We assume that capacitance C
l
is chosen large enough to enable
its behavior as a short circuit for all signal frequencies of interest. In the subject figure, the out-
put port of the DSEC is taken at the drain of transistor M2a, which mirrors the current that flows
through the diode-connected device, M2. In turn, the M2-M2a mirror is driven by the current
output signals of M1 and M1a.

Figure (6.56). Simplified schematic diagram of a differential to single ended converter rea-
lized in CMOS technology.
Because the load imposed on transistor M1 differs from the load imposed on M1a, the
network in Figure (6.56) is not balanced. However, if we partition the M1-M1a pair from the
load subcircuit comprised of M2, M2a, and the capacitively coupled load resistance, we can
determine the short circuit (Norton) signal currents, say I
n1
and I
n2
, produced by the M1-M1a
pair. We see in Figure (6.57a) that short circuiting the drains of M1 and M1a to ground makes
the differential M1-M1a pair balanced. We have removed quiescent voltage V
Q
from the input
subcircuit associated with the M1-M1a subcircuit because of our present focus on exclusively
small signal current responses. Because the subcircuit at hand is balanced, currents I
n1
and I
n2

are expressible in terms of their stereotypical common mode and differential mode components,
+
+
R
s
R
s
A V
d di
V +A V
Q c ci
2
M1
M3
M2
M1a
M2a
A V
d di
2
R
l
C
l
V
ods
V
bias
+V
dd

- 604 -
I
cn1
and I
dn1
; namely,

Figure (6.57). (a). Circuit used to determine the Norton equivalent output currents of the M1-M1a differen-
tial pair in the differential to single ended converter of Figure (6.56). (b). Differential mode
half AC schematic of the network in (a). (c). Common mode half AC schematic of the net-
work in (a). (d). Differential mode Norton equivalent output port circuit for the balanced cir-
cuit in (a). (e). Common mode Norton equivalent output port circuit for the balanced circuit
in (a).
dn1
n1 cn1
dn1
n2 cn1
I
I I
2
.
I
I I
2
= +
=
(6-176)
+
+
R
s R
s
A V
d di
A V
d di
A V
c ci
2 2
M1
M3
M1a
A V
d di
2
I
n1
I
n2
+
R
s
M1
I /2
dn1
2r
o3
A V
c ci
+
R
s
M1
I
cn1
r
o1
I
dn1
2
r
o1
Drain
Of M1a
I
dn1
2
Drain
Of M1
I
cn1
R
oc
Drain
Of M1
I
cn1
R
oc
Drain
Of M1a
(a).
(c).
(b).
(d).
(e).

- 605 -
In concert with the differential theory propounded earlier, I
cn1
in this expression is understood to
be directly proportional to the common mode input signal, V
ci
, and independent of differential
mode input signal, V
di
. On the other hand, current I
dn1
is independent of V
ci
and directly propor-
tional to the differential mode input signal, V
di
.
Figure (6.57b) is the pertinent differential mode half AC circuit schematic of the topol-
ogy in Figure (6.57a). In arriving at this schematic form, we have exploited (6-176) to express
the short circuit signal drain current in M1 as I
dn1
/2. In this half circuit, the centroidal electrical
node to which the current sink forged by transistor M3 is connected is properly replaced by a vir-
tual ground. Since M1 in this half circuit reduces to a simple common source amplifier that is
operated without source degeneration, we write
dn1 d di
m1
I A V
g .
2 2
| |
=
|
\ .
(6-177)
The associated single ended Thvenin resistance is the channel resistance, r
o1
, of transistor M1
(and M1a). Naturally, g
m1
denotes the forward transconductance of transistor M1 (and M1a).
The resultant differential mode Norton equivalent circuit of the output port for the structure in
Figure (6.57a) appears in Figure (6.52d). We observe the current direction of the signal current
source, I
dn1
/2 in M1a, is source to drain, as opposed to the conventional drain to source polarity.
This change of current direction is necessitated by the fact that for differential mode, the gate-
source signal drive for transistor M1a is V
di
/2 whereas for transistor M1, it is +V
di
/2.
On the other hand, the common mode Norton equivalent circuit of the output port in
Figure (6.57a) is the structure in Figure (6.57e). This model derives from the relevant common
mode half AC schematic diagram offered in Figure (6.57c). The centroidal node to which the
drain of transistor M3 in Figure (6.57a) is incident is no longer the short circuit observed in the
differential mode half circuit. Instead, this node is returned to signal ground through a resistance
of twice the M3 channel resistance, r
o3
. Recall that twice resistance value is germane to this cen-
troid-ground path since both transistors M1 and M1a conduct common mode signal currents, but
only half the M1-M1a subcircuit is drawn in the common mode half circuit. In view of the fact
that transistor M1 in Figure (6.57c) is a simple common source amplifier operated with resistive
source degeneration in the amount of 2r
o3
, we perceive a common mode signal drain current, I
cn1
,
of
m1
cn1 c ci
m1 o3
g
I A V .
1 2g r
| |
=
|
+
\ .
(6-178)
Observe that this common mode signal current is likely to be small, especially if (g
m1
r
o3
) >>
and/or the common mode gain, A
c
, of the balanced pair is small. The Thvenin shunt resistance,
which we represent as R
oc
in Figure (6.57e), derives from (6-21) and (6-22), where in those two
relationships, g
m
is g
m1
, the transconductance of transistor M1, r
o
is r
o1
, the channel resistance of
M1, bulk transconductance parameter
b
is
b1
, and resistance R
ss
is 2r
o3
. Accordingly,
( ) ( )
oc o3 b1 m1 o3 o1 m1 o1 o3
R 2r 1 2 1 g r r 2 1 g r r . = + + + ~ + (

(6-179)
The upshot of these two disclosures is the common mode equivalent circuit constructed in Figure
(6.57e).
The small signal performance characteristics of the DSEC in Figure (6.55) can now be
evaluated with the aid of the foregoing Norton models. For this first order evaluation, we shall
condescend to adopting the simplifying approximations of infinitely large channel resistances in
all transistors and zero bulk transconductances in M1 and M1a. With channel resistances pre-

- 606 -
sumed infinitely large, r
o1
in Figure (6.57d) and R
oc
in Figure (6.57e) are infinity. As a result, the
differential and common mode Norton models coalesce into a simplified single modeling cell
depicted by the small signal representation in Figure (6.58). In this model, the power supply vol-
tage, V
dd
, is set to zero to reflect our focused attention on only small signal circuit characteristics.
Additionally, capacitance C
l
is replaced by a short circuit in that its capacitance value is chosen
to emulate a short circuited branch element for all signal frequencies of interest. By inspection
of the subject model, we see that the current delineated as I
2s
is

Figure (6.58). Approximate signal schematic diagram of the differential to
single ended converter postured in Figure (6.56). The driving
circuit for the converter has been replaced by a Norton equiva-
lent model. The signal schematic diagram exploits the
assumptions of infinitely large channel resistances and zero
bulk transconductances in all transistors.
dn1
2s cn1
I
I I .
2
= + (6-180)
This current flows through the drain of transistor M2. Since transistors M2 and M2a are matched
devices having identical gate aspect ratios and since the source-gate voltages applied to these two
PMOS devices is the same, current I
2as
mirrors current I
2s
; that is,
dn1
2as 2s cn1
I
I I I .
2
= = + (6-181)
Now, current I
ds
is
dn1
ds cn1
I
I I .
2
= (6-182)
It follows that the current, I
os
, conducted by load resistance R
l
is
dn1 dn1
os 2as os cn1 cn1 dn1
I I
I I I I I I ,
2 2
| | | |
= = + =
| |
\ . \ .
(6-183)
which is laudably independent of the common mode current component generated in the drain
circuits of transistor M1 and M1a. Since common mode responses are inherently (at least in the
idealized sense of infinitely large channel resistances) absent in the load resistance, we can dis-
pute the necessity of transistor M3, as opposed to the deployment of a simple resistance con-
nected from the source terminals of M1-M1a and ground. In particular, (6-178) confirms that the
invariably large channel resistance, r
o3
, of transistor M3 substantially attenuates the common
mode current response for a given common mode input voltage signal. But since common mode
currents disappear at the DSEC load, a reasonable resistance supplanting M3 arguably suffices.
I
dn1
2
I
dn1
2
I
cn1
I
cn1
M2 M2a
R
l
V
ods
I
2s
I
ds
I
os
I
2as

- 607 -
Continuing with (6-183), (6-177) allows us to write
os dn1 m1 d di
I I g A V , = = (6-184)
whence an output signal voltage, V
ods
, of
( )
ods os l m1 l d di
V I R g R A V , = = (6-185)
thereby confirming a single ended output voltage response that is proportional to the ungrounded
voltage, A
d
V
di
, developed differentially across the output terminals of the predecessor balanced
differential amplifier. Equation (6-185) suggests that the apparent single ended output to
differential input voltage gain, A
ds
, of the DSEC is
ods
ds m1 l
d di
V
A g R .
A V
= = (6-186)
As we noted earlier, this gain is generally set to near unity in order to minimize the bandwidth
impact of the DSEC on the balanced differential pair.
It is interesting to observe that if we simply extract the single ended responses of the
balanced differential pair, as opposed to running these responses through the considered DSEC,
three engineering costs accrue. First, the quiescent standby voltage, V
Q
, must be neutralized,
likely through deployment of a coupling capacitor similar to that used in Figure (6.56). Second,
the common mode signal, A
c
V
ci
, needs to be mitigated through ensuring a suitably large common
mode rejection ratio in the balanced pair. And finally, we note that the desired differential sig-
nal, unlike the output gleaned as (6-185), is attenuated by a factor of two; that is we lose 6-dB in
overall voltage gain.
The foregoing results are, of course, only approximate in light of the approximations on
which they are predicated. In order to investigate the small signal characteristics of the DSEC
more definitively, we shall need to account for finite, but large, channel resistances and nonzero
bulk transconductances in transistors M1 and M1a. The differences between the Thvenin resis-
tances of the differential mode and common mode Norton equivalent circuits for the M1-M1a
driver encourage us to exploit superposition theory with respect to the differential and common
mode components of the signals applied to input ports of the DSEC.
To the foregoing end, we begin with differential mode considerations by advancing the
small signal model depicted in Figure (6.59a). In this low frequency model, which assumes that
coupling capacitance C
l
functions as a short circuit for the signal frequencies of interest, diode-
connected transistor M2 is simply replaced by its effective terminal resistance. Our earlier work
indicates this resistance as r
o2
/(1+g
m2
r
o2
). Transistor M2a, which is matched to M1, is modeled
in the traditional fashion by a dependent source, g
m2
V, in shunt with channel resistance r
o2
, where
we understand voltage V is the gate-source signal voltage applied to M2a. As it turns out, vol-
tage V is also the signal voltage dropped as indicated across the effective resistance that
represents the small signal terminal properties of diode-connected transistor M2. The signal
drive circuit for the drain terminals of M2 and M2a derives directly from Figure (6.57d). An
inspection of the model in at hand reveals
dn1 o2 o2 d di
o1 m1 o1
m2 o2 m2 o2
I r r A V
V r g r ,
2 1 g r 1 g r 2
( ( | |
= =
( ( |
+ +
( \ .
(6-187)
where we have made use of (6-177). Since resistances R
l
, r
o1
, and r
o2
are all connected in paral-
lel with one another, the output voltage, V
odd
, due exclusively to differential mode excitation of
the DSEC, must satisfy

- 608 -

Figure (6.59). (a). Small signal model of the differential to single ended converter of
Figure (6.56) for differential mode input signal excitation. (b). Small
signal model of the differential to single ended converter for common
mode input signal excitation. The capacitance, C
l
, in Figure (6.56) is
presumed to emulate a short circuit for the signal frequencies of imme-
diate interest.
odd dn1
m2
l o1 o2
V I
g V 0 .
2 R r r
+ = (6-188)
If we substitute (6-187) and (6-177) into this expression, we arrive at
( )
o2 d di
odd m1 l o1 o2 m2 o1
m2 o2
r A V
V g R r r 1 g r .
1 g r 2

(
| |

= +
( ` |
+
( \ .
)
(6-189)
Although this result is algebraically depressing, it is amenable to engineering interpretation, sub-
ject to a few acceptable approximations. First, it is likely that load resistance R
l
is small enough
to satisfy the inequality, R
l
<< (r
o1
||r
o2
). Second, for reasonably large channel resistances,
o2
o1 o1
m2 o2 m2 m2
r 1 1
r r .
1 g r g g
| |
~ ~
|
+
\ .
(6-190)
We can therefore see that the output voltage due solely to differential input signals is given
approximately as
( ) ( )
d di
odd m1 l m1 l d di
A V
V g R 1 1 g R A V .
2
~ + = (6-191)
I
dn1
2
r
o1
M1 Drain
I
dn1
2
r
o1
r
o2
(a).
R
l
V
odd
1+g r
m2 o2
r
o2
g V
m2
+
V
M1a Drain
I
cn1
R
oc
M1 Drain
r
o2
(b).
R
l
V
odc
1+g r
m2 o2
r
o2
g V
m2
+
V
M1a Drain
I
cn1
R
oc

- 609 -
We note that this result mirrors the approximate (predicated on infinitely large channel resis-
tances) output voltage relationship stipulated as (6-185).
The common mode small signal model of the DSEC system is essentially the same as
its differential mode partner, save for the fact that the driver circuit is comprised of the model
shown in Figure (6.57e). An analysis similar to the one just completed gives for the common
mode component, V
odc
, of DSEC output voltage,
( )
m1 l oc o2
o2
odc m2 oc c ci
m1 o3 m2 o2
g R R r
r
V g R 1 A V ,
1 2g r 1 g r
(
(
| |

( =
( ` |
+ +
(
( \ .
)

(6-192)
where resistance R
oc
derives from (6-179). For large channel resistances, and hence, large R
oc
,
l l
odc c ci c ci
o3 m2 oc m2 o3 oc
R R 1
V A V A V .
2r 1 g R 2g r R
| || | | |
~ ~
| | |
+
\ .\ . \ .
(6-193)
This voltage is invariably very small, especially if the preceding stage is characterized by a low
common mode voltage gain, A
c
. The net output response, dominated by the voltage component
precipitated by differential input signals, is
( )
( )
l
ods odd odc m1 l d di c ci
m2 o3 oc
m1 l d di
R
V V V g R A V A V
2g r R
g R A V .
| |
= + =
|
\ .
~
(6-194)
6.8.0. REFERENCES
[1]. R. L. Geiger and E. Snchez-Sinencio, Active Filter Design Using Operational Transconduc-
tance Amplifiers: A Tutorial, IEEE Circuits and Devices Magazine, pp. 20-32, March 1985.
[2]. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
Inc., 1997, chap. 15.
[3]. T. Bakken and J. Choma, Gyrator-Based Synthesis Of Active On Chip Inductances, Journal
of Analog Integrated Circuits And Signal Processing, vol. 34, pp. 171-181, March 2003.
[4]. R. Duncan, K. Martin, and A. Sedra, A 1 GHz Quadrature Sinusoidal Oscillator, Proceedings
of the Custom Integrated Circuits Conference, pp. 91-94, 1995.
[5]. Y. Chang, J. Choma, Jr., and J. Wills, A 900 MHz Active CMOS LNA with Bandpass Filter,
1999 Southwest Symposium On Mixed-Signal Design, Tucson, Arizona, April 11-13, 1999.
[6]. Y. Chang, J. Choma, Jr., and J. Wills, The Design of CMOS GigahertzBand Continuous
Time Active Lowpass Filters with Q-Enhancement, 1999 Great Lakes Symposium on VLSI,
Ann Arbor, Michigan, March 4-6, 1999.
[7]. Y. H. Cho, S. C. Hong and Y. S. Kwon, A Novel Active Inductor and Its Application To
Inductance-Controlled Oscillator, IEEE Transactions on Microwave Theory and Techniques,
vol. 45, pp. 1208-1213, August 1997.
[8]. J. Choma and W-K Chen, Feedback Networks: Theory and Circuit Applications. Singapore:
World Scientific Press, 2007, chaps. 4 and 5.
[9]. L. J. Giacoletto, Differential Amplifiers. New York: Wiley-Interscience, 1970.
[10]. S. A. Witherspoon and J. Choma, Jr., The Analysis of Balanced Linear Differential Circuits,
IEEE Transactions on Education, vol. 38, pp. 40-50, February 1995.


- 610 -
EXERCI SES
PROBLEM #6.1
The constant voltages, V
B1
, V
B2
, and V
dd
, implement biasing in the amplifier of Figure (P6.1) to en-
sure that all transistors operate in saturation. These transistors have negligible CLM and negligible
BITM. While capacitance C
L
is a small energy storage element used to set the 3-dB bandwidth, say
B, of the network, capacitors C
b
and C
c
are large bypass and coupling capacitances, respectively. In
particular, coupling capacitance C
c
is chosen to emulate a short circuit for all signal frequencies
above a radial frequency of
low
. On the other hand, bypass capacitance C
b
behaves as a short cir-
cuit for all frequencies larger than
low
/10. In the course of completing this problem, do not assume
that all transistors have identical forward transconductances. In light of the given approximations,
try to respond to the queries below by exploiting only inspection techniques.

Figure (P6.1)
(a). In terms of signal voltage V
s
and for
low
< < B, what is the signal component, V
is
, of the in-
put port voltage, V
i
?
(b). In terms of signal voltage V
s
and for
low
< < B, what is the signal component, I
d1s
, of the M1
drain current, I
d
?
(c). In terms of signal voltage V
s
and for
low
< < B, what is the signal component, V
rs
, of the vol-
tage, V
r
, developed across resistance R
L
?
(d). In the passband,
low
< < B, give an expression for the small signal voltage gain, A
v
=V
os
/V
s
.
(e). In terms of suitable transistor parameters and for
low
< < B, give expressions for both the in-
put resistance, R
in
, and the output resistance, R
out
.
(f). In terms of suitable transistor parameters and assuming
low
<< B, give an expression for the 3-
dB bandwidth, B, of the amplifier.
(g). What fundamental purpose is served by transistors M4, M5, and M6?
(h). If transistors M4, M5, and M6 are identical and have identical gate aspect ratios, what are the
quiescent values, V
iQ
and V
bQ
, of node voltages V
i
and V
b
, respectively?
(i). Give the design criterion pertinent to selecting capacitance C
c
.
(j). Give the design criterion pertinent to selecting capacitance C
b
.
PROBLEM #6.2
In the amplifier of Figure (P6.2), all transistors are presumed to operate in their saturation regimes.
The bulk terminals of PMOS transistors M2 and M3 are connected to the V
dd
line, while the bulk ter-
minal of NMOS transistor M1 is incident with circuit ground. Observe that the load imposed on the
drain of M1 is the two terminal network comprised of M3 and resistance R. Capacitor C
b
is selected
+
M1
M8
M9 M3 M4
M5
M6
C
c
C
b
R
s
R
L
V
s R
in
R
out
M2
M7
+V
dd
V
B1
V
B2
V
o
C
L
V
i
V
b
V
r
I
d1

- 611 -
to ensure that it approximates a short circuit for all signal frequencies of interest. Do not assume
that the small signal model parameters are respectively identical for each transistor.

Figure (P6.2)
(a). Without ignoring CLM effects in transistor M3, derive an expression for the effective load
resistance, R
leff
, imposed on the drain of transistor M1.
(b). If channel length modulation (CLM) and bulk-induced threshold modulation (BITM) effects
are ignored in all transistors, use inspection techniques to give an approximate expression for
the small signal voltage gain, A
v
= V
os
/V
s
, of the amplifier.
(c). If CLM and BITM effects are ignored in all transistors, produce approximate expressions for
both the input resistance, R
in
, and the output resistance, R
out
.
(d). In order to ensure that transistor M3 operates in saturation at the quiescent operating point of
the circuit, what is the maximum possible value of resistance R? Express this result in terms of
drain current I
d
and PMOS threshold voltage V
hp
.
PROBLEM #6.3
In the amplifier of Figure (P6.3), all transistors operate in their saturation regimes where they have
negligible CLM and negligible BITM.

Figure (P6.3)
(a). Evaluate the small signal voltage gain, A
v
= V
os
/V
s
.
(b). Derive an expression for the output resistance, R
out
. Comment on the low frequency output
+
V
gg

M3
M2
R
R
2
R
1
R
s
M1
C
b
V
s
V
o
+V
dd
R
leff
R
out
R
in
I
d
+
V
gg

R
s
R
V
s
M1
M3
M4
M2
+V
dd
V
o
R
out

- 612 -
resistance for the case in which resistance R is replaced by a capacitance.
(c). Is the amplifier better suited for voltage gain signal processing, transresistance signal
processing, or transconductance signal processing?
PROBLEM #6.4
Figure (P6.4) is the schematic diagram of a CMOS, folded cascode amplifier. In this amplifier, all
transistors operate in their saturation regimes where they have negligible CLM and negligible
BITM. Capacitances C
a
and C
b
are selected to emulate short circuits for all signal frequencies that
are at and above the lowest frequency of interest, which is defined herewith as
low
. Assuming that
all transistor capacitances are inconsequential to the high frequency characteristics of the network,
capacitance C
L
can be used to set the 3-dB bandwidth of the circuit. Transistors M4, M5, and M6 are
identical, inclusive of identical gate aspect ratios. M2 and M3 are identical, but their respective gate
aspect ratios are k-times larger than the gate aspect ratios of M4, M5, and M6.

Figure (P6.4)
(a). For signal frequencies that are significantly higher than
low
, but much smaller than bandwidth
B, determine the small signal voltage gain, A
v
= V
os
/V
s
.
(b). Determine, in terms of V
dd
, the quiescent values of the voltages, V
2
and V
3
, respectively estab-
lished with respect to ground at the gate terminal of transistor M2 and the gate terminal of
transistor M3.
(c). Assuming that capacitance C
b
acts like a short circuit at frequency
low
, what design criterion
must be satisfied by capacitance C
a
? Give the simplest answer possible.
(d). If the quiescent value of the drain current, I
d6
, conducted by transistor M6 is I
dQ
, what is the
value, I
3Q
, of the quiescent drain current, I
d3
, conducted by transistor M3?
(e). What effective resistance, say R
eff
, is forged with respect to ground at the junction of the drain
terminals of transistors M1 and M3 and the source terminal of transistor M2?
PROBLEM #6.5
In the amplifier of Figure (P6.4), resistance R
L
is realized by the active subcircuit depicted in Figure
(P6.5). Transistors M7 and M8 can be presumed to operate in their saturation domains where they
exude negligible BITM. However, CLM in these two transistors must not be ignored.

Figure (P6.5)
+
V
gg

R
L
R
k
C
L
C
a
R
s
V
s
M1 M2
M3
M6
M5
M4
+V
dd
V
o
C
b
V
2
V
3
I
d6
I
d3
R
eff
V
bias7
V
bias8
M7
M8
+V
dd
+V
dd
To Drain Of M2
To Drain Of M2

- 613 -
(a). What effective value, say R
Le
, of load resistance R
L
is realized by the M7-M8 subcircuit?
(b). If resistance R
L
in Figure (P6.4) is supplanted by the M7-M8 subcircuit, is the magnitude of vol-
tage gain likely to be enhanced or reduced?
(c). If resistance R
L
in Figure (P6.4) is supplanted by the M7-M8 subcircuit, is the 3-dB bandwidth
of the amplifier likely to be enhanced or impaired?
PROBLEM #6.6
In the multi-transistor amplifier shown in Figure (P6.6), the bulk terminals of all transistors are pre-
sumed grounded. All transistors boast negligible CLM as well as negligible BITM. Because of
these two approximations, the questions itemized below can likely be answered without exploiting
the analytical crutch of a small signal transistor model. The capacitors, C
1
and C
2
, are chosen large
enough to ensure that each emulates a short circuit for radial signal frequencies above
L
.

Figure (P6.6)
(a). Give expressions for the signal drain currents, I
d1s
and I
d3s
, conducted respectively by transistors
M1 and M3.
(b). What is the Miller multiplier of the gate-drain capacitance of transistor M1? Is this multiplied
gate-drain capacitance likely to degrade significantly the 3-dB bandwidth of the amplifier? Ex-
plain your rationale.
(c). What analytical criterion must capacitance C
1
satisfy if it is indeed to behave as a signal short
circuit at frequency
L
? In deducing this criterion, assume that the time constant associated
with capacitor C
2
is significantly larger than the time constant attributed to capacitance C
1
so
that in effect, C
2
emulates a robust AC short circuit at frequency
L
.
(d). What individual purposes are served by sufficiently large capacitances, C
1
and C
2
? You should
note that different purposes are served by these respective AC-shorted capacitors.
PROBLEM #6.7
In the amplifier studied shown in Figure (P6.6) all transistors appear in an integrated circuit and are
thus nominally identical devices except for possible differences in gate aspect ratios. As in the
preceding problem, continue to ignore the effects of CLM and BITM.
(a). The circuit is biased so that the quiescent value, V
4Q
, of the gate to ground voltage applied to
transistor M4 is V
dd
/4. Moreover, the quiescent value, V
3Q
, of the gate to ground voltage ap-
plied to transistor M3 is V
dd
/2. Determine the required gate aspect ratio,
6
= W
6
/L
6
, in terms of
the gate aspect ratio,
7
= W
7
/L
7
, of M7. Without necessarily solving for the gate aspect ratio of
transistor M5, would you expect this gate aspect ratio to be smaller or larger than
7
? Explain
your conclusion.
+
V
gg
M3
M4
M1
M2 M7
M6
M5 R
L
I
d3
I
d1
I
d4
I
d7
V
o
V
3
V
dd
R
s
V
s
C
2
C
1
V
4
R
out

- 614 -
(b). If the gate aspect ratio of transistor M4 is 4-times that of transistor M7, what relationship pre-
vails between the quiescent drain currents, I
d4Q
and I
d7Q
?
(c). The biasing voltage, V
gg
, is adjusted so that the Q-point gate-source voltages of transistors M2
and M7 are identical. Transistor M2 has a gate aspect ratio that is one-half as large as the gate
aspect ratio of transistor M4. Recalling that the gate aspect ratio of transistor M4 is 4-times that
of M7, determine the quiescent value, V
oQ
, of the output voltage, V
o
, in terms of V
dd
, R
L
, and
I
d7Q
.
(d). Suppose that channel length modulation (CLM) cannot be ignored in transistors M1, M2, and
M3, but it can be ignored, presumably because of long channel length, in transistor M4. Is the
out
, large or small?
(e). What impact does transistor M4 exert on R
out
? Explain your rationale.
PROBLEM #6.8
In the two stage feedback amplifier shown in Figure (P6.8), both transistors are identical, save for
possibly different gate aspect ratios; both project negligible CLM and negligible BITM. Note that
the circuit utilizes two biasing sources (+V
dd
and V
ss
), both of which can be taken as ideal, constant
voltage sources.

Figure (P6.8)
(a). Since this amplifier is a new topology that you have not yet encountered, it is necessary to ex-
ecute a circuit analysis on the small signal model of the network. To this end, draw the small
signal model, making use of the approximations regarding channel length modulation (CLM)
and bulk-induced threshold voltage modulation (BITM).
(b). Use the model deduced in Part (a) to derive an expression for the indicated input resistance, R
in
,
seen by the signal source, which is modeled herewith as a Norton topology comprised of the
shunt interconnection of signal current I
s
and resistance R
s
.
(c). Assuming an infinitely large source resistance (R
s
= ), use the model of Part (a) to establish
an expression for the small signal current gain, A
i
= I
os
/I
s
. You will find it algebraically conve-
nient to express this gain result in terms of the input resistance found in the preceding part of
this problem.
PROBLEM #6.9
In the amplifier whose schematic diagram appears in Figure (P6.9), the input is a voltage
signal, as shown. The signal component of the net output voltage, V
o
, is the small signal
voltage response, V
os
, to this input. The coupling capacitor, C, is selected large enough so
that it emulates a short circuit for all signal frequencies of interest. The constant battery
voltages, V
dd
and V
B
, are chosen to ensure that both the NMOS transistor and the PMOS de-
vice operate in their saturation domains. Assume that the channel resistances of both
transistors are infinitely large, and that the signal frequencies are such that all transistor
R
1
R
2
R
A
R
B
M1 M2
+V
dd
V
ss
I
o
R
s
I
s
R
in

- 615 -
capacitances can be neglected. Note, however that since one of the transistors in the circuit
is NMOS and the other is PMOS, their corresponding small signal parameters are not likely
to be numerically the same.

Figure (E1)
(a). Is the network at hand a common source, a common drain, or a common gate amplifier?
(b). Derive or give an expression for the indicated small signal input resistance, R
in
.
(c). Let the two transistors be biased in such a way as to achieve an input port resistance match; that
is, R
s
= R
in
. Under this condition and assuming the capacitor behaves as a signal short circuit,
derive an expression for the small signal voltage gain, A
v
= V
os
/V
s
.
(d). What circuit voltage must be adjusted to obtain an input port resistance match? What device
characteristics or properties are being exploited to achieve this input port resistance match
merely by changing the appropriate circuit voltage?
(e). What is the small signal output resistance, R
out
?
(f). For the input port resistance match addressed in parts (b) and (c), give the criterion by which
capacitance C can be selected to ensure it emulates a short circuit for all radial signal frequen-
cies above
L
.
PROBLEM #6.10
In the amplifier of Figure (P6.10), V
s
is the applied input signal, while V
o
is the resultant voltage re-
sponse. All transistors operate in their saturation regimes, have infinitely large channel resistances
and negligible BITM, or body effect. While all PMOS devices are similar as are all NMOS devices,
differing gate aspect ratios incur potentially different forward transconductances in all eleven
transistors. To this end, denote the forward transconductance of the j
th
transistor by g
mj
. Capacitors
C
1
and C
2
are chosen big enough so that they each behave as electrical short circuits for signal
frequencies above a given lowest frequency of interest, say
L
. On the other hand, C
L
is a relatively
small load capacitance that is employed to set the upper 3-dB frequency, which is essentially the
bandwidth, B, of the network if frequency
L
is indeed small. Finally, the indicated biasing sup-
plies, V
dd
, V
gg
, and V
B
, can be presumed to be ideal, constant voltage sources.
(a). A sufficiently large value of capacitance C
1
forces transistor M3 to operate as what kind of
branch element in this network?
(b). A sufficiently large value of capacitance C
2
forces transistor M6 to operate as what kind of am-
plifier in this network?
(c). In terms of signal voltage V
s
and relevant transistor parameters, what is the signal value, I
1s
, of
the current, I
1
, conducted by the drain of transistor M1? Reduce this answer for the case in
which the gate aspect ratio of transistor M1 is 9-times larger than the gate aspect ratio of
transistor M2.
(d). If the gate aspect ratio of transistor M1 is 9-times larger than the gate aspect ratio of transistor
M2, what is the signal value, I
7s
, of the current, I
7
, conducted by the source of transistor M7?
Express results in terms of signal voltage V
s
and relevant transistor parameters.
+
V
s
R
s C
V
B
+V
dd
R
L
V
o
R
in
R
out
M1
M2

- 616 -

Figure (P6.10)
(e). In terms of signal voltage V
s
and relevant transistor parameters, what is the signal value, V
8s
, of
the voltage, V
8
, established at the gate of transistor M8? Reduce this answer for the case in
which the gate aspect ratio of transistor M1 is 9-times larger than the gate aspect ratio of
transistor M2.
(f). Give an expression for the small signal voltage gain, A
v
= V
os
/V
s
, for signal frequencies above
L
but still significantly smaller than the 3-dB bandwidth of the network. Continue to enforce
the constraint that the gate aspect ratio of transistor M1 is 9-times larger than the gate aspect ra-
tio of transistor M2.
(g). If the load capacitance, C
L
, is the only capacitance that determines the 3-dB bandwidth, B, of
the amplifier, give an analytical expression for B.
PROBLEM #6.11
The following queries pertain to the amplifier depicted in Figure (P6.10).
(a). What purposes are served by the transistor pairs, M4-M5 and M10-M11?
(b). If transistors M4 and M5 are identical, inclusive of gate aspect ratios, what is the static voltage
to which capacitor C
1
charges in the steady state?
(c). Can the static voltage to which capacitance C
2
charges in the steady state be the same as the
steady state voltage developed across capacitance C
1
? If not, must the voltage to which C
2

charges be smaller or larger than the voltage to which C
1
charges. Explain your rationale.
(d). Assume that the gate aspect ratio of transistor M1 is 9-times larger than that of transistor M2
and that each device has a threshold voltage of 500 mV. Let the desired quiescent drain current
be conducted by M1 when its quiescent gate-source voltage is 750 mV. What is the required
value of the battery voltage, V
gg
?
PROBLEM #6.12
In the circuit of Figure (P6.12), the PMOS and NMOS transistors have negligible CLM and BITM.
Because of the PMOS and NMOS nature of the active devices, the transistors cannot be expected to
have identical small signal parameters.
(a). In terms of appropriate transistor parameters, give an expression for the small signal voltage
gain, A
v1
= V
o1s
/V
s
.
(b). In terms of appropriate transistor parameters, give an expression for the small signal voltage
gain, A
v2
= V
o2s
/V
s
.
(c). In terms of appropriate transistor parameters, give an expression for the indicated small signal
output resistance, R
out1
.
+
V
gg

M4 M10
M6
M7
M3
M5 M11 C
1
C
2
C
L
R
s
M1
M8
M9 M2 V
B
V
o
+V
dd
V
s
I
1
I
7
V
8

- 617 -

Figure (P6.12)
(d). In terms of appropriate transistor parameters, give an expression for the indicated small signal
output resistance, R
out2
.
(e). In terms of the battery voltages, V
dd
and V
gg
, and relevant transistor and circuit parameters,
determine the maximum quiescent current, I
Q
, allowable to ensure the quiescent saturation do-
main operation of the n-channel transistor, M1.
PROBLEM #6.13
In the amplifier of Figure (P6.13), all transistors operate in saturation. They are all presumed to
have infinitely large drain-source channel resistances and zero bulk transconductance factors. All
capacitors utilized in the circuit are chosen to emulate short circuits over the signal frequency range
of interest.

Figure (P6.13)
(a). If g
m1
= g
m9
= g
m10
= g
m11
= g
m12
, give an expression for the indicated input resistance, R
in
.
(b). The circuit is designed to deliver R
in
= R
s
. What static voltage might be carefully adjusted to
fine-tune this matching resistance requirement?
(c). What fundamental purpose is served by realizing R
in
= R
s
?
(d). With R
s
= R
in
, g
m3
= g
m8
, and assuming g
m1
g
m2
, give an expression for the small signal vol-
tage gain, A
vl
= V
ls
/V
s
, where V
ls
is the signal component of the voltage, V
l
, established across
+
R
+V
dd
V
o1
V
o2
R
s
V
s
R
out1
R
out2
M1
M2
I
Q

V
gg

+
M1 M4
M12 M2 M5
M11
M6
M10
M7
M9
M8
M3
V
bias
R
l
R
s
V
s
V
o
R
out
R
in
V
l
C
1
C
2
C
3

- 618 -
resistance R
l
.
(e). Assuming g
m4
= g
m6
g
m1
, find the relationship between the transconductance, g
m7
, of transis-
tor M7 and the transconductance, g
m5
, of M5 so that the overall voltage gain, A
v
= V
os
/V
s
, is the
negative of A
vl
; that is, A
v
= A
vl
.
(f). How must the gate aspect ratio of M5 relate to that of M7 if the constraint determined in Part
(e) is to be satisfied?
(g). Give an expression for the indicated output resistance, R
out
.
(h). What individual purposes are served by capacitances C
1
, C
2
, and C
3
?
PROBLEM #6.14
In the amplifier of Figure (P6.14), all transistors have negligible CLM and negligible BITM. The
two voltages, V
B1
and V
B2
, are constant voltages applied to the indicated gate terminals to ensure that
all transistors operate in their saturation regimes. The coupling capacitor, C, is chosen large enough
so that for all frequencies above the lowest expected signal frequency, say
L
, it emulates a short
circuit. In the course of addressing this problem, you may find it useful to exploit the effective
transconductance, g
me
, expression,
m
me
m ss
g
g .
1 g R +

Figure (P6.14)
(a). Derive an expression for the small signal voltage gain, A
v
= V
os
/V
s
.
(b). Derive a relationship for the input resistance, R
in
, seen by the signal source.
(c). Give the mathematical criterion for selecting the value of the coupling capacitance, C.
(d). When driven by a 50 ohm signal source, the amplifier is designed to deliver a voltage gain of
4.5 volts/volt. If the input resistance is matched to the signal source resistance, what is the
requisite value of the feedback resistance, R
f
?
PROBLEM #6.15
All NMOS transistors and all PMOS transistors in the amplifier of Figure (P6.15) are identical, save
possibly for differing gate aspect ratios, which manifest potentially different forward transconduc-
tances. All transistors have negligible CLM and negligible BITM. The three voltages, V
B1
, V
B2
, and
V
gg
, are constant voltages applied to the indicated gate terminals to ensure that all transistors operate
in their saturation regimes. The answers to Parts (a) through (d) should be expressed in terms of the
signal source voltage, V
s
. The capacitance, C, is very small and therefore influences the
performance of the amplifier at only high signal frequencies.
(a). What low frequency, small signal current, I
d1s
, flows as indicated into the drain of transistor
M1?
(b). What low frequency, small signal voltage, V
ss
, is developed across resistance R
ss
?
+
M1
M3
M2
R
f
V
B1
V
B2
C
R
s
R
ss
V
s
+V
dd
V
o
R
in

- 619 -

Figure (P6.15)
(c). What low frequency, small signal current, I
d5s
, flows as indicated out of the drain of M5?
(d). What low frequency, small signal voltage, V
ls
L
?
(e). What is the low frequency, small signal voltage gain, A
v
= V
os
/V
s
?
(f). Give an expression for the indicated output resistance, R
out
.
PROBLEM #6.16
In the three-transistor feedback amplifier given in Figure (P6.16), signal is applied as an ideal cur-
rent source, I
s
, to produce the signal voltage response, V
os
, as a component of the net output voltage,
V
o
. All three NMOS transistors are identical, save for the fact that their respective gate aspect ratios
(W/L) are likely not the same. The channel resistances, r
o
, of all transistors can be taken as infinitely
large, all bulk-induced transconductance phenomena can be tacitly ignored, and all capacitances
intrinsic to the transistors can be presumed to be inconsequentially small. The constant voltage, V
Q
,
applied to the gate of transistor M3 establishes a quiescent current, I
Q
, which biases this device in its
saturation regime.

Figure (P6.16)
(a). What circuit connection makes it obvious that transistor M2 operates in saturation?
(b). Explain why saturation region operation of transistor M1 is guaranteed.
(c). Draw the small signal equivalent circuit of the entire amplifier. In the process of forging this
diagram, replace appropriate transistors by their effective small signal resistances.
+
M1
M2
M5
M3
M4
M6
M7
V
B1
V
B2
R
s
R
ss
R
L
V
s
+V
dd
V
o
R
out

V
gg

I
d1s
I
d5s

V

+
ls
C

V

+
ss

V
Q

M1
M2
M3
V
o
I
s
R
in
R
+V
dd
I
Q

- 620 -
(d). Use the small signal model of (c) to deduce an expression for the forward transresistance, R
m
=
V
os
/I
s
.
(e). Use the small signal model of (c) to deduce an expression for the driving point input resistance,
R
in
.
PROBLEM #6.17
In the scary circuit of Figure (P6.17), all NMOS transistors are identical, save for possibly different
gate aspect ratios. In particular, the gate aspect ratio of transistor M3 is k-times larger than that of
transistor M2. Recall that when two transistors support identical gate-source voltages, the transistor
whose gate aspect ratio is k-times larger than that of the other device conducts k-times the signal and
bias currents conducted by the smaller unit. The gate aspect ratio of the PMOS unit, whose bulk ter-
minal is connected to the positive voltage, +V
dd
, is not necessarily equal to the gate aspect ratio of
any of the NMOS transistors. All NMOS devices have their bulk terminals incident with circuit
ground, all transistors are biased in saturation, all transistors have infinitely large drain-source chan-
nel resistances, and all transistors have negligible bulk transconductances; that is, all devices boast
b
= 0. In response to an input signal that is represented as an ideal voltage source, V
s
, a signal
component, V
os
, to the net output voltage, V
o
, is established. The coupling capacitance, C
s
, is se-
lected large enough to enable its approximation as a signal short circuit over all frequencies of
immediate interest. For these signal frequencies, however, all transistor capacitances can be tacitly
ignored. The answers to all of the following queries can be formulated largely by inspection, with-
out explicit need of drawing equivalent circuits for individual transistors.

Figure (P6.17)
(a). In terms of signal voltage V
s
and pertinent transistor parameters, what is the small signal cur-
rent, say I
d1
, flowing into the drain of transistor M1?
(b). In terms of signal voltage V
s
and pertinent transistor parameters, what is the small signal cur-
rent, say I
d2
, flowing into the drain of transistor M2?
(c). Exploit preceding results to determine the small signal current, say I
d4
, flowing into the drain
terminal of transistor M4.
(d). What resultant small signal voltage, say V
6
, is established with respect to ground at the gate ter-
minal of transistor M6?
(e). What is the voltage gain, V
os
/V
s
, of the amplifier?
PROBLEM #6.18
Reconsider the amplifier in Problem #6.17. As noted earlier, all NMOS devices are identical, save
possibly for differing gate aspect ratios. Assume that the gate aspect ratio of transistor M9 is 4-times
larger than the gate aspect ratio of transistor M8. And also as in Problem #6.17, all device drain-
source channel resistances can be presumed infinitely large, and all bulk-induced transconductances
can be taken to be zero. Implied by this presumption is the fact that the threshold potentials, V
h
, of
transistors M8 and M9 are the same.
(a). Derive an expression for the bias voltage, say V
G
, developed at the gate of transistor M1.
+
M1
M8
M9
M2
M3
M7
M4
M5
M6
+V
dd
V
gg

V
o
C
s
V
s

- 621 -
(b). What relationship must be satisfied by the capacitance, C
s
, if the amplifier voltage gain deduced
in the preceding problem is to be sustained for signal frequencies larger than
L
?
(c). Assume a small, perhaps parasitic, capacitance, C
o
, appears between the source terminal of
transistor M6 and circuit ground. What is the 3-dB bandwidth, say B (in radians -per- second),
established by this capacitance? Assume that B is significantly larger than
L
.
PROBLEM #6.19
At the quiescent operating point established in the circuit of Figure (P6.19), the small signal forward
transconductance of transistor M1 is g
m1
, while the small signal forward transconductance of M2 is
g
m2
. Both transistors are biased in saturation and can be presumed to have infinitely large channel
resistances. Over the signal frequency range of interest, all capacitances intrinsic to the two transis-
tors can be ignored, leaving capacitance C as the only dominant energy storage element in the am-
plifier. The current source of value I
bias
, is applied for biasing purposes, while I
s
is an input signal
current.

Figure (P6.19)
(a). What are the Q-point and small signal values, say I
LQ
and I
Ls
, respectively, of the indicated load
current, I
L
?
(b). Derive an expression for the frequency, say
c
, of the pole established by capacitance C.
(c). Why might a large pole frequency,
c
, be desirable? To achieve large
c
, would you recom-
mend that transistor M2 have a large or a small gate aspect ratio?
PROBLEM #6.20
In the current amplifier of Figure (P6.20), the input signal is the signal component, I
s
, of the net in-
put current, I
Q
+ I
s
, while the output response to the signal input is taken as the signal component,
I
Ls
, of the indicated net current, I
LQ
+ I
Ls
. Of course, I
LQ
and I
Q
are quiescent biasing currents.
Transistors M1 and M2 are identical, save for the fact that the gate aspect ratio of transistor M1 is k-
times smaller than the gate aspect ratios of transistors M2 and M3. All transistors are biased in
saturation, have infinitely large channel resistances, negligible carrier mobility degradation and
negligibly small bulk-induced threshold modulation. In a word, the transistors are presumed to ab-
ide by the simple, square law, Schichman-Hodges model.
(a). Under quiescent operating conditions, express in terms of the aspect ratio parameter, k, the
relationship among the device transconductances, g
m1
, g
m2
, and g
m3
.
(b). Draw the low frequency, small signal equivalent circuit of the network. Make use of the fact
that transistor M2 is configured as a diode-connected device.
(c). Derive an expression for the small signal, low frequency input resistance, R
in
. Express your re-
sult in terms of appropriate circuit parameters and device transconductances.
(d). Derive an expression for the low frequency, small signal current gain, A
i
= I
Ls
/I
s
. Simplify
your result for the case of very large R and express the result in terms of parameter k.
I
s
I
bias
R
M1
M2
V
dd
I
L
R
l
V
ss
C

- 622 -

Figure (P6.20)
(e). Derive an expression for the 3-dB bandwidth, B, of this current gain. Assume that all capacit-
ances implicit to the three transistors are negligibly small.
(f). If the resistances, R and R
L
, satisfy the constraint, R > kR
L
, briefly discuss any problems
encountered with respect to assuring the saturation domain operation of transistor M3.
PROBLEM #6.21
The CMOS amplifier studied in Example #6.1 is modified by adding source degeneration to both
transistors, as shown in Figure (P6.21). In the following queries, ignore BITM. Avoid extensive
analyses by exploiting the fruits of the common source amplifier analyses documented in Section
(6.3.0) and then simply modifying the results proclaimed in Example #6.1.

Figure (P6.21)
(a). Provide an expression for the small signal voltage gain, A
v
= V
os
/V
s
, where V
os
is understood to
represent the small signal component of the indicated output voltage, V
o
.
(b). Provide an expression for the indicated output resistance, R
out
.
(c). Give two disadvantages of the circuit from a biasing perspective.
(d). Give at least one advantage of the circuit from the perspective of utilizing the network as a
transconductor.
PROBLEM #6.22
Repeat Problem #6.21 for the degenerated CMOS unit in Figure (P6.22).
M3
M1 M2
R R
L
C
+V
dd
I + I
LQ Ls
I + I
Q s
R
in
+
V
gg

R
is
R
os
R
s
R
sn
R
sp
V
s
+V
dd
V
o
I
d
V
i
R
l
Mn
Mp
R
out

- 623 -

Figure (P6.22)
PROBLEM #6.23
In the NMOS source follower of Fig. (P6.23), the transistor has a gate aspect ratio, W/L, of 10, a
threshold voltage, V
hn
, of 700 mV, and a channel length modulation voltage, V
, of 20 V. Assume
that the bulk-induced threshold modulation voltage, V
is 0 volts. Also, measurements taken in the

laboratory confirm that K
n
=
n
C
ox
= 50 A/V
2
. The indicated load resistance, R
l
, is 100 , while the
source resistance, R
s
, is 300 . The current sink, I
ss
, is a source of constant current.

Figure (P6.23)
(a). Compute the value of the bias voltage V
bias
so that the indicated output voltage, V
o
, is 0 V when
I
ss
= 100 A.
[Assume that the operating point corresponding to the computed input bias voltage pre-
vails for the following three parts of this question.]
(b). Give a general expression for, and compute the value of, the small signal Thvenin output port
resistance, R
out
.
(c). Give a general expression for, and compute the value of, the small signal low frequency
Thvenin voltage gain, A
th
; that is, the voltage gain of the circuit with the load resistance, R
l
,
open circuited.
(d). Give a general expression for, and compute the value of, the small signal, low frequency vol-
tage gain, A
v
= V
o
/V
s
.
PROBLEM #6.24
The amplifier in Figure (P6.24) consists of a common source-common gate cascode that is coupled
+
V
gg

R
is
R
os
R
s
V
s
+V
dd
V
o
I
d
V
i
R
l
Mn
Mns
Mp
Mps
R
out
+
V
bias

R
l
R
s
2.5 V
2.5 V
V
o
V
s
R
out
I
ss

- 624 -
to an RC load termination through a source follower. All transistors have negligible CLM and
negligible BITM, which coalesce to facilitate an analysis by inspection.

Figure (P6.24)
(a). Give an expression for the low frequency, small signal voltage gain, V
os
/V
s
, of the amplifier.
(b). Give an expression for the indicated output resistance, R
out
, of the amplifier.
(c). What is the radial 3-dB bandwidth, B, of the network?
PROBLEM #6.25
All NMOS transistors and all PMOS transistors in the amplifier of Figure (P6.25) are identical, save
possibly for differing gate aspect ratios, which manifests potentially different forward transconduc-
tances. All transistors have negligible CLM and negligible BITM. The three voltages, V
B1
, V
B2
, and
V
gg
, are ideal constant voltage sources applied to the indicated gate terminals to ensure that all
transistors operate in their saturation regimes. The answers to Parts (a) through (d) should be ex-
pressed in terms of the signal source voltage, V
s
. The capacitance, C, is very small and therefore
influences the performance of the amplifier at only high signal frequencies. Use inspection
techniques to the extent possible to respond to the following queries.

Figure (P6.25)
+
V
gg

M1
M3
M2 V
bias
R
s
R
l
R
V
s
C
+V
dd
V
o
R
out
+
M1
M2
M5
M3
M4
M6
M7
V
B1
V
B2
R
s
R
ss
R
L
V
s
+V
dd
V
o
R
out

V
gg

I
d1s
I
d5s

V

+
ls
C

V

+
ss

- 625 -
(a). What low frequency, small signal current, I
d1s
, flows as indicated into the drain of transistor
M1?
(b). What low frequency, small signal voltage, V
ss
ss
?
(c). What low frequency, small signal current, I
d5s
, flows as indicated out of the drain of M5?
(d). What low frequency, small signal voltage, V
ls
L
?
(e). What is the low frequency, small signal voltage gain, A
v
= V
os
/V
s
?
(f). Give an expression for the indicated output resistance, R
out
.
(g). If capacitance C is the only dominant energy storage element at high signal frequencies, what is
the 3-dB bandwidth of the amplifier?
PROBLEM #6.26
In the amplifier depicted in Figure (P6.26) consists all transistors have negligible CLM and negligi-
ble BITM, which coalesce to facilitate an analysis by inspection.

Figure (P6.26)
(a). Give an expression for the low frequency, small signal voltage gain, V
os
/V
s
, of the amplifier.
(b). Give an expression for the indicated output resistance, R
out
, of the amplifier.
(c). What is the radial 3-dB bandwidth, B, of the network?
PROBLEM #6.27
In the amplifier of Figure (P6.27), all transistors operate in their saturation regimes where they boast
negligible CLM and negligible BITM. The coupling capacitor, C
c
, is chosen to emulate a short cir-
cuit for radial signal frequencies that are larger than a given low frequency,
L
. On the other hand,
capacitor C
L
dominates over all other circuit and device capacitances at high signal frequencies.
(a). At frequencies above
L
but well below the 3-dB bandwidth of the circuit, what is the approx-
imate voltage gain, A
v
= V
os
/V
s
, where V
os
is the signal component of voltage V
o
.
(b). Give an approximate value for the 3-dB bandwidth, B, of the network.
(c). What approximate bandwidth results if transistors M4 and M5 are removed from the amplifier
and capacitance C
L
is connected between ground and the drain node of M2? The output voltage
remains the voltage developed across capacitance C
L
.
(d). What design condition must be satisfied by the coupling capacitance, C
c
?
(e). Assuming that capacitance C
c
emulates a signal short circuit, what is the approximate voltage
gain, A
v1
= V
o1s
/V
is
, where V
o1s
represents the signal component of voltage V
o1
, and V
is
is the
signal component of the indicated gate voltage, V
i
, of transistor M1. If transistor M2 is sized to
deliver g
m2
> g
m1
is the Miller multiplication of gate-drain capacitance in transistor M1 likely to
be significant?
(f). If a large capacitance that behaves as a signal short circuit is connected from the gate of transis-
tor M2 to ground, does the magnitude of the gain determined in Part (e) increase or decrease?
Briefly explain your rationale.
+
V
gg

M1
M2
M3
M4
R
s
V
s
V
bias
R
l
R C
V
o
R
out
+V
dd

- 626 -

Figure (P6.27)
PROBLEM #6.28
Figure (P6.28) is the schematic diagram of a buffered, balanced differential, folded cascode am-
plifier. All transistors operate in saturation where they have negligible CLM and negligible BITM.
Voltages V
dd
, V
ss
, V
bb1
, V
bb2
, and V
bb3
are constant biasing voltages. In general, transistor Mi is
matched (inclusive of gate aspect ratio) to transistor Mia. In the analyses requested below, designate
the transconductance of i
th
transistor Mi or Mia as g
mi
. Minimal mathematical analyses are required
to respond efficiently to the following queries.

Figure (P6.28)
(a). Using a differential mode half circuit model, determine the differential voltage gain, A
d
.
(b). Using a differential mode half circuit model, determine the differential output resistance, R
do
.
(c). Determine the common mode voltage gain, A
c
.
(d). What is the common mode output resistance, R
co
?
(e). Give an expression for the single-ended voltage gain, A
v
= V
o2s
/V
s
, where V
o2s
is the signal
+
M1 M5
M4
M2
M3
R
ss
R
L
R R
1
R
2
C
c
C
L
V
bias
V
o
V
o1
+V
dd
R
s
V
s
V
i
+
M1
M7
M
2
M6 M6a
M5 M5a
M4 M4a
M1a
R
ss
R
ss
V
bb1
V
bb2
R
s
R
s
V
s M
3
V
bb3
M
3
a
V
ss
+V
dd
M7a
V
o2
R
out
V
o1

- 627 -
component of voltage V
o2
.
(f). Give an expression for the single-ended output resistance, R
out
.
(g). If the balanced source followers comprised of transistors M6 and M6a are to prove effective
buffers, give an opinion on whether the gate aspect ratios of transistors M7 and M7a should be
relatively large for a fixed bias voltage, V
bb1
.
(h). What purpose is served by transistors M4 and M4a, particularly at high frequencies?
PROBLEM #6.29
Except for possible differences in gate aspect ratios, all transistors in the two-stage differential am-
plifier of Figure (P6.29) are identical. Transistors M1, M2, M3, and M4 are identically matched to
one another, the same is true for transistors M6, M7, M14, and M15, transistors M8 and M9 are
identically matched to one another, as are M12 and M13, and finally, M5 and M11 are identical de-
vices. All transistors are biased in saturation, they have infinitely large channel resistances, and they
boast negligible BITM. The capacitance, C, is sufficiently large to enable it to function as a short
circuit for the signal frequencies of interest.

Figure (P6.29)
(a). Respond to the following queries as briefly and as clearly as you can.
(a1). Under small signal operating conditions, what fundamental purpose is served by the cur-
rent sink formed of transistor M5 and its associated biasing?
(a2). Note that the second differential stage comprised of transistors M3 and M4 does not use
active current sinking at the source terminal interconnection of these devices. Why might
active current sinking here be construed as superfluous?
(a3). What purpose is served by the indicated interconnection of transistors M8 and M9?
(a4). What purpose is served by capacitance C?
(a5). Is the circuit a balanced architecture? If it is not balanced, what would need to be changed
architecturally if balance is to be restored?
(b). What is the output resistance, R
out
?
(c). Recall that transistors M8 and M9 are identical, inclusive of gate aspect ratios. If transistors M6
and M7 are biased so that their respective source to drain quiescent voltages are one PMOS
threshold voltage above their source-drain saturation voltages, what quiescent voltage is estab-
+
R
s
R
s
R
ss
R
ss
V
s
M1 M3
M10
M11
M12
M13
M6 M7
M9
M8
M5
M2
R
1
R
2
M4
V
ss
V
o
R
out
C
M
1
4
M15
+V
dd

- 628 -
lished with respect to ground at the drains of transistors M1 and M2?
PROBLEM #6.30
In the amplifier of Figure (P6.30), all transistors operate in their saturation regimes where they have
negligible BITM and negligible CLM. All transistors are fabricated on the same chip. The NMOS
transistors are physically identical, save for the prospects of having different gate aspect ratios. The
only network capacitance of immediate importance is the indicated load capacitance, C.

Figure (P6.30)
(a). Evaluate the small signal voltage gain, A
v
(s) = V
os
/V
s
. You can assuredly conduct this evalua-
tion largely by inspection, with but minimal and trivial algebraic gymnastics. However, do not
ignore the output port capacitance, C.
(b). Determine the voltage gain, A
v
(0), at very low signal frequencies and the 3-dB bandwidth, B, of
the amplifier. You should be able to determine these performance metrics directly from the
transfer function determined in (a).
(c). Determine the output resistance, R
out
. You should not need to exploit classic mathematical
ohmmeter methods here; instead, study the answers to the preceding part of this problem.
(d). Comment as to the reproducibility of, and ability to predict accurately, the low frequency vol-
tage gain of the network.
(e). If the amplifier before us is to serve as a good quality voltage amplifier, should transistor M4 be
set up for relatively low or relatively high quiescent drain current?
PROBLEM #6.31
In the balanced differential amplifier shown in Figure (P6.31), all transistors operate in saturation,
have negligible CLM, and offer negligible BITM. In general, matching can be assumed for only the
transistor pairs, Mi and Mia. It is important to note that the current, I
bias
, is a constant that contains
no signal component.
(a). Determine the small signal voltage gain, A
v1
= V
o1s
/V
s
. Note that this computation requires that
you determine the differential and common mode gains of the differential pair comprised of
M1M1a, M2M2a, M3M3a, and M4M4a.
(b). Derive an expression for the indicated Thvenin resistance, R
th
, seen looking into the port at
which voltage V
o1
is established. Note that this computation requires that you determine the
differential and common mode output resistances of the differential pair comprised of
M1M1a, M2M2a, M3M3a, and M4M4a.
(c). Determine the single-ended, small signal voltage gain, A
v
= V
os
/V
s
.
(d). What is the indicated output resistance, R
out
.
(e). Since transistors M3 and M3a operate as common gate cascodes, it is traditional to ensure that
M1
M2
M3
M4
R
s
+
V
gg

V
s
V
bias
V
o
C
+V
dd
R
out

- 629 -
their gates are grounded for signal conditions. This tradition is best implemented by appending
a sufficiently large capacitance, say C, from the gate of M3/M3a to ground. But in the present
case, this action is detrimental to the small signal performance of at least the first stage
differential amplifier. Explain (clearly, but briefly) why C hurts the small signal performance
of the first differential amplifier.

Figure (P6.31)
PROBLEM #6.32
In the amplifier of Figure (P6.32), all transistors operate in saturation, have negligible CLM, and
have negligible BITM. Transistors M3 and M4 are identical transistors, but all other transistors in
the amplifier are not necessarily matched to one another. Capacitance C is selected to ensure that it
behaves as a short circuit for signal frequencies greater than
L
.

Figure (P6.32)
(a). Determine the Thvenin signal voltage and Thvenin resistance of the effective signal that
drives the source terminal of transistor M2.
(b). Use the results of Part (a) to deduce the small signal voltage gain, A
v
= V
os
/V
s
.
M1
M3
M4
M4a
M3a
M8
M9
M9a
M2
M2a
M1a
M10
M7
R
s
R
ss
R
s
R
ss
+
V
s
M5 M6
I
bias
V
dd
M8a
+V
dd
V
o
V
o2
V
o1
V
do
+
R
out
R
th
+
V
gg

M1
M5
M3
M4
M2
R
ss
R
4
R
1
R
2
R
3
R
s
V
s
+V
dd
C
V
o
R
out

- 630 -
(c). Determine the expression for the indicated output resistance, R
out
.
(d). Deduce an analytical guideline for the determination of capacitance C.
(e). What circuit node is likely to support the capacitance that dominantly determines the 3-dB
bandwidth of the amplifier?
PROBLEM #6.33
In the amplifier of Figure (6.43), all transistors abide by the SPICE parameters itemized in Tables
(6.1) and (6.2). When driven from a 50 signal source, the amplifier is to be designed for a small
signal, low frequency, voltage gain of V
outs
/V
s
= 10 volts/volt. Moreover, the amplifier drives a
capacitive load (C
l
) of 15 pF. The voltages, V
bias
and V
gg
are to derive from the applied power line
voltage, V
dd
, which is stipulated to be 3.5 VDC. In the case of V
gg
, a coupling capacitor is required.
Choose this capacitance so that it emulates a signal short circuit for frequencies that are at least as
large as 1 MHz. The quiescent output voltage, V
outQ
, is to be nominally 1.5 VDC. For this output
voltage, the net static power dissipation is to be no more than 10 mW. To initiate the design it is
recommended that the static I-V characteristics be simulated for various gate aspect ratios in order to
ascertain suitable ranges for saturation domain operation, suitable gate-source bias voltages,
observed threshold voltage, and other device metrics.
(a). Design the circuit using the fruits of the analyses propounded in Section (6.6.0).
(b). Simulate the design to check quiescent operating points against those deduced in the manual
design. Make adjustments to ensure that all transistors operate safely in saturation.
(c). Simulate the design to check the frequency response. Make adjustments, as required. Decide if
C
l
indeed functions as a dominant capacitance.
(d). For the optimized design, simulate the frequency responses of the driving point output imped-
ance seen by capacitance C
l
and the driving point input impedance seen by the signal source.
(e). For the optimized design, simulate the transient response to a rectangular input signal whose
amplitudes vary from 10mV to +10 mV with rise and fall times of 10 pSEC. The frequency of
this test input signal is 100 MHz.
Plot all simulated results. Be sure to discuss all adjustments deemed necessary to achieve targeted
performance specifications. Finally, discuss how the alleged dominance of load capacitance C
l
is
ascertained?
PROBLEM #6.34
The CMOS circuit given in Figure (P6.34) is a partial schematic diagram of a commercially availa-
ble operational amplifier (op-amp). All transistors are biased in their saturation regimes and can be
presumed to offer negligible CLM and negligible BITM. All NMOS transistors are identical, save
for differences in gate aspect ratios, which are delineated in the schematic diagram as the bold
numerical ratio, W/L, with W and L understood to be in microns. Similarly, all PMOS transistors
are identical, save again for the indicated differences in gate aspect ratio. The biasing current, I
k
, is
a constant current source that is supplied from an off chip current reference. The response to the ap-
plied input voltages, V
i1
, and V
i2
, which have no static voltage component under routine operating
circumstances, is the voltage, V
o
, which is developed at the drain of transistor M8.
(a). In terms of the reference current, I
k
, give the quiescent drain currents conducted by each of the
ten (10) MOSFETs in the amplifier.
(b). Let the quiescent value, V
oQ
, of output voltage V
o
be zero when V
dd
= V
ss
= 1.5 volts. For a first
order biasing approximation, assume that for proper circuit operation, the required quiescent
gate-source voltage of each NMOS device and the required Q-point source-gate voltage of each
PMOS transistor is 600 mV. What resultant Q-point drain-source voltage is established across
M1 and M2 and what static voltage is imposed across the current source, I
k
?
(c). Although the circuit at hand is not a balanced architecture, take signal voltage V
i1
to be +V
x
/2
and V
i2
to be V
x
/2, so that the input difference voltage is (V
i1
V
i2
) = V
x
. Conduct a
straightforward small signal analysis by inspection to deduce the small signal voltage gain,
V
os
/V
x
. Is this result appropriate to an op-amp operated under open loop conditions; that is, no

- 631 -
feedback connected?

Figure (P6.34)
PROBLEM #6.35
In the balanced differential amplifier of Figure (P6.35), V
s
is the applied input signal, while V
o
is the
resultant voltage response. In the interest of simplicity and the fact that the gates of the transistors
draw no current at low to even moderately high frequencies, the Thvenin resistance, R
s
, of the sig-
nal source is tacitly ignored. In other words, the gate leads of transistors M1 and M1a contain resis-
tances R
s
, but R
s
= 0. All transistors operate in their saturation regimes, have infinitely large chan-
nel resistances, and have negligible body effect. In general, transistor Mj is identically matched to
transistor Mja, inclusive of gate aspect ratios; moreover, transistors Mj and Mja are identically bi-
ased. Otherwise, all other PMOS devices are similar as are all other NMOS devices, but differing
gate aspect ratios and/or different quiescent drain currents incur potentially different forward
transconductances in transistors that are not identically matched and biased. To this end, denote the
forward transconductance of the k
th
transistor by g
mk
. Capacitors C
1
, C
2
, and C
3
are selected big
enough so that they each behave as electrical short circuits for signal frequencies above a given low-
est frequency of interest, say
L
. On the other hand, capacitance C is a relatively small capacitance
(only small capacitances can be realized practically in an integrated circuit realization) that is em-
ployed to set the 3-dB bandwidth of the amplifier. Finally, the indicated biasing supplies, V
dd
, and
V
ss
, can be presumed to be ideal, constant voltage sources.
(a). For signal frequencies at which capacitances C
1
, C
2
, and C
3
emulate short circuits, draw the
differential mode, half circuit, signal (or AC) schematic diagram. Do not ignore capacitance C.
(b). For signal frequencies at which capacitances C
1
, C
2
, and C
3
emulate short circuits, draw the
common mode, half circuit, signal (or AC) schematic diagram.
(c). Use the differential mode half circuit schematic to deduce the differential mode voltage gain, A
d

= V
do
/V
di
, and the differential mode output resistance, R
do
. Do not ignore capacitance C.
(d). Use the common mode half circuit schematic to deduce the common mode voltage gain, A
c
=
V
co
/V
ci
, and the common mode output resistance, R
co
.
(e). Use the results of parts (c) and (d) to obtain the small signal voltage gain, A
v
= V
os
/V
s
, and the
out
.
(f). Give an expression for capacitance C, such that the differential mode 3-dB bandwidth is a given
number, say B (in units of radians -per- second).
(g). Why does it make sense to set the 3-dB bandwidth through insertion of capacitance C between
the drain terminals of transistors M2 and M2a, as opposed, for example, to inserting a capacit-
ance between the drains of transistors M3 and M3a?
(h). Give a guideline for selecting capacitances C
1
, C
2
, and C
3
. In developing a design guideline for
defining the i
th
of these three capacitances, assume that the other two capacitances act as signal
short circuits.
8/2
12/2
M1
M9
M2
10/2 10/2
14/2
M3 M4
M5
8/2
2/2
M10
4/2 20/2
14/2
M6
M8
M7
V
o
V
i1
V
i2
+V
dd
V
ss
I
k

- 632 -

Figure (P6.35)

+
M1
M8
M7
M1a
M2
M3
M4 M4a
M6
M2a
C
M3a
R
R R
V
o
V
ss
+V
dd
M9
M10
M11
V
s
R
out
C
1
C
2
C
3

Chapter 6 - Analog Integrated Circuit Design by John Choma

Diunggah oleh

Informasi Dokumen

Deskripsi Asli:

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Chapter 6 - Analog Integrated Circuit Design by John Choma

Diunggah oleh

Hak Cipta:

Format Tersedia

LECTURE SUPPLEMENT #6 . . .

Chapter 6 Analog MOS

Chapter 6 Analog MOS

is 0 volts. Also, measurements taken in the

Anda mungkin juga menyukai