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Specification No: TST00294 Rev.

A
TITLE: Product Specific Burn-In Process Qualification Requirements Template

REVISION HISTORY

Revision history for this document is located in adlib. Hard copy of this document, if not marked
CONTROLLED DOCUMENT in red, is by definition uncontrolled and may be out of date.
Downloaded copies of this document are also considered out of date.

1.0 PURPOSE
The purpose of this document is to specify the qualification and validation requirements for the Burn-In
process.

2.0 SCOPE
This document applies to all products requiring Burn-In.

3.0 OWNERSHIP
It shall be the responsibility of the WW Manufacturing Department, to ensure that this specification
reflects current practice and requirement at all times.

4.0 APPLICABLE DOCUMENTS

LK01800 Correct Method of Drawing up Burn-In Diagrams
LK06347 ADBV1 (Burn-In), ADBV4 (Hast) Style PCB Building Specification
TST00035 Burn-In Subcontractor Procurement Specification
TST00146 Correct Method for Generating Schematics using Cadence Design Entry HDL
K1006 Word template K Specs HTOL /HAST/THB Circuit
K Spec Product Specific Burn-In, HAST PMR Diagrams and Conditions.
P-Spec Product Specific Burn-In Hardware documentation.
TST00290 Burn-In Socket Qualification Requirements
















SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 1 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

5.0 TABLE OF CONTENTS
6.0 Burn-In Board Test Results.
7.0 Supplier Package Socket Fit Analysis Report.
8.0 Burn-In Board Test Verification Results
9.0 Burn-In Board Bench Check Test Verification Results
10.0 Burn-In Board Oven Check Test Verification Results
11.0 Power Supply Verification and Required Power ON and OFF Sequence
12.0 Power Supplies ON Sequencing
13.0 Power Supplies OFF Sequencing
14.0 Noise & Ripple Power Supply Results
15.0 Dynamic Burn-In Conditions Clock Requirements
16.0 Dynamic Burn-In Conditions Input Clock Signals Verification
17.0 Output Waveform Observations Validation Outputs: Level 1
18.0 Output Waveform Observations Validation Test Points: Level 2
19.0 Oven Temperature Profile
20.0 Junction Temperature Evaluation
21.0 Process Performance
22.0 Conclusion

6.0 SUPPLIER BURN-IN BOARD TEST RESULTS

COMPLI
COMPLIANT
Result: Pass/Fail PASS
AN
Point to the Cert of Conformance that specifies the Burn-In Boards were designed, manufactured and tested
in accordance with the K-Spec and Board Building Requirements spec provided.
Details of this are at <LINK> to HLM.

7.0 SUPPLIER PACKAGE SOCKET FIT ANALYSIS REPORT
COMPLIANT
COMPLIANT
Result: Pass/Fail PASS

<LINK> to TRB for the details of this.








SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 2 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

10% SOCKET TEST RESULT


No. DATE TIME BOARD NAME
SERIAL
NUMBER
SOCKET TEST LOCATION RESULT
1 03-Dec-08 6:12:35 ADXL180 1 A3;A12;A16;A20; B9;B18;D2;D6;E13; F4;F9;F16;F19;G11 PASSED
2 03-Dec-08 6:32:09 ADXL180 63 A3;A11;A16A20;B7; B13;D9;D18;E4;E15;F11;G6;G13;G19 PASSED
3 03-Dec-08 6:52:26 ADXL180 49 A1;A7;A11;A15;A20; D4;D10;D14;D18;F1; F13;F16;F20;G8 PASSED
4 03-Dec-08 7:12:35 ADXL180 43 A1;A10;A16;A18;A20;C7;E16;E10;E19;F2; F5;G16;G20 PASSED
5 03-Dec-08 7:24:26 ADXL180 37 A1;A17;B5;C1;C12; C15;C20;D7;E1;F12; F15;F19;G4;G8; PASSED
6 03-Dec-08 7:54:15 ADXL180 60 A1;A6;A11;A14;A20; C4;C17;E2;E7;F11;F15;F19;G4;G9 PASSED
7 03-Dec-08 8:15:24 ADXL180 10 A2;A4;A7;A12;A20; C17;D1;D7;D10;E5;F15;F20;G1 PASSED
8 03-Dec-08 8:37:13 ADXL180 53 A5;A8;A15;C1;C18;D10;D14;D20;F3;F9;F18;D1;D12;D20 PASSED





SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 3 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.


No. DATE TIME BOARD NAME
SERIAL
NUMBER
SOCKET TEST LOCATION RESULT
9 03-Dec-08 9:06:14 ADXL180 14 A1;A4;A14;A10;A20; B18;D1;E7;E16;E19;F1;F11;G14;G20 PASSED
10 03-Dec-08 9:23:09 ADXL180 18 A5;a11;A15;B1;B8; B20;D9;E6;E11;F1; F15;G9;G13;G19 PASSED
11 03-Dec-08 9:34:11 ADXL180 23 A1;A4;A14;B8;B12;B19;C5;D20;E13;F2;F17;G5;G11;G20 PASSED
12 03-Dec-08 9:58:09 ADXL180 38 A7;A9;B1;B15;C5;C10;C13;D20;E16;F3;F9;F11;F14;G6 PASSED
13 03-Dec-08 10:13:35 ADXL180 34 A1;A7;A12;A19;B3;B16;C14;D11;D17;E8;F3;F20;G12;G16 PASSED
14 03-Dec-08 10:33:12 ADXL180 29 A6;A14;A17;A20;B2;BB11;D3;D18;E9;F7; F11;G4;G13;G20 PASSED
15 03-Dec-08 10:50:15 ADXL180 36 A2;A5;A13;A16;B16; B9;C3;D12;D16;D19; E7;F4;F9;G14 PASSED
16 03-Dec-08 11:12:23 ADXL180 15 A1;A7;A10;A16;A20 B3;C17;C20;D10;D14; E4;F1;F19;G11 PASSED
17 03-Dec-08 11:37:20 ADXL180 33 A12;A20;B2;B10;C5; D8;E2;E11;E15;E19; G1;G6;G9;G14; PASSED
18 03-Dec-08 11:59:28 ADXL180 22 A4;A11;A14;A18;B16;C18;D7;D11;D20;E15;F4;F7;F10;F20 PASSED
19 03-Dec-08 13:10:30 ADXL180 9 A1;A8;B11;B14;B18; C4;D12;E6;E15;F2;F5; F10;G13 PASSED
20 03-Dec-08 13:35:10 ADXL180 19 A3;A5;AA10;AA15;B20;C3;C8;C13;D17;E4;E10;F2;F7;F19 PASSED
21 03-Dec-08 13:54:27 ADXL180 58 A2;A14;B9;B18;C5;C20;D3;D14;E1;E11;F7;F17;F20;G5 PASSED




SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 4 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.


No. DATE TIME BOARD NAME
SERIAL
NUMBER
SOCKET TEST LOCATION RESULT
22 03-Dec-08 14:11:35 ADXL180 3 A7;A12;A16;B20;C1; C4;C9;D15;D18;F1;F12;F19;G5;G15 PASSED
23 03-Dec-08 14:11:00 ADXL180 30 A5;A14;A17;A20;B1; B8;D18;E5;E8;F10; F14;G2;G7;G17 PASSED
24 03-Dec-08 14:51:26 ADXL180 12 A1;A13;B15;B18;D2; D10;E13;F7;F18;G1; G10;G16;G20 PASSED
25 03-Dec-08 15:10:22 ADXL180 32 A3;A9;A14;B11;C1;C7;C13;D16;D20;E10;G3;G7;G13;G20 PASSED
26 03-Dec-08 15:30:36 ADXL180 25 A7;A14;B4;B20;C16; D7;D11;E3;E8;E18;F14;G8;G11;G20 PASSED
27 03-Dec-08 15:57:12 ADXL180 2 A1;A13;A20;C3;C9; C12;C16;E1;F6;F8;F12; F15;F19;G4 PASSED
28 03-Dec-08 16:16:20 ADXL180 39 A1;A7;A10;A16;C4; C12;C19;D9;E2;F6;F10;F17;G1;G14 PASSED
29 03-Dec-08 16:34:11 ADXL180 64 A6;A8;A14;A19;B3;C16;D1;D4;D6;F3;F13; F20;G5;G8; PASSED
30 03-Dec-08 16:51:22 ADXL180 42 A1;A15;A20;B17;C3; C8;D12;E1;E6;E18; E20;G5;G16 PASSED
31 03-Dec-08 17:11:20 ADXL180 44 A1;A4;A9;A11;A18;C19;D9;E1;E12;F6;F14; F16;G10;G20 PASSED
32 03-Dec-08 17:35:23 ADXL180 21 A10;A14;B2;B8;B19; D13;E3;E7;E20;F1; F17; G5;G8;G14 PASSED
33 03-Dec-08 17:57:16 ADXL180 40 A10;A14;B2;B8;B19; D13;E3;E7;E20;F1; F17; G5;G8;G14 PASSED






SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 5 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.



No. DATE TIME BOARD NAME
SERIAL
NUMBER
SOCKET TEST LOCATION RESULT
34 03-Dec-08 20:37:41 ADXL180 51 A6;A8;A13;A17;B3; B19;C9;C15;D18;E1; F4; F8;F13;F17 PASSED
35 03-Dec-08 20:57:11 ADXL180 55 A12;A19;B3;B14;C6; C17;D1;D12;E9;E15; E19;F3;;F19;G13 PASSED
36 03-Dec-08 21:13:16 ADXL180 17 A2;A5;A13;A20;C7;C11;D1;D3;D14;D20;E11;F9;F17;G20 PASSED
37 03-Dec-08 21:32:29 ADXL180 59 A1;A9;A13;A20;B18; C5;D15;E3;E8;F12; F19;G1;G10;G15 PASSED
38 03-Dec-08 21:55:19 ADXL180 26 A7;A10;A13;A18;C20;D3;D7;D10;D16;E12; F1;F14;G9;G16 PASSED
39 03-Dec-08 22:16:33 ADXL180 35 A12;A19;B2;B8;C14; C17;E2;E4;E9;E20;F1; F12;F15;F18 PASSED
40 03-Dec-08 22:34:26 ADXL180 28 A1;A6;A10;A13;A15; A20;C3;D9;E1;E17;F5 ;F8;F12;F19 PASSED
41 03-Dec-08 22:56:46 ADXL180 20 A5;A20;B13;C3;C15 ;C18;E1;E4;E10;E6;E12;E15;G3;G19 PASSED
42 03-Dec-08 23:16:18 ADXL180 24 A1;A4;AA7;AA9;A12; A19;C15;D9;E4;E20; F12;G1;G10;G18 PASSED
43 03-Dec-08 23:32:25 ADXL180 62 A1;A6;A12;A17;A20; B9;D2;E4;E11;E15;F7; G1;G13 PASSED
44 03-Dec-08 23:54:29 ADXL180 52 A4;A9;A15;A18;B7;C11;C1;D14;E4;E19;F1; F9;F13;F16 PASSED
45 04-Dec-08 0:13:29 ADXL180 51 A2;A8;A14;AA20;C19;D5;D11;D14;E8;E16; F2;F20;G10;G14 PASSED
46 04-Dec-08 0:35:41 ADXL180 27 A1;A5;a9;A16;B11;B19;C2;D17;E4;E6;E10;F2; F13;F20 PASSED
47 04-Dec-08 0:55:33 ADXL180 16 A13;A20;B3;B7;B9; C10;C16;C18;D20;E5; E13;F1;F9;F20 PASSED
48 04-Dec-08 2:16:26 ADXL180 4 A10;A12;A20;B1;B6; B14;B18;C9;D12;E3; E15;F19;G1;G11 PASSED
49 04-Dec-08 2:36:22 ADXL180 56 a3;a6;a19;b10;b16; d1;d13;e3;e8;e18;f12; f15;g9;g11 PASSED
50 04-Dec-08 2:51:36 ADXL180 6 A2;A7;A17;B14;C3; C11;D1;D5;E9;E15; F19; G3;G6;G12 PASSED
51 04-Dec-08 3:09:32 ADXL180 31 A1;A5;A17;A20;C3;C13;C19;D10;E1;F5;F9; F14;F17;F20 PASSED
52 04-Dec-08 3:37:25 ADXL180 8 A2;A11;A13;A18;B5; B8;C1;D11;D15;E3;E8;F6;F18;G11 PASSED




SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 6 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

8.0 TYPICAL BURN-IN BOARD VALIDATION PROCESS
8.1 The following process to verify the Burn-In Boards is required:
8.1.1 Verify a single board at the Test Station with no units loaded.
8.1.2 Verify with Engineering Units a single row of devices, loaded at the Test Station
8.1.3 Verify using Engineering Units in a fully loaded board of devices at the Test Station.
8.1.4 Verify a single board in the Oven with no units loaded.
8.1.5 Verify the loaded board of devices in each oven slot.


NO
BIB
NO
RESISTANCE

NO BIB NO
RESISTANCE
EMPTY BIB
WITH
LOAD

EMPTY BIB
WITH LOAD
1 6 4.94M 1.408K 27 15 1.358M 1.403K
2 51 14.17M 1.415K 28 40 1.252M 1.423K
3 56 5.06M 1.920K 29 1 1.345M 1.346K
4 35 1.183M 1.399K 30 59 1.486M 1.401K
5 8 1.471M 1.410K 31 33 1.515M 1.415K
6 23 1.475M 1.440K 32 19 0.773M 1.436K
7 17 1.506M 1.426K 33 37 1.481M 1.483K
8 52 1.501M 1.403K 34 31 0.167M 1.415K
9 16 1.361M 1.400K 35 60 1.038M 1.350K
10 44 1.441M 1.424K 36 3 2.309M 1.819K
11 27 1.420M 1.920K 37 12 1.760M 1.418K
12 34 1.415M 1.328K 38 43 1.253M 1.444K
13 58 1.531M 1.409K 39 26 2.847M 1.466K
14 14 14.40M 1.323K 40 30 2.818M 1.450K
15 38 20.18M 1.416K 41 53 1.213M 1.434K
16 22 14.64M 1.477K 42 42 1.308M 1.434K
17 62 14.17M 1.470K 43 28 1.248M 1.425K
18 25 1.180M 1.391K 44 39 2.617M 1.415K
19 24 1.120M 1.470K 45 41 2.154M 1.384K
20 4 3.185M 1.397K 46 9 2.199M 1.395K
21 20 14.17M 1.405K 47 36 3.902M 1.440K
22 10 2.949M 1.471K 48 2 2.464M 1.457K
23 63 3.91M 1.396K 49 29 3.404M 1.424K
24 55 8.29M 1.385K 50 18 2.044M 1.678K
25 64 1.834M 1.511K 51 49 2.338M 1.412K
26 32 1.083M 1.473K 52 21 1.324M 1.457K


FIGURE 1 : LOADING :RESISTANCE MONITORING SHEET QUALIFICATION LOT (8.1.1)





SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 7 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices




NO BIB NO
EMPTY BIB WITH LOAD
RESISTANCE VOLTAGE RESISTANCE VOLTAGE CURRENT
1 36 3.185M 14.5V 1.391K 13.88V 2.0A
2 35 14.17M 14.5V 1.394K 13.84V 2.0A
3 56 5.06M 14.5V 1.392K 13.87V 2.0A
4 51 1.183M 14.5V 1.395K 13.86V 2.0A
5 6 1.471M 14.5V 1.407K 13.88V 1.99A
6 52 1.475M 14.5V 1.401K 13.9V 1.99A
7 8 1.213M 14.5V 1.412K 13.88V 1.96A
8 16 1.308M 14.5V 1.399K 13.88V 1.99A
9 17 1.248M 14.5V 1.427K 13.87V 1.96A
10 27 2.617M 14.5V 1.428K 13.9V 1.93A
11 23 2.154M 14.5V 1.439K 13.85V 1.92A
12 44 2.199M 14.5V 1.422K 13.87V 2.0A
13 58 3.902M 14.5V 1.402K 13.76V 1.98A
14 34 14.40M 14.5V 1.386K 13.87V 2.0A
15 38 20.18M 14.5V 1.415K 13.82V 1.97A
16 22 14.64M 14.5V 1.464K 13.84V 1.87A
17 14 14.17M 14.5V 1.313K 13.89V 1.95A
18 62 1.180M 14.5V 1.386K 13.88V 1.99A
19 24 1.120M 14.5V 1.425K 13.87V 1.93A
20 25 3.185M 14.5V 1.388K 13.83V 2.01A
21 4 14.17M 14.5V 1.391K 13.82V 2.01A
22 10 2.949M 14.5V 1.470K 13.88V 1.92A
23 63 3.91M 14.5V 1.395K 13.87V 1.99A
24 20 14.40M 14.5V 1.386K 13.87V 2.0A
25 40 1.345M 14.5V 1.422K 13.85V 2.0A
26 59 1.486M 14.5V 1.398K 13.88V 2.03A
27 37 1.515M 14.5V 1.482K 13.94V 1.91A
28 31 0.773M 14.5V 1.413K 13.82V 1.92A
29 40 1.345M 14.5V 1.422K 13.85V 1.97A
30 59 1.486M 14.5V 1.398K 13.88V 2.03A
31 37 1.515M 14.5V 1.482K 13.94V 1.91A
32 31 0.773M 14.5V 1.413K 13.82V 1.92A
33 33 1.481M 14.5V 1.406K 13.74V 2.02A
34 60 0.167M 14.5V 1.388K 13.84V 2.03A
35 3 1.038M 14.5V 1.381K 13.92V 2.01A
36 43 2.309M 14.5V 1.441K 13.91V 1.94A
37 12 1.760M 14.5V 1.414K 13.9V 1.99A
38 26 1.253M 14.5V 1.406K 13.87V 2.0A
39 83 2.847M 14.5V 1.431K 13.91V 1.96A
40 28 2.818M 14.5V 1.423K 13.91V 1.91A
41 30 1.213M 14.5V 1.435K 13.92V 1.95A
42 42 1.308M 14.5V 1.431K 13.92V 1.92A
43 39 1.358M 14.5V 1.412K 13.9V 1.99A
44 29 1.252M 14.5V 1.420K 13.94V 1.91A
45 9 1.345M 14.5V 1.392K 13.9V 2.03A
46 32 2.199M 14.5V 1.470K 13.53V 1.91A
47 1 3.902M 14.5V 1.431K 13.91V 2.0A
48 49 2.464M 14.5V 1.408K 13.87V 1.92A
49 21 3.404M 14.5V 1.453K 13.9V 1.94A
50 18 2.044M 14.5V 1.454K 13.91V 1.99A
51 41 2.338M 14.5V 1.382K 13.9V 1.98A
52 2 1.324M 14.5V 1.422K 13.91V 1.97A

FIGURE 2 : LOADING :RESISTANCE AND VOLTAGE MONITORING SHEET QUALIFICATION LOT
(8.1.2-8.1.4)
SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 8 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices





Z
O
N
E

A

BIB # QTY SLOT #
PRE BURN IN
Z
O
N
E

C

BIB # QTY SLOT #
Pre Burn In
TEMP VOLT
CURRENT
TOTAL
TEMP VOLT
CURRENT
TOTAL
62 140 1
A
M
B
I
E
N
T

14.02V
102A
20 139 1
A
M
B
I
E
N
T

14.01V
102A
36 140 2 14.02V 19 136 2 14.03V
35 139 3 13.88V 64 134 3 14.04V
56 140 4 14V 40 137 4 13.94V
51 140 5 14V 59 140 5 14.02V
52 139 6 14.02V 37 132 6 14.06V
14 139 7 14.26V 33 139 7 13.91V
8 139 8 14.02V 31 137 8 13.89V
16 139 9 14V 60 140 9 13.89V
17 136 10 13.98V 3 140 10 14.02V
27 137 11 14.03V 43 135 11 14.03V
23 135 12 14.03V 26 139 12 14.01V
44 138 13 14V 53 136 13 14.04V
Z
O
N
E

B

58 138 1
A
M
B
I
E
N
T

14.03V
102A
Z
O
N
E

D

12 138 1
A
M
B
I
E
N
T

14.02V
102A
34 140 2 13.92V 28 137 2 14.03V
22 133 3 13.93V 30 136 3 14.02V
38 137 4 14.01V 42 135 4 14.03V
6 137 5 14.01V 29 137 5 14.04V
24 136 6 14.01V 39 139 6 14.02V
25 140 7 14V 32 133 7 13.8V
10 133 8 13.99V 1 135 8 14.05V
4 140 9 13.96V 9 140 9 14V
63 140 10 14.01V 49 138 10 14V
15 138 11 14.03V 21 134 11 14.01V
55 140 12 14.01V 48 138 12 14.02V
41 140 13 14V 2 137 13 14.01V

FIGURE 2 : LOADING :RESISTANCE AND VOLTAGE MONITORING SHEET QUALIFICATION LOT
(8.1.5)








SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 9 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices



RESULTS SUMMARY



Verification Result:
Generic **
K-Spec/ OM K0942
Test part Number
1552793
Package / Lead Count 5X5 32 LFCSP
Burn In Oven 001 VX-52
Burn In Board P/N (P-Spec.) N/A
Burn In Program Name ADXL180
Burn In Program revision REV.00
BIB (Probe) ID ADXL 180
Cert of Conformance
Results: (Pass/Fail) PASS
Comments:


Prepared by: ____________________________ Date: ______________________

ADI Approved by: _______________________ Date: ______________________


















SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 10 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices



9.0 BURN-IN BOARD TEST STATION CHECK TEST VERIFICATION RESULTS

The following Burn-In board TEST STATION tests are required. The required and actual results
must be documented as outlined below:
10.0 Power Supply Verification and Required Power ON and OFF Sequence
11.0 Power Supplies ON Sequencing
12.0 Power Supplies OFF Sequencing
13.0 Noise & Ripple Power Supply Results
14.0 Dynamic Burn-In Conditions Clock Requirements
15.0 Dynamic Burn-In Conditions Input Clock Signals Verification
16.0 Output Waveform Observations Validation Outputs: Level 1
17.0 Output Waveform Observations Validation Test Points: Level 2

10.0 BURN-IN BOARD OVEN CHECK TEST VERIFICATION RESULTS

The results for the Burn-In board OVEN tests are to be compared to the Test Station tests and documented
that the results are common as follows:

10.0 Power Supply Verification and Required Power ON and OFF Sequence
11.0 Power Supplies ON Sequencing
12.0 Power Supplies OFF Sequencing
13.0 Noise & Ripple Power Supply Results
14.0 Dynamic Burn-In Conditions Clock Requirements
15.0 Dynamic Burn-In Conditions Input Clock Signals Verification
16.0 Output Waveform Observations Validation Outputs: Level 1
17.0 Output Waveform Observations Validation Test Points: Level 2
18.0 Oven Temperature Profile
19.0 Junction Temperature Evaluation







SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 11 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.


11.0 POWER SUPPLY VERIFICATION AND REQUIRED POWER ON AND OFF SEQUENCE
Bias voltages should be applied to DUT in sequence as shown on the supply page of the Burn-In
Specification.

POWER SUPPLY SPECIFIED BY K-Spec:


Dash Number
Signal Name Pin Numbers Notes
LFCSP 5X5 32 pin
VBP (+14.5V) 22, 23, 24 Individually connect pins 22-24 to power plane
and connect C2 between pin 23 and GND plane
VBN (GND) 14, 15, 16 Individually connect pins 14-16 to GND plane
VDD 9, 10, 11 Connect pins 9-11 together via etch, and
connect C1 between pin 10 and GND plane.


Table 1: Nominal Voltage and Power ON / OFF Sequence as per K-spec


POWER SUPPLY RESULTS:

Power
Supply
Power
Supply
Name
DUT Pin
Power
Supply
Measured
BIB
Power
Supply
Measured
V Sense
(0.1R res)
Imax per
DUT (calc)
V1
VCC1

13.99V N/A 14.49275362mA
V2
V3
V4
V5
V6








SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.


12.0 POWER SUPPLIES ON SEQUENCING

The supplied DC voltage should be powered ON in sequence that is to be shown in Table 1 and the actual
sequence down (scope shots) is to be inserted as Fig. 1.

TEST STATION COMPLIANT
Result: Pass/Fail PASS

SPECIFIED Power Supply Conditions (See K-Spec) ACTUAL Power Supply Conditions

Power
Supply
Voltage Imax/DUT Sequence Power
Supply
Voltage Imax/DUT Sequence
V1 14.5V 1 V1 14.4 1
V2 V2
V3 V3
V4 V4
V5 V5
V6 V6

Table 1: Power ON Sequence

Tested On:
Insert scope plot of Supplies.



Fig 1: DC Voltage Supply ON Sequence

OVEN COMPLIANT
Result: Pass/Fail PASS


SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 13 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.


13.0 POWER SUPPLIES OFF SEQUENCING

The supplied DC voltage should be powered OFF in sequence that is to be shown in Table 2 and the actual
sequence down (scope shots) is to be inserted as Fig. 2.

TEST STATION COMPLIANT
Result: Pass/Fail PASS

SPECIFIED Power Supply Conditions (See K-Spec) ACTUAL Power Supply Conditions

Power
Supply
Voltage Imax/DUT Sequence Power
Supply
Voltage Imax/DUT Sequence
V1 0V 1 V1 0V 1
V2 V2
V3 V3
V4 V4
V5 V5
V6 V6

Table 2 Power OFF Sequence
Tested On:
Insert scope plot of Supplies.



Fig 2: DC Voltage Supply OFF Verification
OVEN COMPLIANT
Result: Pass/Fail PASS

SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 14 of 23
24355
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

14.0 NOISE & RIPPLE POWER SUPPLY RESULTS
Using an oscilloscope, the noise and ripple content on each DC Supply is to be checked. The acceptable
ripple limit is a maximum of 200 mV. The measured ripple scope plots are to be inserted below.

TEST STATION COMPLIANT
Result: Pass/Fail PASS




Fig 3 Fig 4
V1 Noise = 58.4V pk-pk. V2 Noise = 35.6mV pk-pk.


OVEN COMPLIANT
Result: Pass/Fail PASS











SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 15 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

15.0 DYNAMIC BURN-IN CONDITIONS CLOCK REQUIREMENTS
Paste in specific clock patterns as per ADI specification



NOTE: NO CLOCK REQUIREMENTS FOR THIS DEVICE



16.0 DYNAMIC BURN-IN CONDITIONS INPUT CLOCK SIGNALS VERIFICATION
Using an oscilloscope, the clock signals are to be checked. The measured scope plots are to be inserted
below.

TEST STATION COMPLIANT
Result: Pass/Fail N/A

Tested On:
BIB & Device Present : YES

Clock Signal Verification:

Test Point Pin Name Pin No. Expected Signal Actual Signal Pass/Fail
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.1
2.2
2.3
2.4
2.5
2.6
2.7

OVEN COMPLIANT
Result: Pass/Fail N/A


SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 16 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

Input Clock Waveforms
Insert Scope shots for each Input Clock signal




Figure 10 Frame, Data, CLK



Figure 11



Figure 12



Figure 13










NOTE: NO CLOCK REQUIREMENTS FOR THIS DEVICE

SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 17 of 23
24355
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

17.0 OUTPUT WAVEFORM OBSERVATIONS VALIDATION OUTPUTS: LEVEL 1
Insert Scope shots for each Output Clock signal

TEST STATION COMPLIANT
Result: Pass/Fail N/A


Figure 14 Output Clocks



Figure 15 -



Figure 16


OVEN COMPLIANT
Result: Pass/Fail N/A











NOTE: NO CLOCK REQUIREMENTS FOR THIS DEVICE
SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 18 of 23
24355
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES, INC.
It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

18.0 OUTPUT WAVEFORM OBSERVATIONS VALIDATION TEST POINTS: LEVEL 2
Insert Scope shots for each Test Point signal

TEST STATION COMPLIANT
Result: Pass/Fail N/A






Figure 17 TP1



Figure 18 TP2

OVEN COMPLIANT
Result: Pass/Fail N/A







NOTE: NO TESTPOINT ( TP ) REQUIREMENTS FOR THIS DEVICE
SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 19 of 23
24355
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

19.0 TEMPERATURE PROFILING
The purpose of this section is to map and visualize the actual reading of individual DUT output in a
particular BIB at a given temperature during the bench checking or during oven qualification. The
reading can be obtained from the oven host computer (i.e. VX36 Criteria-V oven) or to an external data
acquisition then the data will be encoded to a spreadsheet. The data shall be forwarded to the REL and
Burn-In Engineer responsible for the qualification activity for review and approval (See Figure22 as a
sample data presentation).

19.1 For products that have no temperature output pins that can be datalogged, then profile the DUT(s) by
monitoring the case temperatures using 10-point or 20-point thermocouples. From this data set then
calculate the die or junction temperature using the Theta JC of the specified package.

19.2 DATA MAPPING PROCEDURE AND DETAILS

19.2.1. DUT Socket Position.
i. A table will be use for specifying each socket position for one BIB. See Fig 19 for example.
19.2.2. DUT Temperature Sense Output.
i. Encode the data from the DUT socket position respectively on the created table.
ii. In terms of voltage, the readings shall fall within the limits.
19.2.3. BIB to Oven Slot Mapping.
i. The burn-in board identity and oven slot mapping should be defined.
19.2.4. Specify the oven set point and the date it was being performed.
19.2.5. Create a legend and conditional formatting to indicate that the DUT experienced out or within
specification limits. (See sample format in Figure 19.)


Figure19. Table shows the chamber mapping and Board Lay-out
SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 20 of 23
24355
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.
DEVICE NAME: ADXL180 BURN IN REQUIREMENTS:
PACKAGE: 32 QFN TEMPERATURE: 140C
BURN IN OVEN: 01VX-52 VOLTAGE: 14.5V
SERIAL NUMBER: VX52-01
CHAMBER INFO: 4 ZONES / 52 SLOTS
BOARD NAME: ADXL 180
BOARD TYPE: BV1
SOCKET POISTION: 140

19.3 DUT TEMPERATURE PROFILE
19.3.1 Indicate the burn-in board number and to what slot number the board was placed in the specific zone of
the oven. (See details in Figure 20)
19.3.2 Unless specified by the BI or REL engineer, there will be 12 subdivided time-sheet to encode the
readings for at least 4 hours in a 49 BI hours for close monitoring.


19.4 OVEN TEMPERATURE PROFILE
20.4.1 The actual air temperature of the chamber shall be monitored using 10-Point Oven profiling or 20- Point
Monitoring. (See details in Figure 21).
20.4.2 Provide an illustration showing the location of the zone in the oven for BI/Equipment Engineer
visualization purposes. (See details in Figure 22).

Oven Set Point is 140 C -, -0/+16C
Burn-In Time is 24 hours




Figure22. VX 52 Oven Pictorial View
SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 21 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
180.0
200.0
0
9
:
3
0
:
0
0
0
9
:
5
4
:
0
0
1
0
:
1
8
:
0
0
1
0
:
4
2
:
0
0
1
1
:
0
6
:
0
0
1
1
:
3
0
:
0
0
1
1
:
5
4
:
0
0
1
2
:
1
8
:
0
0
1
2
:
4
2
:
0
0
1
3
:
0
6
:
0
0
1
3
:
3
0
:
0
0
1
3
:
5
4
:
0
0
1
4
:
1
8
:
0
0
1
4
:
4
2
:
0
0
1
5
:
0
6
:
0
0
1
5
:
3
0
:
0
0
1
5
:
5
4
:
0
0
1
6
:
1
8
:
0
0
1
6
:
4
2
:
0
0
1
7
:
0
6
:
0
0
1
7
:
3
0
:
0
0
1
7
:
5
4
:
0
0
1
8
:
1
8
:
0
0
1
8
:
4
2
:
0
0
1
9
:
0
6
:
0
0
1
9
:
3
0
:
0
0
1
9
:
5
4
:
0
0
2
0
:
1
8
:
0
0
2
0
:
4
2
:
0
0
2
1
:
0
6
:
0
0
2
1
:
3
0
:
0
0
2
1
:
5
4
:
0
0
2
2
:
1
8
:
0
0
2
2
:
4
2
:
0
0
2
3
:
0
6
:
0
0
2
3
:
3
0
:
0
0
2
3
:
5
4
:
0
0
0
0
:
1
8
:
0
0
0
0
:
4
2
:
0
0
0
1
:
0
6
:
0
0
0
1
:
3
0
:
0
0
0
1
:
5
4
:
0
0
0
2
:
1
8
:
0
0
0
2
:
4
2
:
0
0
0
3
:
0
6
:
0
0
0
3
:
3
0
:
0
0
0
3
:
5
4
:
0
0
0
4
:
1
8
:
0
0
0
4
:
4
2
:
0
0
0
5
:
0
6
:
0
0
0
5
:
3
0
:
0
0
0
5
:
5
4
:
0
0
0
6
:
1
8
:
0
0
0
6
:
4
2
:
0
0
0
7
:
0
6
:
0
0
0
7
:
3
0
:
0
0
0
7
:
5
4
:
0
0
0
8
:
1
8
:
0
0
0
8
:
4
2
:
0
0
0
9
:
0
6
:
0
0
0
9
:
3
0
:
0
0
0
9
:
5
4
:
0
0
1
0
:
1
8
:
0
0
1
0
:
4
2
:
0
0
1
1
:
0
6
:
0
0












POINTS ( TC WIRE / DATA
LOGGER )
SET TEMPERATURE SPECIFICATION LIMIT ACTUAL TEMPERATURE DEVIATION
POINT 1
140C
-0/+16
140C UP TO 156C
141.1C 1.1C
POINT 2 141.3C 1.3C
POINT 3 142.2C 2.2C
POINT 4 140.0C 0
POINT 5 140.0C 0
POINT 6 140.9C .9C
POINT 7 140.2C .2C
POINT 8 140.3C .3C
POINT 9 141.5C 1.5C
POINT 10 141.3C 1.3C
Figure23. Oven Temperature and DUT Sample Data Presentation

20.0 JUNCTION TEMPERATURE EVALUATION
Characterization of Diode in Power-Up mode:
Insert Plot of Voltage vs. Temperature of Package vs. Oven Temperature
Junction Temperature Results
Oven
Temperature
50 75 100 110 125 135 150
Package Temp
50.5 75.2 100.1 110.2 125.3 135.4 150.1
Diode
Voltage
TJ
Calculation


Characterization of Diode in Power-Down mode:
Insert Plot of Voltage vs. Temperature of Package vs. Oven Temperature
Junction Temperature Results
Oven
Temperature
50 75 100 110 125 135 150
Package Temp
50.5 75.2 100.1 110.2 125.3 135.4 150.1
Diode
Voltage
TJ
Calculation


SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.

21.0 PROCESS PERFORMANCE

Pre Burn-In LOT # LOT # LOT #
Qty In
Qty Out
Yield % % %


Burn-In LOT # 1552793
(1
st
turn)
LOT # 1552793
(2
nd
turn)
LOT #
Qty In 7151 1492
Qty Out 7140 1492
Yield 99.8% 100% %


Post Burn-In LOT # LOT # LOT #
Qty In
Qty Out
Yield % % %



22.0 CONCLUSION
22.0.1 Based on these results obtained the Burn-In Process for the ADXL-180 for this configuration is
validated and available for use in production.




SPEC NO.: TST00294 Rev. A
CODE IDENT NO.

Page 23 of 23
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It is not to be reproduced or copied, in whole or in part, or used for
furnishing information to others, or for any other purpose detrimental
to the interests of Analog Devices. The equipment shown here on
maybe protected by patents owned or controlled by Analog Devices.