130nm CMOS Technology

Yang Hong, Chi Fat Chan, Jianping Guo, Yuen Sum Ng, Weiwei Shi, Lai Kan Leung, Ka Nang Leung,
Chiu Sing Choy and Kong Pang Pun
Department of Electronic Engineering,
The Chinese University of Hong Kong, Shatin N.T, Hong Kong
yhong@ee.cuhk.edu.hk; knleung@ee.cuhk.edu.hk

Abstract This paper presents a low-power, passive, UHF RFID
tag design compatible with EPC
TM
C1G2 protocol. In order to
reduce its cost, diode-connected NMOS in a standard CMOS
technology is used instead of Schottky diodes. With the help of
low-threshold-voltage, triple-well NMOS, a minimum input
power of -7.6dBm is achieved. A sub-1V, low temperature-
coefficient voltage reference using self-biased mutual
compensation is proposed without large resistors to save the
chip area. In addition, an energy-aware irregular clock
structure, together with clock gating, achieves low power
consumption in the baseband processor. The whole tag is
implemented in a 130nm CMOS technology and the total chip
area is 1200umx1220um.
I. INTRODUCTION
Passive UHF RFID distinguishes itself from others in the
near field item-level tagging applications, mainly due to its
high data rates, small antenna sizes and low costs. To lower
the tag cost to a few cents for wide applications, such as
supply chain management, chip area for tags is one of the
crucial considerations [1]. Apart from its cost, low power
consumption is also required for passive UHF RFID, not only
due to the passive working principles, but also for a longer
operating range in the order of several meters or even longer
[2]. As the RF signal power decreases rapidly with its
communication distance, the induced voltage across the
antenna is quite small, typically in the order of 200mV [2].
This means micro-power rectifier has to function properly
with such low input voltages. Moreover, the voltage reference
following the rectifier needs to be optimized for low voltage
operation to reduce the burden on the rectifier.
Fig. 1 shows the diagram of the proposed tag IC. The
rectifier, regulator, demodulator, modulator, clock generator
and the baseband processor are all integrated into the tag IC
and put onto the same chip. The rectifier, using low-threshold-
voltage, triple-well NMOS to reduce the required minimum
input voltage, will be proposed in Section II. The self-biased,
resistor-less bandgap voltage reference using mutual
compensation, which achieves sub-1V operation with low
temperature coefficient will be presented in Section III. The
clock generator together with ASK modulator and
demodulator will be introduced in Section IV. Section V will
discuss the design of the baseband processor using energy-
aware, irregular clock structure together with clock gating to
achieve good power saving. Finally, Section VI is the
conclusion of the design.

Fig.1 Passive UHF RFID tag diagram

II. RECTIFIER
The rectifier converts the input AC voltage into DC
voltage, which is further regulated by the voltage regulator to
provide power supply to the circuits in the tag. The single-
stage structure and the simplified circuit diagram for the
CMOS rectifier are shown in Fig. 2a and Fig. 2b,
respectively. Low threshold-voltage NMOSFET is chosen to
minimize the conduction loss of the rectifier. Compared with
the case using Schottky diodes, the utilized approach saves
the fabrication cost for extra masks the Schottky diode needs.


(a) (b)
Fig. 2 (a) single-stage structure (b) circuit of the proposed rectifier

A 16-stage rectifier is designed to generate an output
voltage of 1.3V from the worst-case of input peak-to-peak
Design of Passive UHF RFID Tag in
This work was supported by the Innovative Technology Commission
(GHS/020/06), Hong Kong.
1371 978-1-4244-2342-2/08/$25.00 2008 IEEE.
voltage of 180mV under the condition of 50- input
impedance. T The minimum input power entering the rectifier
is -7.6dBm, and the optimum area for the rectifier is 1200m
x 600m.

III. REGULATOR
Voltage regulator provides stable power supply to front-
end and other circuits. Moreover, the tag should function
properly when there is very little or even no RF power
available during backscattering [3]. A voltage regulator,
shown in Fig. 3, including voltage reference, bias current
generator, low dropout (LDO) convertor and power-on-rest
(POR) circuit (not displayed), is used in the tag design.

Fig. 3 Proposed LDO voltage regulator

A Bandgap voltage reference is used mainly due to its low
temperature coefficient (tempco) and high reliability in most
cases. Conventional bandgap voltage reference suffers low
voltage issue under sub-1V operation since the bandgap
voltage is around 1.25V. Although there are many new
structures proposed [4], it is not favorable to use bandgap
voltage reference in passive RFID tag design because the
very large resistor, up to tens of mega Ohm, is needed to
achieve ultra low quiescent current down to sub-1A, or even
tens of nano-ampere.
To achieve sub-1V operation with low tempco, a voltage
reference using self-biased mutual thermal compensation is
adopted without large resistors to save area and reduce
parasitic capacitance. The reference voltage is equal to [5].

+ =
L
W
C
I
V V
ox n
D
TH REF

2
(1)
With proper bias current I
D
, zero tempco can be achieved
by compensating the tempco of V
TH
and
n
. A self-biased
current generator is introduced to save power more
effectively. A startup circuit is included to initiate the circuit
after powering on. There are two feedback loops. One is
negative, coming from OP
1
and M
1
, while another is positive,
coming from OP
1
and M
1
M
4
. A large MOS capacitor M
C1
,
is used to slow down the speed to make the circuit stable.
Simulation results are shown in Fig. 4. The reference voltage
is 470mV at 27C with 25ppm/C tempco, while the tempco
of bias current is 550ppm/C. To get proper I
D
to lower the
tempco, a trimming strategy to resistor R
1
is introduced.
To save power and simplify the compensation of the LDO
converter, a single stage amplifier is adopted to drive the
power PMOSFET directly. The NMOSFET input transistors
work in sub-threshold region for low-voltage (sub-1V) and
low-power operation. A 1-nF MOS capacitor is used to store
sufficient charge to power up the tag when there is very little
or even no RF power available to the chip during
backscattering. The simulated load transient response of the
voltage regulator is shown in Fig. 5. The proposed regulator
can recover within 3 s with only 1mV voltage spike when
the loading current changes from 1A to 10A. Moreover, it
can also work well under 50A load transient change. To
save chip area, seven PMOS transistors with substrate
connected to the source terminal are used as a potential
divider to be the output feedback network.
The total quiescent current of the voltage regulator,
including trimming and POR circuits, is 0.73A at room
temperature when input voltage is 1.2V. The regulated output
voltage is 1.1V, which are the typical operational condition.
-20 0 20 40 60 80 100
0.4685
0.469
0.4695
0.47
0.4705
Temperature (degree)
R
e
f
e
r
e
n
c
e

V
o
l
t
a
g
e

V
R
E
F

(
V
)


-20 0 20 40 60 80 100
5.8
5.9
6
6.1
6.2
x 10
-8
I
b
i
a
s

(
A
)


VREF
Ibias

Fig. 4 Reference voltage and bias current vs. temperature

6 6.1 6.2 6.3 6.4 6.5 6.6 6.7
x 10
-4
1.07
1.08
1.09
1.1
1.11
Time (s)
V
O
U
T

(
V
)
6 6.1 6.2 6.3 6.4 6.5 6.6 6.7
x 10
-4
0
2
4
6
x 10
-5
Time (s)
I
O
U
T

(
A
)

Fig. 5 Load transient response of the voltage regulator

IV. CLOCK, ASK DEMODULATOR & MODULATOR
In analog domain, most of power consumed in the RFID
tag is by the oscillator [6]. To comply with the EPC C1G2
protocol, the clock frequency tolerance is required to be
within 4% under nominal temperature [7]. The largest
source of frequency variation comes from the variation in the
supply voltage since the incoming RF energy is weak and
1372
unstable. To strike a balance among power consumption,
frequency accuracy, and die area, a five-stage current-starved
ring oscillator is proposed, as shown in Fig. 6. The oscillator
consumes a maximum power of 500nW with frequency
variation being 0.6% when the supply voltage changes from
0.65V to 1.3V.
It is mentioned in [8] that 1.92MHz is the minimum
frequency required to decode the incoming PIE data correctly
according to the EPC C1G2 specification. To leave sufficient
margin, a frequency of 4MHz is selected.
Fig. 7 shows the ASK demodulator, which is composed of
an envelope detector and a voltage comparator. M
1
M
4
are
low-threshold transistors, while M
5
M
8
are normal ones.
The number of stages to generate V
env
and V
ref
is the same,
and the ideal values with no loading [2] are
) ( 5 . 2
low T in env
V RF V = (2)
) ( 5 . 2
nor T in ref
V RF V = (3)
VDD
Mb1
VDD
VSS
Mb
2
Ib
VDD
Vo Level
Converter
VSS
VSS

Fig. 6 Current starved ring oscillator



Fig. 7 Envelope detector

When input signal is applied to the RF
in
terminal, V
env
is
higher than V
ref
due to lower the threshold voltage of M
1

M
3
.In the absence of input signal, C
3
discharges through M
4
,
and C
6
discharges through M
8
. As diode-connected M
4
has a
lower threshold voltage, C
3
discharges faster than V
ref
. ASK
demodulation is completed after feeding V
env
and V
ref
to a
voltage comparator. The simulated output of the envelope
detector with RF
in
= 150mV
pk
and modulation index of 0.2at
900MHz is shown in Fig.8.
The modulator of the tag sends its replies to the RFID
reader by backscattering. This can be achieved by modulating
the input impedance of the tag when the RFID reader is
sending a continuous wave to it. In this work, ASK
modulation is chosen. Since high input impedance of the tag
reflects the continuous wave back to the reader while low
input impedance absorbs the wave, a switch is added at the
input of the tag IC. The difference of the two impedances is
given by
) // ( ) // (
tag ON SW tag OFF SW diff
Z Z Z Z Z

= (4)
Increase of the value of Z
diff
eases the detection of the
backscattering signal in the reader. For the maximum Z
diff
, the
optimal W/L aspect ratio of the switch is 42um/0.12um.
0 0.5 1 1.5 2 2.5
x 10
-5
-0.05
0
0.05
0.1
0.15
0.2
Time (s)
V
o
l
t
a
g
e

(
V
)


Venv
Vref

Fig. 8 Simulated output of the envelope detector

V. BASEBAND PROCESSOR
One of the constraints in the baseband processor design is
the limited power consumption under low supply voltage.
Another constraint is the weak wireless input from the RFID
reader. The input is prone to interference and data integrity is
a critical issue in the processor design [9]-[11]. Moreover, the
input is in a serial, PIE format [12]. Thus, the throughput of
the processor is limited.
The block diagram of the proposed baseband processor is
shown in Fig. 9. The data flow of the processor is based on
the input-verify-respond steps. Input PIE_LEN_COUNTER
is the extracted time value from the Demodulator. In the PIE
Decoding block, the preamble, frame and PIE data embedded
in the input is identified and decoded. When error is detected,
the whole circuit goes back to the ready state. In order to
increase the efficiency of the baseband processor, reception
and verification of the input data is implemented in a
pipelined manner.
To achieve good power saving, an energy-aware, irregular
clock is used in this design. As shown in Fig. 9, the
conventional command handler is partitioned into two parts.
One part, including the PIE Decoding block and the
Command Receiving block, is triggered by an irregular clock,
PIE_CLK. The remaining part, the Command Processing
block, is triggered by a regular clock, CMD_PROC_CLK. As
shown in Fig. 10, pulses with width of 20ns in the irregular
clock, PIE_CLK, are synchronized by the rising edges in the
1373
envelope of the RF signal. Because the energy supply is
abundant after the rising edge of the RF envelope, the clock
can easily trigger the PIE Decoding block and Command
Receiving block without any interruption in the power supply.
The regular clock, CMD_PROC_CLK, comes from the ring
oscillator outputs. Its frequency (62.5kHz ~ 500kHz) is equal
to the link frequency for the backscattering signal,
FM0_DATA.
To reduce dynamic power dissipation, Clock Gating
blocks (CK_G) are added into the design to stop the
propagation of the clocks when the blocks are in the idle
state. The structure of CK_G is shown in Fig. 11. Because all
the blocks are triggered at rising edge, CK_G can also avoid
the racing condition, which may cause failure of operation.
Table I summarizes the key performance of the baseband
processor. With the partition of the command handler, the
application of energy-aware, irregular clock and the use of
clock gating, the power consumption of the baseband
processor is only 1.1W. Efficiency of the baseband
processor is also increased under such low power
consumption by the pipelined architecture.


Fig. 9 Block diagram of baseband processor



Fig. 10 Timing steps with irregular clock


Fig. 11 Clock gating circuit (CK_G)

Table I Summary of Baseband Processor
Function Implemented Inventory (Query Command)
Area 215m 115m (Core & Buf.)
Leakage Power 700pW (EDA estimation)
Power Consumption 1.1W (EDA estimation)

VI. CONCLUSION
A low-voltage, low-power, cost-effective, passive UHF
RFID tag design has been proposed in this paper. It is
implemented in a 130nm CMOS technology and occupies an
area of 1200m 1220m. For the proposed rectifier, a
minimum input power of -7.6dBm is achieved by using
NMOS with low threshold voltage to reduce both cost and
input power. A low-tempco voltage reference using bias
mutual compensation is proposed for sub-1V operation
without using large resistors to save chip area. Energy-aware
irregular clock structure in the proposed baseband processor
together with clock gating helps to achieve good power
saving. All circuits have been designed in a 130nm CMOS
technology to satisfy EPC C1G2 protocol with emphasis on
reduction of both the power consumption and silicon area.
Simulations were done to verify all the proposed ideas.
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