Analog Integrated Circuits and Signal Processing, 39, 191204, 2004

c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits
TURGAY TEMEL

AND AVNI MORGUL

Electrical and Electronics Engineering Department, Bo gazici University, 80815 Bebek, Istanbul, Turkey
E-mail: temeltur@boun.edu.tr; morgul@boun.edu.tr
Received May 15, 2002; Revised May 7, 2003; Accepted June 11, 2003
Abstract. In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits.
The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel
threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared
to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of
analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in
terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is
designed to demonstrate the advantages of new current-mode multi-valued logic circuits.
Key Words: current-mode CMOS design, multi-valued logic, higher-radix full-adder
1. Introduction
Multi-valued logic, MVL, is a hybrid design technique
of binary logic and analogue signal processing which
retains noise advantages of a digital signal while pro-
cessing greater informational content in analogue man-
ner. MVL has also the advantages of less intercon-
nection, and circuitry to effectively implement many
arithmetic and logical functions on one chip [13].
Due to design simplicity and larger dynamic range,
current-mode approach is preferred for designing MVL
circuits. Some current-mode multi-valued logic (CM-
MVL), studies are proposed for I
2
L[4, 5], for CCD[6],
and for CMOS [1, 7]. Most CMOS CM-MVL studies
prefer using voltage-mode internal circuits for switch-
ing a desired level of output current by exploiting the
comparator scheme in [8].
The hybrid or switched current mode operation
[1, 7], have two main drawbacks: rst, as the in-
put current range increases, comparator transresis-
tance decreases, hence alleviating the advantages of
current-mode design; second, a desirable radix opera-
tion should satisfy certain DC operation constraints.
The consequence is that as the radix increases, in-

Present address: Division of Informatics, University of Edinburgh,

Edinburgh, EH1 2HQ, UK.
creased area, and parasitic capacitances may drive the
circuitry into oscillations with a poor transient re-
sponse. Therefore, the radix can not be chosen as high
as desired.
On the other hand, well-known current-mode stud-
ies employing current as the unique design quantity
[9, 10], exploit positive-feedback current-mode thresh-
old and truncated-difference topologies, respectively.
A full current-mode realization of a min gate is given
in [7]. DC behavior of the positive-feedback threshold
topology [9], for designing some MVLprimitives, such
as max, and min, is highly sensitive to transistor mis-
matches, introducing undesirable output level shifts.
Transient response is also slower compared to trun-
cated difference-oriented design [10]. The truncated
difference topology is investigated in [10], despite the
fact that the logic primitives, such as max, min and
literal, have not been supplied. Due to low current
driving of nodes, this topology is expected to yield
slower transient response [11], compared to our study.
Moreover, the threshold value is obtained by adjusting
the transistor dimensions within the circuit while all
variables can be externally supplied with this topology
[12].
The lack of a proper design topology for developing
full current-mode MVLcircuitries is also valid for win-
dowliteral operations. Despite some studies [7, 1315],
192 Temel and Morgul
no methodic study has been announced for full current-
mode CMOS literal circuit design to our knowledge.
In this study, a new approach is introduced for
designing MVL gates and higher-radix subsystems.
Statistical relationships between an achievable radix
and noise characteristics of designs are studied with
a model circuit. Proposed gates are designed using
Mietecs ES2 0.7 m HSPice (level 6) parameters,
given in Appendix A, with full-extraction for 2.7 V
power supply voltage.
2. Background and Notation
Consider an r-valued m-variable function f (X) where
X = {x
1
, x
2
, . . . , x
m
}. Each x
i
takes on a value from
the set R = {0, 1, . . . , r 1} in whichr is the radix. The
function f (X) is a mapping f : R
m
R. Therefore,
there are r
r
m
possible different functions [7].
In CM-MVL, logic levels are represented by multi-
ples of a base current value, I
b
, set to 10 A for this
study. Thus, level 0 is associated with the value of null,
level 1 is associated with I
b
= 10 A and so on. A
logic level l corresponds to an interval of the continu-
ous quantity x, such that
x l if x [(l 0.5)I
b
, (l +0.5)I
b
] (1)
Denition 2.1. The min operation is represented by
min(x, y) = x y (2)
or alternatively, is to be used instead of in clear
context.
Denition 2.2. The max operation is represented by
max(x, y) = x y (3)
or alternatively, + is to be used instead of in clear
context.
Denition 2.3. The complement of x, [16], is dened
as
x = r 1 x (4)
Denition 2.4. The window literal, or shortly, literal,
L [17], is dened as
a
x
b
=
_
r 1 if a x b
0 otherwise
(5)
where a, b R. The complementary-literal, CL [16],
is dened as
a
x
b
=
_
r 1 if x < a or x > b
0 otherwise
(6)
From(2) and (5) or (6), a k
l
-valued literal and k
c
-valued
complementary literal are of the forms k
l

a
x
b
and
k
c

a
x
b
, respectively.
Denition 2.5. The y-cyclic clock-wise, (y-CWC),
and its counter, (y-CCWC), operations are dened as
y-CWC: x
y

= x + y (mod r) (7a)
y-CCWC: x
y

= x y (mod r) (7b)
From (7a), it can be shown that
x
y

= x
ry

(7c)
Denition 2.6. A k-valued product term is given by
P
k
:
_
i {1,2,...,m}
g(x
i
) = k (8)
where refers to min operator over unary operations,
g(x
i
), such as L, CL, CW and CCW [7], i.e.,
P
k
:
_
k
1

a1
x
b1
1
_

_
k
2

a2
x
b2
2
_
x
a3

3
. . . = k (9)
In this study, product terms are assumed to include only
literals and/or complementary literals as unary opera-
tions. However, cyclic and its derivatives are generally
used to realize symmetric functions.
Denition 2.7. A multi-valued function can be ex-
pressed in terms of the product terms as, [17].
f (x
1
, x
2
, . . . , x
m
) =
_
j R
P
j
(10)
where implies the max operator.
Implementation of Multi-Valued Logic Gates 193
3. Basic Circuit Elements
3.1. Primitives
(1) Sum: Basically, a sum is a node in the circuit,
where some currents enter and/or some currents
leave.
(2) Constant: Logic levels represent constant cur-
rents in CM-MVL. They can be generated
with a reference circuit using either enhance-
ment mode p-type or n-type transistors, depend-
ing on the current sourcing or sinking action
desired.
(3) Current-Mirror: They are used for generating sin-
gle or multiple-replicas of a current. An n-type cur-
rent mirror and its symbol are shown in Fig. 1
where N
d
stands for diode-connected transistor
while N
m,1,..n
for mirror transistor.
A current can be redirected by cascading n and
p type mirrors, as shown in Fig. 2 where z
1
, . . . , z
n
can be any multiple of x.
(4) Input/Output Circuit: Adiode-connected transistor
with aspect ratio of W/L = 1.5/1 is used as the
input and output circuit. This aspect ratio refers
to the minimum feature size to t the technology
used.
Fig. 1. The n-type current mirror and its symbol.
Fig. 2. Multiplying and redirecting a current.
3.2. Secondary Blocks
Inthis study, gate circuits are formedbyusingtruncated
difference operation [10], dened by
x ky =
_
x ky iff x ky
0 otherwise
(11)
It can be shown that
min(x, y) = x(xy) = y(yx) (12a)
max(x, y) = min( x, y) = x +(yx) (12b)
The truncated difference can be realized as shown in
Fig. 3.
Based on the truncated difference, current-mode
threshold operations can also be realized. The upper
and lower threshold operations for a, b, c R are de-
ned as
upper-threshold, th
u
: a

c
b
=
_
c if a b
0 otherwise
(13a)
lower-threshold, th
l
:
c
b

a =
_
c if a b
0 otherwise
(13b)
The th
u
operation can be realized as shown in Fig. 4
[12]. A similar topology is proposed in [9]. However,
the topologyproposedinthis studyprovides full control
over output current. The lower threshold operation, th
l
,
can be realized with a and b interchanged in the circuit
of th
u
.
The transition region, I = 2.5 A,can be adjusted
by changing the W/L ratio of the transistor N4. The
transistors N5, N6 and N7 should be also adjusted ac-
cordingly to satisfy s3 (1.5)

r +0.5 > s2 > 1.

The parameter 0.1 is for the adjustment purpose
in order to account for transistor mismatches, modu-
lations in transistor model and their effects in current
level degradation.
4. Design of Gate Circuits
(1) Min Gate: The z = min(x, y) operation can be
realized using Eq. (12a), as shown in Fig. 5, where
No represents the input circuit of the following
gate.
(2) Max Gate: Using Eq. (12b), the operation, z =
max(x, y), can be constructed as shown in Fig. 6.
194 Temel and Morgul
Fig. 3. Truncated difference: (a) DC characteristics, (b) symbol, and (c) circuit.
Fig. 4. (a) Upper-threshold DCcharacteristics, (b) two-output block diagram, (c) circuit diagramand (d) minimumfeature size transistor aspect
ratios.
Fig. 5. (a) z = min(x, y) DC characteristics, (b) block diagram, (c) circuit diagram and (d) minimum feature size transistor aspect ratios.
Implementation of Multi-Valued Logic Gates 195
Fig. 6. (a) z = max(x, y) DC characteristics, (b) block diagram, (c) circuit diagram and (d) minimum feature size transistor aspect ratios.
Fig. 7. Literal and complementary literal structure.
(3) Inverter: An MVL inverter can be designed as a
truncated difference (Fig. 3), in which y is replaced
with x and x is replaced with (r 1)I
b
.
(4) Literals: A k
l
-valued literal and k
c
-valued com-
plementary literal can be simultaneously produced
from the same circuitry [12]. The circuit basically
consists of two cascaded lower-threshold circuits
as shown in Fig. 7.
The constants are normalized to base current I
b
.
The auxiliary variables, a

= a 0.5, b

= b +0.5
and r

= r 0.5 correspond to logic levels of hard-

ware threshold levels for a, b andr, respectively, as
dened in Eq. (1). They can be generated as shown
in Fig. 8.
(5) Cyclic Gates: It can be shown that
x
y

= (x + y)(x + y)

r
r

(14)
Using the denition of r

above, y-CWCoperation
can be realized as shown in Fig. 9.
Fig. 8. Generating auxiliary parameters for literal gates.
The y-cyclic counter clock-wise, y-CCWC, operation
can easily be realized by replacing y with r y. The re-
peated quantities can be reproduced with proper mirror
structures.
Of above gates, the layouts of min and max gates are
given in Appendix B, while the layout of cyclic gate is
given in Appendix C associated with an application.
5. Simulation of Basic Gates
Designed gates with indicated transistor feature sizes,
Figs. 59, are simulated with input waveforms shown
in Fig. 10. Gate simulation results are given in
Figs. 1114.
6. Comparison with Previous Designs
Due to lack of a proper current-mode switch topol-
ogy, most Postian MVL, [17] studies prefer exploiting
196 Temel and Morgul
Fig. 9. (a) y-CWC operation DC characteristics, (b) block diagram, (c) circuit diagram and (d) minimum feature size transistor aspect ratios.
Fig. 10. Input waveforms for simulations.




0 125 250 375 500 625 750 875 1000
0
20
40
60
80
time, nsec.
o
u
t
p
u
t
,

u
A
min(x,y)
Fig. 11. Simulation results of min(x, y) gate.
the voltage mode-binary logic circuits [1, 7], shown in
Fig. 15, which can be named as hybrid or switched-
current mode approach. Although hybrid-mode MVL
design is studied in [18] with regard to DC behavior,
no condition is put forward on optimumoperating size.
In Fig. 15, N
i
is the input current mirror, x

is
the reected input current, I
o
is the desired output



0 125 250 375 500 625 750 875 1000
0
20
40
60
80
time, nsec.
o
u
t
p
u
t
,

u
A
max(x,y)
Fig. 12. Simulation results of max(x, y) gate.
Fig. 13. Simulation results of: (a) 5
3
x
5
and (b) 3
3
x
5
.
Implementation of Multi-Valued Logic Gates 197



0 125 250 375 500 625 750 875 1000
0
20
40
60
80
time, nsec.
o
u
t
p
u
t
,

u
A
x
y
Fig. 14. Simulation results of y-CWC gate.
Fig. 15. General structure of switchedcurrent-mode, MVLdesigns.
current, M
o
is the input transistor of the following
gate, M
sw
is the NMOS or PMOS switching transis-
tor, M
k
is the current source supplying the current I
o
.
The binary logic level signal at node D is a function of
voltage at node C and it is obtained with conventional
voltage mode logic gates. For proper design, neglect-
ing the required scaling within the voltage-mode block,
the output block, which may be the input block of the
following gate, has to satisfy certain sizing conditions.
M
sw
conducts if VDD V
gs,o
V
th,sw
, where sub-
scripts o and sw denote the transistors M
o
and
M
sw
, respectively. Assuming long-channel transistors
are in use, for a given output transistor size, the upper
bound for output current is given by
I
o
<
[VDD (VTO
o
+ V
th,sw
)]
2
KP
o
2
_
L
W
_
o
(15)
where VTO
o
, is the zero-bias threshold voltage of M
o
and V
th,sw
is the threshold voltage of M
sw
and KP is the
process transconductance of the transistor considered.
The upper bound of output current, or the achievable
radix is determined by M
sw
, which has to operate in
triode-mode. Therefore, it can be shown that
_
W
L
_
sw

2I
o
_
VDD
_
2I
o
(W/L)
o
KP
o
(VTO
o
+ V
th,sw
)
_
2
KP
sw
(16)
As can be seen from Eq. (16), dimensions of M
sw
is lower bounded and increases severely as the out-
put current approaches the desired output current given
by Eq. (15). Moreover, the situation becomes worse
with body-bias effect. The fact, that M
k
has to operate
in saturation as a current source, puts forward larger
(W/L)
sw
values. Hence, the output block area, which
is directly proportional to
o
and
sw
, becomes very
large, where = KP(W/L) is the transistor conduc-
tance.
Aminimumarea of the output block is achieved with
a resized M
o
by a constant factor (1 + ) for a given
radix, with being a scale parameter. Therefore, input
block of the succeeding gate has to be scaled up with
the same factor, which degrades the performance of
its input current comparator. It can be shown that =
3.1 if M
sw
is not body-biased and independent of the
parameters used. If M
sw
is body-biased, = 1.8 is
found, depending on the parameters used. With scaled-
up output transistor, (W/L)
sw
can be calculated from
_
W
L
_
sw

KP
o
(W/L)
o
(1 +)
_
1
_
1
1+
_
2
KP
sw
(17)
Therefore, there exists an asymmetry between input
and output blocks. Due to asymmetric input and output
stages, each gate, and particularly voltage-mode block,
would have to operate with larger capacitive loads. The
output capacitance driven by the voltage-mode block
is further increases due to cascode structure formed
by M
sw
and M
o
. If operation is performed with body-
biased M
sw
, it can be shown that there is a two bounded
operation range, which may not allow for higher-radix
operation.
In order to illustrate radix-limitation, the literal
(5
3
x
5
) has been designed using the circuit given in
[7] for both body-biased and no body-biased M
sw
, in
which input quantities sink while the output sources.
Using the MOS model in [19], transistor dimen-
sions can be estimated for short-channel, small devices.
198 Temel and Morgul
Assuming similar parameter descriptions and linear re-
lationship between V
GS
and I
D
of a short-channel MOS
transistor, it can be shown that
I
o
z
o
[VDD (V
th,o
+ V
th,sw
)] (18)
and switch transistor dimension is given by
_
W
L
_
sw,eff

I
o
K
sw
v
sat,sw
C
ox,sw
L
sw,eff
[VDD (V
th,o
+ V
th,sw
)] z
o
I
o
(19)
In Eqs. (18) and (19), z = Kv
sat
C
ox
W
eff
, (A/V)
with K <1 being a constant accounting for the short-
channel effects for the transistor considered, [19]. For a
saturated transistor, it is simply taken as 0.75. The pa-
rameter v
sat
is the saturation velocity, which is 8
10
4
m/sec and 6.5 10
4
m/sec for electrons and
holes, respectively. W
eff
=W 2WD, L
eff
=L 2LD
where WD and LD are the spice parameters indi-
cating the overlap region width. Solving Eqs. (15)
and (16) with both body-biased and no body-
biased M
sw
shows that, for I
o
= 50 A it is
necessary to set (W/L)
sw,nobody-bias
= 20.5 and
(W/L)
sw, body-bias
= 454 if (W/L)
o
= 1.5. If
(W/L)
o
= 5, (W/L)
sw,body-bias
= 13 satises the equa-
tions.
In Fig. 16, the simulation results show that it is not
possible to obtain the required 50 A current if the
output load transistors W/L ratio, (W/L)
O
, is less
than 5 for body biased transistor and 2.5 for no body
biased transistor. In the gure, > implies no varia-
tion is observed despite further increases in considered
transistors dimensions. Table 1 summarizes HSPice
simulation results of designs given in this study and
[7], respectively.
The DC performance of proposed gates can be stud-
ied with a typical circuit in Fig. 17, where M
m
repre-
sents the output transistor of the gate andM
O
represents
the input circuit of the next gate.
It can be shown that the maximum current range for
which the circuit with long-channel transistors func-
tions linearly may be given by
I
o
= x iff x
_

o
2
__
VDD VTO
o
1 +

o
/
m
_
2
(20)
Table 1. Comparison of simulation results of proposed circuits in
this study (New), and switched current-mode designs with body-bias
(no body-bias) in Ref. [7], for minimum feature size, i.e., (W/L) =
1.5/1.
Trans. Av. del. Av. pow.
Gate count (ns) diss. (mW)
Min New 8 1.6 0.25
Ref. [7] 8 1.6 0.25
Max New 7 1.4 0.23
Ref. [7] NA NA NA
CWC, x
3

New 19 1.8 0.81

Ref. [7] 23 4.2 (3.1) 0.65 (0.75)
Literal, 5
3
x
5
New 23 4.3 0.50
Ref. [7] 21 7.1 (6.2) 0.42 (0.46)
Compl. Liter. 3
3
x
5
New 19 4.1 0.43
Ref. [7] 21 6.8 (6.3) 0.42 (0.40)
NA: Not available.
Fig. 16. HSPice simulation results for switched current-mode re-
alization of literal 5
3
x
5
: (a) with body-biased M
sw
and (b) no
body-biased M
sw
.
Again using the small transistor model [19], it can be
shown that
I
o
= x iff x
1

_
VDD VTO
o
1/z
d
+1/z
o
_
(21)
Equations (20) and (21) are investigated for (W/L)
o
=
1.5 and (W/L)
d
= (W/L)
m
= 5.5, i.e., = 1,
Implementation of Multi-Valued Logic Gates 199
Fig. 17. The basic circuit to determine DC characteristics of
designed gates.
yielding maximum current values as x
,max
= 73 and
86 A respectively.
7. Analog Design Constraints
on Operating Radix
Linear current range describedinthe previous sectionis
not the only parameter for choosing the operating radix.
The step size between logic levels, which is limited by
the noise margin, must also be considered.
The output current of the mirror circuit in Fig. 17
is constituted with random and nominal components.
The former is attributed to random design parameter
variations, and physical noise current generated in the
devices [20, 21]. Denoting the output current variation
by x

, which can be taken as Gaussian, it sufces to

take |x

| |3
x
| where
x
is the standard deviation
of x

. Therefore, for unity transfer ratio, = 1,

r
max

x
max
6
x,max
(22)
where x
max
is the maximum linear current range of the
mirror circuit, while
x,max
is the standard deviation
of the output current at x = x
max
.
For transistor dimensions of (W/L)
n
= 1.5/1 and
(W/L)
p
= 5.5/1, the circuit in Fig. 17 is simu-
lated using Monte-Carlo analysis of 100 iterations.
Gaussian standard deviations are
W,L/WL
= 5%
and
VTO
= 50 mV (Fig. 18). Table 2 illustrates out-
put current standard deviation with respect to different
process sizes at x
max
.
The chosen feature sizes, (W/L)
n
= 1.5/1, (W/L)
p
= 5.5/1, satisfy threshold requirement for eight-level
Table 2. Monte-Carlo analysis results of the model cir-
cuit versus process sizes.
Process (W/L)
n
, (W/L)
p
% (
x/x
) |x
max
|
1.5/1, 5.5/1 2.5 4.7 A
2.25/1.5, 8/1.5 1.7 3.5 A
3.5/2, 11/2 1.4 2.4 A
Fig. 18. Transistor mismatch characteristics of the current-mirror
of Fig. 17.
logic design, while larger feature size may be preferred
to increase the noise margins.
A quantitative noise margin measure of gates can
be expressed in terms of the number of the considered
identical gates that can be directly cascaded without
loosing a given logic level description. HSPice simula-
tionresults of maxandmingates are showninFig. 19. It
is seen that maximum4 identical gates can be cascaded
for these feature sizes. Regeneration circuits must be
used if more gates are to be cascaded.
8. Designs with Proposed Circuits
Consider a radix-8, r = 8, 2-to-1multiplexer function,
f (x, y) =
0
x
3
y
4
x
7
y = y
0
x
3
+ y
0
x
3
=
y
3

x + x

7y
3
(23)
=
_
y if 0 x 3
7 y otherwise
Due to disjoint product terms, the max operator is re-
placed with ordinary sum circuit.
As stated previously, most symmetric functions can
be designed using cyclic gates. A useful application
would be a higher radix full-adder. Using Eq. (7)
and its corresponding circuit, a higher-radix full-adder
can be designed as shown in Fig. 20 where (W/L)
200 Temel and Morgul
Fig. 19. Cascaded stage behaviours of min and max gates.
Fig. 20. A higher-radix current-mode full adder circuit.
of M9 is 1.5/1. Taking normalized quantities, the
sum, S, and the carry output, C, can be obtained as
follows:
S = x
y+C
in

=
_
x + y +C
in
iff x + y +C
in
< r

x + y +C
in
r otherwise
(24)
C =
_
0 iff x + y +C
in
< r

1 otherwise
where C
in
is the input carry and r

= r 0.5 as dened
previously. The circuit is similar to that in [10], how-
ever, the operating radix can be controlled externally
with our design. HSPice transient simulation results
of the radix-8 multiplexer and full-adder circuits are
shown in Fig. 21.
Since 3 bits in conventional binary logic can rep-
resent one digit in radix-8, performance comparison
is given between 3-bit binary adder and 1 digit MVL
adder, designed with the same parameters. Two well-
known adder schemes, the ripple-carry, RCA, and
carry-look-ahead, CLA, binary adders, described in
[22], are constructed using the same parameter set and
loaded with a capacitive load of 70 fF. In order to eval-
uate a worst-case performance, a large number of ran-
dom input vectors are applied to binary adders. In both
design styles, delays and power dissipation vary with
Table 3. Performance comparison of new MVL-based and binary
adders (T = time duration of one step).
Av. power diss. (mW)
Adder
Trans.
count
Max.
delay
(ns) T = 40 ns T = 10 ns
Area
(m)
2
MVL, radix-8 21 3.2 0.95 1.05 87 24
3-bit RCA 84 6.5 0.14 0.52 160 85
3-bit CLA 108 7.3 0.23 0.93 175 93
Implementation of Multi-Valued Logic Gates 201
Fig. 21. (a) Input waveforms and simulation results of, (b) Radix-8
multiplexer function and (c) Radix-8 full-adder circuit.
Appendix A: Mietecs ES2 0.7 m HSPice parameters
. MODEL Nchan NMOS LEVEL=6
+ LD=1E07 XL=0.04e6 XW=0.9e6 WD=0.45e6 TOX=1.5E08 BETA=97e6 NSUB=1.965E+16
+ XJ=0.25e6 VTO=0.815 VBO=1.50 GAMMA=0.764 LGAMMA=0.705 SCM=1.733 VSH=0.65
+ NWE=193.7E9 NWM=0.197 UFDS=99.5E3 VFDS=0.2 FDS=84E3 MOB=2 F1=372E+3
+ F2=0.2 UTRA=0.563 LAMBDA=10.63E6 ECRIT=87E+3 CLM=3 MCL=4.63 KCL=1.08
+ MAL=0.295 KA=0.974 MBL=0.555 KU=1.4052 NU=1 NFS=5E+11 NSS=0.0 WIC=2.0
+ WEX=17 TLEV=1 BEX=1.5 TCV=2E3 RSH=65 JS=2E6 ACM=2 CJ=503E6 MJ=0.43
+ CJSW=109E12 MJSW=0.43 PB=0.675 CGDO=200E12 CGSO=200E12

. MODEL Pchan PMOS LEVEL = 6

+ LD=1E07 XL=0.042e6 XW=0.9e6 WD=0.45e6 TOX=1.5E08 BETA=30.2e6 NSUB=2.5E+16
+ XJ=0.5e6 VTO=1 VBO=1.50 GAMMA=0.587 LGAMMA=0.653 SCM=1.01 VSH=0.116
+ NWE=56.1E9 NWM=0.442 UFDS=0.331 VFDS=0.5 FDS=0.286 MOB=2 F1=483E+3
+ F2=0.32 UTRA=0.197 LAMBDA=14E6 ECRIT=486E+3 CLM=3 MCL=6.97 KCL=41.9E3
+ MAL=0.0 KA=1.082 MBL=0.803 KU=9.871 NU=1 NFS=6E+11 NSS=0.0 WIC=2.0 WEX=14.3
+ TLEV=1 BEX=1.0 TCV=1.52E3 RSH=80 JS=20E6 ACM=2 CJ=776E6 MJ=0.51
+ CJSW=572E12 MJSW=0.51 PB=0.7 CGDO=200E12 CGSO=200E12
input values. (Layouts of binary-RCAand radix-8 full-
adder are given in Appendix C). The simulation results
are summarized in Table 3. It is observed that, when
the input data speeds up four times, the power dissipa-
tion of MVL design remains nearly the same (1 mW),
while the power dissipation increases severely for bi-
nary adders, as expected.
9. Conclusions
In this study we introduced a complete set of multi-
valued logic gates and a novel current-mode threshold
circuit. Based on this circuit, MVL literal and cyclic
gates are constructed. Designs are technology indepen-
dent, hence allowing different technology realizations
in the same simplicity. As an application, a radix-8
full-adder circuit is designed with a cyclic gate. The
full-adder circuit exhibits faster dynamic behavior with
much less chip area compared to its binary counter-
parts. The disadvantages of current mode multi-valued
logic circuits are the larger static power dissipation
and reduced noise margins for high radices. The linear
transferring capability of a current-mirror, as a typical
stage of MVL gate circuit, for long and short channel
devices is investigated. The achievable maximumradix
of MVL circuits is calculated in terms of device sizes
and statistical mismatching properties of technology
parameters.
202 Temel and Morgul
Appendix B: Layouts of Min and Max Gates
Appendix C: Layouts of 3-Bit Binary-RCA and MVL Radix-8 Adders
Implementation of Multi-Valued Logic Gates 203
Acknowledgment
This work is sponsored by Bo gazi ci University Re-
search Fund (01HA201).
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Turgay Temel received the B.S., M.S. and Ph.D.
degrees, all in Electrical and Electronic Engineer-
ing, in 1990, from Uludag University, 1996, from
University of Newcastle Upon Tyne, UK, and 2002
from Bogazici University, respectively. He is cur-
rently a postdoctoral research fellow in School of In-
formatics in University of Edinburgh, taking a part
in CIRCE project, a EU funded biomimetic robotics
design.
His research interests include mixed signal and ana-
log design, computer aided design, fault tolerant circuit
design, electrical drives, signal processing, hardware
and software development for microprocessor and DSP
based system designs.
204 Temel and Morgul
Avni Morgul received the B.S.+M.S. and Ph.D. de-
grees in Electrical and Electronics Engineering from
Technical University of Istanbul, in 1970 and 1981 re-
spectively. He joined University of Edinburgh for one
year as a Post Doctoral Research Fellow in 1982.
He has been with Electrical & Electronics Depart-
ment of Bogazici University since 1983. Professor
Morguls research is concentrated on high frequency,
microwave, and satellite communication electronics,
analog IC design, electro-magnetic compatibility and
biologic effects of EM signals. He is part time con-
sulting some companies manufacturing Satellite TV
receivers and RF equipment. He is a member of In-
stitute of Electrical and Electronics Engineers (IEEE),
Chamber of Turkish Electrical Engineers (EMO) and
Turkish Amateur Radio Association (TRAC).