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UNIVERSITY OF DAR ES SALAAM



DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION
ENGINEERING

COURSE TITLE: EXPERIMENTS IN DIGITAL ELECTRONICS
COURSE CODE: ES222
COURSE WEIGHT: 2 Units
INSTRUCTOR: Mr. Baraka Maiseli
LABORATORY ENGINEER: Ms. Aloyce Agripina
TUTORIAL ASSISTANT: Mr. Nassor Ally

VENUE: Physics Building, PHLAB3
TIME TABLE: Wednesday (08:00 HRS-10:55 HRS)
Friday (08:00 HRS-10:55 HRS)






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Introduction
The world we live in has been developing every day in the field of Science and Technology.
We have moved from the Analog world to the Digital world. In the digital world, one deals
with ON and OFF signals. The ON signal is described as logic state HIGH while the OFF signal
is described as logic state LOW. Various digital components manufactured from different
companies exist. These components are capable to analyze and process digital information.
Examples of digital components are counters, encoders, seven segment displays, registers,
logic gates and so on. In this course, we are going to explore the features and functionalities
of common and frequently used digital components.
Course Objectives
The following are specific objectives of the course:
a) Familiarization of digital components
b) Realization of digital systems in a block form
c) Design and implementation of digital circuits and systems
d) Realization of practical application examples of digital circuits and systems
Apparatus and Tools
You will be provided with the following materials and tools during practical sessions: Power
Supply Unit (PSU), Function Generator (FGEN), Oscilloscope (SCOPE), connecting wires,
jumpers, digital components and prototyping board. On your side, you are required to have
a Digital Multimeter (DMM), electronics toolbox with all necessary tools and any simulation
software (Multism, Proteus or Circuit Maker) installed in your laptop.
Mode of Course Delivery
Due to limited number of laboratory facilities you will be organized in groups of four
students to share the available laboratory resources. For a given laboratory session, all
groups will be given the same experimental problem. Where necessary a brief theory of a
given laboratory work will be provided. It is, however, strongly recommended to revise the
concepts of the courses Digital Electronics I and II.
Course Evaluation
Each student will be evaluated independently. The marks will be given on the spot at the
time you submit your complete design to the course instructor. Upon submission of the
design a few oral questions will be asked to each student in a group to measure
understanding and involvement capabilities towards the given design problem. You are not
required to write a lengthy laboratory report. What is needed is to let your complete
designed circuit along with answers to the given questions checked by the course instructor
or laboratory assistant or laboratory engineer and marks will be awarded at that instant. At
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the end of the course an average for all marks you acquired during practical sessions will be
taken. The criteria which will be used during evaluation process are:
a) Quality of the design
b) Involvement and participation of an individual in a group
c) Correctness of the answers to the given problems
d) Attitude and commitment towards practical work
Course Contents
1. Laboratory Assignment One: Digital Timing Circuits and Clock Generators
(a) LM555 Timer Circuits
Monostable Operation Mode
Astable Operation Mode
(b) NOT Gate Square Wave Generator
(c) NAND Gate Square Wave Generator
2. Laboratory Assignment Two: Operation and Functions of Digital Components
(a) Seven Segment Display
(b) BCD to Seven Segment Decoder
(c) Encoder
(d) Decoder
(e) Counter
(f) Shift Registers
(g) Multiplexer
(h) Demultiplexer
3. Laboratory Assignment Three: Interfacing Digital Components and Systems
(a) Encoder, Decoder and Seven Segment
(b) Counter and Seven Segment
(c) PISO shift register and SIPO shift register
(d) Multiplexer and Demultiplexer
4. Laboratory Assignment Four: Design and Implementation of Practical Digital Circuits
and Systems





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LABORATORY ASSIGNMENT ONE
DIGITAL TIMING CIRCUITS AND CLOCK GENERATORS

(A) LM555 TIMER CIRCUITS
The LM555 timer is a popular IC that has been used over years for various applications. It
suit both hobby and industrial projects. With LM555 timer one can ideally create any timing
circuit. In many occasions, this chip is used to control timing of digital systems. Typical
applications of this chip are:
Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation and
Linear Ramp Generation
Examples of time dependent applications which can benefit from this chip are elevator
control systems, production line systems, police siren systems and traffic light control
systems. The LM556 is a dual LM555 timing circuit in a sense that it contains two LM555
timers contained in a single package. In this laboratory assignment, you will be introduced
to the general features of an LM555/556 chip and its applications. Figure A1 illustrates the
pinout of an LM555 timer and table A1 shows the function each pin serves.

Figure A1: The 555 Timer Pinout
Pin Name Function
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
5

No.
1 Ground
(GND)
Reference Voltage
2 Trigger (TR) Triggers the timer to start the timing sequence. If this pin goes
LOW the output Q goes HIGH and remains at this state until the
timer times out. The triggering circuitry of the timer is activated
when the voltage at the TR pin falls below 1/3 of the supply
voltage V
CC
.
3 Output (Q) Drives the external circuitry. It is driven LOW when either
Threshold (TH) pin is taken HIGH or Reset (R) pin is taken LOW.
4 Reset (R) Resets the system. It drives the output Q LOW regardless of the
state of the circuit. When not used this pin is connected to V
CC
.
5 Control
Voltage
(CV)
Used in a Voltage-Controlled mode when a user wants to control
the width of the output pulse irrespective of the R
1
C
1
timing
network. If this pin is not used it is recommended to connect to
ground through a bypass ceramic capacitor of about 0.01F to
give the circuit immunity against noise. In the absence of a
capacitor we may experience false triggering.
6 Threshold
(TH)
Drives the output LOW when the voltage applied to it just
exceeds 2/3 of the supply voltage V
CC
.
7 Discharge
(DC)
Discharges the timing capacitor C
1
to ground when the output Q
goes LOW.
8 Supply
Voltage
(V
CC
)
Power Supply Voltage
Table A1: Functions of Pins of LM555 Timer
Monostable (Single-Shot) Operation of LM555 Timer
The LM555 timer can be configured to produce a pulse of a fixed duration at its output. This
is called a Monostable operation because the output has a single stable state, HIGH or LOW.
In this mode, the output goes HIGH for a predefined amount of time when the Trigger pin is
pulled LOW. The state of the output pin can be interrupted at any stage by issuing a LOW
signal on the reset pin. Figure A2 illustrates Monostable operation of an LM555 timer. The
timing components of the system are resistor R1 and capacitor C1. If the TR pin is pulled
LOW the output Q goes HIGH for a duration of T=1.1R
1
C
1
. In this circuit, R
1
=47k and
C
1
=100F. Thus, the duration for the output of the timer to stay in the HIGH state when the
trigger pin is pulled LOW is 1.1x47x1000x100x0.000001 5seconds. Notice that the
minimum value of R
1
should be 1K to prevent much current to flow into the TR pin of the
chip and hence damaging its internal circuitry. The maximum value of R should be 1M so
that enough current can flow into the TR pin of the chip and there is current to allow for the
electrolytic capacitors leakage current. The minimum value of C
1
should be 100pF to avoid
the timing equation being too far off. The maximum value of C
1
should be 1000F because a
bigger capacitor will discharge too much current through the TR pin of the chip. Using these
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minimum and maximum conditions, we can achieve minimum timing duration of 0.1s and
maximum timing duration of 1000s.

Figure A2: Monostable Operation of an LM555 timer
From the given circuit in figure B4, the decoupling (bypass) capacitor C3 decouples the
supply voltage V
CC
. This prevents unwanted ripple signals from the supply to interfere the
functioning of circuit internal parts. If this capacitor is not included we may experience false
triggering of the circuit while a button connected to TR pin of the timer is not pressed.
Questions
(a) Mount the circuit on the prototyping board and test its functionality.
(b) Redesign the circuit to provide a timing sequence of your choice.
(c) Do you think the circuit is ideal for high precision time critical applications? Explain.
(d) Suggest two application examples which can benefit from the design.
Astable Operation of LM555 Timer
This is a free running operation mode in which the timer output does not stay in a single stable state.
The output toggles between LOW and HIGH logic states; resulting into formation of continuous train
of square or rectangular pulses. Figure A3 illustrates an LM555 timer configured to operate in
Astable mode. The figure shows a slightly modified copy of a Monostable circuit presented in figure
A2. In this figure, the Threshold (TR) terminal is connected to the Trigger (TR) terminal to allow for
an automatic self-retriggering of the device.
When the circuit is just powered, the capacitor C1 starts to charge up through the resistors R
1
and
R
2
. When the voltage V
C
across the terminals of the capacitor reaches 2/3 of the supply voltage V
CC
,
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
R2
10k
R1
47k
C1
100uF
C2
0.01uF
R4
330R
R3
10k
D1
C3
47uF
+5V TO +15V
5seconds
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hence the voltage at the terminals TR and TH, the circuit becomes triggered. Consequently, the
output Q toggles and becomes HIGH. The HIGH state of the output will be maintained for a period of
T
1
=0.693(R
1
+R
2
)C after which it becomes LOW. The LOW state of the output Q enables the internal
discharge transistor of the timer hence causing the capacitor C1 to start discharging. The discharging
process takes a period of T
2
=0.693R
2
C
1
. The process of discharging is done through the resistor R
2

only because the discharge pin (DC) of the timer has low impedance to ground during LOW states of
the output signal. When the capacitor C
1
discharges to 1/3 of the supply voltage V
CC
the discharge
transistor in the timer becomes disabled and the capacitor starts to charge again. This process
repeats continuously, leading to generation of rectangular train of pulses at the output Q of the
timer.

Figure A3: Astable Operation of LM555 Timer
Thus, the period of a signal is T=T
1
+T
2
=0.693(R
1
+R
2
)C
1
+0.693R
2
C
1
=0.693(R
1
+2R
2
)C
1
and the frequency
of a signal is
2 1
2
44 1 1
R R
.
T
f

.
It is interesting also to determine the duty cycle (also called mark-to-space) of the output signal. The
term duty cycle refers to the percentage of time in which a system (LM555 timer in this case) spends
in the active state measured as a fraction of the total time under consideration. It is given by the
formula
OFF ON
ON
T T
T
D

, where T
ON
is a time spent during HIGH or ON state and T
OFF
is the time spent
during the LOW or OFF state. Figure A4 shows a rectangular signal from which a duty cycle can be
deduced. Recall that T
ON
=0.693(R
1
+R
2
)C
1
and T
OFF
=0.693R
2
C
1
. Thus, the duty cycle formula reduces to
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
+5V To +15V
R2
C1 C2
0.01uF
R1
T1
T2
Vc
8

2 1
2 1
1 2 1
1 2 1
2 2 693 0
693 0
R R
R R
C ) R R ( .
C ) R R ( .
T T
T
D
OFF ON
ON

. Using this formula, the output duty cycle can be


varied between 50% and 100%. When R
2
is very small compared to R
1
the duty cycle is 100% and
when R
2
is much larger than R
1
the duty cycle is 50%. The problem with this circuit is that the duty
cycle cannot be regulated to below 50% because the T
ON
cannot be shorter that the T
OFF
. From the
given formulae, T
ON
=0.693(R
1
+R
2
)C
1
must always be greater or equal to T
OFF
=0.693R
2
C
1
. One way to
overcome this challenge is to connect a diode in parallel with the resistor R
2
. If this is done, the
capacitor C
1
charges through R
1
only and discharges as usual through R
2
. Thus, T
ON
=0.693R
1
C
1
and
T
OFF
=0.693R
2
C
1
.
Therefore, the duty cycle becomes:

2 1
1
1 2 1 1
1 1
693 0 693 0
693 0
R R
R
C R . C R .
C R .
T T
T
D
OFF ON
ON

.
With this formula, the duty cycle can be varied from 0% to 100%. Figure A5 illustrates an LM555
timer used to dim an array of five LEDs by changing their duty cycles through a variable resistor RV1.
Notice from the figure that diode D1 in parallel with resistor R
2
is added to allow flexibility in varying
the duty cycle from 0% to 100%.

Figure A4: Duty Cycle of a Rectangular Signal
Use figure A5 to attempt the following laboratory activity.
Questions
(a) Mount the circuit on a prototyping board
(b) Vary a variable resistor RV1 from minimum to its maximum value. What changes to you
observe on the brightness of LEDs? Explain your observation.
(c) Connect one channel of the oscilloscope to the output Q of the timer. While varying the
variable resistor RV1 from minimum to maximum value, observe the nature of a signal on
the screen of the oscilloscope for different values of RV1. What changes do you see? Explain
your observation.
T
ON
T
OFF
T
ON
=T
1,
T
OFF
=T
2


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(d) What technical name is given to the phenomenon observed in (c) above? What does it
mean?
(e) Suggest one possible typical application of the circuit.

Figure A5: Varying LED Brightness Using LM555 Timer
One of a very nice and simple to build project using the LM555 timer configured in Astable mode is
the Electronic Metronome. A Metronome is an electronic device used to mark time in pieces of
music by producing a regular and recurring musical beat or click. Using LM555 timer in Astable
mode, a simple metronome can be made by adjusting the output frequency to generate different
tempo or beats per minute. If the output of a timer is set to a tempo of 60 beats per minute, for
example, it means one bit occurs every one second. In electronics terms, this is equivalent to 1Hz.
Table A2 illustrates different frequencies required for a metronome circuit shown in figure A6. Table
A3 illustrates different values of the variable resistor RV1 for different corresponding frequencies.
Musical Definition Rate Beats per Minute Cycle Time (T) Frequency
Larghetto Very Slow 60 1Sec 1.0 Hz
Andante Slow 90 666ms 1.5Hz
Moderato Medium 120 500ms 2.0Hz
Allegro Fast 150 400ms 2.5Hz
Presto Very Fast 180 333ms 3.0Hz
Table A2: Metronome Frequency Table
Position of RV1 Beats per Minute
71.6K 60
47.5K 90
35.6K 120
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
+5V To +15V
R2
10k
C1
4.7uF
C2
0.01uF
R3
330R
R4
330R
R5
330R
R6
330R
R7
330R
5
0
%
RV1
22k
D1
1N4148
10

28.4K 150
23.5K 180
Figure A6: Beats per Second for Different Values of RV1


Figure A6: Astable LM555 Electronic Metronome
Use the circuit shown in figure A6 to attempt the following questions.
Questions
(a) Build the circuit on a prototyping board
(b) Vary a variable resistor RV1 from minimum to maximum. What changes to you hear on the
nature and pitch of sound produced from a speaker? Explain the cause of the changes
observed.
(c) What can be one possible application of the circuit?
Another interesting project which uses LM555 timer configured in Astable mode is a Voltage
Controlled Oscillator (VCO). The VCO (also called a Voltage to Frequency converter) is an oscillator
whose output frequency depends on the variation of the input voltage. That is to say, the frequency
of the output waveform changes in response to the change of the input voltage. Recall the internal
circuitry of the 555 timer. The inverting input of the upper comparator is directly connected to pin 5
(Control Voltage or CV). This pin is used to control the threshold and triggering levels. When not
used the pin is usually connected to ground through a small capacitor of 0.01F or 10nF. In this case,
the reference voltage at the inverting terminal of the upper comparator is internally set to
CC
V
3
2

through a potential divider network. However, in the VCO applications this pin is used to acquire
varying voltages from the voltage source or some other device. If the voltage at pin 5 is increased
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
+5V To +15V
R2
1k
C1
10uF
C2
0.01uF
1
0
%
RV1
100k
LS1
SPEAKER
C3
10uF
T
11

the charging capacitor takes longer to charge and discharge. Consequently, the frequency of the
output waveform is decreased. Conversely, if the voltage at pin 5 is decreased the charging capacitor
takes shorter to charge and discharge, resulting into output waveform of low frequency. Figure A7
illustrates an LM555 timer configured to operate as a voltage-controlled oscillator. From the
illustration, a pot RV2 connected to CV terminal of the device is used to vary voltages from 0V to V
CC
.
The voltage across the timing capacitor C1 varies from
CONTROL
V
2
1
to V
CONTROL
, where V
CONTROL
stands
for the voltage going to CV pin set by RV2 pot. The diodes D1 and D2 prevents a transistor Q1 from
being damaged due to back e.m.f generated when the device is switched ON and OFF continuously.
The driving transistor Q1 is used to boost the current and voltage from the output pin Q of the
device, hence making a speaker to produce louder sound. In many occasions, a power transistor
such as TIP41A or 2N3055 is connected at the output Q to amplify the sound signal produced by a
loudspeaker.

Figure A6: Voltage Controlled Oscillator Using LM555 Timer
Questions
(a) Mount the circuit presented in figure A6 on the prototyping board
(b) What changes do you realize for the pitch of sound produced on the loudspeaker when pot
RV2 is varied from minimum to maximum?
(c) Clearly explain the causes for the changes of sound pitch observed in (b) above
The circuit presented in figure A6 can be extended to make a Police Siren (Dee-Dah or Warble-Tone
Alarm). Figure A7 illustrates a circuit which can produce a Dee-Dah sound effect similar to that
observed in a Police Siren system. From the figure, the output Q of the first LM555 timer on the left
side is fed to Control Voltage CV input pin of the second LM555 timer through a resistor R2. The first
timer is configured to produce a low frequency note while the second timer is configured to produce
+5V To +15V
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
R2
1k
C1
10uF
5
4
%
RV1
100k
5
1
%
RV2
10k
C2
47uF
R1
1.2k
Q1
BC547
D1
1N4001
D2
1N4001
LS1
SPEAKER
12

a high frequency note. The output Q of the first timer frequency modulates the output Q of the
second timer by varying the voltage at its Control Voltage pin.

Figure A7: Police Siren Using LM555 Timer
Questions
(a) Mount the circuit on a prototyping board
(b) While varying the values of RV1 and RV2 interchangeably from minimum to maximum,
observe the changes of the sound pitch produced at the loudspeaker. Keep fixed the values
of RV1 and RV2 when you hear sound from a loudspeaker similar to that of a police siren.
(c) Briefly explain the principle of operation of the device.









R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
+5V To +15V
C1
10uF
C2
0.01uF
LS1
SPEAKER
R1
68k
D1
1N4148
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
C3
100nF
R3
8.2k
D2
1N4148
R2
10k
1
3
%
RV1
68k
3
6
%
RV2
8.2k
Q1
BD139
R4
1.2k
D3
1N4148
D4
1N4148
C4
47uF
13



(B) NOT Gate Square Wave Generator
A NOT gate can be briefly defined as a logic circuit which is capable to invert the input logic
state. It has one output and only accepts a single input. The output of a NOT gate is logic state
HIGH if its input is logic state LOW and logic state LOW if its input is logic state HIGH.

In one of its applications, a NOT gate can be configured to operate as a Square Wave Generator.
In this configuration, a NOT gate operates as an Astable multivibrator or oscillator because it
produces at its output continuous train of rectangular pulses of a given frequency and duty
cycle. Figure B1 illustrates a NOT gate configured in Astable mode.

Figure B1: NOT Gate Astable Multivibrator

From the illustration provided in figure B1, assume initially the input of gate N1 is logic HIGH and
consequently its output is logic state LOW. The capacitor C1 starts charging through the resistor
R1 and the input of the first NOT gate N2 is kept at logic state LOW until C1 becomes fully
charged. When fully charged, C1 can no longer hold the input of N2 to logic state LOW and thus
toggles it to logic state HIGH. Consequently, the output of N2, and hence the input of N1,
becomes logic state LOW and the output of N1 becomes logic state HIGH. The capacitor C1 starts
to discharge through R1 and when it is fully discharged the circuit returns to the original
conditions and the cycle repeats all over. This causes the system to oscillate. The frequency of
oscillations of the system is determined by two components; resistor R1 and capacitor C1.
Resistor R2 is normally very small compared to R1 and it contributes insignificant effect on the
frequency of the output signal.
Mathematically,
If R2=R1, then
1 2 1 1
559 0 559 0
C R
.
C R
.
f
If R2<<R1, then
1 1
455 0
C R
.
f
1 2
74HC04
3 4
74HC04
R2
10R
R1
1M
D1
C1
1uF
N2 N1
14

The supply voltage can be up to 5V for 74HC04 or 74LS04 and up to 15V for MM74C04. The
higher the voltage the higher the system can oscillate. The Minimum value of C1 is 27pF and the
minimum value of R1 is 2.2K with a supply voltage of 10V or more and 4.7K with a supply
voltage of 5V. For very high frequencies use R1=R2.
Questions
(a) Prototype the system shown in figure B1.
(b) Design the system by calculating the values of R1, R2 and C1. The frequency of oscillation
must be between 1Hz to 15Hz.
(c) What observations do you see on LED D1?
(C)NAND Gate Square Wave Generator
A NAND gate is digital logic component which produces at its output a logic state HIGH when any
of its inputs is logic state LOW and logic state LOW when all of its inputs are LOW. It accepts at
least two inputs but produces a single output. In certain design applications, a NAND gate can be
converted to a NOT gate by connecting all its inputs together. Consider a situation that you need
twelve NOT gates in your circuit and you only have six NOT gates and 10 NAND gates in the store.
A better option solve this challenge is to convert some NAND gates into NOT gates. Figure C1
shows a 74LS00 NAND gate of two inputs configured to operate as a NOT gate. From the
illustration, A Q which is a function of a NOT gate.

Figure C1: Implementation of NOT gate using NAND gate
Figure C2 illustrates two NAND gates, G1 and G2, connected to produce continuous train of
square pulses. The operation of the circuit is very similar to the operation of a NOT gate square
wave oscillator. Assume initially the output of G2 is logic state HIGH. According to the operation
of a NAND gate, the input of G2 and hence the output of G1 is forced to attain a logic state LOW.
The capacitor C1 starts to charge up through resistor R1 and the potential difference between its
terminals increases at a rate determined by the time constant of the C1 and R1 components. As
the capacitor C1 charges up, the potential at the junction of the capacitor C1 and resistor
connected to the input of G2 through a stabilizing resistor R2 decreases until the lower threshold
value of G1 is reached. At this point, the input of G1 becomes logic state LOW and consequently
the output of G1 and hence the input of G2 becomes logic state HIGH. On the basis of the
operation of a NAND gate, the output of G2 becomes logic state LOW. As a result, the capacitor
C1 starts to discharge through the input of G1 because its polarities will have been reverse biased
then. Capacitor C1 charges up again in the opposite direction at a rate determined by the time
constant given by R1 and C1 components until it reaches the upper threshold value of the NAND
gate G1. This causes G1 to change its logic states and the cycle repeats itself over again. The
frequency of oscillation of the output signal at G2 is governed by the formula:
1 1
2 2
1
C R .
f .
1
2
3
74LS00
A Q
15

QUESTIONS
(a) Mount the circuit on a prototyping board with designed value of R1, R2 and C1 to give a
frequency of 1KHz
(b) Connect one of the channels of the oscilloscope to the output of G2. Determine the
frequency of the signal on the oscilloscope. Compare and contrast the theoretical (calculated)
frequency value and practical frequency value.

Figure C2: NAND Gate Square Wave Oscillator
















1
2
3
G1
74LS00
1
2
3
G2
74LS00
R2 R1 C1
A
B
C
D
16

LABORATORY ASSIGNMENT TWO
OPERATIONS AND FUNCTIONS OF DIGITAL COMPONENTS

(A) Seven Segment Display
A Seven Segment Display is an electronic component made up of seven LED segments
configured to display numeric numbers 0 through 9 for a given combination of binary
patterns at its inputs. The seven segments of the display are usually labeled a, b, c, d, e, f
and g or A, B, C, D, E, F and G. A particular LED in a Display illuminates when forward biased.
In addition to the seven segments contained in the display, there is an extra LED which is
used to show a decimal point for decimal numbers. The LED decimal point is recognized by a
label dp or DP. If a decimal number, such as 4.78, is required to be displayed the decimal
point of a corresponding display is illuminated. In practical applications, when a decimal
point is used to display decimal numbers at least two Seven Segment Displays are involved.
There are two configuration types of seven segment displays. These are Common Cathode
(CC) and Common Anode (CA). In a CC configuration, the cathode terminals of ALL LEDs in
the module are connected together, hence sharing a common point called common
cathode. Data is sent through the anode lines of the display. A particular LED segment in a
CC Seven Segment Display becomes illuminated when the common cathode terminal of the
display is connected to Ground and its Anode terminal is connected to the supply Voltage of
+5V. On the other hand, a CA configuration has the Anode terminals of ALL LED segments
connected together, hence forming a common point called common anode. Data is sent
through the cathode lines of the display. A particular LED segment in a CA Seven Segment
Display becomes illuminated by applying a supply voltage of +5V to the common terminal
and connecting its cathode terminal to Ground. Figure 2A1 and figure 2A2 illustrate CC and
CA Seven Segment Display configurations.
QUESTIONS
(a) Draw the truth tables for both figure 2A1 and figure 2A2 to illustrate active and inactive
LED segments for decimal numbers 0 through 9 when binary patterns are sent through
the inputs of the displays.
(b) Given a Seven Segment Display of unknown configuration. Mount the device on a
prototyping board with each leading terminal connected to either +5V or 0V through a
protecting resistor of 290R. Use appropriate testing techniques to identify the
configuration mode of the display.
(c) Using the result obtained in (b), implement the corresponding truth table created in (a).
17


Figure 2A1: CC Seven Segment Display

Figure 2A2: CA Seven Segment Displays
(B) BCD to Seven Segment Display Decoder
This is an electronic device used to convert the Binary Coded Decimal numbers into their
corresponding Seven Segment Display input binary patterns. The device has four inputs
which accept a Binary Coded Decimal from another digital device like counter, register or
encoder. Examples of BCD to Seven Segment Display Decoder ICs include 74LS47 and
74LS48. Figure 2B1 illustrates an active LOW 74LS47 BCD to Seven Segment Decoder
1
1
1
1
1
1
1
1
8x290R
a
b
c
d
e
f
g
dp
0
0
0
0
0
0
0
0
8x290R
a
b
c
d
e
f
g
dp
18

connected to a CC Seven Segment Display through 74LS04 HEX inverters and some current
limiting resistors. The inverters are used because the outputs of the decoder are active LOW
while the inputs of the CC Seven Segment Display are active HIGH. Thus, inverters provide a
match of the logic states. Figure 2B2 illustrates an active LOW 74LS47 BCD to Seven Segment
Decoder connected to a CA Seven Segment Decoder through some protecting resistors.
Connection is done without inverters included because the outputs of 74LS47 decoder are
active LOW and the inputs of the CA Seven Segment Displays are active LOW, thus there is a
perfect match of the logic states. Figure 2B3 illustrates the 74LS48 active HIGH decoder
connected directly to a CC Seven Segment Display through some current limiting resistors.
Since 74LS48 decoder is an active HIGH device and CC Seven Segment Display is active HIGH
device, there is no need to invert the logic states at the outputs of decoder because of a
perfect match of the logic states of the decoder outputs and display inputs. Figure 2B4
illustrates a 74LS48 active HIGH decoder connected to a CA Seven Segment Display through
some current limiting resistors along with inverters. A CA Seven Segment Display is an active
LOW device while 74LS48 decoder is active HIGH device, thus inverters are requires to
provide proper matching of the logic states. Generally, the 74LS47 decoder is designed to be
connected directly to a CA Seven Segment while the 74LS48 decoder is designed to be
connected directly to a CC Seven Segment Display.

Figure 2B1: The 74LS47 Decoder Connected to CC Seven Segment Display
A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS47
1
1
0
0
7x290R
CC DISPLAY
1 2
3 4
5 6
13 12
11 10
9 8
1 2
19


Figure 2B2: The 74LS47 Decoder Connected to CA Seven Segment Display

Figure 2B3: The 74LS48 Decoder Connected to CC Seven Segment Display

A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS47
1
1
0
0
7x290R
CA DISPLAY
0
1
0
0
A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS48
7x290R
CC DISPLAY
20


Figure 2B4: The 74LS48 Decoder Connected to CA Seven Segment Display
QUESTIONS
(a) Draw a functional truth table of a 74LS47 decoder shown in figure 2B2.
(b) Mount the circuit presented in figure 2B2 on a prototyping board
(c) Using the truth table in (a), observe the functionality of your design in (b)
(d) What actual names are represented by the input pins LT, RBI and BI/RBO of the
decoder?
(e) What roles are played by the decoder inputs LT, RBI and BI/RBO? Verify your answer by
putting the pins at different logic states.

















0
1
0
0
A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
U1
74LS48
7x290R
1 2
3 4
5 6
13 12
11 10
9 8
1 2
CA DISPLAY
21

(C) Encoder
Encoder is a digital electronic device that converts decimal numbers into their corresponding
binary patterns. The purpose of an encoder is to change user defined decimal digits (0, 1, 2,
3, 4, 5, 6, 7, 8 and 9) into a form which can be easily recognized, interpreted and processed
by a digital system. Have you ever seen or even applied a system where you are required to
enter some pieces of information through a keyboard or keypad? Well, the pieces of
information indicated on a keyboard or keypad are only meant for user convenience and
cannot be recognized by the processing device. Consider a simple example when you enter
an alphanumeric (combination of alphabet and numeral) characters from the computer
keyboard. It is only you who can understand and interpret that character but not the
computer. There is a digital device in a computer, called binary or digital encoder, which is
responsible to convert every character you enter from the keyboard into its corresponding
binary equivalent. If you enter number 3 (three), for example, it must be converted into its
equivalent binary pattern 00000011 by the encoder.

The binary encoder is a multi-input combinational circuit. Generally, it accepts 2
n

inputs and
produces n outputs, where n stands for a positive integer greater than 0. If it is an 8-to-3
encoder, for example, then it accepts 8 combinational inputs and produces 3 outputs
equivalent to a single binary pattern of the inputs. Figure 2C1 illustrates a standard 4-to-2
encoder and its corresponding truth table.

Figure 2C1: A 4-to-2 encoder and its corresponding truth table
One of the main disadvantages of standard digital encoders is that they can generate a
wrong output code when two or more HIGH logic states are simultaneously applied at the
inputs. From figure 2C1 if both D
1
and D
3
, for example, are held at logic state HIGH, the
output code can neither be binary pattern 01 nor binary pattern 11 respectively. The only
possibility left is for the output code to be binary pattern 10, which is different from the
actual input present. Another disadvantage is that the output code 00 can be generated
when the input binary pattern is 0001 or 0000, and this can lead to confusion.

There is a very simple way to solve the above mentioned challenges. The level of each input
must be prioritized such that when two or more HIGH logic states appear at the inputs only
the input level with the highest designated priority is selected. The encoder with the priority
functionality is called priority encoder. Figure 2C2 illustrates an 8-to-3 priority encoder and
its corresponding truth table. From the illustration, if, for example, the input lines D
1
, D
3
and
D
6
are simultaneously held at logic state HIGH the output code will be 110. This is equivalent
to the input level D
6
which is the highest input level compared to the input lines D
1
and D
3
.
22

When D
6
is removed (held at logic state LOW) the output code will be 011. This is equivalent
to the input level D
3
which is the highest input level compared to D
1
and so on.

Figure 2C2: The Priority Encoder and its Truth Table
Figure 2C3 illustrates a 74LS148 priority encoder connected to a single CA seven segment
display through a 74LS47 BCD to Seven Segment Decoder. The system displays the number
(between 0 and 7 inclusive) of the highest pressed key.

Figure 2C3: A 74LS148 Priority Encoder Connected to a Seven Segment Decoder
Priority encoders find a wide range of applications in various electronics gadgets and
systems. The following are few of the applications:
Keyboard Encoder
Priority encoders are used to minimize the number of wires and connections in applications
with multiple inputs. Consider a standard QWERTY keyboard type that has 104 character
keys. In the absence of the priority encoder there would be 104 wires, each wired to a single
7x330R
A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS47
0
10
1
11
2
12
3
13
4
1
5
2
6
3
7
4
EI
5
EO
15
A0
9
A1
7
A2
6
GS
14
U1
74LS148
8x1K
23

key, going to the PC processing circuits. You can see that this is impractical for a small home
PC. A better way is to use a priority encoder to encode all 104 keys into a standard ASCII
code of only 7 bits representing each key or character on a keyboard. This implies that 104
wires will have been reduced to 7 wires which is a manageable and reasonable size to be
connected to the computer processing circuits. Example of a keyboard/keypad encoder is
74C923 which can encode up to 20 keys.
Positional Encoders
Another very common application of priority encoder is in magnetic positional control used
in ships, robots and so on. In this case, a priority encoder converts the angular or rotary
position of a compass into a digital code which can be sent to a control system, such as
computer, to provide navigational data. Figure 2C4 illustrates an 8-to-3 priority encoder used
to convert compass direction data (North, NE, East, SE, South, SW, West and NW) into an
angular positional code.

Compass Direction Binary Output
Q2 Q1 Q0
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
Figure 2C4: Positional Encoder Used in Magnetic Positional Control
QUESTIONS
(a) Mount the circuit shown in figure 2C3 on a prototyping board
(b) Test and analyze the functionality of the circuit
(c) Practically demonstrate the roles played by the input EI and outputs E0 and GS


24



(D) Counters
Counter is a digital electronic component which is used to count events. They can be put
into three main categories; which are (i) UP counter (ii) UP/DOWN counter and (iii) Special
Counters. An UP counter increments by one from 0 to a given number. A decade UP counter
such as 74LS160, for example, counts from 0 through 9 continuously when a clock signal is
applied at its CK or CP clock input, illustrated in figure 2C1.

An UP/DOWN counter, sometimes called bidirectional counter, counts either UP or DOWN
when a clock signal is applied at its CK or CP clock input. Depending on the logic state at its
UP/DOWN control input this counter can be made to continuously increment by one from 0
to a given number or decrement by one from a given number to 0. If the UP/DOWN control
input is 1 the counter increments and if it is 0 the counter decrements. Example of an
UP/DOWN counter is 74LS169 decade counter, illustrated in figure 2C2. Another example of
an UP/DOWN counter is a binary counter 74LS191. This counter counts from 0 to 15 when
clocked by a signal of a given frequency. Notices that when binary counter, such as 74LS191,
is connected to a Seven Segment Display through a BCD to Seven Segment Display some
numbers displayed will be letters at one stage during counting. These letters are A (decimal
number 10), B (decimal number 11), C (decimal number 12), D (decimal number 13), E
(decimal number 14) and F (decimal number 15). A special counter is the one that has a
counting sequence customized by a user to suit a particular application. It does not
increment or decrement by one the usual way. A special counter can be designed to count
odd numbers, even numbers or powers of number 2. If you need a special counting
sequence, say 1, 3, 5 and 7, for your own application you need to design a counter from first
principles because a counter of this counting sequence cannot be easily obtained from the
market. Example of a very common special counter is a Johnson Counter (also called ring
counter) illustrated in figure 2C3. A Johnson Counter counts powers of 2 (1, 2, 4, 8, 16, 32,
64 and 128). This fashion of counting is known as a Knight Rider style and it is usually used in
decoration applications like disco lights and so forth.

Counters fall under sequential type of devices because the current states of its outputs
depend on the previous states. This implies that the next state of a counter is determined by
the condition and value of the previous state. For example, for a counter to advance from
number 5 to number 6, it must previously locate number 5 prior to getting into number 6.
This is what is termed as sequential operation.

In this experiment, you will learn about 74LS169 UP/DOWN binary counter and 74LS17 Ring
counter. Figure 2C4 illustrates the pinout of a 74LS169 counter and figure 2C5 illustrates
interfacing of 74LS169 to CA Seven Segment Display. Table 2C1 describes the functions of
each pin of the 74LS169 counter. In figure 2C5, 74LS169 counter is interfaced to 74LS47
decoder to display decimal numbers on a CA seven segment display. A clock signal is derived
from a push button connected at CLK input pin of a counter. When a button is pressed a
logic state LOW appears at a CLK pin and when a button is released a logic state HIGH
25

appears at a CLK pin, thus a LOW-HIGH clock pulse is generated. This makes a device to
advance its counting sequence.

The action of pressing and releasing a button is very mechanical and doesnt guarantee
stable settling times. When a button is pressed, it usually bounces several times before
attaining a stable state. If the device is operated at a relatively high clock frequency, these
bouncing effects can be remarkably noticeable by the counting device. This can disrupt the
normal counting sequence of the counter. Figure 2C6 shows a bouncing effect observed
when a button connected to CLK pin of a counter (see figure 2C5) is pressed and released.


Figure 2C4: Pinout of 74LS169

Pin
Number
Pin
Name
Description
1
D / U
UP/DOWN count control pin. If this pin is logic state HIGH the counter
increments and if set at logic state LOW the counter decrements
2 CLK Input for a clock signal
3 D0 Data line 0 (LSB)
4 D1 Data line 1
5 D2 Data line 2
6 D3 Data line 3 (MSB)
7
ENP
Enable/Disable input pin. If this pin is logic LOW the counter is allowed
to count. If it is logic state HIGH the counter is PAUSED or disabled from
count, in which case the counter holds the current value.
8 GND Reference Voltage (GROUND)
D0
3
Q0
14
D1
4
Q1
13
D2
5
Q2
12
D3
6
Q3
11
RCO
15
CLK
2
LD
9
U/D
1
ENT
10
ENP
7
74LS169
26

9
LD
Input pin for loading data values. If this pin is logic LOW the counter
starts counting from the data value set at the data lines D0 through D3.
If it is logic HIGH the counter performs normal counting sequence; that
is from 0 through 15 if it is a binary counter like 74LS169. If this mode is
not used, ALL data lines must be grounded and the LDpin must be held
logic HIGH.
10
ENT
Enable/Disable input pin. If this pin is logic LOW the counter is allowed
to count. If it is logic state HIGH the counter is PAUSED or disabled from
count, in which case the counter holds the current value.
11 Q3 Output 3 (MSB)
12 Q2 Output 2
13 Q1 Output 1
14 Q0 Output 0 (LSB)
15
RCO
Terminal Count. This is an output pin that becomes logic LOW when the
counter reaches the final value (fifteen (15) if it is a binary counter like
74LS169), and logic HIGH otherwise.
16 V
CC
Supply Voltage
Table 2C1: Description of pins of 74LS169 binary counter


Figure 2C5: Interfacing 74LS169 to CA Seven Segment Display


A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS47
D0
3
Q0
14
D1
4
Q1
13
D2
5
Q2
12
D3
6
Q3
11
RCO
15
CLK
2
LD
9
U/D
1
ENT
10
ENP
7
COUNTER
74LS169
10k
27

Figure 2C6: Bouncing Effects of a Button Pressed and Released
The bouncing effects of button can be eliminated by using delay circuits. This can be achieved by
connecting a button to a delay circuit in that when a button is pressed and released the CLK pin
remains logic HIGH for a given time, usually 100ms, before returning to its original logic state LOW. A
better delay circuit for this function is a 555 timer configured as a Monostable (one-shot) device.
Figure 2C7 illustrates a debounce circuit using 555 timer in one-shot mode. The output Q of a timer
is connected to a CLK input pin of a counter; hence acting as a source of clock.

Figure 2C7: Switch Debouncing Using 555 Timer
QUESTIONS
(a) Mount and test the circuit shown in figure 2C7 on a prototyping board
(b) While the D / U pin of a 74LS169 counter is held logic HIGH, continuously press and release a
button connected at TR pin of a 555 timer. What changes do you observe on the seven
segment display? What happens to the display if D / U pin is held logic LOW and the same
procedure is repeated?
(c) Set a binary number of your choice through the data lines D0, D1, D2 and D3 with the LD
input pin of a counter held logic LOW. Press and release a button. What number is displayed
on a seven segment display? Explain.
(d) Hold the LDpin logic HIGH with the binary number set in section (c) unchanged. What
happens to the numbers shown on the Seven Segment Display when a button is pressed and
released several times?
(e) Design a simple control circuit to make the counter continuously count UP from 3 to 7.
(f) Demonstrate practically the functions of ENT , ENPandRCO .


A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER
74LS47
D0
3
Q0
14
D1
4
Q1
13
D2
5
Q2
12
D3
6
Q3
11
RCO
15
CLK
2
LD
9
U/D
1
ENT
10
ENP
7
COUNTER
74LS169
R
4
DC
7
Q
3
G
N
D
1
V
C
C
8
TR
2
TH
6
CV
5
R
100k
C
1uF
Approx. 100ms
C2
0.01nF
28




Contrary to the counting sequence just observed in the previous experiment, the outputs of a
Johnson Counter increment in powers of 2. That is, it counts 0, 1, 2, 4, 8, 16, 32, 64, 128, 256 and
512. This fashion of counting can be used in control applications and animations in entertainment
occasions. Figure 2C8 shows a 4017 Johnson Counter driven from a 555 timer oscillator. The timer is
configured in Astable mode to produce a clock signal at 5Hz.

Figure 2C8: Operation of a Johnson Counter
QUESTIONS
(a) Mount and test the circuit on a prototyping board.
(b) What roles do the pins E, CLK, CO and MR serve? Verify your answer practically.
(c) Design a simple control circuit to enable a continuous counting sequence of 0, 1, 2 and 4.







CLK
14
E
13
MR
15
CO
12
Q0
3
Q1
2
Q2
4
Q3
7
Q4
10
Q5
1
Q6
5
Q7
6
Q8
9
Q9
11
JOHSON COUNTER
4017
555 TIMER
OSCILLATOR
(5Hz)
11x290R
29




In several occasions, multiple seven segment displays are used to display at least two-digit numbers.
Figure 2C9 illustrates a system to display a two-digit number. From the figure, COUNTER-ONES
counter increments the ones-digit and COUNTER-TENS counter increments the tens-digit. The two
control circuits, A and B, limit the COUNTER-ONES and COUNTER-TENS counters to have a maximum
count of 9 respectively.

Figure 2C9: Cascading Two Binary Counters to Display a Two-Digit Number
QUESTIONS
(a) Mount and test the circuit on a prototyping board
(b) Briefly describe how the control circuits A and B limit the counts of the two counters,
COUNTER-ONES AND COUNTER-TENS.





A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER-ONES
74LS47
D0
3
Q0
14
D1
4
Q1
13
D2
5
Q2
12
D3
6
Q3
11
RCO
15
CLK
2
LD
9
U/D
1
ENT
10
ENP
7
COUNTER-ONES
74LS169
A
7
QA
13
B
1
QB
12
C
2
QC
11
D
6
QD
10
BI/RBO
4
QE
9
RBI
5
QF
15
LT
3
QG
14
DECODER-TENS
74LS47
D0
3
Q0
14
D1
4
Q1
13
D2
5
Q2
12
D3
6
Q3
11
RCO
15
CLK
2
LD
9
U/D
1
ENT
10
ENP
7
COUNTER-TENS
74LS169
A
B
30




(E)