Datasheet

DesignWare Sensor IP Subsystem

Features
` Complete, pre-veried subsystem
integrating hardware and software
` Hardware accelerators and DSP
software libraries enable sensor
signal processing
` Congurations as small as
0.01mm
2
consuming <4uW/MHz in
a 28-nm process
` Digital and analog interfaces provide
multi-sensory input and output
` Extremely low gate count and highly
efcient processing performance
Target Applications
` Industrial
y Real-time control
y Robotics
` Automotive
y In-vehicle networking
y ABS
y Electric power steering
y Digital motor control
` Consumer
y Mobile phones/tablets
y E-metering
y Home automation
y Headsets and speakers
y Connected appliances
` Portable Medical Devices
y Blood-pressure monitors
y Heart-rate monitors
y Digital thermometers
Overview
The DesignWare

Sensor IP Subsystem is a complete, pre-veried, scalable

subsystem for sensor control applications. It is designed for fast and easy
integration within a larger system context. The subsystem is either the basis of an
independent system controller on a system-on-chip (SoC) or it provides higher
abstraction sensory input to a main controller by combining sensor inputs. The
sensor subsystem includes a low gate count and energy-efcient ARC

EM core
for control processing accompanied by a large collection of I/O functions and
DSP accelerators. The software libraries of the subsystem contain small footprint
drivers for all I/O plus DSP functions supporting signal processing. The integrated
hardware/software solution is optimized for small area and low power.
Figure 1: DesignWare Sensor IP Subsystem functional block diagram
The sensor subsystem supports multiple integration approaches for sensor and
actuator interfaces:
` PCB level integration: sensor (and/or actuator) is contained in a different package
from the package that contains the subsystem
` System-in-Package: sensor (and/or actuator) and subsystem are integrated as a
SiP but each on a separate die
` Single-Die: both sensor (and/or actuator) and sensor subsystem are part of the
same die
Sensor
Sensor
ADC
Peripheral
Signal
processing
Signal
processing
Mixer/data
fusion
Peripheral
Actuator
Actuator
driver/DAC
Peripheral
Analog in
Digital in
Data (DSP) part
Data
output
Analog out
Digital out
Control (CPU) part
Events
Start
State 1
State n
State 2
Transition 1
Transition 2
Transition 3
Transition 4
DesignWare Sensor IP Subsystem 2
The Synopsys ARChitect IP
conguration tool allows users
to fully congure the subsystem.
Conguration options include
processor settings, number of digital
and analog I/O interfaces and use of
hardware accelerators. The MetaWare
Development Toolkit can be used for
development of user applications that
are built on the sensor subsystem
software libraries.
Software Architecture
The sensor subsystem software offering
includes a library of DSP functions for
signal processing such as linearization,
ltering, and complex mathematical
operations. Software drivers are also
included to ease I/O peripheral integration.
In lieu of an operating system,
a lightweight event processing
framework is included with the example
implementations to quickly get customers
started with subsystem integration.
Hardware Architecture
The sensor subsystem provides an
optimized hardware architecture
consisting of an ARC EM processor,
tightly coupled digital I/O interfaces via
custom registers and a library of DSP
accelerator functions.
The software DSP functions provide
conguration options to make use of these
accelerators. The overall system is highly
congurable and extensible (Figure 3).
Key Features
` Efcient processor
` Sensor and actuator interfaces
` SoC hardware interfaces
` Host interfaces
` Hardware accelerators
` Power management
` Software I/O drivers and DSP libraries
` Implementation examples
` Demonstrator
` Synopsys ARChitect IP
conguration tool
` Extension options
Efcient Processing
A power-efcient, low gate count 32-bit
ARC EM processor is at the center
of the sensor subsystem. The EM
processor is highly congurable and can
be optimized for area and performance
using a large range of parameters.
Users can add or remove features that
improve the efciency of the core for
their application, including options
such as instruction and data closely-
coupled memory congurations, custom
instructions (EIA interface), address bus
width, timers, interrupts, register le
structure and debug interface.
Signal
processing
User application
Drivers
Peripherals
Drivers
Peripherals
ARC EM processor
Event
processing
DSP
library
Hardware
accelerators
Hardware
accelerators
Software
Hardware
Customer IP
Synopsys IP
Figure 2: Sensor IP subsystem system view
AHB master
AHB slave
JTAG
Host
interface
Sensor
and actuator
connectivity
Pipeline
Hardware
accelerators
ARC EM4
Commit Execute
Debug
IFQ
Embedded
ROM/SRAM
Interrupt
controller
Filtering
accelerators
Vector
accelerators
APB
IF
First math
accelerators
GPIO
I
2
C
master
SPI
master
ADC
IF
I
2
C
slave
Interpolation
accelerators
Direct
memory port
Embedded
SRAM
Timers
Figure 3: Sensor IP subsystem hardware architecture
DesignWare Sensor IP Subsystem 3
Sensor and Actuator Interface
The sensor subsystem has multiple
partitioning schemes for interfacing with
sensors or actuators. (Figure 4)
The Analog Interface (AIF) is the analog
partition scheme, generally used for
hybrid solutions where the sensor
is made in a different technology
compared to the control subsystem.
The Parallel Digital Interface (PDIF)
is a digital 1-1 partition scheme used
for more intelligent (smart front-end)
sensors or actuators where the analog-
to-digital conversion is done close to
the sensor. The Serial Digital Interface
(SDIF) is a digital 1-N serial partition
scheme for smart front-end sensors
or actuators. This interface supports
connecting multiple devices to the
subsystem using only a limited number
of I/O signals.
SoC Hardware Interface
Hardware integration to a SoC is
provided via two ARM

AMBA

AHB
master bus interfaces for connection
to other IP attached to the bus and two
ARM AMBA AHB slave interfaces for
direct access to the closely coupled
ARC EM processor memories. If the
subsystem is not integrated into a SoC,
the subsystem can be congured to
omit these interfaces.
Host Interface
The host communication to the sensor
subsystem can be managed via shared
memory or via a dedicated peripheral. The
currently supported I/O interface is I
2
C.
Power Management
The sensor subsystem supports clock
switching. All I/O functions and the
processor core can be switched off
independently. Clock disabling (or
enabling) of an I/O function is software
controlled. The processor core can be
put into sleep mode when it runs idle
and wakes up on any interrupt.
In a hosted conguration, the lowest
power mode of a subsystem node is
reached when the host processor stops
the node completely and switches off Vdd.
Implementation Examples
With the release package customers
receive two example sensor control
implementations. These are fully functional
designs demonstrating two different use
cases for the sensor subsystem:
` Use case 1 is an intelligent sensor
demonstrating the calibration, ltering
and linearization functions required for
communicating with analog sensors.
Also it demonstrates the use of
DSP accelerators and their positive
impact on cycle count (translating into
performance or power benets) and
memory footprint.
` Use case 2 is an example of sensor
fusion where multiple digital sensors
are connected to the subsystem and
their signals are combined to derive an
improved calibrated output signal.
Figure 5: ARC EM Starter Kit
Demonstrator
An ARC EM Starter Kit (Figure 5) can be
separately licensed for demonstration
and hardware accelerator evaluation
purposes. The included sensor
implementation examples can also be
mapped on the Starter Kit.
A/D
Analog
Transducer
A/D
Analog
Transducer Transducer
A/D
Analog
Bus IF
Digital
SDIF
Bus IF
Digital
PDIF
Bus IF
Digital
AIF
Figure 4: I/O interfaces
Synopsys, Inc. 700 East Middleeld Road Mountain View, CA 94043 www.synopsys.com
07/13.AP.CS3224.
2013 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.
Deliverables
` IPLib installation le which includes:
y User-congurable hardware
(RTL) and software source code
(using Synopsys ARChitect IP
conguration tool)
y Complete set of front-end views
y 2 demonstration applications
available as design templates
y ARC EM IPLib installation le
` Databook (PDF)
` Release notes (PDF)
` ARChitect conguration tool
Synopsys ARChitect IP
Conguration Tool
The Synopsys ARChitect IP conguration
tool is a comprehensive environment
for conguring all IP in the subsystem
and the generation of RTL and software
inline with the chosen conguration. Most
conguration options are cross checked
for validity during the conguration
process. Some options can only be
veried during the generation phase. In
any case, the designer is protected against
creating erroneous designs. During the
conguration process the impact of
conguration choices on the overall gate-
count is fed back to the user continuously.
Extension Options
The subsystem is easily extensible
via standard ARM AMBA AHB bus
interfaces. For example, the extensive
portfolio of Synopsys DesignWare IP
can be connected via these interfaces.
Another option is to use the EIA
interface of the ARC EM processor. This
interface is also used internally in the
subsystem to connect I/O functions and
DSP accelerators.
About DesignWare IP
Synopsys is a leading provider of high-
quality, silicon-proven IP solutions for
SoC designs. The broad DesignWare
IP portfolio includes complete interface
IP solutions consisting of controllers,
PHY and verication IP for widely
used protocols, analog IP, embedded
memories, logic libraries, processor
cores and subsystems. To support
software development and hardware-
software integration of the IP, Synopsys
offers drivers, transaction-level models,
and prototypes for many of its IP
products. Synopsys HAPS

FPGA-
Based Prototyping Solution enables
validation of the IP and the SoC in the
system context. Synopsys Virtualizer

virtual prototyping tool set allows
developers to start the development
of software for the IP or the entire SoC
signicantly earlier than traditional
methods. With a robust IP development
methodology, extensive investment
in quality, comprehensive technical
support, software development and IP
prototyping support, Synopsys enables
designers to accelerate time-to-market
and reduce integration risk.
For more information on DesignWare
IP, visit: http://www.synopsys.com/
designware. Follow us on Twitter at
http://twitter.com/designware_ip.