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R09 SET-1
Code No: 09A51002
B. Tech III Year I Semester Examinations, May/June - 2012
PULSE AND DIGITAL CIRCUITS
(ELECTRONICS AND INSTRUMENTATION ENGINEERING)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---
1.a) What are the drawbacks of uncompensated attenuators? Prove that the condition to
prevent input signal from distortion is R
1
C
1
=R
2
C
2,
in an adequately compensated
attenuator.
b) An RC differentiator circuit is driven from a 500Hz symmetrical square wave of
10V Peak-to peak. Calculate the output voltage levels under steady state if
RC =1msec. [10+5]

2.a) A symmetrical 10 kHz square wave whose peak -to-peak excursion are 10V with
respect to ground is impressed upon the diode clamping circuit shown in figure.1.
The Diode has R
f
=100, R
r
= and V =0. Sketch the steady state output
waveform, indicating clearly the voltage levels.

Figure.1
b) Explain positive peak voltage limiters above and below reference level. [10+5]

3.a) Explain the switching characteristics of bipolar junction transistor.
b) Explain the switching characteristics of diode. [8+7]

4.a) With reference to multivibrators, explain:
i) stable-state (ii) loop-gain (iii) quasi stable-state
b) For the given circuit shown in fig.2, find UTP & LTP. What is this circuit called?
Data given h
fe
(min) = 40, V
CE
(sat) = 0.1V, V
BE
(sat) = 0.7V, V

= 0.5V,
V
BE
(active) =0.6V. [6+9]

Figure.2
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5. Explain the basic principal of Miller and Bootstrap time base generators and also
derive the expressions for sweep speed error. [15]

6.a) Explain the principle of synchronization and synchronization with frequency
division.
b) Explain the method of pulse synchronization of relaxation devices, with
examples. [7+8]

7.a) Draw the circuit of an emitter-coupled bidirectional sampling gate and explain.
b) What is Pedestal? How pedestal can be reduced in a sampling gate circuit?
[7+8]

8.a) Realize a three-input NAND GATE using Transistor-Transistor Logic. Explain its
operation with Totem-pole o/p circuit.
b) With reference to logic gates, explain the terms:
i) Fan-out ii) Noise- Margin
iii) Propagation Delay iv) Figure of Merit. [7+8]



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Code No: 09A51002
SET-2 R09
B. Tech III Year I Semester Examinations, May/June - 2012
PULSE AND DIGITAL CIRCUITS
(ELECTRONICS AND INSTRUMENTATION ENGINEERING)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---
1.a) Prove that for any periodic input waveform the average level of the steady state
output signal from the RC high pass circuit is always Zero.
b) Draw the RC low pass circuit. With necessary waveforms and expressions explain
its working for a step voltage input. [8+7]

2.a) For the circuit shown in figure.1, an input voltage V
i
varying linearly from 0 to
150V is applied. Sketch the output waveform V
O
to the same time scale. Assume
ideal diodes.

Figure.1
b) What is meant by a d.c restoration circuit? Explain. [10+5]

3.a) Explain Piecewise linear characteristics of diode.
b) Discuss in detail about transistor switching times. [7+8]

4. Describe multivibrators from the view points of construction, principle of
working, classification based on the output states, applications and specifications.
Mention one specific application of each. [15]

5.a) Define the three errors that occur in a sweep circuit and obtain an expression for
these errors for an exponential sweep circuit.
b) In the UJ T sweep circuit, V
BB
=20V, V
yy
=50V, R =5k, C =0.01 micro F. UJ T
has =0.5. Calculate (i) amplitude of sweep signal (ii) Slope and displacement
errors and (iii) estimated recovery time. [8+7]

6.a) What is the condition to be met for pulse synchronization?
b) Describe synchronization with 2:1 frequency division with neat waveforms.
c) Define the terms, phase delay and phase jitter. [3+8+4]


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7.a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate
for multiple inputs.
b) Explain with circuit diagram the operation of a two input sampling gate which
does not have any loading effect on control signal. [7+8]

8.a) Realize two-input AND & OR gates using diodes and explain their operation with
the help of truth-tables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its
operation with the help of truth-table. [8+7]


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Code No: 09A51002
SET-3 R09
B. Tech III Year I Semester Examinations, May/June - 2012
PULSE AND DIGITAL CIRCUITS
(ELECTRONICS AND INSTRUMENTATION ENGINEERING)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---

1.a) A symmetrical square wave whose peak-to-peak amplitude is 2V and whose
average value is zero is applied to an RC integrating circuit. The time constant is
equals to half -period of the square wave find the peak to peak value of the output
amplitude.
b) Describe the relationship between rise time and RC time constant of a low pass
RC circuit. [7+8]

2.a) For the circuit shown in figure.1, R
S
=R
f
=100, R =10K, C=1.0F. At t=0
symmetrical square wave is applied with an amplitude of 10V and a frequency of
5KHz, sketch the output wave form for the first two cycles.

Figure.1
b) Discuss about Emitter coupled clipper. [10+5]

3. Define rise time and fall time of a transistor switch. Derive expressions for these
in terms of the transistor parameters and operating currents. [15]

4.a) Explain the operation of emitter coupled bistable multivibrator.
b) Explain how an astable multivibrator can be modified as voltage to frequency
convertor. [7+8]

5.a) Draw the circuit of a Boot strap sweep generator and explain its operation.
Derive an expression for its sweep time.
b) Explain with a circuit the working of a UJ T sweep circuit and obtain the
expressions for the intrinsic standoff ratio (). [8+7]






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6.a) With neat waveforms explain sine wave synchronization and compare it with
pulse synchronization.
b) The relaxation oscillator when running freely, generates an output sweep
amplitude of 100V and frequency 1kHz. Synchronizing pulses are applied such
that at each pulse the breakdown voltage is lowered by 20V. Over what frequency
range the synchronizing pulse frequency may be varied if 1:1 synchronization is
to result? [8+7]

7.a) With the help of a neat diagram, explain the working of two-diode sampling gate.
b) Derive expressions for gain and minimum control voltages of a bi-directional
two- diode sampling gate. [7+8]

8.a) What is logical noise in a diode AND gate? Explain how it can be reduced by
connecting a clamping diode in the circuit.
b) Realize NAND & NOR gates using emitter coupled logic (ECL) and explain their
operation with the help of truth-tables. [7+8]


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Code No: 09A51002
SET-4 R09
B. Tech III Year I Semester Examinations, May/June - 2012
PULSE AND DIGITAL CIRCUITS
(ELECTRONICS AND INSTRUMENTATION ENGINEERING)
Time: 3 hours Max. Marks: 75
Answer any five questions
All questions carry equal marks
---

1.a) What is the ratio of the rise time of the three sections in cascade to the rise-time of
Single section of low pass RC circuit?
b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no
tilt and is coupled to the oscilloscope via a 4.7F capacitor. Calculate the input
resistance of the oscilloscope. [9+6]

2.a) Explain the principle of clamping. Discuss the effect of source impedance, shunt
resistance and cut in voltage.
b) For the figure.1 shown below, V
i
is a sinusoidal voltage of peak 100 volts.
Assume ideal diodes & R
L
= . Sketch the output voltage and transfer
characteristic. [5+10]

Figure.1

3.a) Explain how transistor can be used as a switch in the circuit, under what condition
a transistor is said to be OFF and ON respectively.
b) A germanium transistor is operated at room temperature in the CE configuration.
The supply voltage is 6 V, the collector-circuit resistance is 200 and the base
current is 20 percent higher than the minimum value required to drive the
transistor into saturation. Assume the following transistor parameters:
I
co
=-5A, I
EO
=-2A, h
FE
=100, and r
bb'
=250 . Find V
BE
(Sat) and V
CE
(Sat).
[7+8]

4. What is a monostable multivibrator? Explain with the help of a neat circuit
diagram the principle of operation of a monostable multi, and derive an
expression for pulse width. Draw the wave forms at collector and Bases of both
transistors. [15]



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5.a) What are the essential requirements of TV horizontal sweep circuit? How do you
achieve them using a current sweep?
b) With neat sketches and necessary expressions, explain the transistor Miller time-
base generator. [7+8]

6.a) With neat waveforms explain sine wave synchronization and compare it with
pulse synchronization.
b) The relaxation oscillator when running freely, generates an output sweep
amplitude of 100V and frequency 1kHz. Synchronizing pulses are applied such
that at each pulse the breakdown voltage is lowered by 20V. Over what frequency
range the synchronizing pulse frequency may be varied if 1:1 synchronization is
to result? [8+7]

7.a) Explain the operation of multiple input unidirectional sampling gate using diodes.
b) Give an alternate circuit whose output is not sensitive to upper level of control
voltage.
c) Illustrate the principle of operation of a linear gate using series switch and shunt
switch. What are the disadvantages? [6+3+6]

8.a) Realize a two-input NAND gate using Diode Transistor Logic and explain its
operation with the help of truth-table.
b) Explain the terms:
i) Wired- AND connection
ii) Current Source Sink
iii) Tri-state logic. [7+8]


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