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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
Dragan Maksimovic, Senior Member, IEEE, and Regan Zane, Senior Member, IEEE
Abstract—The letter presents an exact smallsignal discretetime model for digitally controlled pulsewidth modulated (PWM) dc–dc converters operating in constant frequency continuous conduc tion mode (CCM) with a single effective A/D sampling instant per switching period. The model, which is based on wellknown approaches to discretetime modeling and the standard trans form, takes into account sampling, modulator effects and delays in the control loop, and is well suited for direct digital design of digital compensators. The letter presents general results valid for any CCM converter with leading or trailing edge PWM. Speciﬁc examples, including approximate closedform expressions for controltooutput transfer functions are given for buck and boost converters. The model is veriﬁed in simulation using an independent system identiﬁcation approach.
Index Terms—DC–DC converter, digital control, discretetime model, pulsewidth modulation (PWM) converter, smallsignal model.
I. INTRODUCTION
D ISCRETETIME modeling of dc–dc switching converters has had a long history of contributions, starting from [1].
Effects of sampling due to the pulsewidth modulator in the con text of averaged smallsignal models and standard analog con trollers were discussed in [2]. Extensions of discretetime mod eling have included generalizations to various analog control techniques including constraint modulations [3], [4], as well as applications to computeraided modeling and simulations [5], [6]. Exact continuoustime smallsignal converter models have been developed based on a combination of discretetime models and the concept of equivalent hold [7]. Recently, the growing in terest in practical digital control for highfrequency dc–dc con verters has prompted renewed interest in discretetime analysis and modeling [8]–[12] to facilitate direct digital compensator design. In a digitally controlled constantfrequency pulsewidth modulated (PWM) converter, an example of which is shown in Fig. 1(a), the output voltage error is sampled by an A/D con verter. A discretetime compensator computes a dutycycle con trol signal for a digital pulsewidth modulator (DPWM). Dis cretetime models suitable for sampling rates lower than the switching frequency have been discussed in [8]. Sampling rates equal to or even exceeding the switching frequency are now practical, with dynamic performance dependent on controlloop delays [10]–[12]. As noted in [10], the previously derived dis cretetime models describe the behavior of the control variable
Manuscript received May 10, 2007; revised June 19, 2007. This work was supported through the Colorado Power Electronics Center. Recommended for publication by Associate Editor R. Teodorescu. The authors are with the Colorado Power Electronics Center, Electrical and Computer Engineering Department, University of Colorado, Boulder, CO 803090425 USA (email: maksimov@colorado.edu; zane@colorado.edu). Color versions of one or more of the ﬁgures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identiﬁer 10.1109/TPEL.2007.909776
and the converter states at a particular instant during a switching period (e.g., at a beginning of the switch ontime [3], [4]). There fore, these models are not directly applicable to digitally con trolled converters where the A/D sampling instants can occur
at any time during a switching period. To address this problem, a frequencydomain approach based on Laplacedomain modu lator modeling [13] and the modiﬁed transform has been de scribed in [10]. This approach results in an exact discretetime model that correctly takes into account sampling, modulator ef fects and delays in the digital control loop. However, according to [10], the approach is straightforwardly applicable only to bucktype converters. The purpose of this letter is to show how the wellknown dis cretetime modeling [1]–[4] can be extended to take into ac count the sampling, modulator effects and delays in a digitally controlled converter. The result is an exact smallsignal dis cretetime model applicable to any constantfrequency PWM converter. Section II describes the modeling approach. Model examples and veriﬁcation results are presented in Section III. Conclusions are given in Section IV.
II.
DISCRETETIME MODELING WITH DIGITAL CONTROLLER SAMPLING AND _{D}_{E}_{L}_{A}_{Y}_{S}
Fig. 1(a) shows a dc–dc converter (e.g., a buck converter) with digital voltagemode control. In the discussion, without loss of generality, a sensing gain of 1 is assumed together with a constantfrequency trailingedge PWM having an equivalent sawtooth amplitude 1. The converter operates in contin uousconduction mode. In each state of the switch (1 or 2), the converter circuit is linear, timeinvariant, with the corresponding statespace description
(1)
where is the vector of converter states (e.g., inductor current and capacitor voltage, ). We assume the input voltage
is constant, since the primary interest is in the controlto output responses. The A/D converter samples the output voltage error at the sampling rate equal to the switching frequency . The error signal samples are processed by a discretetime compensator
. The compensator output samples control the switch duty cycle via a digital pulsewidth modulator (DPWM). This modulator can be viewed as a D/A converter including a sample andhold followed by signal sampling at the modulated edge [2]. It is important to note that there are two samplers in the feed back loop: A/D sampling of the error voltage, and the modulator sampling. As a result, the system smallsignal model does not include a sampleandhold. Instead, the relationship between the smallsignal perturbations of the voltage error signal and the dutycycle includes a delay between the A/D sampling
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
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Fig. 1. (a) Switching dc–dc converter with digital voltagemode control. (b) Smallsignal model of the digitally controlled dc–dc converter. (c) Waveforms illustrating discretetime model derivation for the digitally controlled dc–dc converter with A/D sampling during interval 2.
, the derivation of
is not necessary. We simply pro
ceed with the discretetime model derivation according to the waveforms shown in Fig. 1(c). These waveforms are shown for the speciﬁc case of trailing edge modulation and the A/D sam pling in interval 2 . The smallsignal dis cretetime model can be written as
(2)
where the matrix and vector coefﬁcients can be solved by propa gating the effect of each perturbation during the converter switch
where is the steadystate duty ratio. Next, consider only the effect of perturbation in the duty cycle. The initial per turbation in the states occurs at the modulation edge of the PWM output signal and can be found from (1) as linear exten sions of the previous and next switch states
matrix and vector coefﬁcients for the model (2) are given in
(5)
The output statespace equation can be added according to (1) as follows:
at and the modulator sampling at , as shown in Fig. 1(b), and illustrated by the waveforms in Fig. 1(c). The total delay in the control loop includes the A/D conversion time, the computation delay (i.e., the time it takes to compute the dutycycle control signal ), as well as the modulator delay (i.e., the time between the update of and the switch transi tion from state 1 to state 2). In the discussion that follows, we as sume that the total delay is shorter than the switching period ,
0 . Inclusion of the delay in the discretetime model presented here is the key extension compared to the models in
[1]–[4].
As shown in the model of Fig. 1(b), the samples af fect the converter state perturbations through the equivalent hold which models the converter responses between the samples, leading to exact continuoustime models [7]. Since the digital control system only operates on the values of the state variables or the outputs sampled at the A/D sampling instants
(6)
Note that is the statetooutput matrix in the subinterval
when the A/D sampling occurs [interval in the case of the timing diagram in Fig. 1(c)]. Finally, the standard transform
of (2) and (6) gives the desired discretetime controltooutput
transfer functions. Although a buck converter is shown in Fig. 1(a), the results
in Table I are valid for any PWM converter that can be deﬁned
by the statespace description in (1). In addition, although the waveforms in Fig. 1(c) and the discussion above are based on
trailingedge modulation and A/D sampling in interval 2, ex
tensions to other modulation types or other sampling times are
simple. The results in Table I cover both leading and trailing
edge modulation with A/D sampling in either interval 1 or 2. All that is required to derive an exact discretetime model of a digitally controlled PWM converter in CCM is to deﬁne the statespace description in the form of (1). Component losses,
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
TABLE I
DISCRETETIME SMALLSIGNAL MODEL _{P}_{A}_{R}_{A}_{M}_{E}_{T}_{E}_{R}_{S} FOR _{T}_{R}_{A}_{I}_{L}_{I}_{N}_{G} AND _{L}_{E}_{A}_{D}_{I}_{N}_{G} _{E}_{D}_{G}_{E} _{P}_{W}_{M} _{C}_{O}_{N}_{V}_{E}_{R}_{T}_{E}_{R}_{S} IN _{C}_{C}_{M}
input ﬁlters and other converter elements can all be accounted for in the statespace description. The smallsignal model is then obtained from (2) and (6) according to the coefﬁcients in Table I. Such models can be easily deﬁned in matrixbased tools such as MATLAB and used for direct digital controller design. Exten sions to modeling converters in discontinuous conduction mode are not difﬁcult. Examples of direct digital design of proportional, integral, derivative (PID) and higherorder compensators, as well as ex perimental veriﬁcations of digitally controlled converters based on the discretetime model presented in this letter have been dis cussed in [14]–[16].
III. MODEL EXAMPLE AND VERIFICATION
As an example, consider the buck converter of Fig. 1(a) with
Note that only the output voltage is used in (10) since the primary interest is in solving the controltooutput voltage transfer function. Additional outputs could be easily deﬁned based on the desired transfer function (e.g., inductor current). The description of (7)–(10) can then be used to deﬁne the exact smallsignal model according to (2), (6), and Table I in a soft ware tool such as MATLAB. In addition, approximate closed form expressions can be derived to gain insight into the effects of system parameters, including the control loop delay . As an example, in order to simplify the analysis, losses are neglected except for the dominant effect of the capacitor ESR,
, in (9). Resulting simpliﬁed equations for and are given by
(11)
(12)
Approximate expansions of the matrix exponentials in (14) and (15), such as or the alternatives proposed in [17], can be employed to obtain an approximate closedform an alytical discretetime model. Using the approximation
, the standard
transform of (13) and (16) yields the
controltooutput transfer function in closed form
(17)
where the numerator and denominator polynomials in (17) are shown in Table II. Results are shown for the ideal (no losses)
buck converter and the ideal boost converter with A/D sampling
in interval 1 or in interval 2. Further discussions related to boost
or ﬂyback converters with capacitor ESR can be found in [16].
Note in all cases that the zeros of the discretetime controlto
output voltage transfer functions depend on the total delay in
the control loop, while the poles are not affected by the delay.
For the nonideal buck converter, it is also interesting to note that
the capacitor ESR does not add another zero. Rather, it just shifts
the zero in the direction opposite to the effect of . Fig. 2 shows
the magnitude and phase responses of for the buck con
verter with the parameters deﬁned earlier at the nominal
16 m for 0, 0.5 , and . The delay effects, which are clearly visible, especially in the phase responses, must be taken into account in the design of highperformance digital controllers.
The model results are also shown in Fig. 3 at
0.5
and compared to an independent method of frequency response
identiﬁcation. The comparison was generated by performing
a switching level timedomain simulation in Simulink and in
jecting perturbation signals on the steadystate duty cycle for crosscorrelation based system identiﬁcation, as described in
[18]. The simulation was performed using the buck converter
parameters deﬁned above, a delay element to adjust
according
to Fig. 1 (interval 2 sampling) and no quantization in the PWM
or output signal sampling. The samples (dots) obtained through
transient identiﬁcation are exact matches to the smallsignal
model (17), as shown in Fig. 3.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
TABLE II
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POLYNOMIALS FOR APPROXIMATE BUCK AND BOOST CLOSEDFORM CONTROLTOOUTPUT _{T}_{R}_{A}_{N}_{S}_{F}_{E}_{R} _{F}_{U}_{N}_{C}_{T}_{I}_{O}_{N}_{S} _{(}_{T}_{R}_{A}_{I}_{L}_{I}_{N}_{G} _{E}_{D}_{G}_{E} _{P}_{W}_{M}_{)}
Fig. 2. Magnitude and phase responses of 
for the digitallycontrolled
,
.
16 m , for three 1 MHz, 0.5 
Fig. 
3. 
Comparison of modelbased 
(line) to identiﬁcation results 

buck converter example operating at values of the total delay : 0, 
(dots) for the digitallycontrolled buck converter example operating at 1 MHz,
0.5 , 16 m . 

IV. CONCLUSION
The letter presents an exact smallsignal discretetime model for digitally controlled dc–dc converters. The model, which is based on wellknown approaches to discretetime modeling and the standard transform, takes into account sampling, modu lator effects and delays in the control loop. Complete models are derived that can be used for any leading or trailing edge PWM converter operating in continuous conduction mode and with a single A/D sampling instant per switching period. The models can be used directly in software tools such as MATLAB for system analysis and direct digital compensator design. Approx imate closedform controltooutput responses are derived for buck and boost converters, with either trailingedge or leading edge PWM, and arbitrary A/D sampling instants. A model ex ample is given for a buck converter to illustrate the effects of controller delay and the capacitor ESR. The model is veriﬁed in simulation using an independent system identiﬁcation approach.
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