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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

Small-Signal Discrete-Time Modeling of Digitally Controlled PWM Converters

Dragan Maksimovic, Senior Member, IEEE, and Regan Zane, Senior Member, IEEE

Abstract—The letter presents an exact small-signal discrete-time model for digitally controlled pulsewidth modulated (PWM) dc–dc converters operating in constant frequency continuous conduc- tion mode (CCM) with a single effective A/D sampling instant per switching period. The model, which is based on well-known approaches to discrete-time modeling and the standard -trans- form, takes into account sampling, modulator effects and delays in the control loop, and is well suited for direct digital design of digital compensators. The letter presents general results valid for any CCM converter with leading or trailing edge PWM. Specific examples, including approximate closed-form expressions for control-to-output transfer functions are given for buck and boost converters. The model is verified in simulation using an independent system identification approach.

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of

Index Terms—DC–DC converter, digital control, discrete-time model, pulsewidth modulation (PWM) converter, small-signal model.

I. INTRODUCTION

  • D ISCRETE-TIME modeling of dc–dc switching converters has had a long history of contributions, starting from [1].

Effects of sampling due to the pulse-width modulator in the con- text of averaged small-signal models and standard analog con- trollers were discussed in [2]. Extensions of discrete-time mod- eling have included generalizations to various analog control techniques including constraint modulations [3], [4], as well as applications to computer-aided modeling and simulations [5], [6]. Exact continuous-time small-signal converter models have been developed based on a combination of discrete-time models and the concept of equivalent hold [7]. Recently, the growing in- terest in practical digital control for high-frequency dc–dc con- verters has prompted renewed interest in discrete-time analysis and modeling [8]–[12] to facilitate direct digital compensator design. In a digitally controlled constant-frequency pulsewidth modulated (PWM) converter, an example of which is shown in Fig. 1(a), the output voltage error is sampled by an A/D con- verter. A discrete-time compensator computes a duty-cycle con- trol signal for a digital pulse-width modulator (DPWM). Dis- crete-time models suitable for sampling rates lower than the switching frequency have been discussed in [8]. Sampling rates equal to or even exceeding the switching frequency are now practical, with dynamic performance dependent on control-loop delays [10]–[12]. As noted in [10], the previously derived dis- crete-time models describe the behavior of the control variable

Manuscript received May 10, 2007; revised June 19, 2007. This work was supported through the Colorado Power Electronics Center. Recommended for publication by Associate Editor R. Teodorescu. The authors are with the Colorado Power Electronics Center, Electrical and Computer Engineering Department, University of Colorado, Boulder, CO 80309-0425 USA (e-mail: maksimov@colorado.edu; zane@colorado.edu). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2007.909776

and the converter states at a particular instant during a switching period (e.g., at a beginning of the switch on-time [3], [4]). There- fore, these models are not directly applicable to digitally con- trolled converters where the A/D sampling instants can occur

at any time during a switching period. To address this problem, a frequency-domain approach based on Laplace-domain modu- lator modeling [13] and the modified -transform has been de- scribed in [10]. This approach results in an exact discrete-time model that correctly takes into account sampling, modulator ef- fects and delays in the digital control loop. However, according to [10], the approach is straightforwardly applicable only to buck-type converters. The purpose of this letter is to show how the well-known dis- crete-time modeling [1]–[4] can be extended to take into ac- count the sampling, modulator effects and delays in a digitally controlled converter. The result is an exact small-signal dis- crete-time model applicable to any constant-frequency PWM converter. Section II describes the modeling approach. Model examples and verification results are presented in Section III. Conclusions are given in Section IV.

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of

II.

DISCRETE-TIME MODELING WITH DIGITAL CONTROLLER SAMPLING AND DELAYS

Fig. 1(a) shows a dc–dc converter (e.g., a buck converter) with digital voltage-mode control. In the discussion, without loss of generality, a sensing gain of 1 is assumed together with a constant-frequency trailing-edge PWM having an equivalent saw-tooth amplitude 1. The converter operates in contin- uous-conduction mode. In each state of the switch (1 or 2), the converter circuit is linear, time-invariant, with the corresponding state-space description

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of

(1)

where is the vector of converter states (e.g., inductor current and capacitor voltage, ). We assume the input voltage

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
  • is constant, since the primary interest is in the control-to- output responses. The A/D converter samples the output voltage error at the sampling rate equal to the switching frequency . The error signal samples are processed by a discrete-time compensator

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
  • . The compensator output samples control the switch duty cycle via a digital pulse-width modulator (DPWM). This modulator can be viewed as a D/A converter including a sample- and-hold followed by signal sampling at the modulated edge [2]. It is important to note that there are two samplers in the feed- back loop: A/D sampling of the error voltage, and the modulator sampling. As a result, the system small-signal model does not include a sample-and-hold. Instead, the relationship between the small-signal perturbations of the voltage error signal and the duty-cycle includes a delay between the A/D sampling

2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of
2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Small-Signal Discrete-Time Modeling of

0885-8993/$25.00 © 2007 IEEE

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

2553

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

Fig. 1. (a) Switching dcdc converter with digital voltage-mode control. (b) Small-signal model of the digitally controlled dcdc converter. (c) Waveforms illustrating discrete-time model derivation for the digitally controlled dcdc converter with A/D sampling during interval 2.

  • , the derivation of

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

is not necessary. We simply pro-

ceed with the discrete-time model derivation according to the waveforms shown in Fig. 1(c). These waveforms are shown for the specic case of trailing edge modulation and the A/D sam- pling in interval 2 . The small-signal dis- crete-time model can be written as

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

(2)

where the matrix and vector coefcients can be solved by propa- gating the effect of each perturbation during the converter switch

states according to (1) and Fig. 1(c). Consider first the effect of only a perturbation 1
states according to (1) and Fig. 1(c). Consider first the effect of
only a perturbation
1 of the states. Starting from the A/D
sampling at 1 , the perturbation 1 propagates
through switch state 2 for , state 1 for , and fi-
nally state 2 for
. Therefore, the resulting perturbation
after one period
is given by
(3)
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

where is the steady-state duty ratio. Next, consider only the effect of perturbation in the duty cycle. The initial per- turbation in the states occurs at the modulation edge of the PWM output signal and can be found from (1) as linear exten- sions of the previous and next switch states

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
(4) where instant, are the steady-state states at the PWM sampling . The perturbation then propagates
(4)
where
instant,
are the steady-state states at the PWM sampling
. The perturbation then propagates
through the system over the remaining part of the switching
period, which is in switch state 2 for
. The resulting

matrix and vector coefcients for the model (2) are given in

Table I, where and
Table I, where
and

(5)

The output state-space equation can be added according to (1) as follows:

at and the modulator sampling at , as shown in Fig. 1(b), and illustrated by the waveforms in Fig. 1(c). The total delay in the control loop includes the A/D conversion time, the computation delay (i.e., the time it takes to compute the duty-cycle control signal ), as well as the modulator delay (i.e., the time between the update of and the switch transi- tion from state 1 to state 2). In the discussion that follows, we as- sume that the total delay is shorter than the switching period ,

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
  • 0 . Inclusion of the delay in the discrete-time model presented here is the key extension compared to the models in

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

[1][4].

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

As shown in the model of Fig. 1(b), the samples af- fect the converter state perturbations through the equivalent hold which models the converter responses between the samples, leading to exact continuous-time models [7]. Since the digital control system only operates on the values of the state variables or the outputs sampled at the A/D sampling instants

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

(6)

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

Note that is the state-to-output matrix in the subinterval

when the A/D sampling occurs [interval in the case of the timing diagram in Fig. 1(c)]. Finally, the standard -transform

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553 Fig. 1. (a) Switching

of (2) and (6) gives the desired discrete-time control-to-output

transfer functions. Although a buck converter is shown in Fig. 1(a), the results

in Table I are valid for any PWM converter that can be dened

by the state-space description in (1). In addition, although the waveforms in Fig. 1(c) and the discussion above are based on

trailing-edge modulation and A/D sampling in interval 2, ex-

tensions to other modulation types or other sampling times are

simple. The results in Table I cover both leading- and trailing-

edge modulation with A/D sampling in either interval 1 or 2. All that is required to derive an exact discrete-time model of a digitally controlled PWM converter in CCM is to dene the state-space description in the form of (1). Component losses,

2554

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

TABLE I

DISCRETE-TIME SMALL-SIGNAL MODEL PARAMETERS FOR TRAILING AND LEADING EDGE PWM CONVERTERS IN CCM

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

input lters and other converter elements can all be accounted for in the state-space description. The small-signal model is then obtained from (2) and (6) according to the coefcients in Table I. Such models can be easily dened in matrix-based tools such as MATLAB and used for direct digital controller design. Exten- sions to modeling converters in discontinuous conduction mode are not difcult. Examples of direct digital design of proportional, integral, derivative (PID) and higher-order compensators, as well as ex- perimental verications of digitally controlled converters based on the discrete-time model presented in this letter have been dis- cussed in [14][16].

III. MODEL EXAMPLE AND VERIFICATION

As an example, consider the buck converter of Fig. 1(a) with

trailing edge PWM and: 5 H, 25 m , 5 F, 16 m , 1 ,
trailing edge PWM and:
5
H,
25 m
,
5
F,
16 m
,
1
,
10 V,
1 V,
0.2,
1
1 MHz. In the buck converter,
,
are given by
0,
,
,
0. The coefficients in (1)
(7)
(8)
(9)
(10)

Note that only the output voltage is used in (10) since the primary interest is in solving the control-to-output voltage transfer function. Additional outputs could be easily dened based on the desired transfer function (e.g., inductor current). The description of (7)(10) can then be used to dene the exact small-signal model according to (2), (6), and Table I in a soft- ware tool such as MATLAB. In addition, approximate closed- form expressions can be derived to gain insight into the effects of system parameters, including the control loop delay . As an example, in order to simplify the analysis, losses are neglected except for the dominant effect of the capacitor ESR,

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

, in (9). Resulting simplied equations for and are given by

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

(11)

(12)

for , . The model (2), (6) and Table I then simplify to (13) (14) (15)
for
,
. The model (2), (6) and Table I then
simplify to
(13)
(14)
(15)
(16)

Approximate expansions of the matrix exponentials in (14) and (15), such as or the alternatives proposed in [17], can be employed to obtain an approximate closed-form an- alytical discrete-time model. Using the approximation

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

, the standard

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

-transform of (13) and (16) yields the

control-to-output transfer function in closed form

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

(17)

where the numerator and denominator polynomials in (17) are shown in Table II. Results are shown for the ideal (no losses)

buck converter and the ideal boost converter with A/D sampling

in interval 1 or in interval 2. Further discussions related to boost

or yback converters with capacitor ESR can be found in [16].

Note in all cases that the zeros of the discrete-time control-to-

output voltage transfer functions depend on the total delay in

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

the control loop, while the poles are not affected by the delay.

For the nonideal buck converter, it is also interesting to note that

the capacitor ESR does not add another zero. Rather, it just shifts

the zero in the direction opposite to the effect of . Fig. 2 shows

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

the magnitude and phase responses of for the buck con-

verter with the parameters dened earlier at the nominal

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

16 m for 0, 0.5 , and . The delay effects, which are clearly visible, especially in the phase responses, must be taken into account in the design of high-performance digital controllers.

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

The model results are also shown in Fig. 3 at

  • 0.5

2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE I D ISCRETE

and compared to an independent method of frequency response

identication. The comparison was generated by performing

a switching level time-domain simulation in Simulink and in-

jecting perturbation signals on the steady-state duty cycle for cross-correlation based system identication, as described in

[18]. The simulation was performed using the buck converter

parameters dened above, a delay element to adjust

  • according

to Fig. 1 (interval 2 sampling) and no quantization in the PWM

or output signal sampling. The samples (dots) obtained through

transient identication are exact matches to the small-signal

model (17), as shown in Fig. 3.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

TABLE II

2555

POLYNOMIALS FOR APPROXIMATE BUCK AND BOOST CLOSED-FORM CONTROL-TO-OUTPUT TRANSFER FUNCTIONS (TRAILING EDGE PWM)

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE II 2555 P OLYNOMIALS
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE II 2555 P OLYNOMIALS
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE II 2555 P OLYNOMIALS

Fig. 2.

Magnitude and phase responses of

for the digitally-controlled , . 16 m , for three 1 MHz, 0.5

for the digitally-controlled

, .
,
.

16 m , for three

1 MHz,

0.5

Fig.

3.

Comparison of model-based

(line) to identi fi cation results

(line) to identication results

buck converter example operating at

values of the total delay

buck converter example operating at values of the total delay : 0,

:

buck converter example operating at values of the total delay : 0,

0,

(dots) for the digitally-controlled buck converter example operating at

(dots) for the digitally-controlled buck converter example operating at 1 MHz, 0.5 , 16 m .

1 MHz,

(dots) for the digitally-controlled buck converter example operating at 1 MHz, 0.5 , 16 m .

0.5

,

16 m .

 

IV. CONCLUSION

The letter presents an exact small-signal discrete-time model for digitally controlled dcdc converters. The model, which is based on well-known approaches to discrete-time modeling and the standard -transform, takes into account sampling, modu- lator effects and delays in the control loop. Complete models are derived that can be used for any leading or trailing edge PWM converter operating in continuous conduction mode and with a single A/D sampling instant per switching period. The models can be used directly in software tools such as MATLAB for system analysis and direct digital compensator design. Approx- imate closed-form control-to-output responses are derived for buck and boost converters, with either trailing-edge or leading- edge PWM, and arbitrary A/D sampling instants. A model ex- ample is given for a buck converter to illustrate the effects of controller delay and the capacitor ESR. The model is veried in simulation using an independent system identication approach.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE II 2555 P OLYNOMIALS

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