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Unit - I
1. The ICs can operate over a _____________ range of voltages.
a) 3 to 30 b) 4 to 40 c) 5 to 5o d) 6 to 60
2. The No. of transistors in a chip developed under VLSI technology ____________.
a) 1-100 b) 100-1000 c) 1000-100000 d)100000-1000000

3. The diffusion of impurities is usually carried out at _________________ temperature to obtain
the desired doping profile.
a) 1000-1200 b) 1200-1400 c) 1400-1600 d)1600 -1800

4. The metal layer deposition for the interconnection process is done via ___________ process.
a) sputtering b) oxidation c) metalization d)none

5. In __________________ region channel is strongly inverted and the drain current flow is ideally
independent of the drain source voltage.
a) cut-off b) non saturated c) saturated d)none

6. The thickness of the disc in the nMOS process is ______________microns.
a) 500 b) 600 c) 700 d)800

7. The direct contacts between lower polysilicon layer and the moat are termed as ___________.
a) burried b) stripping c) poly d)none

8. Kinetic SIO2 growth at _________________ temparartue
a) 800 -900 b) 1400-1600 c) 700-1300 d)none

9. ___________________ is the process of introducing controlled amount of dopants into
a) diffusion b) saturation c) cutoff d)none

10. _________________________ is the process of introduction of high energy charged particles
into substrate.
a) ion implantation b) saturation c) cutoff d)none

Unit - II
1. The aspect ratio is _______________ proportional to channel resistance.
a)channel resistance b) channel capacitance c) channel inductance d)none

2. In CMOS and nMOS logic circuitry, the basic element is __________
a) resistor b) capacitor c) inductor d)all

3. The inverter has ______________ noise margins.
a) low b) high c) medium d)very high

4. _____________________ is the aspect ratio.
a) L/W b) W/L c) R/C d)C/R

5. The figure of merit of MOS transistor is given by _________________

6. The fabrication process parameter () is given by___________________.

7. The inverter has __________________ input impedance.
a) low b) medium c) high d)very high

8. The channel capacitance cg = ____________________.

9. The induced charge Qc = _______________________.

10. The transit time ds = ___________________.
a) L/V b) V/L c) LC d)L/C

Unit - III
1. The system design process starts with system specification called as ___________________.
a) Topdown b) Downtop c) Medim d)None

2. The bottom layer is a sheet of insulator on a base material called as _____________.
a) Substace b) MOS layer c) Bottom layer d)None

3. Generally the Sio2 is known as ________________.
a) Quartz glaa b) Bronze glass c) Light Glass d) None

4. In _____________based design rules all rules were defined in terms of single parameter.
a) b) c) both d) None

5. The spacing between two electrically separated active diffusion regions in 2m CMOS design is
a) 2.5 b) 2.6 c) 2.7 d)2.8

6. The design rules must be simplified in order to reduce the ______________ required in
designing layout.
a) cost b) time c) complexity d)all

7. The more IC is scaled, the higher becomes its _______________.
a) performance b)packing density c) cost d) all

8. The electric field in the constant voltage scaling is ______________________ proportional to
feature length.
a) Directly b) indirectly c) no relation d) none

9. The constant field yields the largest reduction in the power delay product of ____________
a) single b) double c) three d) many

10. Inverters and inverter based logic comprise a ________________ structure.
a) pull up b) pulldown c) any d) none

Unit - IV
1. Logic gates are created using set of __________________ switches.
a) uncontrlled b) controlled c) individual d)all

2. MOSFETS are intrinsically ______________ devices.
a) electrical b) elctronic c) magnetic d) all

3. In CMOS output always produces ___________operation acting on input variable.
a) and b) or c) not d)nand

4. De Morgans law ___________.

5. Transmission gate is constructed by connecting nMOS and pMOS __________________.
a) perpendicularly b) parlelly c) vertically d) any

6. The switch transmits logic 0 and logic 1 equally well from source to drain is called as __________
a) reflection gate b) forwarded gate c) transmission gate d) all

7. The sheet of resistance is a measure of resistance of ______________ that have a uniform
a) thin film b) thik film c) mass film d) none

8. The overall propagation for n sections in pass transistor chain is ________________.

9. The width factor increases, the capacitive load presented at the inverter input
a) increases b) decreases c) stable d) not dependent

10. In bipolar transistor Ic is __________________ to vbc.
a) exponential b) parabolic c)directly proprtional d) none

Unit - V
1. Barrel shifter produces n output bits and accepts ___________ data bits.
a) 5n b) 4n c) 2n d) 3n

2. Shifting is required during ______________arithmetic.
a) fixed point b) floating point c) binary d) all

3. The n bit adder built from n one bit address is called________________.
a) full adder b) half adder c) carry select d) ripple carry

4. ________________________ is the best known method for speeding up accumulation.
a) wall trace b) wooley c) array d) all

5. Odd Parity generator detects whether the number of ones in an input word is _______.
a) even b) odd c) same d) no relation

6. A counter whose output can change at varying times with respect t the clock edge is known as
______________ counter.
a)synchronous b)asynchronous c) multiple d) all

7. The three transistor circuit is used as simplest dynamic ________________ cell.
a) DRAM b) SRAM c) PROM d) all

8. CMOS system design involves partitioning the system in to _________________.
a) subsytem b) different systems c) unworkable d) parts

9. The Booth Recording multiplier reduces the number of adders by examining a _____________
of bits at a time.
a)singularity b) plurality c) multiple d) any number

10. The I/O subsystem is responsible for ____________________.
a) communication b) controlling c) execution d) all

Unit - VI
1. ASIC is useful for high volume ______________.
a) no production b) high production c) implementation d) all

2. _________________ are known as standard cells.
a) AND b) NAND c) XOR d) all
3. Standard cells design allows the _______________ of the process of assembling ASIC.
a) Automation b) discontinue c) both d) none
4. The logic cells in a gate array library are often called ______________.
a) macros b) symbols c) levels d) formats
5. A structured gate array can be either ____________________.
a) channeled b) channel less c) both d) none
6. FPGA is usually larger and complex than ____________.
a) ASIC b) PLD c) PROM d)all
7. The PLA structure can be realized in ___________ technology.
8. FPGA is a block of __________________.
a) Program logic b) PLA c) PROM d) PLD
9. Expand plice. _______________________________.

10. In antifuse technology the no.of gates are ________________
a) 10-100 b) 120-1200 c)150-1400 d)all

Unit - VII
1. Synthesis is the process f constructing _______________ form model of circuit.
a) gatelist b) resistor list c) capacitor list d)none
2. _____________________ is the process of converting unoptimized boolean description to PLA
a) flattering b) factoring c) mapping d)none
3. __________________ is the process of adding intermediate terms to add structure to
4. a) flattering b) factoring c) mapping d)none
5. _______________________ technique involves dividing modules into sub modules .
a) divide b) conquer c) both d)none
6. ________________means hierarchical decomposition of large system.
a) regularity b) modularity c) locality d)none
7. Multiplexers can be synthesized using _____________ statements.
a) if b) case c) switch d)all
8. ________________ are used to control the output of optimization process.
a) capacitors b) resistors c) constrains d)attributes
9. _________________are used to specify the design environment.
a) capacitors b) resistors c) constrains d)attributes
10. ___________________specifies the control resistance.
a) drive b) capacitor c) resistor d)all
11. ____________________ holds all the information necessary for synthesis tool.
Unit - VIII
1. YIELD is defind as ______________________.

2. ________________ fault corresponds to shorting of certain number of primary input lines.
a) input bridging fault b) feedback bridging c) both d)none
3. __________________ occurs if there is a short between output and input line.
4. a) input bridging fault b) feedback bridging c) both d)none
5. ______________________ occurs due to break in the transistor.
a) input bridging fault b) feedback bridging c) stuck -open d)none
6. ____________________is the measure of ease of setting the node to 0 or 1 state.
a) fault simulation b) fault coverage c) controllability d)none
7. ___________________is the measure of goodness test program.
a) fault simulation b) fault coverage c) both d)none

8. Expand ATPG ___________________________
9. _____________ combines all the collection of tricks and techniques.
a) ad-hoc testing b) fault coverage c) both d)none
10. Expand BIST______________