Optimized Complementary 40V Power LDMOS-FETs Use Existing Fabrication Steps
In Submicron CMOS Technology
Taylor Efland, Theresa Keller, Steve Keller, J ohn Rodriguez Power ICs CustomAutomotive, PRISM Productization Texas Instruments Incorporated Dallas, Texas, USA Abstract This paper discusses development of state-of-the-art complementary isolated lateral 40V rated power MOSFETs. The goals 01 this project were to provide BV specific devices for use with an existing merged VLSI technology. Devices meeting this goal were fabricated in a production manufacturing envirorunent with no extra cost added to the process. The p-channel I ET has a BV=60V, and R,=2.71 mi2 cm2 @V,=lSV, and for the n-channel E T , BV47V and K,,=0.67 mn cm2 @V,=lSV. These devices are seen to be very competitive solutions with advanced integral on-chip intelligence Introduction Diverse applications requiring more intelligent and area efficient PICS have Icd to the development of BV specific power components because of the well-known relationship of BV to specific &con,, (l i sp), that is, as BV decreases so does R5,. Previously it wi14 considered that possibly a medium 60V and higher 80V rated power part would cover most applications. In fact they will; however, the rising cost of modern technology and a competitive market now demands lower price for equal or better performance. Since the outputs consume thelargest percentage of area on power ICs, then, it makes sense to provide power devices that have a BV tailored specifically to the application needs if possible. A large group of the applications involving general motor driving has a voltage requirement of less than 40V; one such cxample would be a printer motor driver. A 50% decrease in K,, is realized for an optimized 4OV LDMOS device over a h0V 1,DMOS device. The significantly lower Rsp results in huge area savings on the IC which leads to higher die yield per wafer and hence reduced cost. Of course it would also be preffered if the lower BV and Ksp could be achieved without additional process costs. The approach taken for this work was to produce at least 40V rated BV, minimum pitch compe titive power components having full compatibility with existing submicron technology without adding process cost. Device Description [Ire 40V rated devices discussed in this work were integrated into TIS modular microcontroller and DSP based PRISM technology using a scaleable p-epi based, submicron merged CMOS(2 process. These devices are manufactured using 1p.mlayout rules and the standard process flow without additional steps. They can be used along side the 60V and 80V3 existing power LDMOS components. Taking advantage of VLSI processing yielded minimum pitch devices with minimumfield oxide thickness and 500A gate oxide. Both devices take advantage of the existing 60V LDMOS high voltage n-well (HVn) to provide isolation from other circuitry. The 60V LDMOS design (shown in figure l a for reference) is further modified with the combinational use of the available low voltage CMOS n and p type wells to produce the new devices. A minimum geometry nitride opening at the LOCOS field Si02 level yields a necessary bubble of oxide that is sufficiently thick to avoid deep depletion BV while providing good field plating for the required BV condition. An SEM of such a region is illustrated in figure 2. A cross-section of the 40V n-channel FET (&ET) is shown in figure lb. This device is produced by scaling down the drift length of the existing 60V LDMOS structure and adding LVn to the drift region. LVn being much higher doped than HVn results in a significant reduction in the lateral drift resistance. The layout position of LVn with respect to the LOCOS region was varied in the experiment to determine its effect on breakdown. The p-channel FET @?ET) is a drain extended RESURF(4 device and is shown in the cross-section of figure IC. The pFET drain extended RESURF, drift region is composed of the LVp region used in conjunction with the p-type, channel stop (CS) diffusion; the latter of which is self aligned to the LOCOS bubble of field oxide. The I Nn forms the bodykhannel region of the pFET. Since the surface doping N(s) is relatively low for the IWn, the low voltage logic n- well (LVn) is added to the body region and spaced relative to the p+source diffusion. The LVn is allowed to penetrate laterally beyond the source into the channel, and because of its higher concentration, provides a higher VT. The increased channel doping allows for a shorter channel length while preventing premature source to drain punch-through. The combination of LVn and HVn results in a split channel diffusion. 16.2.1 0 7803-2111-1 $4 00 1994 IEE:E I EDM 94-399 I HV-n-well I p-epi / p-substrate L- I S (1 n p-epi / p-substrate L- I S G D I HV-n-well In I I h \ l p-epi I p-substrate I S D W-n- well p-epi I psubstrate ( c ) , Figure 1. (a) Existing 60V LDMOS built in high voltagen-tank in pepUpsubstrate material. Thefield length ld (drift region length) is scaled down for the lower voltage devices. @) nFET devicewith LVn added to the drift region and variable spacing Lo (LVn extending into LOCOS). (c) pFET devicewith added LVn and LVp. Variablespacing lc (LVn space to channel) and lp (LVp space to source moat) are shown. Figure 2. SEM photograph of mmmum lpm oltnde opemg LOCOS StO: formahon for mehum voltagecapability. Data and Discussion Averaged manufacturable device data processed in a production facility is featured. Layout spacing of the complementary low voltage p-channel, n-type (LVn) and n-channel, ptype (LVp) logic wells were varied to optimize Rsp and BV. The relationship of BV and Rsp of the nFET to the alignment of LVn extending into LOCOS (In, figure lb) was studied, and averaged experimental results are displayed in figure 3.. Since surface walking BV was not observed it is assumed that BV occurs in thecurvature region of the junction caused by the vicinity of the more heavily doped LVn well. As the LVn is moved away from thep-well the field is decreased and BV increases. Interestingly because of the BV mechanism, the srructure exhibits voltage scaling with LVn spacing; a feature that was believed to exist only in RESURF devices. Rsp as expected follows the increasing / decreasing trend with BV. The increase in Rsp is a result of the decreasing ratio of lower resistive LVn to the higher resistive HV-n-well. Rsp and BV vs LVn best performance for a manufacturable device with BVAOV is at BV=47V and R,=0.67 mSZ.cm2@V,=15V. Since this device is based on the existing 60V LDMOS, the channel is fixed and therefore 0.76 , 48.0 0.74 0.71 -5 0.69 0.66 0.64 2 0.61 0.59 0.56 v 45.5 43.0 40.5 E 38.0 3 33.0 30.5 28.0 35.5 g -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 In (pn) LVn extending into LOCOS S=120 mVIdec, V~ d . 2 5 V Figure 3. Averaged experimental & and BV dependence of the nFET on the higher concentration LVn extending into the field oxidewith respect to thedrain. the subthreshold slope S and VT remain fixed as shown in the caption. A micro photograph of this particular device type being designed into an intelligent IC (general purpose motor driver) in an H-bridge configuration along side the Figure 4. A piece of an IC shows 4 of the 4OV rated nFETs representative of this work configured as an H- bridge (top) and integrated along side 60V LDMOS (bottom). 16.2.2 400-LEDM 94 62.0 1 I 59.5 ! (a) -0.5 -0.25 0 0.25 0.5 ,- -2.3 3.05 3.00 2.95 h 3 1: 2.90 E pz" 2.85 2.80 v 2.75 -2.1 ....... ........ .................... ............ -0.9 .................. ..... s.. ........ .:. .............. .:. .; ................... -0.5 -0.25 0 0.25 0.5 IC (pm) LVn space to channel ( IP (pm) LVP space to source moat) (11) Figure 5 (a)Averaged expenmental BV, and @) & @ V,=lSV, V,, S for thepFET is shown vs layout parameters. existing 60V LDMOS is shown in figure 4. The graph shown in figure 5b relates the two major %, , , components (drift and channel) for the lateral pFET. Experimental RJp of the pFET was found to decrease as the LVn spacing to the channel inaeases. Raising the peak n- type, channel concentration (decreasing IC spacing) results in an increasing VT; this further results in a significant performance loss to the channel region of the pFET because b is V,-VT dependent. This trend indicates a dominance of the channel region resistance component due to the lower p-channel inversion mobility. For a given LVn spacing, the drift concentration is increased as LVp encroaches on the source side of the field oxide region (lp decreasing), and as expected Rsp shifts downward. As the graph indicates, the Rsp is dominated by the effects of the channel doping on VT until the drift region resistance is substantially reduced (lp=0.5 pn). As expected the channel parameters, S and VT, were only seen to decrease with decreased peak channel doping as set by the spacing IC. Figure 5a shows the pFET BVCk, for the same set of layout spacings. BV shifts down as lp increases; this is the normal trend of decreasing BV for decreasing drift length for lateral RESURF devices. The increasing BV with IC spacing is 5 5 5.0 45 4.0 $ 3.0 a 2.5 2.0 1.5 1 .o 0.5 N8 3.5 v 2 4 6 8 10 12 14 16 18 20 Vs. (V) [+VP nFJXT, -V, pFET] Figure6. Experimental Rspvs V, for the nFET and PET. assumed to be a form of enhanced field relief from a lower concentration profile in the channel. Figure 6 shows a comparison of measured Rsp vs V, data for a p and n E T . The nFET has spacing ln=O.O p; the pFET has spacings 1-0.5 pn and 1~0. 5 p. The dominance of the channel region and its inferior inversion mobility is indicative of the sharp increase in Rp for the PET. The nFJ3Tby comparison looks relatively flat at low V,. 70 60 2 50 E 40 9 b.30 E P, 20 10 0 100 80 h a: 60 3 b 40 5 20 0 0 50 100 150 200 250 300 (b) nFET vds (mV) Figure 7. h vs V, charactexistics for typical (a) pFET and (b) nFET axe shown for the same devices featured in figure 6. 16.2.3 IEDM 94-401 10 h v 8 1 d 0.1 10 100 BV (V) (b) Figure S. Curve trawr photographs show BV, for (a) thepFET and (b) fhz nFET The vertical scale IS set at lpA/dlv, and the horizontal scale1 . 7 set at IOV/div. Typical best result IV and BV characteristics for the devices are shown in figures 7 and 8. At V,=15V and Va=350mV, tds=60mA so 1<,=(5.83l2)~(0.466m cm2)=2.71 m0cm2 for the pFET; and at V,=15V and V,h=150mV, I,=87mA so Ksp=( I .72Q)x(0.391m-cm)=0.67 m12.cm2 for the nFET as shown in figure 7a and 7b respectively. Figure 8 shows sharp avalanche type BV&, to be 6OV for the pFET and 47V for the nFET at Ick=l .OpA Conclusion Power devices in the 40V raiige exhibiting excellent electrical performance and complcmentary functionality for switching applications have been manufactured in a production submicron technology. These devices show very competitive performance as can be seen in comparison to previously published work shown for reference (5 ~(6)d7)48)7(g) in figure 9. This IS the first modular submicron VLSI process reported to have a competitive power CMOS capability of Figure9. Graph shows R+, vs BV for previously published values 00 lateral devices as compared to this work. Previous work is number referenced according to decreasing BV. this voltage and resistance range making it very useful for intelligent driver markets. These devices will be able to take advantage of the 0 . 8 ~ minimum feature size offered by the PRISMprocess. Acknowledgments The authors thank Sleve Sutton and Steve IIatch for supporting the addition of these devices to the PRISM technology. We also thank Larry Latham, Steve Kwan, and Mike Smayling for technical input, review, and approval, and very greatly appreciate theoutstanding technical support provided by Margie Campbell, Reba DeBruhl, Charlie Do, Doyle Jackson, Micheal Ogrady, and Lloyd Salter. PRISM, Texas Instruments Technical J ournal (ddicnted issue), 1994, Vol. 1 1, No.2 )M. Smayling, J. Reynolds, D. Redwine, S. Keller, and G. Fallessi, A MODULAR MERGED TECHNOLOGY PROCESS INCLUDING SUBMICRON CMOS LOGIC, NONVOLATILE MEMORIES, LINEAR FUNCTIONS, AND POWER COMPONENTS, IEEE CICC, 1993, pp.24.5.1-24.5.4 13)T. Efland, et al., AN OPTIMIZED RESIJ RF LDMOS POWER DEVICE MODULE COMPATIBLE WITH ADVANCED LOGIC PROCESSES, IEDM, 1992, pp.237-240 4J.A. A pl s and H.M.J. Vaes, HIGH VOLTAGE THIN LAYER DEVICES (RS Wrathall, et al., CHARGE CONTROLLED 80 VOLT LATERAL DESIGNED FOR AN INTEGRATED POWER PROCESS, IEDM, 1990, O.Kwon, et al., OPTIMIZED 60V LATERAL DMOS DEVICE FOR VLSI POWER APPLICATIONS, VLSI Technology Symp, 1991, pp.115-116 M.Hos~~, et al., TOW ON-RESISTANCE POWER LDMOSFET USING DOUBLE METAL PROCESS TECHNOLOGY, ISPSD, 1991, pp.61-64 @.Mei, et al.. A HIGH PERFORMANCE 30V EXTENDED DRAIN RESURF CMOS DEVICE FOR VLSI INTELLIGENT POWER APPLICATIONS, V U1 Technology Symp, 1994, pp.81-82 9M. Morikawa, et al., A 30V 75 mR.irud POWER MOSFET FOR INTELLIGENT DRIVER LSIs, ISPSD, 1992, pp.150-154 (RESURF DEVICES), IEDM, 1979, pp.238-241 DMOSFET WITH VERY LOW SPECIFIC ON-RESISTANCE pp.954-957 16.2.4 402-IEDM 94