40Gbit/s multi-lane distribution interface converter and its application

to cost-effective optical transceiver for 40G SONET/SDH signals

. Aisawaa,
b
, T. Onoa, and w. Tomizawaa,
b
aNTT Network Innovation Laboratories, NTT Corporation, 1-1 Hikari-no-oka, Yokosuka, Kanagawa,
Z'-+J Japan;
b
Photonics Electronics Technology Research Association, 1-1 Hikari-no-oka, Yokosuka, Kanagawa,
Z'-+J Japan
AU1HAL1
We create a 40Gbit/s multi-lane distribution (MLD) interface converter for STM-256 to STL-256.4 and OTU3 to
OTL3.4. We successflly demonstrate a cost-effective optical transceiver for STM-256/0C-768/40G-POS by using our
40Gbitls MLD interface converter prototype.
WcjW0YUS. Multi-Lane Distribution (MLD), interface converter, parallel transmission, STM-256/0C-768, 40Gbit/s
Etheret (40GbE), Optical Transport Network (OTN)
1. DHtLtD
Driven by high defmition video and the penetration of high-speed broadband access, the rising volume of consumer IP
traffc is bolstering the overall IP growth rate, e.g. the IP trafc in Japan nearly tipled fom 2005 (424.5Gbitls) to 2010
(l708.9Gbit/s) [1]. Figure 1 shows Interet trafc in Japan. The growth rate per year ranges fom 20 to 35%. If the
growth of the traffc continues over 10 years, the resultant traffc volume is about 20 times the current trafc. High speed
LAN interfaces such as 40Gbitls Etheret (40GbE) and 100Gbit/s Etheret (lOOGbE) have been standardized to support
huge traffc demands [2]. These standards adopt parallel transmission, which pairs parallel logical lanes with parallel
physical lanes, in order to cost effectively achieve the high speed interfaces needed. ITU-T has defmed parallel
transmission fame structures such as Synchronous Transport Lane 256.4 (STL-256.4) for STM-256, Optical channel
Transport Lane 3.4 (OTL-3.4) for OTU3, and OTL-4.4/0TL-4.l0 for OTU4, in order to realize cost effective
transmission by re-using the optical parallel transmission modules developed for 40GbEil00GbE [3][4]. In the long term,
serial transmission will be the low cost solution, because fewer parts are used in the optical transceiver module and the
power consumption of the module also can be reduced. However, parallel transmission remains the better solution for
near term 40G applications on the metro-access network, since lOG based optical components are now very cost.

U
-
O

M
L
+
Q
E
w
+
C
Z
Jb
Jb
J4
JZ
3
b

4
Z

:.I1b|tlsg2010
@

J
/
f
2g20

Z ZZ Z4 Z Z Z3 ZJZ
|SC8Y88l
Figure 1 Interet trafc in Japan
Optical Transmission Systems, Subsystems, and Technologies IX, edited by Xiang Liu,
Ernesto Ciaramella, Naoya Wada, Nan Chi, Proc. of SPIE-OSA-IEEE Asia Communications and Photonics,
SPIE Vol. 8309, 830925
.
~2011 SPIE-OSA-IEEE
.
CCC code: 0277-786X/11/$18
.
doi: 10.1117112.903893
Proc. of SPIE-OSA-IEEENol. 8309 830925-1
This paper presents a 40Gbit/s multi-lane distribution (MLD) interface converter prototype and its application in a cost
effective optical transceiver for STM-256/0C-768/40G-POS (Packet over SONET). First, we present the confguration
and specifcations of the MLD interface converter. Then, the confguration of a cost effective optical transceiver is
shown. Finally, we present the experiments conducted on an MLD interface converter. We successflly demonstate
40km transmission over SMF using the MLD interface converter prototype and a parallel optical transceiver with STL-
256.4 interface.
Z. +t 1-1^D hHtD DH^L LtDHH
Figure Z shows a schematic diagram of the 40Gbit/s MLD interface converter prototype. It can convert two sorts of
signal transmission fames; one is STM-256/0C-768/40G-POS, and the other is OTU3. That is, STM-256/0C-768/40G
POS fames are converted into STL-256.4 fames and OTU3 fames into OTL-3.4 fames. Conversion between SFI-5.2
[5] and SFI-5.1 [6] is also possible by bypassing the STM256/STL256.4 conversion block and bypassing the
OTU3/0TL3.4 conversion block. The operating mode of the MLD interface converter is selected by register setting via
an exteral controller. Since the SFI-5.1 interface is used at the STM-256/0TU3 fame 110 side, the conventional 40G
SONET/SDH mapper and OTU3 mapper can be effectively used. This prototype has pseudo random bit sequence
(PRES) generation and detection fnctions for both electrical I/O interfaces. Therefore, connectivity between chips can
be evaluated without using dedicated measurement equipment. The de-skew range for STL-256.4 and OTL-3.4 is more
than 180nsec (+/- 2048bit), which satisfes the 40GbEil00GbE standards defned in IEEE802.3ba. The prototype is
fabricated with 65nm CMOS process in the form of a 575 pin BGA package. The package size is 25mm x 25mm. The
supply voltages for the core logic, high speed 110 interfaces, and control interfaces are + l.OV, + l.2V, and +2.5V,
respectively. The power consumption of the prototype is less than 4W in typical operating condition. Table 1
summarizes the specifcations of the MLD interface converter prototype mentioned above. Figure 3 shows the STM-256
fame for serial transmission and STL256.4 fame for four parallel lane transmission. Regarding the STM-256 fame,
38880 blocks, each block has 16byte data, are transmitted as a serial signal. Regarding to the STL256 fame, each 16
byte block signal of STM-256 fame is distibuted to four physical lanes in round-robin manner. In order to distinguish
the lane number, the last A2 byte of 16 A2 bytes is employed as logical lane marker. Since the STM-256 fame has 64
successive Al bytes followed by 64 successive A2 bytes for fame synchronization, afer multi-lane distribution, each
physical lane has 16 successive Al bytes and followed 16 successive A2 bytes [7]. Thus, fame synchronization using
Al and A2 bytes in each physical lane is possible. Since Al bytes and A2 bytes are not scrambled in STM-256 fame,
fame synchronization using Al and A2 bytes is easily executed with simple patter matching. Afer the frame
synchronization process is performed using fame alignment bytes (AI and A2 bytes), de-skew processing and lane re
order processing are carried out using fame alignment bytes. By these three processes (fame synchronization in each
physical lane, de-skew among lanes, and lane re-order processing), the original serial transmission fame (STM-256
fame) is recovered.
_
@
en.
STM26l
@
g.
-
STL26.4
-
-

Z. -
l-b.Z
OOnv
-b.J DS
-
b
-
1XHX 6D|L6 XHX bH|
-
L
-
OTU3l
Lb
-
-
-
OTL3.4 -
-
-
11.2G X
6t. CohV
6t.
2.SG x1T
|
Figure 2 Block diagram of 40Gbit/s MLD interface converter prototype
Proc. of SPIE-OSA-IEEENol. 8309 830925-2
Table 1 Specifcations of MLD interface converter prototype
Items
Target signal
Low speed side interace
High speed side |nterface
2.8G PRBS checker
11.2G PRBS checker
De-skew range 0 M LD
rab. Process
Numberof p|ns
Power supply
Package size
Power (target)
Specifications
STM-256/0C-768(39.8Gbitls)
OTU3(43Gbitls)
STM256/0TU3 with SFI-5.1
STL-256.4/0TL3.4
PHUS gen.UbH1
HUU gen.UbHT
STM256
2048 bit
65nmCMOS
575 pin
1.0V, 1.2V, 2.5V
25mm x 25mm (PBGA)
4W@STM-256
Transmissionorder
4

52(A2) 51(A2) 50(A2) 49(A2) 48(A1) 47(A1) 46(A1) 5(A:j
\
8640 1zz1} 4

3 4 22 z:
864 r sz 64
17280 1zc+ :z 3 : cz zc
: 21600
17284 :72 : 82 17281
zzo 21604 :o 2 02 21601
1uz+u 25 924 z 292 25 921
34560 30244 343 3 z 30241
38880 34564 33 l2 34561
De-kew

5
|
J
r ( r ( s(sz,

+(AJ}

s
|

'
Lane#
\ \
.
6

Z :: [ :r. [ :e(sz, +c(AJ}

l
J
l
c
l
Lane#
b1L-Z.4

7
|
3 38879 j r: j :(sz, +I(A:}
|
:: [ I
|
Lane#
\.
.
8

. ssro [ srtt
l
:z(sz, +s(AJ}
l
12
l
s
|
.
l
Lane#
Figure 3 Interface conversion between STM-256 and STL256.4 fames
. Lth L t1L^1 H^DhLH tH +t-1thlhMlhtD
Figure 4 shows an application of the 40G MLD interface converter in a cost-effective optical transceiver for 40G-POS
signals. At the present time, a 300-pin multi source agreement (MSA) serial transmission based a very short reach (VSR)
module is used as the optical interface of router/L2-SW and is also used as the client interface of 40G long haul (LH)
DWDM systems. By using a standards-based low cost 40GbE parallel transmission optical module to establish
SONET/SDH signal transmission, we can cost effectively confgure a 40G-POS/SDH/SONET transceiver for metro
access regions. Since existing 40G-POS/SDH/SONET mappers have the SFI-5.1 interface, an interface converter
between STM-256 signals, which use SFI-5.1, and STL-256.4 is required. Thus, a low cost optical transceiver for 40G
POS/SDH/SONET can be created by combining the 40Gbit/s MLD interface converter with 40GbE based parallel optics.
By applying lOGbit/s based parallel transmission, the transmission distance can be extended without using a dispersion
compensator. The transmission distance of the conventional 40Gbitls serial transmission module in the l.55 flm band is
limited to 2km due to chromatic dispersion. On the hand, the lOGbit/s 4-lane parallel transmission module uses l.3flm
CWDM. Thus, the waveform distortion due to the chromatic dispersion is reduced.
Proc. of SPIE-OSA-IEEENol. 8309 830925-3
40G
POS
LHDWDM system
Mapper g co::v
:
.
,
: "
: "
1------------------------1 g
Lo cost opical module
:
:
,
L ______________________ : 40G DPSKDOPSK
! Lo cost opical module 40G DP-QPDK
----------------------------------______1 L _________________________________________________________ .
S2
[SLZ.4]
Figure 4 Application of 40G MLD interface converter in low cost optical module
+. 1HD
Figure 5 shows the experimental setup used for 40km SMF transmission. The parallel transceiver consists of a MLD
interface converter and parallel transmission optics with 40GbE-LR4 wavelength compatibility. A serial STM-256 signal
is generated by a 40G SONET/SDH analyzer. The signal output by the analyzer is OlE converted in the OlE conversion
block of the 300-pin VSR tansceiver, and then input into the MLD interface converter via the SFI-5.1 electrical interface.
The serial STM-256 signal is converted into a STL256A signal, which has lOG based 4-lane signals. The resultant
STL256A signal is OlE converted, CWDM-multiplexed, and fnally input into the 40km standard single mode fber
(SMF)[8]. Afer transmission, the CWDM signal is de-multiplexed and then reverse processing is done. Finally, the
regenerated STM-256 signal is input into a 40G SONET/SDH analyzer. This experiment used four SFP+ transceivers
that are wavelength compatible with 40GBASE-LR4. The outut power of each transmitter is + IdBm and the input
power at the receiver is -15dBm. The CWDM multiplexer and de-multiplexer have insertion loss under 2dB. Given these
specifcations of optical components, the acceptable optical power budget is 12dB. When we assume the loss of the
transmission fber is OAdBlm, estimated transmission distance is 30km. In order to confrm the feasibility of the
proposed confguration, the experiment was carried out using a 40km transmission fber.
Figure 6 shows a photograph of the 40km transmission experiment. Four commercially available SFP+ transceivers and
a commercially available integrated CWDM MUX and DEMUX flter were used as the 40GbE-LR4 based optics in this
experiment, in order to confrm the feasibility of the MLD converter prototype. The integrated transmitter optical
subassembly (TOSA) and receiver optical subassembly (ROSA) for 40GBASE-LR4 can be used, and a cost effective
parallel transmission transceiver would be created by combining the MLD converter with integrated TOSA/ROSA for
40GBASE-LR4.
ElOH1
121nm
1.3mm
CDB
ElOH2
1291nm
NUX
STM2561

OlE
|
E
STL2:6.4
ElOH3
1311nm
(40CV5R)
Conv

ElO#
1331nm

40G
SONET/SDH
121nm
H O/EH1
Analyzer

1291nm
E/O
STL256.4

|
O/EH2
I I
SFI-5.1
<
ISTM256
1311nm
[40GN8R)
Tx
Cony |
O/EH3
1.3m
1331nm
CDB

OlE #
DENUX
MLD|lFconveder 40GbE-LRbasedopcs
Costeheclveparalleloptlcaltransce|ver
Figure 5 Experimental setup for 40km SMF transmission with STL-256A format
Proc. of SPIE-OSA-IEEENol. 8309 830925-4
40km
8MF
4U
bLNL1
analyz0f
Figure 6 Photograph of 40km transmission experiment confguration
Figure 7 shows the input and output spectra. At the transmission fber input, the power difference among the four
wavelength channels is very small, less than 1 dB, so no variable attenuators were placed B each channel. At the output
end of the fber, the power difference is about 2dB due to the wavelength dependence of the transmission fber's loss.
The insertion loss of the transmission fber at 1270nm is about UAdB/km. Figure 8 shows a screen shot of the 40G
SONET/SDH analyzer afer 40km transmission. Bit error fee transmission (BER better than 10.
12
) over the 40km SMF
was achieved for more than one hour.
10
0
-10

m
-20
"
-30
j <0
-@0
-60
-70

10
^

r
w

10 10 1320
T
m

+
!
D
1M
10
0
-10
-20
-30
<0
<0
40

-70
10
Le55 ln Z0U
-- ------ --.---- ----- ------ ------- .-----
W ~ ~

10 10 1320
wavo|onqth(om) wavo|onqth(om)
Figure 7 Optical spectra before and afer transmission
Proc. of SPIE-OSA-IEEENol. 8309 830925-5
--
+
1M0
M08SUf0m0Ht Q0fOU. - T hOUf
LH
Alarm IFrae
O
cl|O IRate
O
DISpIaydata Icurrent O
LOS U gDC. 0 l1 U.DEJ2
I Scction P[AU} I
NO0ffOf
LL 0 J U.UL1b
LL Z U.E1
P J U.UL=1O M
Ll 0 Frame U.UL1
Figure 8 Screen shot of 40G SONET/SDH analyzer
b. h^H
We have created a 40Gbitls signal processing LSI prototype that realizes 40Gbit/s MLD interface conversion between
STM-256/0C-768 and STL-256.4, and OTU3 and OTL3.4. We successflly demonstrated a cost-effective 40G optical
transceiver for STM-256/0C-768/40G-POS with transmission over 40km of SMF by using the 40Gbit/s MLD interface
converter prototype.
b. ^LbDt1tD
The part of this work related to high speed electrical interfaces belongs to "Next-generation High-efciency Network
Device Project" assigned to PETRA under contract with New Energy and Industrial Technology Development
Organization (NEDO).
H111H1PL1
[1] Ministry of Interal Affairs and Communications, Japan, Press Release "Estimate of Interet Trafc in Japan,"
(in Japanese) (03/2011) http://www.soumu.gojp/menu_news/s-news/01kiban04_01000006.html.
[2] IEEE802.3baAmendment:Media Access Control Parameters, Physical Layers and Management Parameters for
40 Gb/s and 100 Gb/s Operation (06/2010)
[3] ITV-T Recommendation G.709, "Interfaces for the Optical Transport Network(OTN)", (12/2009)
[4] ITV-T Recommendation G.707 Amendment 2, "Network node interface for the synchronous digital hierarchy
(SDH)", (11/2009)
[5] OIF Implementation Agreement OIF-SFI5-02.0, "Serdes Framer Interface Level 5 Phase2 (SFI-5.2) :
Implementation Agreement for 40Gb/s Interface for Physical Layer Devices", (Oct. 2006)
[6] OIF Implementation Agreement OIF-SFI5-01.0, "Serdes Framer Interface Level 5 (SFI-5) : Implementation
Agreement for 40Gb/s Interface for Physical Layer Devices", (Jan. 2002)
[7] ITV-T Recommendation G.707, "Network node interface for the synchronous digital hierarchy (SDH)",
(12/2003)
[8] ITV-T Recommendation G.652, "Characteristics of a single-mode optical fbre and cable", (11/2009)
Proc. of SPIE-OSA-IEEENol. 8309 830925-6