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Panasonic Flat Screen

Tau
[Tau]
FLAT
DIGITAL
By Jim Urosevic
Panasonic
TAU MD2 New Circuit
Panasonic
MD2 CHASSIS LAYOUT
D7
D11
D12
D13
A1
A2
(D)POWER CIRCUIT
TNPH0234
A11
A25
A26
A3
A12
A9 A10 A13
G1 G2 G3
A6
TO BUS
Adj
(A)MAIN-BORD
TNPH0235
G4
K2
L3
TO X7
L1
TO A15
(L)CRT-DRIVE
TNPA0754
(DG)DIGITAL CORE
TNPA1183
A44
P2
TO D4
L2
A5
TO P3
P3
TO A5
A15
A4
TO(L)
G8 G9
C-SP/R-SP L-SP
L4
TO A4
TNR2
TNR1
P1
TO FBT
B1
A26
B2
TO(X)
TO(DG)
A44
GEOMAG
A8
A24
A24
B1
A32
A33
A31
A14
TO(T)
TO(B2)
T1
T2
T3
A32
A33
A31
H2
A11
A12
H1
(H1)AV-SW
TNPA1182
G10
D6
D8
X1
X2
X3
D4
DY/V
VOUT
D9 DY/H
SOUND-CONTROL/AMP
MPU
(Z)VGA
TNPA0645
(B)MAIN VIF/SIF
TNPA0796
(K)KEY/ GEOMAG
TNPA1184
(G)AV2/HEAD-PHON/SYNC-SEPA
TNPA1181
A25
TO VM-
COIL
(X)DAF
TNPA1180
(P)LINE FILTER
TNPA0753
(T)TEXT
TNPA1185
AC CORD
M.W.
(IC1304)
F43226
2PGJ
M.W.
(IC1304)
F43226
2PGJ
DFU
IC1308
FJB007S
DFU
IC1308
FJB007S

(IC1301)
VPC3215

(IC1301)
VPC3215

(IC1306)
MB87F172
0

(IC1306)
MB87F172
0
DISPLAY
PROCE.
IC1309
TDA9330H
DISPLAY
PROCE.
IC1309
TDA9330H

(IC1307)
SDA925
5E

(IC1307)
SDA925
5E
MN102****
TEXT
SDA5454
TEXT
SDA5454
TEXT
MPU
VPC
VPC3210A
VPC
VPC3210A
H DRIVE
H OUT
2SC5144LB22
8
H DRIVE
H OUT
2SC5144LB22
8
V OUT
LA7845N
(A-Board)
V OUT
LA7845N
(A-Board)
POWER
STRM6831AF0
4
POWER
STRM6831AF0
4
L OUT
TDA7481
L OUT
TDA7481
R DRIVE
TDA6111Q
R DRIVE
TDA6111Q
G DRIVE
TDA6111Q
G DRIVE
TDA6111Q
B DRIVE
TDA6111Q
B DRIVE
TDA6111Q
STANBY
POWER
MIP0210S
Y1TV
STANBY
POWER
MIP0210S
Y1TV
DAF
AN5422K
DAF
AN5422K
VOL . DOUBLE
STR83145LF55
VOL . DOUBLE
STR83145LF55
R
G
B
T board
L board
D board
VM
OUT
HV100
HV50
13.5MHz
27MHz
HV50
R OUT
TDA7481
R OUT
TDA7481
2.8Mbit
MEMORY
2.8Mbit
MEMORY
B board
Y
B-Y
R-Y
OSD R/G/B
V
G
A

H
/
V
Y/U/V
H/V/13.5MHz
C OUT
C OUT
SYNC
PRO.
M52346SP
SYNC
PRO.
M52346SP
H board
J board
MAIN PICTURE
SUB PICTURE
SUB H.P.
AN5265
SUB H.P.
AN5265
G board

CXA2069Q

CXA2069Q
H board
AV1
AV3
AV4
AV4 (DD)YUV
MOUT
G board
AV2
1s

1s

MSP3415D

MSP3415D
B board
BOOSTER
+
1st
TUNER
BOOSTER
+
1st
TUNER
SOUND
CONTROL
AN5295NK
SOUND
CONTROL
AN5295NK

TUNER

TUNER
MPU
MPU
MN102****
BLOCK DIAGRAM OF MD2 CHASIS
BLOCK DIAGRAM OF MD2 CHASIS
VGA
DG board
TEXT R/G/B
DVD Y/U/V
S board
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
31
30
29
28
27
26
25
24
23
22
32
64
63
62
61
60
59
58
57
56
55
45
46
47
48
49
50
51
52
53
54
44
34
35
36
37
38
39
40
41
42
43
33
RMIN
SDA1
SCL1
P03
ADIN1
ADIN2
ADIN3
P07
/IRQ2
ADIN6
P12
P13
M. SP14
PMW0
P16
P17
PWM4
PWM5
P23
SP24
VDD
CREF0
VPH0
VPC
CVBS0
P31
P32
TM21OB
P35
P36
TM2IV
SEARCH&SYNC
VSS
OSC2
OSC1
VDD
P57
P56
P55
P54
/IRQ0
/VSYNC
/RST
P50
/TEST
VCOI
AVDD
YM
VREF
IREF
COMP
B
G
R
YS
VPC
P44
VSS
OSDXI
OSDXO
P40
P37
P41
PDO
P20
MN102L35GTLJ
VSS RMT IN
OSC2 SDA1
OSC1 SCL1
VDD SYNC1
SCL2 AFC1
SDA2 AFC2
TEXT PROTECT
5V DET TEXT ENA.
RMT IN
RESET ENAB
KEY IN
/V SYNC
RESET PROG/FF
PC STATE LED
VDD M. SOUND DEFEAT
VCOI RF AGC1
SOUND DEFEAT PDO
AVDD SIF1
YM SFF2
VREF DAF SW
IREF
VIDEO GAIN
COMP VCR/GAME
B
G VDD
CREF
R
YS VPH
VPC
/RST-DEV
/H SYNC CVBS
VSS RELAY
SRQ
H. FREQUENCY
SOUND AI V.FREQUENCY
BEAM SW
SCL3 SDA3
BUS LINE CONNECTING
IC1101 MPU
SCL3
SDA3
59 60
SDA1/SCL1
33
32
2 3
SDA2/SCL2
IC1301
VPC1
SDA1/SCL1
55 56
IC1307
V.PRO.
SDA1/SCL1
21 20
IC1308
DFU
SDA1/SCL1
9 8
IC1001
EX.DAC
SDA1/SCL1
14 15
IC2401
SOUND
CONT.
SDA1/SCL1
16 15
TNR002
TUNER2
SDA2/SCL2
TNR001
TUNER1
SDA2/SCL2
IC1102
EEPROM
SDA1/SCL1
5 6
IC1302
VPC2
SDA2/SCL2
55 56
IC1304
M.WINDOW
SDA2/SCL2
75 76
IC1306
CIP
SDA2/SCL2
83 82
IC1309
DISPLAY
PRO
SDA2/SCL2
11 10
IC3001
AV SW.
SDA1/SCL1
34 33
IC2001
MSP
SDA1/SCL1
8 7
IC3504
TEXT
SDA1/SCL1
73 74
< A >
< DG >
< H > < B > < T >
M52760SP
B3
A26
8
V
6
A12/
H2
Q160
Q161
IC201
SW
1
2
3
5
20
15
13
11
9
12, 4
VIF/SIF
SIF TRAP
IC101
VIF
4
5
7
11
X180 5.5
TUNER
1
A25
8
Q102
X101
Q104
18
13
10
Q151 X181 6.0
X182 6.5
Q163
AMP
V.
DET
IF
SAW
X183 4.5
BPF
6.0
X204 5.5
X203 6.5
X202
Q140
IC2001
A2
NICAM BG/I
47 24
25
4.5 AMP
IF
DET
SIF
FM
DET
S1/S2 MPU
A2 L (Main L+R)
6
4
B3 A26
NICAM R / A2 R
5
7
A12/
H2
3
2
NICAM L
TUNER 2
V
AUDIO (Mono)
Q051
VIF/SIF
The IF Signal from Tuner 1 is sent to IC101 on the B2 Board. The VIF passes through Buffer
Q102 then through Saw filter X101 (to improve selectivity of the signal) before it is input to pins 4
and 5 of IC101. The SIF signal passes through buffer Q104 and is input to Pin 7 of IC101. Both
Signals are amplified and detected, and the VIF is Output on Pin 18. Due to this Chassis having
21 System capabilities, the VIF signal passes through several sound traps and IC201 selects the
appropriate Sound Trap input (Depending on the command from main MPU on pins 12 and 4 of
IC201). The selected signal is then demodulated and a composite video signal is output on 20 of
IC 201. The Video signal is sent to the H-Board for switching.
The SIF signal is sent to a series of band pass filters and IC201 selects the appropriate filter input
(Depending on the command from main MPU on pins 12 and 4 of IC201). At the same time the
SIF is sent to Pin 47 of IC2001. This IC is a stereo decoder for the NICAM stereo and 2
nd
sound
carrier (A2 R channel) for A2 stereo. Pin 24 is R Out and Pin 25 is L Out. This is sent to H board
for switching.
The A2 left channel (Main sound L+R) is input to pin 11 of IC101, where the signal is detected and
demodulated and output at pin 10. This is sent to Pin 4 of B3 connector and sent to H board for
switching.
The Tuner 2 signal is demodulated within the Tuner and the Video signal is sent to Pin 3 of A12
connector and the Mono (L+R) signal is sent to Pin 2 of A12 connector.
AV SW.
IC1101
MPU
4
A11/H1
SCL1
5 SDA1
6
A12/H2
TV1-V
5 TV1-R
TV1-L 7
3
A12/H2
TV2-V
2 TV2-R&L
AV1 Terminal
14
A11/H1
AV2-V or Y
11 AV2-C
AV2-R 13
15
AV2-L
16 AV2-S
AV2-S1
AV1-V
AV1-Y
AV1-R
AV1-L
AV1-S1
AV1-C
AV1-S
1
3
5
7
6
4
2
TNR002
15 AV3-V
AV3-R
AV3-L
18
16
22 AV4-V
AV4-R
AV4-L
25
23
AV3 Terminal
AV4 Terminal
60
42
10
12
13
11
14
9
33
34
63
29
30
64
62
56
58
54
52
44
47
43
41
40
38
9
26
25
21
7
22
TV MAIN
V or Y
TV SUB
V or Y
C
Monitor Out
V or Y
R
L
Monitor Terminal
H1
A11
30
IC1101 MPU
M Sound defeat
13
L
R
C
H1/A11
AUDIO 18
H1/A11
+ 9 V
IC3001
AV SW.
TNR001
IC3001
IC3001 is the AV switching chip. It switches all of the Tuner and AV Inputs and
supplies 3 Outputs.
Output 1 (Pins 52, 54, 56, 68) Is the A/V Output of the Main Picture.
Output 2 (Pins 43, 44, 47) Is the A/V Output of the Sub Picture.
Output 3 (Pins 38, 40, 41) Is the A/V Output for the Monitor Out terminal. Monitor
Out outputs the same picture and sound as the Main Picture. Monitor out can also
be muted when the MUTE button on the remote control is pressed.
AUDIO CONTROL
8
7 3
IC2401
AUDIO
CONT.
16 15
20
30
1
32
19
SCL SDA
12
IC1101 MPU
35
3
2
Sound AI
SCL
SDA
Q2405
Q2404
Q2402
Q2406
25
H1/A11
26
IC2305
OP AMP
2
10 8
IC2301
AMP
9 1
R
R
A10/G4
7
G
8
5
L
Q2308 A40
3
Q2307
IC2304
OP AMP
2
10 8
IC2301
AMP
9 1
A9/G3
L
G9
A41
3
A8/G2
Head
Phone
IC2303
AMP
12 1
A9/G3
10
G8
1
CENTER
CENTER
AUDIO CONTROL
The L and R signals from the H-Board are input to IC2401 (Audio Control IC). The L and R signals are also
combined to form the center channel (Input to pin 30). This center Channel Output is also returned to MPU
for detection of Music content when the sound menu is set to AUTO. When music is detected, the the MPU
lowers the volume level. This is especially useful when watching a program on TV and a loud musical
Advertisement appears.
This IC is controlled by the MPU via IIC and in turn controls Volume, Bass, Treble, Balance and Surround
Sound effects. The Center Channel is sent to an Audio Amp for out via pin 19 of IC2401.
The L and R outputs (Pins 20,12) are fed to an Op Amp before they are amplified. The reason for this, is the
AFB (Acoustic Feed Back) circuit. Each L and R speaker housing has a microphone attached. The mic.
feeds back the actual sound coming from the speakers back to the Op Amp, where the Actual Audio Signal
and the Heard Audio Signal is mixed, and any distortion is removed to deliver crisp clear audio. The AFB
circuit is always active except when the main Headphone sockets is used. In this case a switch in the
headphone socket itself disables the sound to the amp and disconnects the feedback circuit.
SUB HEADHONES
IC2251
Sub AMP.
16
15
5
A8/G2
2
3 2 8
4
Vol.
H1/A11
SUB HEADHONES signal
18
IC1101 MPU IC1001 EXT
3
2
SCL
SDA
SCL1
Vol. Control
SDA1
The Sound from the sub picture is sent from the AV switching IC directly to the Sub Amp on the G-Board.
The Main MPU controls the the volume via IIC lines connected to IC1001 on A-board.
DG-Board TXNDG10ECU
IC1308
FJB007
DFU
IC1301
(MAIN)
VPC3215CY/C,
SYNC
SEPA
IC1304
F432262PG
Multi Window
IC
13
06
IC1302(SUB)
VPC3215C
Y/C,SYNC
SEPA
IC1307
SDA9255E
100Hz
3M bit
IC1309
TDA
RGB SW
(100Hz or VGA)
IC1305
Memory
IC13
03
CLK (13.5MHz)
MAIN
U50,V50
U50,V50
U50,V50
Y50
Y50
Y50
MAIN
Video
Sync 50
Sync 50
Sync 50
U50,V50
Y50
Y100
U100,V100
V100
MAIN C
SUB
Vide
o
SUB
C
TEXT
TDA9
151
TEXT
RGB
CLAMP
VM OUT
VG
A
IN
VGA
RGB
DVD
IN
Y Pb Pr
A/D
A/D
A/
D
D/A
U100
Y100
D/A
D/A
Sync
100
Sync
VGA
CLK (27MHz)
MAIN
CLK (13.5MHz)
SUB
A/D
A/D Sync 50
Sync
V-Drive A
V-Drive B
HD
A
DG-Board
VPC ( Video Processor circuit )
Front -End
ADCx 2
8 bit
Adaptive
Comb Filter
Colour
Decoder
NTSC
PAL
SECAM
Output
Formatter
Clock Gen.
DCO
IIc
Sync Processing
V/Y 62
Y/V
C
Y
C
Y/UV
PLL/ACC
4:2:2
IC 1301 VPC3215C
MAIN
20 - 28
YUV
38 - 47
C 63
Clock
13.5MHz(19) TO IC1306
27.0MHz(18) TO DEF 5
H/V OUT
to CIP
IC1306
V - 12
H - 14
6
20.25
MHz
5.0V VCC2 31, 36
3.5V VCC1 4, 86
IIC
55,56
IC1301
The main Video Signal (Including V and Y/C) is input to pins 62 and 63 of IC1301. This signal is then converted
to digital via 2 D/A converters. (1 for V/Y and 1 for C).
The Digital signal is sent to a Digital Comb Filter. Y/C signals are passed straight through but V signals are
separated into Y/C.
At this point all of the signals are are now Y/C. these are now sent to a Colour Decoder whereby the signal is
demodulated and converted to YUV.
This YUV Signal is sent to the Output Formatter. Here the sampling rate of the YUV signal is formatted to a rate
of 4:2:2.
IC1301 is connected to IIc for Manual and Auto system selection. It also processes the Sync for the different
types of signals (PAL/NTSC/SECAM).
IC1301 produces CLK 27.0 MHz and CLK 13.5 MHz for the processing and timing of all digital circuits within
the DG Board.
The Sub Picture Processing occurs in IC1302. The Inputs and Outputs are the same as IC1301, only difference
being the IC is defeatured (No Digital Comb Filter etc.) due to a much smaller screen size. All Sub Picture
adjustments are performed in this IC.
CIP(Digital Video Signal processing)
MAIN
Clamp
ADC
ADC
ADC
ADC
Clamp
Contrl
Matrix
BRT
CNT
SAT
(ADJ)
Sync. Det.
Soft
Mix(SW)
Timing
Gen.
IIC VCO Div.
IC1306
MB87F1720
Y/UV
Y-in 31-38
UV-in 21-28
98/99/101-106
Y out
108/109/111-116
UV out
DVD
52
Y/G in
60
U/B in
69
V/R in
77
FBL
135 HS
134 VS
V- in 6
H- in 5
5.0V VCC3 2, 97,
107, 119, 136
29
CLK
(13.5MHz)
90
Xin
91
RCK2
3.5V VCC1 20, 40, 42, 80, 84,
100, 120, 138, 158, 160
3.5V VCC2 49,
57, 66, 75
SDA 82
SCL 83
(13.5MHz) (13.5MHz)
IC1306
IC1306 Converts the DVD input (YUV) from Analogue to Digital.
This IC also controls the switching between the Main Picture and DVD Input. The Sync from the
Main Picture is input to pins 5 & 6. The DVD Sync is Generated Internally and both Syncs are
Output at Pins 134 & 135 depending on the switching. 16:9 and 4:3 switching for DVD Input is
processed with this IC via the IIC controls from main MPU.
M.W. (Multi Window)
Y
D/L
Hori.
LPF
H-Compress
Interpolaion
Ver.
Interpolation
Out
MASK
Y/C
Mix
Y/C
Hori.
LPF
H-Compress
Interpolaion
V-Compress
Memory
Control
Ver.
LPF
Line
Memory
Line
Memory
Y/C
Horizontal Compression Vertical compression
IC1304 F432262PGJ
Hs 111
Vs 110
IIC
MAIN
Y-IN 14-21
UV-IN 6-13
Hs 5
Vs 4
84-91
Y out
SUB
92-101
UV out
120-127
Y-IN
Hs 102
Vs 103
SUB
112-119
UV-IN
Memory control
5.0V VCC2 83, 98 3.5V VCC1 1, 23, 63, 108
2, 3
CLK
(13.5MHz)
Field Memory
IC1305(2.8M)
SDA 74
SCL 76
IC1304
IC1304 Controls P in P and Multi Window processing. The Main Picture passes directly to the Output Mask
where the Main Picture is mixed with the Sub Picture.
The Sub Picture passes through Horizontal and Vertical Compression to reduce the size of the Picture. In
case of Multi Window or CH Search, the Digital signal is sent to Field Memory IC1305, where constant
reading and writing is performed in order for the set to store and display several different pictures. The signal
is the fed to the Output Mask for mixing, then output to IC1307.
V.P. (Video Processing)
SCL
SDA
Memory
Controller
IIC-Bus Interface
Up conversion
Vertical
Zooming
Panning
(NONE USE)
Noise
Reduction
SYNC. Signal
Generator
Form
Field
Memory
Reform
IC1307 SDA9255E
5.0V VCC 9, 25 40, 56
UV-OUT 13-13
Y-OUT 7-1,63-64
H-OUT 60 36-39
UV-IN
V-OUT 61
Blanking 62
42-49
Y-IN
H-IN
23
V-IN
22
58
CLK2
(27MHz)
IC1307
IC1307 Converts the 50Hz scan signal to a 100Hz scan signal. It performs this by copying 1 field into
memory then adding the copied field to the original. Normally Field A (25Hz) and Field B (25Hz) are joined
together to make 1 frame (50Hz). This is the basic operation of a PAL 50Hz system. However, with the
field memory circuit, each field becomes 50Hz, and when these fields are joined together, 1 frame
becomes 100Hz.
As the signal at this stage is in a Digital format, before the 100Hz conversion takes place the signal
passes through a noise reduction circuit before to clean up any noise in the signal so that any noise which
is present in the signal is not doubled after 100Hz conversion.
TAU 100Hz Processing
<PAL>
TAU
(50Hz) <-----1/50-----> <-----2/50----->
<-----3/50----->
<-----4/50----->
<PAL>
TAU1
(100Hz)
1/100
2/100
3/100
4/100
5/100
6/100
7/100
8/100
<PAL>
GIGA
(100Hz)
1/100
3/100
5/100
6/100
2/100
4/100
7/100
8/100
Creates Motion Compensated intermediate frames
DFU(Digital Future Unit)
New
Digital AI
VM
Oscillator
CTI
Vertical
Sharpness
Correction
FIFO
Peaking
LTI
CRI
D/A
D/A
D/A
D/A
Adaptive
YNR
Horizontal
Sharpness
Correction
IC1308 FJB007
TO IC1309
FROM
IC1307
119 V-OUT
44-51
UV-IN
117 U-OUT
113 Y-OUT
55-62
Y-IN
111 VM-OUT
CLK 52
27.0
5.0V VCC2 12, 16, 19, 25,
31, 37, 43, 64, 74, 84, 86,
90, 99, 108
5.0V VCC1 110, 116, 122
IC1308
IC1308 is the final stage of Digital Processing of the Video (YUV) Signal. This IC controls and processes all of
the Digital Picture Improvement circuits.
Adaptive YNR (Luminance noise reduction) - This circuit constantly monitors noise in the luminance signal and
adapts to the most suitable level of Digital Noise Reduction when the P.DNR is set to Auto. The more frequent
the noise in the picture, the stronger the effect from this circuit. Override of this circuit is possible by switching
the D.PNR to OFF.
Digital AI This constantly monitors the overall picture content and is responsible for ensuring that maximum
detail is achieved in dark or bright areas of the picture content and at the same time improving the contrast ratio.
CTI (Colour Transient Improver)- This circuit improves the different gradations of colour in a signal. Slight
differences in the shade of a colour is more easily recognizable giving more accurate colour reproduction.
LTI (Luminance Transient Improver)- This circuit improves the different gradations of Luminance in a signal.
Slight differences in the brightness of a part of a picture is more easily recognizable giving more accurate
definition in picture detail.
CRI (Colour Reproduction Improver) This circuit dramatically improves the brightness of a colour without
making the colour of a picture appear unnatural. E.g. if you can picture a scene where a woman is holding a red
rose up to her nose, you will notice the red in the rose is a bright sparkling Red, but the skin tone of the woman
is remarkably natural.
The sharpness of the H and V lines in the Luminance Signal is also improved within IC1308. As well as VM
(Velocity Modulation) which also improves the sharpness and contrast of the picture. As can be seen, a lot of
Digital processing of the original signal has taken place. The final stage is to convert this signal back to analogue
so that it can be displayed.
SWITCH
IC1309
TDA9332HN1-T
SATURATION
CONTROL
COLOUR DIFF.
MATRIX
CONTRAST
CONTROL
RGB
INSERTION
WHITE POINT
+BRIGHT
CONTROL
OUTPUT AMP
+BUFFER
BLUE STRETCH
RGB-YUV
MATRIX
BLACK
STRETCH
Y
U
V
Y U
V
PMW
+BEAM CURRENT
LIMITER
CONTINUOUS
CATHODE
CALIBRATION
POWER
SUPPLY H/V DRIVER 19X6-BIT DAC'S
2X4-BIT DAC'S
IIC BUS
TRANSCEIVER
SOFT
START/STOP
LOW-POWER
START-UP
CLOCK
GENATION
+ 1ST LOOP
PHASE-2
LOOP
HORIZONTAL
OUTPUT
PAMP
GENERATOR
VERTICAL
GEOMETRY
EW-GEOMETRY
R
G
B
SAT CONTR.
H-SHIFT
GEOMETRY CONTROL
SDA
SCL
Geomagnetic
BEAM CURR.
BLACK CURR.
TV/PC BLK
R
G
B
R2 G2 B2
BL2
WHITE P.
B
R
T.
OSD
Display Processor
30
31
32
17
39
23
24
20
11
10
44
38 37
36
35
33
40
41
42
43
25
V
28 Y
FROM
DFU
27 U
26 V
FROM
VGA
R1(VGA)
G1(VGA)
B1(VGA)
8V
8V
V
H
21
8 4 3
1 2
V-OUT
EHT EW-
DRIVE
H-OUT
IC1309
The Display Processor inputs the analogue YUV Inputs, then through a MATRIX converts the signal to RGB for
output to the CRT (Pins 40-42).
IC1309 Functions
-Processes VGA signal via input to Pins 30, 31 and 32, VGA/TV Blanking via Pin 33, and H (Pin 23) and V (Pin 24)
inputs. These same pin connections are also inputs for the Teletext Signal. The switching between Teletext and
VGA are controlled by the following ICs on the A Board.
IC3501 switches the RGB signals.
IC4002 switches the H Sync.
IC4002 switches the V Sync.
The command for switching these ICs is from MPU IC1101pin 58.
- The OSD is input to pins 35-38 and inserted to the picture.
- The V Drive is output at pins 1 & 2 to the V Output IC. The H Output is output at pin 8 for the H OUTPUT
Transistor. EHT (FBT) is input at pin 4. The IC uses this signal to regulate the H and V geometry during Beam
current changes so that the Geometry does not drastically alter during large changes in EHT.
-This IC adjusts all of the Picture (Brightness, Contrast etc) and Geometry (Height, width etc.) Functions via the IIC
bus on pins 10 & 11 connected to the MPU.
-This IC controls the AUTO WHITE BALANCE function. It Monitors the Beam current input at pin 43 and continually
adjusts the Cut Offs according to the scene of the picture. This information is sent to White Point where a RGB a
LINE is inserted to the Blanking Interval of each RGB Drive. It adjusts the RGB to maintain a white line and hence,
maintain white balance. The initial calibration is set at the factory which forms the main reference for this circuit to
perform effectively. During Service mode, the white balance is touched up by adjusting the screen control on FBT
only. During this period each RGB Output feeds back Black Current information to pin 44 to calibrate the cathodes
on the CRT.
IC1308
FJB007
DFU
IC1301
(MAIN)
VPC3215CY/C,
SYNC
SEPA
IC1304
F432262PG
Multi Window
IC
13
06
IC1302(SUB)
VPC3215C
Y/C,SYNC
SEPA
IC1307
SDA9255E
100Hz
3M bit
IC1309
TDA
RGB SW
(100Hz or VGA)
IC1305
Memory
IC13
03
CLK (13.5MHz)
MAIN
U50,V50
U50,V50
U50,V50
Y50
Y50
Y50
MAIN
Video
Sync 50
Sync 50
Sync 50
U50,V50
Y50
Y100
U100,V100
V100
MAIN C
SUB
Vide
o
SUB
C
TEXT
TDA9
151
TEXT
RGB
CLAMP
VM OUT
VG
A
IN
VGA
RGB
DVD
IN
Y Pb Pr
A/D
A/D
A/
D
D/A
U100
Y100
D/A
D/A
Sync
100
Sync
VGA
CLK (27MHz)
MAIN
CLK (13.5MHz)
SUB
A/D
A/D Sync 50
Sync
V-Drive A
V-Drive B
HD
A
DG-Board
R
E
V
I
S
I
O
N
DG-Board TXNDG10ECU
Protection Circuit
D509
Q807 / 15V Line
Over Current DET. IC1101 MPU
Protect >1.1V 7
Power
27
Q802
D842
D843
D510
Q502
D511 D513
D838 D850
Q806 / 140V Line
Over Current DET.
D519
D402 D405
Q801 Double Rectifier
DET.
D822
Power ON : L OFF:H
140V Line
Over Voltage DET.
H pulse
Over Voltage DET. RL801
EHT
Over Voltage DET.
Q805
Vertical +B line
Over Voltage DET.
Q452 Vertical plus
Over Voltage DET.
D525 / 6.5V
D526 / 12V DAF
D502 / 36V Sound
D505 / 22V Sound
D504 / 15V
D508 / H PULSE
Voltage DET.
Protection Circuit
There are several protection circuits in the MD2 Chassis. In the event of any abnormal operation that is monitored by
one of the protectors occurs, a H signal will be sent to pin 7 of MPU IC1101. Normally the voltage sits at around 0V. If
the voltage exceeds 1.1 V, the protection will trigger and Output a H on Pin 27 to switch the Power Relay OFF.
To find which Circuit has caused the trigger, monitor the voltages at the anodes of each diode with an analogue
meter at switch ON. Alternatively, disconnecting the diodes one by one (Not recommended) until power stays On.
However this is risky and it is urged to take care as disconnecting certain protection circuits such as Power Supply,
EHT, Vertical Deflection etc.. can destroy the CRT. Look at what the protection circuit does and take appropriate
action to make sure no inadvertent damage can happen (Use Variac, Disconnect CRT Board etc..).
Special Functions for Servicing
the Tau MD2 and E3D Chassis
TZSC07012
Use this Extension cable Kit to Service the DG-Board
TZS709010
Use this Extension cable Kit to Service the B and X-Boards
Special Functions
SELF CHECK
Purpose:
- To Check IIC communications between MPU
and all other ICs connected to it via IIC Bus
-Protection Information
To Activate:
- Simultaneously press the OFF TIMER button on the remote
and the VOLUME DOWN button on the set.
NVMEM OK AVSW OK
VPC1 OK TUNER1 OK
VPC2 OK TUNER2 OK
MW OK EXDAC OK
V.PRO OK SOUND OK
DFU OK MSP OK
CIP OK TEXT OK
DISP OK
SELF CHECK
Panasonic MD2 Vx,xx 1999/**/**
OP1 81
OP2 E2
OP3 DE
OP4 F3
OP5 9D
OP6 FF
OP7 73
OP8 02
Check results of ICs
OK = Normal
NG = Abnormal
(Check IC or its
nearby components)
Note: To Exit from
SELF CHECK mode,
Switch the power Off
on the remote or at the set.
Protection Information
Black: Normal
Red: Abnormal Voltage
Yellow: Shut Down
Green: Hold Down
Option Code Display
The numbers are displayed in hexadecimal
Note: Option codes on the screen will vary
depending on the model
IC Locations
NVMEM : IC1102 A-BOARD
VPC1 : IC1301 DG-BOARD
VPC2 : IC1302 DG-BOARD
MW : IC1304 DG-BOARD
V.PRO : IC1307 DG-BOARD
DFU : IC1308 DG-BOARD
CIP : IC1306 DG-BOARD
DISP : IC1309 DG-BOARD
AVSW : IC3001 H-BOARD
TUNER1 : TNR1 A-BOARD
TUNER2 : TNR2 A-BOARD
EXDAC : IC1001 A-BOARD
SOUND : IC2401 A-BOARD
MSP : IC2001 B-BOARD
TEXT : IC3504 T-BOARD
Market Mode Function (Service Mode)
The MPU controls all of the switching functions of all ICs connected to the IIC Bus line.
The following settings and adjustments can be adjusted by remote control once the set has
been set to Service Mode.
To enter Service mode: Adjust VOLUME to zero and set the OFF TIMER to 30 MIN. Then,
simultaneously press the RECALL ( )button on the remote and the VOLUME DOWN
button on the set.
To exit Service Mode: Switch the POWER OFF at the remote or the set.
SERVICE MODE
NORMAL MODE
OPTION/
CODE
SETTING
CHK1
VCJ
ADJUSTMENT
CHK2
WHITE BALANCE
ADJUSTMENT
CHK3
PINCUSHION
ADJUSTMENT
CHK5
SUB PICTURE
ADJUSTMENT
CHK4
2 2
2 2
2 1
1 1
1
1
-To scroll through the menus use the number 1 and 2 keys on the remote.
-To scroll within a CHK menu use the number 3 and 4 keys on the remote.
-To make an adjustment use the VOLUME +/- keys on the remote
Note: Any adjustments
made to CHK2-CHK5
are memorized
instantly.
EXIT: Switch the
Power OFF.
Replacing Memory IC
When replacing the memory IC, the OPTION Codes and MEMORY
Data must be set. All other settings should be set to Factory
Average Values listed on pages 11 and 12 of the Service Manual.
Ref. No.
IC1102 TVRJ214
Part No.
CHK1
OPTION
OP1 81
OP2 E2
OP3 DE
OP4 F3
OP5 9D
OP6 FF
OP7 73
OP8 02
CHK1
To memorize,
Press 0 button
On the remote.
OPTION SETTING TX-68P100Z
OPTION
OP1 81
OP2 E2
OP3 DE
OP4 F3
OP5 85
OP6 FF
OP7 73
OP8 02
TX-79P100Z
OPTION
OP1 81
OP2 E2
OP3 DE
OP4 F3
OP5 9D
OP6 FF
OP7 73
OP8 02
-Use the 3 and 4 keys on the remote to advance through the different OPTION settings.
-Use the VOLUME +/- to adjust the setting.
- Press the 0 button on the remote to memorize the adjustment of the setting.
Memory Edit
000 00
001 00
002 0E
003 02
004 01
005 0E
006 04
007 01
Address Data
Re-memorize Address and Data
MEMORY EDIT MODE
792
790
782
6B8
6B6
692
68E
67D
664
642
637
62F
301
Address
58
D8
39
64
64
E3
F1
02
AC
A3
47
87
4B
TX-79PIOOZ
NO
CHANGE
4B
TX-68P100Z
-To enter Memory Edit Mode: While in CHK1 mode, simultaneously press the MUTE button on
the Remote and the VOLUME DOWN button on the set.
-Use the Left/Right/Up/Down Cursor button on the remote to select a Memory Address.
-Adjust the data with the VOLUME +/- button on the remote.
-Press the 0 button on the Remote to memorize each adjustment individually.
-Switch the Power OFF at the MAIN POWER SWITCH to activate the new settings.
White Balance
An Automatic White Balance system is incorporated in the MD2 chassis.
This system automatically adjusts the LOW LIGHTS according to the
Varied picture content on the screen. However Standard initial adjustment is still required.
1. Input a BLACK pattern from a pattern generator and operate the
Set for at least 30 minutes.
2. Set the TV to Service Mode. Set to CHK3 and select CUT OFF
3. Adjust the SCREEN control on FBT until the ON SCREEN value
of the CUT OFF reads 0 (ZERO).
Note: R,G and B Drive adjustments are not required
Since these are set at the Factory.
Hotel Mode
This function locks out all MENU and PRESET functions
and maximizes the VOLUME level to the last position set.
To set Hotel Mode:
Set the OFF TIMER to 30 minutes. Simultaneously press the
RECALL ( ) button on the remote and the CHANNEL UP
Button on the set.
To Cancel Hotel Mode:
Simultaneously press the OFF TIMER button on the remote
And the VOLUME DOWN button on the set.
NOTE: This information is only provided in the Service Manual
VGA INPUT
For VGA Input to work, the PC must be set to the following Resolution:
640 x 480 (31.5 KHz H and 60Hz V)
The set has 2 Error messages which are displayed by the OSD.
1. SET TO 640 x 480
(Check Display settings in Control Panel of computer. If notebook
computer, switch OFF LCD screen at the notebook)
2. NO INPUT SIGNAL
(Check cables. If notebook computer, check if the VGA output terminal
is switched ON at the notebook)
Structure of PF CRT
Tau Pure Flat CRT
Conventional CRT
Pure Flat CRT
CLICK
Tau Shadow Mask
Pure Flat CRT
Conventional CRT
CLICK
SST(Semi Stretched Tension)
Tension
CLICK
Pressed Mould
Cause for Mislanding
V=0.35G
S
S
N
H=0.3G
N
Moves down
Facing East
M.F.
I
D
Moves up
Facing West
M.F.
D
I
Facing South
Moves clockwise
Facing North
Moves anti-clockwise
150
90
200
Shadow-Mask pitch
79
675
675
127
New SST
Conventional
150
90
200
How to Minimize Geomagnetism
Geomagnetism Auto Canceller
1. Geomagnetism Sensor
2. Correction Coil
CLICK CLICK CLICK
N
1. Geomagnetism Sensor
Flux Gate Type Magnet meter
CLICK CLICK CLICK
N
Flux Gate Type Magnet meter
Turn
CLICK CLICK CLICK
N
Flux Gate Type Magnet meter
Turn
CLICK
N
Flux Gate Type Magnet meter
CLICK
Turn
CLICK
Flux Gate Magnet Meter Output
CLICK
North
Vh
+ Max
East South West
Vh
- Max
Vh
N-S
E-W
Vh
N
1. Direction Detector
CLICK CLICK CLICK CLICK CLICK
Facing North
V
h
N
-
S
E
-
W
V
h
Facing West
N
CLICK CLICK CLICK CLICK CLICK
N - S
E - W
V h
V h
Facing South
N
CLICK CLICK CLICK CLICK CLICK
V
h
E
-
W
V
h
N
N
-
S
CLICK CLICK CLICK CLICK CLICK
Facing East
TV Direction detector Output
CLICK
North
Vh
+ Max
East South West
N-S
E-W
Vh
- Max
Auto /
Manual
SW
CLICK
E-W
Detector
N-S
Detector
3. Block Diagram
Control
Corner
correction
output
Center
correction
output
Corner
Correction
Coil
Center
Correction
Coil
LC4801 IC4861
7
1
5
6 6
2
GM-PCB
G
M
1
Geomagnetic
Sensor
Voltage
Control
IC4805
IC4804 IC4803
IC4801 IC4802
8
5,6
10
2
4
1,3
9,10
5
10
1
6 14
5 14 6
1
10
G-PCB
K-PCB
G
1
1
K
2
G
1
0
K
1
G
7
Auto/Manual
Switch
Voltage Amp Output
Voltage Amp Output
E-W
Center
Correction
N-S
Corner
Correction
IC1309
25
DG-PCB
Corner Coil
Correction
Control
IC1101
IC1001
6
7
A-PCB
Center Coil
Correction
Control
Auto/Manual
Switch
MPU
GEOMAGNETIC
Auto/Manual
Switch
IIC
Geomagnetic
In Auto mode, IC1001 pin 6 outputs a L and switches IC4805 to pass through the voltage applied
from Geomagnetic Sensor. The signal from the Geomagnetic sensors is input to Voltage Controller
IC4861 and is then amplified by IC 4805 (E-W), IC4802 (N-S) and Output by IC4803 (E-W), IC4801
(N-S) and sent to the correction coils providing DC current.
In Manual mode, IC1001 pin 6 goes H and control for the Center correction coils is output at pin 7 of
IC1001, and the control for the Corner correction is output at pin 25 of IC1309. After passing through
switch IC4805 the remainder of the circuit operation remains the same as in Auto mode.
The initial commands for Auto/Manual switching and Manual adjustments are sent from the MPU
IC1101 via IIC to IC1001 and IC1309.
4. Correction Coil
Center correction coil
Corner Correction Coil
Degaussing coil
CLICK
How to check Beam Landing
S
L
-
0
6
With the aid of a Dot Scope, it is possible to view the beam landing at any given point.
There are 3 main points which need to have correct beam landing in order to achieve
good overall purity.
1. Center area of CRT.
2. Center Left of CRT.
3. Center Right of CRT.
Note: When viewing images through a Dot Scope, the image is reversed due to the
Optical nature of the lenses. IE. When you look through the scope and glance at
the left side of the image, you are actually glancing at right side of the image.
The following slides are as viewed through a Dot Scope.
Good Beam Landing
No Adjustment necessary
Beam moved too far Right
Adjust Purity Magnet
Beam moved too far Left
Adjust Purity Magnet
Beam moved too far Out
Move DY Back
Beam moved too far IN
Move DY Forward
Beam moved too far Left
What to adjust?
Move the beam Right
Equal error
Adjust Purity Magnet until both
sides have an equal error.
Beam moved too far Out
Move DY Back
Good Beam Landing
Adjustment Completed
Correction Magnets
Purity Correction Magnet
TSN63115-2
Convergence Correction Magnet
TSM10032-3
TAU E3D New Circuit
Panasonic
IIC BUS links
<W>
ABL
In Television, a normal ABL operation detects current flowing through the secondary coils of the FBT. However this
system is not ideal for a projection TV because it has 3 CRTs. An abnormal current drain from only 1 of 3 CRTs may
not be detected as sufficient current to activate the ABL. In this case a circuit has been added to monitor the current
for each CRT at the output of the RGB Drives. A standard ABL is also used for extra protection.
Normally the Base of Q7735 is low and the Transistor is On. The transistor receives its input via 3 diodes D3352,
D3362 and D3372.
The output value of Q7735 is input to pins 5, 7, 9 and 11 of IC7705. The compared result is output from pins 1, 2, 13
and 14. This data is then input to IC7702 as P0 P3. From this, the CRT current is separated into 5 levels. Level A
will incur maximum ABL effect and Level E will incur no ABL effect.
W
SHADING
To correct variations in the left and right shading due to differences in the positioning of the CRTs, a
Shading Circuit has been added. It works as a gamma correction circuit to make the colour temperature of
the Red and Blue CRTs uniform across the screen.
A Horizontal Pulse is supplied and is converted to a Sawtooth and Parabola waveform.by Q7741-Q7744
and Q7745-Q7747 respectively. The H.PARA is input to pin 2 of IC7704 and the H.SAW is input to pin 5.
These signals are mixed then output from Pin 7 of IC7704.
The mixed correction waveform is split to Pin 10 ( R ) and Pin 8 ( B ). The Red and Blue gain is adjusted
and the Left and right brightness is varied to correct any lack of colour uniformity on the screen.
PICTURE MOVING FUNCTION
This feature operates to prevent burn-out from occurring in the
phosphor substance of the projection tube when the
picture is still for an extended period of time.
The following cases will activate Picture Moving function.
1. Switching the Power On.
2. Changing Channels.
3. Changing AV Inputs
The MPU sends a command to move the screen horizontally and
vertically, to IC1309 (Display Processor DG-Board),
through the IIC Bus, each time the above occurs.
W
SINGLE COLOUR MODE
During Service Mode, each colour (R,G,B) can be switched OFF
individually when in P-Conver Mode when PIP button is
pressed on the remote.
The command data is sent to IC7707 (DAC) from IC1101(MPU)
via IIC bus line. Then a voltage is output from Pin 1, 2 and 9 of
IC7707 as in the table on the diagram.
FAN CONTROL
The E3D chassis requires a cooling fan to maintain the temperature within the set. The fan is located near
the Green CRT.
The internal temperature of the unit is detected by a thermistor attached to the metal chassis at the rear of
the set (Behind G-CRT). The thermistor provides the MPU of the temperature by supplying a voltage
to pin 11 of the MPU. When the temperature rises to 90 DEG C (point A), pin 8 of MPU outputs a
H voltage to the fan to start rotation. After the temperature falls to 80 DEG C (point B0, pin 48 of
MPU outputs a L voltage allowing the fan to switch off.
PROTECTION:
During the following conditions, pin 7 of MPU will receive a H and place the set into stand-by.
1. A5/SG7 connector and SG8 connector are disconnected.
2. The Fan is defective.
W
6
Q400 (F-PCB)
V. Stop Det.
RGB OUT BLANKING
The purpose of RGB blanking circuits is to prevent screen burn during abnormal operation. The different types of
blanking are:
1. Power Off Blanking
When the set is switched to standby the MPU sends a command to the Standby Relay to switch it OFF. The L
applied from the relay circuit switches Q7736 OFF (Normally ON). The higher Collector voltage on Q7736
will switch Q7738 ON to Blank the RGB signal and prevent flashing. This process also occurs if the
Protection Circuit is activated.
2. Horizontal Blanking
During Horizontal retrace, pulses are supplied by H.OUT transistor Q551 to the base of Q7738 for horizontal
blanking, to prevent the projection tubes emitting light during the fly-back interval.
3. VERTICAL STOP BLANKING
If vertical deflection stops, the remaining Horizontal line will burn the CRTs. To prevent this, a vertical pulse from
IC451 vertical output pin8 is applied D402. During normal operation, the pulse is applied to the base of
Q400, keeping Q400 turned on. If the V-pulse is not present, Q400 will switch OFF. The higher Collector
voltage on Q400 will switch Q7738 ON to BLANK the RGB signal.
VERTICAL OVER DEFLECTION BLANKING
If during the deflection period the electron beam goes beyond normal range and hits the neck of the CRT (over
deflection), the beam can burn through and destroy the CRT. The over deflection blanking circuit is
designed to prevent this.
IC 508 receives a vertical pulse at pin 2. This IC is a comparator, and when an abnormal level of V-Pulse is input,
the pin 4 output goes high supplying which is applied to the Base of Q7738, switching it ON to BLANK the
RGB signal.
IIC
IIC
DC-BOARD
When the set is switched ON, the SUB MPU, IC7106 is reset. IIC bus lines link this IC with the EEPROM IC7101
and LSI IC7107. Immediately after reset, the SUB MPU, commands the LSI to read convergence data stored in
the EEPROM. The LSI then writes to the 2 SRAM ICs IC7108 and IC7409. The data in the SRAM is read
continuously by the LSI IC and its output is sent to the DAC;s where the Digital signal is converted to analogue in
order to supply the necessary drive current to the Convergence Yoke (CY).
IC7103 Interface
This is an interface IC for the IIC bus line from the Main MPU. It translates data to a series of Highs or Lows at
its outputs. In Convergence Adjustment Mode it outputs a H (Pin 13) to the SUB MPU. At this time the SUB
MPU sends a L (Pin 110) to the Main MPU to disable the Remote Control function of the Main MPU. Now, only
the SUB MPU receives the Remote Control Commands.
IC7106 SUB MPU
In Convergence Adjustment Mode, this IC expands compressed stored data in the EEPROM and sends it to the
SRAM ICs via the LSI IC to refresh the data in the SRAM. It also controls the data flow between devices and
controls the functions of other ICs and circuits.
IC7101 EEPROM
This memory IC serves as the storage media for convergence data. It is Non Volatile which means it will hold the
data even after the Set is switched OFF. Its function does not change during Convergence adjustment.
IC7107 LSI
In adjustment mode, The LSI generates the Crosshatch pattern using the reference generated by OSD IC7110. It
matches the pattern to the actual convergence data to make correct adjustment possible. It also performs Read/Write
operation to the SRAM and EEPROM ICs.
IC7104 PLL
The PLL (Phase Locked Loop) produces a frequency of 16MHz which is synchronized by the Horizontal pulse output
from the LSI.
IC7102 LATCH
The frequency from the PLL IC is divided by 2. It is then supplied to the LSI at 8.0 MHz. The LSI outputs the 8.0MHz
CLK to IC7102, and divides the CLK signal by 2 and sends it to the Dynamic DAC ICs as a System CLK control signal
(4.0MHz).
IC7110 OSD TEXT
The OSD circuit is one of two OSD circuits in the set. In convergence adjustment mode, it generates the crosshatch
pattern, lettering and graphics seen on the screen. Its output is sent to the LSI as RGB and Blanking.
IC7109 STATIC DAC
This DAC is used to convert static convergence serial data applied to it from the SUB MPU to DC Voltage levels.
The voltages are added to the Dynamic Convergence signals (After DAC process), then amplified by IC7001 and
IC7002 before being applied to the CYs.
IC7111 - IC7113, IC7401 - IC7403 Dynamic DAC
These ICs convert the H and V convergence data to analogue. The DACs utilize 3 CLK signals to perform this
task. The LR CLK (250KHz) which recognizes the data blocks, the BIT CLK (8.0 MHz) which recognizes the data
bits, and the SYS CLK (4.0 MHz) which performs the conversion task.
IC7404 SWITCH
This IC constantly switches the data conversion between DAC Array 1 and DAC Array 2 with the aid of the LR
CLK. As this set is a 100Hz interlaced scan, each field is 50HZ. Each DAC Array represents one of those fields.
IC7108 & IC7409 SRAM
These ICs hold the Convergence data once the set is switched ON. The data is initially copied from the
EEPROM (Via control from the SUB MPU and LSI), each time the set is switched ON. During Convergence
adjustment alignment, the data is updated as alignment progresses. After completion, the data is saved to the
EEPROM.
IC7116 IC7118 LPF
These ICs are Low Pass Filters. The purpose of these ICs is to round off the staircase steps of the signals to
transform them into smooth analogue signals. The Static Convergence Output is joined at the output of this IC,
before being amplified by the convergence amps.
The Convergence can be
adjusted at 15 points
Horizontally (13 points
viewable) by 11 points
vertically (9 points viewable)
giving a total of 165 points of
convergence correction.
The convergence is stored in 4
memory locations within the
EEPROM. P-1 for NTSC signals,
P-2 for PAL signals, P-3 Blank
copy box, and P-4 for Factory
use. The Sub MPU selects the
appropriate location depending
on the input signal. Either P-1
or P-2 data can be copied to P-3
for safe keeping in case of
customer tampering.
AD 13 16
At switch on, RESET IC7105 resets
the SUB MPU, LSI and OSD IC
Data is sent from the main MPU to
inform the the SUB MPU of the
following
- Which system is being used
(PAL/NTSC).
- Which memory address to read
from.
- Is the set in normal or convergence
adjustment mode.
This table indicates the Sub MPU
settings for memory address read
and system selection. When
Convergence mode is activated, a
H is sent to pin 16 of Sub MPU.