Design of an OTA-Miller for a 96dB SNR SC

Multi-bit Sigma-Delta modulator based on /

methodology
Heiner Alarc on Cubas

and Jo ao Navarro

Engineering School of S ao Carlos, USP.

Email: heiner.alarcon@usp.br, navarro@sc.usp.br

LSITEC-S ao Paulo
Email: heiner.alarcon@lsitec.org.br
AbstractThis paper presents the design of an OTA-Miller
amplier of the rst integrator of a Switched-Capacitor Multi-
bit Sigma-Delta Modulator. The rst integrator OTA is the
most critical block in Sigma-Delta Modulator due to the high
bandwidth, high Slew Rate and low noise requirements. The
rst integrator OTA specications are obtained from the Sigma-
Delta Modulator designing for low power consumption. The
gm/ID methodology is used on the OTA design of the rst
integrator to reduce the power consumption. This methodology
is also applied in the other OTAs of the Sigma-Delta Modulator.
The Chopper technique is also implemented to reduce the input
referred noise of the rst integrator. The SDM with the designed
OTAs using the gm/ID methodology is simulated by the Spectre
simulator. Implemented in 0.18 CMOS technology, the SDM
achieves a 96 dB SNR for 20 kHz signal bandwidth and a power
consumption of 2.77 mW for a 1.8 V supply.
Keywords:/

, Sigma-Delta Modulator, Audio, Multi-bit,

low power.
I. INTRODUCTION
Currently, the request for portable audio commercial sys-
tems as phone-mobiles, high quality audio devices and hear-
ing systems is increasing the demand for low-power data-
converters. Audio signals are in the range of 20 Hz to 20 kHz
and, generally, audio digital systems requires converters with
high resolution and low distortion. For this purpose, Sigma-
Delta A/D converters, which reachs high resolution with the
low power consumption, are the best choise.
The Sigma Delta Modulator (SDM) is the most important
part in the Sigma-Delta Converter, because it increases the
converter resolution in-band applying oversampling and noise-
shaping techniques [1]. SDMs can be implemented with
Switched Capacitors (SC) and Continuous Time (CT) struc-
tures. For this work a SC structure is chosen due to the high
precision in the coefcients implementation. The most power
hungry block in a SDMs is the rst integrator OTA (OTA 1),
because it needs to be designed to drive high load capacitance,
to present low noise and high product gain-bandwidth (

).
The Miller architecture is chosen to implement the OTA 1.
In this work, a methodology design for the OTA 1 of a
Third-order Four-bit CIFF (Cascade of Integrators Feedback
Form) SDM is presented. In section II, the SDM circuit is
presented. In section III, the OTA 1 specications are obtained.
In section IV the OTA 1 design is developed. Finally in section
V and VI, the results of the OTA 1 and the Sigma-Delta
modulator and the conclusions are presented respectively.
II. SDM CIRCUIT IMPLEMENTATION
The Third-order Four-bit CIFF SDM shown in the gure 1 is
composed by three SC integrators, a capacitive resettable ana-
log adder with offset cancellation, a four bits ash quantizer,
and a four bits weighted-DAC. The OTA ampliers are applied
in the three DC integrators (OTA 1, OTA 2 and OTA 3) and in
the analog adder (OTA 4). Two chopper modulators are added
at the rst integrator to reduce the in-band icker noise [2].
A Fully differential structure is selected to reduce the charge
injection generated by the switches and to increase the input
value range and the PSRR [3]. A bottom plate technique [1]
is also implemented to reduce the parasitic switch capacitance
error. The switches are implemented with carefully designed
transmission gates to reduce the charge injection and time
constant.
III. OTA 1 SPECIFICATIONS
The input OTA specications are obtained from the SDM
system design. The SDM is designed for high SNR (about
96 dB), so it is necessary to establish the noise budget of
the system. The noise sources can be divided in internal
and external sources. The internal sources are due to the
quantization noise (

), the KT/C noise, the intrisic noise of

the OTAs, and the DAC non linearity (

). The external
sources (

) are due to the references noise and power supply

noise. The sum of all noise source contributions must be less
or equal than the required noise to get the specied SNR.
Hence, the relation in equation 1 must be fullled[4].
10
/10

2
,

2

+
2
,
+
2

+
2

(1)
In equation 1,
,
is the maximum allowed input
signal RMS and
,
is the sum of the intrisic RMS noise of
the OTAs and KT/C RMS noise. As the
,
determines the
978-1-4673-4900-0/13/$31.00 c 2013 IEEE
Fig. 1. Third-order Four-bit SDM
SDM power consumption, it is assumed that
,
contribuits to
80% of the total noise. The

and the

contribuit
to 1%, 9% and 10%, respectively [4]. For

is possible to
determine the SQNR=20(
,
/

)=116 dB. For this

SQNR can be demonstrated that it is necessary an OSR of
48 [4]. Thus, the sampling frequency (

) should be equal to
2 MHz for a bandwidth slightly greater than 20 kHz. Using
the found OSR and the modulator order (L), the modulator
coefcients can be obtained using the Matlab SDM toolbox
[5]. These coefcients are listed in the table I.
TABLE I
SDM COEFFICIENTS

3

2

1

1

2

3

4

1

2

3
3.4 2.4 0.7 0.8 0 0 1 0.8 1.4 1.1
The coefcients are scaled to limit the output swing to 20%
of the full-scale at each output integrator and are rationalized
to implement the capacitance feedback of each integrator [4]
[5].
The rst integrator has the greatest noise contribution, so
it is xed as
2
1
= 0.9
2
,
. The input referred noise of the
OTA 1 is xed in 10%
2
1
, because of the used Chopper tech-
nique. The rst integrator / noise can be expressed as
4/(
1
2) [4], where C2 is the integration capacitance
of the rst stage.
The OTA non-idealities are commanded by the nite DC
gain (

), the nite gain-bandwidth (

), the nite Slew

Rate (), and the input referred noise. The nite DC gain
can modify the transfer function (), shifting to the right
the cut-off frequency. This shift may increase the noise oor
in signal band [6]. Hence, a higher value of

is desirable.
The

and act during the integration phase [5]. For

this design the region holds a third part of the integration
phase, then =

/(

/6).

is the maximum
output value peak to peak of the integrator and

is the
oversampling period.
The remaining time of the integration phase is taken by the
settling time, then

= (()

)/(2

/3) [4], where

is the settling error and

is the feedback factor of the

integrator. To accomplish the specied , the settling error
is xed in 10
6
for the OTA 1. The

factor is equal to
1/(1 +

), being

a SDM coefcient.
An important parameter on the OTA 1 design is the output
load capacitance,

. It is obtained in the integration phase

(OTA 1 working) of the SC integrator and it can be approxi-
mate to the equation 2 [1].

=
2(2
1
+

2
+2
1
+

(2)
where

is the OTA 1 input capacitance. The specications

for the RMS input referred noise (

), 2,

,
and

for the OTA 1 are listed in the table II.

TABLE II
SUMMARIZED DESIGN OTA 1 SPECIFICATIONS

2.22 20 40 7.3 1.85/ 10 4.5

IV. LOW POWER DESIGN FOR THE OTA 1
A. /

Methodology
The OTA 1 is designed using the /

methodology.
In this methodology the design parameters are expressed in
function of /

[7]. The /

parameter varies between

0 and 30 (gure 2), depending on the inversion region. The
conduction operation of a transistor can be divided in three
approximate regions, weak, moderate, and strong inversion
(gure 2).
The / is extracted from simulations of the MOS
transistors varying

and

between 0 and 1, 8 [7].

B. OTA Miller design
The fully differential OTA Miller architecture shown in
gure 3 is chosen for the four OTAs of the SDM. The
advantages of this architecture are the high DC gain, low noise
and low power consumption [3]. The rst stage of the OTA is
a differential pair and the second stage is a common source
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
5
10
15
20
25
30
35
VGS[V]
g
m
/
I
d


TypeN
TypeP
Weak
Inversion
Moderate
Inversion
Strong
Inversion
Fig. 2. /

vs

for each transistor in the three inversion regions

for

= 420 and

= 355
amplier. To increase the Common Mode Gain it is used two
CMFB (Common Mode Feedback). A SC symmetrical load
architecture is applied for the two CMFBs. This architecture
stabilizes faster than traditional SC-CMFBs.
Fig. 3. Fully Differential Two Stage OTA including CMFB
Most of the current consumption is due to the second stage
current,
7
(shown in gure 3). This current can be expressed
in function of
7
/
7
,

, and the second dominant pole,

2
, as can be seen in the equation 3.

7
=

2

(
7
/
7
)
(3)
The Phase Margin (PM) depends on the
2
and can be
expressed by the equation 4.

= 90
1
(

2
) (4)
PM must be designed for 85

to assure stability, so

must be at least ten times

2
. From equation 3 and 4 we can
built the gure 4 curves of
7
vs
7
/
7
.
0 5 10 15 20 25 30
0
1
2
3
4
5
6
7
x 10
3
gm
7
/I
D7
I
D
7
(
A
)
Fig. 4.
7
vs
7
/
7
for the OTA 1
From gure 4 it can be deduced that it is necessary high
values of
7
/
7
(weak inversion) to reduce
7
. However,
high
7
/
7
designing implies in huge transistor dimensions
and, consequently, in large output capacitance. For this reason,
the value of
7
/
7
is conveniently adjusted. The
3
and

4
transistors are designed for the same inversion region of
the
7
transistor to ensure low systematic offset [1].
In order to reduce the power consumption without increase
the current mismatch, it is necessary a current copy factor of 3
as maximum in the current mirrors. For minimize the current
consumption, the following relation is assumed.

7
= 3
5
= 6
1
(5)
where
1
is the differential pair current and
5
is the
current of the transistor
5
. The compensation capacitance
can be obtained from the equation 6.
=
2
1

(6)
The current
1
can also be expressed in function of

and
1
/
1
as it is shown in the equation 7 [1].

1
=
2

1
/
1
(7)
To dene the inversion region of
1
, the parameter

1
/
1
is varied between 0 and 30 in the equation 7. The
former curve is compared with the obtained current (
1
=

7
/6) being both curves shown in the gure 5.
From the gure 5 we can deduce that
1
/
1
should
not be greater than 20, because
1
would be less than the
specied current by 5. Finally,
5
,
6
and
9
transistors are
designed in strong inversion reducing the mismatch between
current mirrors.
The values of
1
/
1
,
5
,

,
7
and
7
/
7
for
the OTA 1 are summarized in the table III.
0 5 10 15 20 25 30
0
0.2
0.4
0.6
0.8
1
1.2
1.4
x 10
3
gm1/ID1
I
d
1
(
A
)


I
D7
/6
fta=7,3MHz
Fig. 5.
1
for xed

of 1 in function of
1
/
1
TABLE III
SUMMARIZED DESIGN RESULTS FOR THE OTA 1

1
/
1

5

7

7
/
7
1 20 120 20 360 20
V. RESULTS
The shown in the gure 1 was designed using the
0.18m CMOS7RF CMOS technology of IBM. The power
supply is 1.8 and the maximum input is 1 (50% of Full
Scale). The input OTA results listed in the table IV, including
input referred offset (

) and the OTA 1 total current (

),
are obtained using the Spectre simulator.
TABLE IV
SUMMARIZED RESULTS FOR THE OTA 1

OTA 1 62dB 8.2MHz 6.2V/s 3.5mV 2.22V 968A

The other OTAs and blocks of the SDM are designed by
following a similar methodology. The SNR of the SDM is
measured from the transient simulation of the circuit of the
gure 1. The modulator input referred noise is generated from
the PSD simulated using the method shown in [8]. The SNR
is simulated using a test frequency of 6.83. In the gure
6 are shown the frequency response of the SDM and the input
referred noise PSD simulated using Spectre-RF.
The performance of the modulator is summarized in table
V and compared with low Power SDM for low power appli-
cations published in recent years.
TABLE V
COMPARISON OF THE PUBLISHED WORKS
[9] [10] [11]
[] 93 83.8 92 96
[/] 18.49 1.81 0.45 1.02
[] 1.35 1.1 0.6 2.77
[] 0.18 0.18 0.18 0.18
[ ] 1.5 1 1.8

[] 10 24 24 20
10
1
10
2
10
3
10
4
10
5
10
6
160
140
120
100
80
60
40
20
0
A
m
p
l
i
t
u
d
e

[
d
B
]
Frequency[Hz]


SDM Output Spectrum
Input Referred Noise PSD
Fig. 6. Output SDM frequency response compared with the input referred
PSD noise
VI. CONCLUSIONS
A /

methodology to design low power SDM input

OTA was described. The merit of this OTA was veried by
simulating third order four bits SDM. The low power in
the OTAs are achieved designing the output source common
transistors in weak inversion.
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