Anda di halaman 1dari 112

Alcatel-Lucent GSM

A9130 MFS Evolution Hardware


Description

MFS Document
Sub-System Description
Release B10

3BK 21270 AAAA PCZZA Ed.03

BLANK PAGE BREAK

Status

RELEASED

Short title

A9130 MFS Evolution HW Description


All rights reserved. Passing on and copying of this document, use
and communication of its contents not permitted without written
authorization from Alcatel.

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3BK 21270 AAAA PCZZA Ed.03

Contents

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Subracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
A9130 MFS Evolution Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
9 JBXGPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3
21 JBXGPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4
Rack Shared Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.5
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cabinet Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Layout and Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Dimensions and Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Temperature and Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2
Atmospheric Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3
Solar Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4
Dust and Particles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5
Lighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6
Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7
Green Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Power Distribution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Power Station Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
Connection to the Hosted Shelves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6
Earthing Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.7
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.8
Provision for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.9
JSXPDU Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.10
Power Distribution Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATCA Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
ATCA Shelf Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2
Node Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3
Hub Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4
Rear Transition Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5
Power Entry Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7
Blowers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.8
Shelf Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.9
Personality Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.10
Air Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.11
Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.12
Distribution Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.13
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
JBXOMCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

4.2.2
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
JBXSSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5
Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6
Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
JAXSSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3
Ethernet Uplink Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
JBXGPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2
JBXGPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
JAXSMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2
Payload Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3
Shelf Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.4
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.5
Frame Ground and ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.6
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.7
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.8
Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
JAXPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2
Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.3
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.4
Alarm I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.5
Handle Toggle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.6
Alarm Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.7
Shelf Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
JBXPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1
JBXPS Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.4
Handle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
JBXFAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1
Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.2
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3
Handle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10
ATCA Fillers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.1
JBXFILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.2
JAXFILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JSXLIU/JSXLIUB Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
JSXLIU/JSXLIUB Shelf Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2
Shelf Position in the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4
Mechanical Housing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5
JSXLIU/JSXLIUB Shelf Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
JBXLIU/JBLIU75 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

5.3

5.4

5.5
5.6
5.7

5.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2.2
Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.2.3
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2.4
Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2.5
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
JBXMUX Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.2
JBXMUX Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.3
Front Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.4
Backplane Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.5
Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.6
Power Supply Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.7
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
JBXPEM Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4.2
JBXPEM Architecture and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4.3
Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.4.4
Back Plane Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.4.5
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Dummy Panel (JBXDUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LIU Filler (JMXF1U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LIUB Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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Figures

Figures
Figure 1: A9130 MFS Evolution 9 JBXGPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2: A9130 MFS Evolution 21 JBXGPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3: A9130 MFS Evolution 9 JBXGPU and A9130 BSC Evolution 1000 TRX Rack Shared
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4: Cabinet Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5: A9130 MFS Evolution Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6: JSXPDU Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7: JSXPDU Front View and Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8: Shelf Airflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9: Block Diagram of a Blower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10: ATCA Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11: ATCA Subrack Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12: ATCA Subrack Back View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13: Shelf Low Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14: Shelf High Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15: JBXOMCP Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 16: Location of Front Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17: Location of Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18: Location of USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19: Blade Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20: JBXSSW Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21: JBXSSW LED Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22: Base Interface LED Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 23: Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24: Reset Key Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 25: Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 26: JAXSSW Front Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27: Single Shelf Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 28: Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 29: JAXSMM Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 30: JAXSMM Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 31: JAXPC Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 32: JAXPC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 33: Rotary Switches on JAXPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 34: JBXPS Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 35: JBXPS Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 36: JBXFAN Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 37: JBXFILL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 38: JAXFILL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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Figures

Figure 39: JSXLIU/JSXLIUB Shelf in the MFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85


Figure 40: JSXLIU/JSXLIUB Shelf Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 41: JSXLIU/JSXLIUB Shelf Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 42: LIU Hosted Strips and Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 43: JSXLIU/JSXLIUB Shelf Back-Plane Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 44: Platform Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 45: JBXLIU/JBLIU75 Board Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46: JBXLIU/JBLIU75 Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 47: LIU Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 48: JBXMUX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 49: 1000 Base-T RJ45 Connector Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 50: JBXMUX Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 51: ESD Mitigation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 52: JBXPEM Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 53: JBXPEM Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 54: JBXPEM Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 55: JBXPEM Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 56: JBXDUM Front and Side Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 57: JMXF1U Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 58: JSXLIUB Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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Tables

Tables
Table 1: A9130 MFS Evolution Configuration Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2: Hardware Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3: Cabinet Dimensions and Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4: Dust and/or Sand Particle Concentration Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5: JBXSSW LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6: Color Coding of Base Interface LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7: Base Interface and RTM LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8: Front Plate LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9: JAXSMM LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 10: JAXPC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 11: Handle Toggle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12: JBXPS LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 13: Handle Switch Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 14: JBXFAN LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 15: Handle Switch Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 16: JSXLIU/JSXLIUB Shelf Backplane Weight and Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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3BK 21270 AAAA PCZZA Ed.03

Preface

Preface
Purpose
Whats New

The A9130 MFS Evolution Hardware Description describes the cabinets,


subracks and modules of the A9130 MFS Evolution.

In Edition 03
Description improvement in NE1OE Block (Section 5.3.2.1).

In Edition 02
Description improvement in JBXGPU (Section 4.5).

In Edition 01
First release of the document.

Audience

This manual is intended for:


Commissioning personnel
System support engineers
Training department personnel (for reference use)
Any other personnel requiring an overview of the A9130 MFS Evolution
hardware.

Assumed Knowledge

3BK 21270 AAAA PCZZA Ed.03

The reader must have a general knowledge of telecommunications systems,


terminology and A9130 MFS Evolution functions.

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Preface

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3BK 21270 AAAA PCZZA Ed.03

1 Overview

1 Overview
The Overview provides information needed by project managers and foremen,
for presentation to the customer and for site planning.

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1 Overview

1.1 Cabinet
The A9130 MFS Evolution hardware consists of an indoor cabinet which
is housed in a telecommunications building. It contains subracks, power
distribution unit, PBAs, modules and cabling.
The cabinet is designed for buildings with a minimum ceiling height of 2.7
meters.
Cable entry to the cabinet can be from:
The top
If the cabinet is mounted on a solid floor, cable ducts in the ceiling carry the
cables to the top of the cabinet.
The bottom
If the cabinet is mounted on a raised floor, cable ducts in the floor carry the
cables to the bottom of the cabinet.
The cabinet consists of a rack fitted with front and rear doors. When the
doors are closed, the equipment is EMI protected. The doors can be easily
removed for maintenance.
The arrangement of the subracks in the cabinet takes into account the
requirements for:
Thermal cooling, achieved with forced-air cooling
Minimization of floor space
Ease of access for maintenance, from the front of the cabinets
Future system expansion.

1.2 Subracks
The following types of subracks are used in the A9130 MFS Evolution:
ATCA
The ATCA 19" subrack is made of stainless steel. There is one mounting
bracket on each side of the shelf, designed for front-mounting into a rack.
Depending on the rack in which the shelf is installed, there are two possible
locations for the mounting brackets on the side of the shelf.
For more information about ATCA subracks and hosted boards, refer to
ATCA Shelf (Section 4).
Line Interface Unit (JSXLIU/JSXLIUB)
The JSXLIU/JSXLIUB subrack assumes the concentration of 256 E1 on one
Giga Ethernet link.
For more information about JSXLIU/JSXLIUB subracks and hosted boards,
refer to JSXLIU/JSXLIUB Shelf (Section 5).
Power Distribution Unit (JSXPDU).
The JSXPDU provides power distribution inside the cabinet.
For more information about the JSXPDU, refer to Power Distribution Unit
(Section 3.1).

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1 Overview

1.3 Configurations
1.3.1 A9130 MFS Evolution Naming Conventions
The following table lists the naming conventions used for A9130 MFS Evolution
configurations.
9* JBXGPU

This configuration allows up to 9* active JBXGPU


boards and 1 standby JBXGPU board.

21 JBXGPU

This configuration allows up to 21 active JBXGPU


boards and 1 standby JBXGPU board.

: In case of centralized clock synchronization mode the number of GP is limited


to 8 GP instead of 9 GP.

Table 1: A9130 MFS Evolution Configuration Naming Conventions


The follwing table gives the boards allocation for the main ATCA shelf.
Physical
Qty

JBXSSW

JBXGPU
number

1 to 9

8
x

10

11

12

13

14

+1 spare
x

JBXOMCP 2
JAXSSW

7
x

Boards

slots

x
x

: In case of centralized clock synchronization mode the number of GP is limited to 8 GP instead of 9 GP.

: Slot is not used and closed with a filler

JBXGPU0 is always in slot 5 for redundancy function.


Configuration evolution and shelf filling from JBXGPU 1 to 9* is done from
left side to right side.
The follwing table gives the boards allocation for the extension ATCA shelf.
Physical
Boards
JBXSSW

JBXGPU
number

1 to 12

10

11

12

13

14

8
x

15

JAXSSW
u

Qty

7
x

slots

10

11

12

13

14

16

17

18

19

20

21

: Slot is not used and closed with a filler

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1 Overview

Configuration evolution and shelf filling from JBXGPU 10 to 21 is done from


left side to right side.

1.3.2 9 JBXGPU Configuration


The following figure shows the rack layout in an A9130 MFS Evolution 9
JBXGPU configuration (stand-alone).

JSXPDU

Free space
(JSXATCA Shelf 4)

OPEN

H/S OOS

OPEN

JBXGPU

JBXGPU

JBXGPU

H/S OOS

JBXGPU

JBXGPU

JBXSSW

JBXOMCP

JBXSSW

JBXGPU

CLOSED

JBXOMCP

CLOSED

H/S OOS

JBXGPU

H/S OOS

OPEN

JBXGPU

OPEN

JBXGPU

JSXATCA
Shelf 3

CLOSED

JBXGPU

CLOSED

1234567890123456789
1234567890123456789
Air inlet
1234567890123456789
1234567890123456789
Free space
1
XPEM

JSXLIU
Shelf 1

48 / 60
VDC

2
XLIU

3
XLIU

4
XLIU

5
XLIU

6
XLIU

7
XLIU

10

XLIU

XLIU

XMUX

11

12

13

14

XMUX

XDUM

XDUM

15
XDUM

16
XDUM

17
XDUM

18
XDUM

19
XDUM

20
XDUM

21
XPEM

48 / 60
VDC

4A
4A

Figure 1: A9130 MFS Evolution 9 JBXGPU Configuration

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1 Overview

1.3.3 21 JBXGPU Configuration


The following figure shows the rack layout in an A9130 MFS Evolution 21
JBXGPU configuration.

JSXPDU
OPEN

H/S

OOS

JBXGPU
JBXGPU

JBXGPU

JBXSSW
JBXGPU

CLOSED

OOS

OPEN

JBXGPU

JBXGPU

OOS

JBXGPU

H/S

JBXSSW

OPEN

CLOSED

JBXGPU

H/S

OOS

JBXGPU
JBXGPU

H/S

JBXGPU

OPEN

CLOSED

JSXATCA
Shelf 4
(Extended Shelf)

JBXGPU

CLOSED

12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
12345678901234567890
/

H/S

OOS

H/S

OPEN

OOS

JBXGPU

CLOSED

JBXGPU

OOS

JBXGPU

H/S

OPEN

JBXGPU
JBXGPU

OPEN

JBXSSW

JBXSSW
JBXOMCP

JBXGPU

CLOSED

JBXOMCP

OOS

JBXGPU
JBXGPU

H/S

JBXGPU

OPEN

CLOSED

JSXATCA
Shelf 3
(Main* Shelf)

JBXGPU

CLOSED

12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
12345678901234567890
Free space
1
XPEM

JSXLIU
Shelf 1

48 / 60
VDC

2
XLIU

3
XLIU

4
XLIU

5
XLIU

6
XLIU

7
XLIU

XLIU

XLIU

10 11 12 13 14 15
XMUX

XMUX

XLIU

XLIU

XLIU

16 17 18 19
XLIU

XLIU

XLIU

XLIU

20 21
XLIU

XPEM

48 / 60
VDC

4A
4A

: In 21 JBXGPU configuration (Multishelf), the main shelf (the one containing the
OMCP boards) is always ATCA shelf 3.

Figure 2: A9130 MFS Evolution 21 JBXGPU Configuration

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1 Overview

1.3.4 Rack Shared Configuration


The following figure shows the rack layout for an A9130 MFS Evolution 9
JBXGPU and an A9130 BSC Evolution 1000 TRX rack shared configuration.

JSXPDU
CLOSED

H/S

OPEN

OOS

OOS

JBXCCP

Not Used

OOS

H/S

JBXCCP
Not Used

H/S

OPEN

JBXCCP

OPEN

JBXTP

JBXSSW
JBXOMCP

JBXSSW

CLOSED

JBXCCP
JBXOMCP

OOS

JBXCCP

H/S

JBXTP

OPEN

CLOSED

ATCA
Shelf 4
(BSC)

JBXCCP

CLOSED

12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
12345678901234567890
OOS

CLOSED

H/S

OPEN

OOS

H/S

OOS

JBXGPU
JBXGPU

JBXGPU

H/S

OPEN

JBXGPU

OPEN

JBXGPU

JBXSSW
JBXOMCP
JBXGPU

JBXSSW

CLOSED

JBXOMCP

OOS

JBXGPU

H/S

JBXGPU

OPEN

CLOSED

ATCA
Shelf 3
(MFS)

JBXGPU
JBXGPU

CLOSED

12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
12345678901234567890
1

XPEM

LIU
Shelf 2
(to BSC)

2 3 4

XLIU

XLIU

XLIU

5 6 7 8

XLIU

XLIU

XLIU

XLIU

XLIU

9 10 11 12 13 14 15 16 17 18 19 20 21

XMUX

XMUX

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

48 / 60
VDC

48 / 60
VDC

4A

4A

1
XPEM

LIU
Shelf 1
(to MFS)

XPEM

2 3 4
XLIU

XLIU

XLIU

5 6 7 8
XLIU

XLIU

XLIU

XLIU

XLIU

48 / 60
VDC

4A

9 10 11 12 13 14 15 16 17 18 19 20 21
XMUX

XMUX

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

XLIU

XPEM

48 / 60
VDC

4A

Figure 3: A9130 MFS Evolution 9 JBXGPU and A9130 BSC Evolution 1000
TRX Rack Shared Configuration

Note:

In rack shared configuration, the MFS can also be positioned in the upper
ATCA shelf:
ATCA Shelf 4 -> MFS
ATCA Shelf 3 -> BSC.

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1 Overview

1.3.5 Standards
The complete system is fully compliant with:
PICMG 3.0 R1.0 (AdvancedTCA) specifications defining mechanics, board
dimensions, power distribution, power and data connectors and system
management.
EN 60950 - Safety of Information Technology Equipment safety standard.
EN 55022 - EMC requirements on system level
ANSI/IPC - A610 Rev.C Class 2 Manufacturing Requirements.

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1 Overview

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2 Cabinet Description

2 Cabinet Description
Cabinet Description describes the A9130 MFS Evolution cabinet and the
required environmental conditions.

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2 Cabinet Description

2.1 Layout and Facilities


The A9130 MFS Evolution equipment is housed in a single 19 standard rack.
The rack provides:
Mechanical housing for up to two ATCA shelves
Connection of the secondary power supply, via duplicated -48V or -60V
distribution, through a power distribution shelf called the JSXPDU
Connection of the external links, essentially comprised of E1 interfaces and
Giga Ethernet on balanced pairs
Safety protection to industry standards.
The following figure shows the layout of the cabinet.
JSXPDU

JSXATCA Shelf 4

Cable
Pipes

JSXATCA Shelf 3

Free Space

JSXLIU Shelf 1

Plinth

Figure 4: Cabinet Layout


The front door is 80% perforated (the maximum possible perforation for the
allowed space).
A 100 mm plinth is provided to allow site installation without opening the
equipment, or to allow back cable entry on a concrete floor. Four levelling
screws provided to allow rack levelling.

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2 Cabinet Description

The front upright racking is welded 100 mm from the front door internal face to
allow space for cables. The back racking upright position can be adjusted to fit
the depth of the ATCA shelves hosted in the cabinet.
The top of the cabinet can be completely removed (including when cable
entry is located at the top of the equipment) to allow easy access for on-site
cabling. It is reversible (front to back) to allow access from the left or right sides,
depending on the configuration. For a corner installation, part of the installation
kit is bolted to the racks using the ring hooks of the cabinet, therefore allowing
the use of a vertical cable guide.
The following facilities are provided for site cabling:
When cable entry is from the bottom, a rectangular pipe is installed on
each side, between the front and the back upright racking, to easily allow
14 power cables (14 mm in diameter ) to be fed from the bottom to the
top (seven on each side)
When cable entry is from the top, these pipes are used to feed 32 PCM
cables (9 mm in diameter and equipped with a 12 x 66 mm connector) from
the top to the bottom (16 on each side). In this case, up to six Ethernet
cables (8 mm in diameter) can also be fed through these pipes.
The bottom of the rack has three windows for bottom cable entry:
One window at the front, covering the complete usable width of the
JSXLIU/JSXLIUB shelf and dedicated principally to PCM cables access
One window on each side, under the pipes, used for power cables routing in
case of bottom access and for PCM cables routing in case of top access.

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2 Cabinet Description

2.2 Hardware Architecture


The following figure shows the hardware architecture of the A9130 MFS
Evolution.

JBXGPU 1

JBXSSW

JBXGPU n

(duplicated)

JBXMUX w

Radio Network links

(duplicated)

JBXLIU 1
E1

JBXOMCP w
(duplicated)

JBXLIU n

JBXOMCP r

JSXLIU Shelf
(21 slots)

JSXATCA Shelf (14 slots)


External Ethernet Links

Figure 5: A9130 MFS Evolution Hardware Architecture


The following table lists the functions provided by each functional block.
Functional Block
Gigabit Ethernet switch (JBXSSW)

Allows exchanges between all


platform elements and external
IP/Ethernet equipment.

O&M Control Processing board


(JBXOMCP)

Acts as system manager for the whole


platform and for O&M applications.

Radio Processing board (JBXGPU)

Manages the user plane packet data


flow processing.

Line Interface Unit (JSXLIU/JSXLIUB)


shelf

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Function

Multiplexes/demultiplexes and cross


connects all E1 external links to/from
NE multiplexed links (n E1 over
Ethernet) on the JBXGPU board.
Equipped with two JBXMUX boards
and n JBXLIU/JBLIU75 boards,
depending on capacity.

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2 Cabinet Description

Functional Block

Function

JBXLIU/JBLIU75 boards (the


interface for radio network links)

These links correspond to the user


plane interfaces.

Ethernet links on the IP ports of the


JBXSSW switch

These links connect the platform to


external IP equipment (i.e. OMC-R,
external alarm box).

Table 2: Hardware Functions

2.3 Dimensions and Weight


The following table describes the cabinets external physical dimensions.
Dimension

Overall Size (mm)

Height

2000 (including a 100 mm plinth)

Width

600

Depth

600

Maximum weight

300 kg

Table 3: Cabinet Dimensions and Weight

2.4 Environment
The equipment must not be exposed to extremes of temperature, or to relative
humidity. To meet the required environmental conditions, air conditioning
equipment may have to be installed.
The environmental conditions are:
Temperature and humidity
Atmospheric pressure
Solar radiation
Dust and particles
Lighting
Cooling
Safety standards
Green compliance.

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2 Cabinet Description

2.4.1 Temperature and Humidity


For altitudes between sea level and 500 meters, the temperature must be
between + 5C and + 40C, within a relative humidity band of between 20 % to
80 %. The temperature gradient must be less than 0.5C per minute.
Electrostatic Danger
Electrostatics may cause minor shocks and/or damage to the equipment.
The relative humidity must be at least 20 % at manned sites or during
maintenance periods.
Cooling, EMI conditions and noise emission are respected only if the doors
are closed during operation.

2.4.2 Atmospheric Pressure


For normal operation of the equipment, the atmospheric pressure must be
between 65 kilopascals (kPa) and 120 kPa. Low pressure extremes must not
be allowed to coincide with upper temperature limits.

Note:

An altitude of 3500 meters corresponds to a pressure of approximately 65.7


kPa.

2.4.3 Solar Radiation


Direct Solar Radiation
Exposure to direct solar radiation may result in damage to equipment due
to overheating.
Ensure that equipment is not subject to direct sunlight.

2.4.4 Dust and Particles


The equipment operates normally in the presence of solid (non-conductive,
non-ferromagnetic, non-corrosive) particles. The following table lists the
maximum sizes and concentrations of particles.
Size of Particles
(micrometers)

Concentration
(millions of particles per cubic meter)

0.5

14

0.7

0.24

0.13

Table 4: Dust and/or Sand Particle Concentration Levels

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2.4.5 Lighting
All optical signals, displays and labels are visible with an ambient light intensity
of 800 lux.

2.4.6 Cooling
The A9130 MFS Evolution equipment uses forced air cooling.

2.4.7 Green Compliance


The A9130 MFS Evolution cabinet complies with the new European directives
concerning the environment:
Wastes of Electrical and Electronic Equipment (WEEE)
The requirements for re-use and recycling capabilities are applicable to the
complete A9130 MFS product line (not only for the cabinet).
Restriction of Hazardous Substances (RoHS).

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3 Power System

3 Power System
Power System describes the power distribution system of the A9130 MFS
Evolution.

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3 Power System

3.1 Power Distribution Unit


3.1.1 Introduction
The new generation of MFS equipment referred to as A9130 MFS Evolution is
housed in a single 19 standard rack called the JRXCAB. Power distribution
inside this cabinet is handled by the Power Distribution Unit (JSXPDU) shelf,
which provides:
Connection to a duplicated secondary -48V or -60V power supply
distribution, through 35 mm2 double skin cables
Breakers and power supply distribution to ATCA shelves (75A each) and
JSXLIU/JSXLIUB shelves (10A each)
Safety protection to industry standards.
In order to supply the two JSXATCA shelves and the two JSXLIU/JSXLIUB
shelves of an A9130 MFS cabinet, the JSXPDU shelf meets the following
external requirements:
19 standard shelf
Connection to the power plant via 12 double skin 35mm2 cables, with
an overall diameter of 14mm each
2

Connection to the loads via 24 x 16 mm cables with an overall diameter


of 7mm each
2

Connection to ground via one double skin 35mm cable with an overall
diameter of 14 mm
Cabling access from the top back part of the equipment
Paint color according to Alcatel standards
The front panel is covered by a light grey label (the other face is not painted)
EMC shielding is not required (no active part)
Earthquake protection
Fire protection
Compliance with the new European directives concerning the environment
Meets the RoHS and WEEE requirements
Safety protection is provided via two independent covers.

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3.1.2 Mechanical Characteristics


The JSXPDU is a standard 19 shelf, 2U in height. The racking brackets are
mounted 60 mm behind the front panel. The overall depth is approximately
250 mm.

3.1.3 Schematic
The JSXPDU consists of two independent branches, the BATA and BATB.
Each branch of the JSXPDU shelf is composed of three independent
distribution systems, independently powered by two 35 mm2 wires with double
skin insulation:
Each distribution system (1 or 2) includes:
One 75A breaker with two outputs
One 10A breaker with one output.
Each distribution system includes one 75A breaker and two outputs.
Each branch comprises:
Three 75A breakers, to supply up to two ATCA shelves. The third 75A
breaker is equipped for future use.
Two 10A breakers, to supply up to two JSXLIU/JSXLIUB shelves.
Branch A

JSXLIU 1

B1 B2

B3 B4

Not used

BATR

JSXATCA 3

A5

JSXLIU 2

JSXATCA 4

JSXLIU 1

A3 A4

Not used

A1 A2

Branch B
BATB

BATR

JSXATCA 3

JSXLIU 2

JSXATCA 4

BATA

B5

Figure 6: JSXPDU Overview

3.1.4 Power Station Connection


Connection to the power station is via two or more 35 mm2 double skin wires
per ATCA shelf and per branch. The JSXPDU therefore provides connection to
the power station via 12 x 14mm power cables and one 14mm ground cable.

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3 Power System

3.1.5 Connection to the Hosted Shelves


Each ATCA shelf is connected to the JSXPDU via eight 16 mm2 wires (7mm in
diameter).
Each JSXLIU/JSXLIUB shelf is connected to the JSXPDU by two 7 mm (three
1.5 mm2 wires ) cords, including the ground.

3.1.6 Earthing Connection


The buildings ground is connected to the JSXPDU by a double stud. This
earthing conductor is distributed to the JSXLIU/JSXLIUB shelves through the
power cord, and to the mechanics of the cabinet via a double stud. A specific
label is added near the connection of the earthing conductor.

3.1.7 Safety
The JSXPDU meets the EN 60950 safety standards. Branch A and branch B are
be independently protected by two separate covers so that service personnel
can safely access one power branch when the other branch is operational.

3.1.8 Provision for Future Use


In the case where an alarm function will be added in the JSXPDU, a free space
of approximately 25 mm width of the whole height (2U) is reserved between
both branches A and B. The front plate is bored with a column of five 4mm
holes. These holes will be hidden by the label which covers the whole front
panel and bears the marking.

3.1.9 JSXPDU Front View


The following figure shows the front view of the JSXPDU.
A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

Shelf 4

Shelf 2

Shelf 4

Shelf 2

Shelf 3

Shelf 1

Shelf 3

Shelf 1

Figure 7: JSXPDU Front View and Marking

3.1.10 Power Distribution Cable Characteristics


3.1.10.1 ATCA Shelves Supplying
The power entry on ATCA shelves is done via 6 mm studs. The power cables
coming from the JSXPDU shelf are terminated by lugs rings.
The cable used is a two wire, 16 mm2 cable. The blue wire corresponds to
VBAT. The black marked wire corresponds to the Battery Return.
The required cable lengths are:
1.5 m for the upper ATCA shelf
2.1m for the second ACTA shelf.

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3.1.10.2 ATCA Shelf Grounding


The ATCA grounding point is a double lug, spaced at 19 mm. The 16mm2
yellow/green ground cable is terminated by a lug with two holes.
There are two possibilities for the ground connection:
One cable between each ATCA shelf and the JSXPDU (same length as
power cable), or
The frame of the cabinet is used as ground, and the JSXPDU and the ATCA
shelves are connected to the frame by a cable.

3.1.10.3 JSXLIU/JSXLIUB Shelf Supply and Grounding


The power connection on the JSXLIU/JSXLIUB shelves is done through three
pin UP connectors. The connector is composed of a moulding and three
contacts.

3.2 Cooling
The JSXATCA shelf provides fault tolerant cooling to front mounted Advanced
Telecom Computing Architecture (Advanced TCA) blades, and to rear transition
modules based on four front-maintainable, intelligent fan trays, with one fan
per tray.
Blower trays are mounted in the shelf top. The following figure shows the
general airflow for the ATCA system. The cooling type is front to rear.

Blowers

Air Outlet

Front

Rear

Air Inlet
Figure 8: Shelf Airflow
The cooling system is designed to manage a heat dissipation of 200W per
front slot and an additional 20-30W per rear slot.
Each of the fan tray units contains an IPMC, which is located on both the
IPMB-A and IPMB-B buses. Individual fan failures are detected by monitoring
the fan rotation speed. Rotation which is 15% below demand is deemed to be a
fan failure. Usually the cooling system runs the fans at 40%. In the case of a

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3 Power System

single fan failure, the fans run at 100% to still provide full air pressure within the
area between the fans and the boards.
Each fan tray monitors and reports air temperature and failure conditions to the
shelf manager. The shelf manager controls the fan speed based on sensor
and failure information acquired from the fan and board sensors. If a fan
tray looses IPMI communication with the shelf manager, it will automatically
run the fans at full speed.
The following figure shows the block diagrams with the main components
of the blower.

HA

Tach

B
l
o
w
e
r
P
C
B

IPMC Bus 1
PWM
IPMC Bus 2
LEDs

RiCool 2
Controller

Hot Swap Switch

Enables

Flame Sensor
Flame Sensor

48 A
48 B
+ V_A
+ V_B

C
o
n
t
r
o
l
I
n
t
e
r
f
a
c
e

Figure 9: Block Diagram of a Blower


JSXLIU/JSXLIUB shelf cooling is managed by natural convection.

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4 ATCA Shelf

4 ATCA Shelf
This section describes the ATCA shelf and its components.

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4 ATCA Shelf

4.1 ATCA Shelf Description


The ATCA shelf is designed for "five nines" uptime (99.999%).
The shelf provides 14 slots which can be equipped with Advanced TCA blades
and corresponding Rear Transition Modules (RTM) at the rear of the system.
The 14 slots are typically set up as two hub slots and 12 node slots.
This is shown in the following figure.

Fan Trays

Air Inlet

Figure 10: ATCA Shelf


The system is always equipped with:
A dual star backplane providing connector interfaces for power distribution,
input/output connectivity between front blades, and mechanical alignment
and support
A backplane with base and fabric interface
A subrack providing attachment points for the backplane, alignment and
support, and a mechanical engagement for insertion and extraction of
the front blades and RTMs
Two JAXSMM shelf manager boards. Each blade and Field Replaceable
Unit (FRU) provides links to the shelf manager through an Intelligent
Platform Management Bus (IPMB)
12 node slots which can be equipped with Advanced TCA node blades
Two hub slots which can be equipped with Advanced TCA hub blades
14 slots at the systems rear side which can be populated with 14 RTMs.
These RTM connections provide user defined input and output connectivity
to the corresponding front blades
Four IPMC-enabled intelligent blowers
Four single entry DC Feed intelligent JBXPSs with 90 Amp / 50 Amp
breakers and line filters
Two alarm boards

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4 ATCA Shelf

An air filter
Rear ESD wrist strap sockets and grounding studs.
The following figures show the ATCA subrack front and back views.
CLOSED / OPEN

H/S OOS

CLOSED / OPEN

H/S OOS

CLOSED / OPEN

H/S OOS

CLOSED / OPEN

H/S OOS

12345678901234567890123456789012
12345678901234567890123456789012
Air inlet
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Figure 11: ATCA Subrack Front View

12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Air outlet
12345678901234567890123456789012
12345678901234567890123456789012

JAXPC

ACT

Telco Alarms & Relays

OK

ACT

Telco Alarms & Relays

OOS

OK

H/S

JBXPS

Open

Handle

+(RETURN)

JBXPS

Closed

Closed
Open

M100
H/S

OOS

OOS
OK

OK

JAXPC
JAXPC

JBXPS

A TCA

M100
H/S

JAXSMM
JAXSMM

JBXPS

+(RETURN)

+(RETURN)

+(RETURN)

H/S

A TCA

GND

Alarm/
Reset

Alarm/
Reset

Handle

(POWER)

(POWER)

(POWER)

(POWER)

JAXPC

OOS

Figure 12: ATCA Subrack Back View

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4 ATCA Shelf

4.1.1 Shelf
The 13U (577 mm) and 440 mm deep shelf for 19" racks is made of stainless
steel.
There is one mounting bracket on each side of the shelf, designed for
front-mounting the shelf into a rack.
The system can be installed in a standard 19 rack.

4.1.2 Node Slots


The node slots are equipped with Advanced TCA blades.
Advanced TCA blades used in MFS configuration are the following
high-performance, single slot, hot-swap node boards:
JBXOMCP
JBXSSW.
Advanced TCA blades offer a high processing performance. They are ideal
for telecommunication applications.

4.1.3 Hub Slots


The hub slots are equipped with JBXSSW switches. The JBXSSW is a Gigabit
Ethernet switch.

4.1.4 Rear Transition Modules


The Advanced TCA blades can be connected to Rear Transition Modules
(RTM) to provide easy access to I/O signals through the zone 3 connector
defined by the Advanced TCA specifications.
RTMs can be used as a rear expansion board for the JBXSSW switch to access
the different interfaces on an AdvancedTCA blade through the JAXSSW
front plate.

4.1.5 Power Entry Modules


Four field hot-swap intelligent JBXPSs with a 50 Amp breaker and line filter
are installed beneath the rear slots of the backplane. The four JBXPSs are
used to provide split power distribution. For details about the JBXPS refer to
JBXPS (Section 4.8)

4.1.6 Power Distribution System


The shelf has two different power distribution systems that run throughout the
shelf. The first is a low power (3.4VVDC) system that provides power to all of
the IPMCs. The second is a high power (-48VDC) system that provides power
to all of the blades, blowers and shelf managers.

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4.1.6.1 Low Power Distribution System


The shelfs low power distribution system powers the IPMCs engines. This
low power source (3.4V DC) manifests itself in the form of a redundant
interconnect. The first (V_A) is sourced from the JAXSMM in the J3 location.
The second (V_B) is sourced from the JAXSMM in the J11 location. The IPMCs
are expected to OR the two sources to allow for redundancy. Current on each
source is limited by the 2 mm connector to approximately 1.5 A.
The inclusion of the low power distribution system is to allow for powering the
IPMCs without having to include an isolated DC-DC and all of its related
circuitry in each IPMC. This is most useful in FRUs such as the blowers and
JAXPCs, where their size essentially prohibits the inclusion of such power
conversion circuitry.
The voltage from the power distribution system can also be found on the
optional IPMC expansion connectors found throughout the shelf.
The following figure shows the low power distribution system found in the
JBXPS shelf.
J
B
X
O
M
C
P

Physical Slot

J
B
X
S
S
W

J
B
X
S
S
W

J
B
X
O
M
C
P

10

11

12

13

14

JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN

JBXPS1
A1

JBXPS2
B1

JBXPS3
A2

JBXPS4
B2

Figure 13: Shelf Low Power Distribution System

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4.1.6.2 High Power Distribution System


The shelfs high power distribution system is for powering the blade, JAXSMMs
and blowers. This high power source (-48V DC - nominal) manifests itself in
the form of one or two sets of redundant interconnects. The JBXPS shelf has
two set of redundant interconnects.
The following figure shows the high power distribution system.
J
B
X
O
M
C
P

Physical Slot

J
B
X
S
S
W

J
B
X
S
S
W

J
B
X
O
M
C
P

10

11

12

13

14

JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN

JBXPS1
A1

Outside the chassis

JBXPS2
B1

Battery
plant A

JBXPS4
B2

JBXPS3
A2

Battery
plant B

Figure 14: Shelf High Power Distribution System

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The first redundant interconnect is made up of the A1 and B1 feeds. The first
feed (-48V_A1) is sourced from the A1 JBXPS in the far left (as viewed from the
rear of the shelf). The second feed (-48V_B1) is sourced from the B1 JBXPS to
the right of the first one. Both feeds are individually routed to each JAXSMM,
blower and odd numbered slots. The second redundant interconnect is made
up of the A2 and B2 feeds. The third feed (-48V_A2) is sourced from the A2
JBXPS (to the right of the B1 JBXPS). The fourth feed (-48V_B2) is sourced
from the B2 JBXPS (to the right of the A2 JBXPS). These feeds only route to
the even numbered slots. In both interconnects, the FRUs are expected to OR
the two sources to allow for redundancy.
The A1 and B1 JBXPS locations are capable of supplying 90 A of current,
although the JBXPSs will only allow for 50 A. The A2 and B2 JBXPS locations
are capable of supplying 50 A. This allows for a single JBXPS in each
interconnect, to support the full power requirement of the interconnect.
For the blowers, the A1 and B1 feeds are capable of supplying 12 A when
derated for a 30 C temperature rise. For the JAXSMMs, the A1 and B1 feeds
are limited by the 2 mm connector to approximately 1.5 A (per feed).

4.1.7 Blowers
The system provides fault-tolerant cooling by using four front accessible,
hot-swap intelligent fan trays. Each fan tray contains one blower with built-in
speed control. A toggle switch is provided to allow supervision interruption
for maintenance reasons.

4.1.8 Shelf Manager


The shelf manager (JAXSMM) is designed to be used in Advanced TCA
systems. It is the central management unit of the shelf. It monitors, controls
and ensures the proper operation of the shelf and all other components of
the Advanced TCA shelf.
It reports anomalies and errors and takes corrective actions if required (e.g.
increases the speed of the blowers). The JAXSMM has access to detailed
inventory information as well as to sensor status information concerning the
shelf and all the components of the shelf.

4.1.9 Personality Card


The personality card (JAXPC) is a shelf configuration and alarm board used
with AdvancedTCA systems. The JAXPC personality card is designed for rear
access applications. It is located below the Rear Transition Module (RTM) area.

4.1.10 Air Filter


The air filter is located in the lower part of the shelf. It ensures that the shelf
operates properly. Regular cleaning and replacement is mandatory.

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4.1.11 Backplane
The backplane provides the following features:
Two hub slots
12 node slots
14-slot fabric interface with a dual star interconnect
A base interface with a dual star interconnect
An update interface between physical adjacent slots
A base interface to the shelf manager slots
Bused IPMB-0 connections
Synchronization of clock buses.

4.1.12 Distribution Board


The distribution board has the following features:
Power lugs and studs for power transfer to the backplane
Blower interface
Interface for two shelf manager boards
Support for up to four JBXPSs
Interfaces for two JAXPC personality cards (Telco I/O).

4.1.13 Mechanical Data


The following table describes the dimensions and the weight of the system.
Measurement

Value

Height

577 mm (13U)

Width

438 mm (14 x 6HP)

Rack mounting

482.6 mm (19)

Depth from rack mounting pane

Top: Towards the front 60 mm in the


blower area
Middle: The wiring area is compliant
with PICMG 3.0
Bottom: Towards the rear 415 mm in
the JBXPS area

Weight

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38kg (Without ATCA blades and


RTMs)

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4.2 JBXOMCP
4.2.1 Introduction
The JBXOMCP is an Advanced TCA compliant single board computer offering
high processing performance. Four on-board PMC sites, a redundant GBit
Ethernet connection to the ATCA Base interface and standard I/O interfaces
make it ideal for telecommunication and datacom applications.
It provides the following features:
A Pentium M processor with up to 1.8 GHz speed
Up to 4 GByte main memory SDRAM with ECC protection
Redundant ATCA Base interface
Two USB 2.0 interfaces on the front plate
60 GByte hard disk
Support for Carrier Grade Linux Ed. 3.1
On-board IPMC compliant to IPMI V.1.5 with redundant IPMB support
Different Rear Transition Modules (RTM) available separately
A CMC module providing two serial interfaces on the front plate.

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4.2.2 Front Plate


The following figure shows the connectors, keys and LEDs available on the
front plate.

JBXOMCP

o
o
s
O
K

P
M
C
1

A
C
T
H
D
D
U
S
B
1
U
S
B
2

P
M
C
2

P
M
C
3
R
E
S
E
T

H
/
S
P
M
C
4

Figure 15: JBXOMCP Front Plate

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4.2.3 LEDs
The following figure shows all LEDs available on the front plate.

o
o
s

O
K

A
C
T
H
D
D

P
M
C
2

H
/
S

Figure 16: Location of Front Plate LEDs


The following table describes the JBXOMCP LEDs.
LED

Description

OOS

Out Of Service
Red: The blade is out of service
OFF: The blade is working properly

OK

Power status
Green: Supply voltages are within threshold values
OFF: Supply voltages are outside threshold values

ACT

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LED

Description

HDD

During booting this LED indicates the boot status. Later


it indicates the combined parallel/serial ATA activity or is
used as user LED. Toggling between both modes is done
via the LED control register.
In user mode:
Depending on the FPGA LED control register, the LED
is either red, green or OFF.
In parallel/serial ATA activity mode:
Red: Combined activity of parallel and serial ATA
interfaces.
OFF: No activity.

H/S

Hot swap
During blade installation:
Permanently blue: On-board IPMC powers up
Blinking blue: Blade communicates with the Shelf
Management controller
OFF: Blade is active
During blade removal:
Blinking blue: Blade notifies the Shelf Management
controller of its desire to deactivate.
Permanently blue: Blade is ready to be extracted.

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4.2.4 Keys
The blade provides one front plate reset key. This is shown in the following
figure.

P
M
C
3
R
E
S
E
T

H
/
S

Figure 17: Location of Reset Key


On pressing the reset key, a hard reset is triggered and all attached on-board
devices are reset.

Note:

The IPMC is not reset via this key.

4.2.5 Connectors
4.2.5.1 Front Plate Connectors
The blade provides two mini USB 2.0 connectors (type AB) on its front plate.
They correspond to the USB interfaces 1 and 2. These interfaces are not
used for MFS application.
This is shown in the following figure.
A
C
T
H
D
D
U
S
B
1
U
S
B
2

P
M
C
2

Figure 18: Location of USB Connectors

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4.2.5.2 On-Board Connectors


The blade provides the following on-board connectors:
CompactFlash
PMC
Parallel ATA
Serial ATA
CMC
ATCA backplane connectors.

4.2.5.3 ATCA Backplane Connectors


The ATCA backplane connectors reside in zones 1 to 3, as specified in the
ATCA standards.
The connector located in zone 1 is used to draw power from the backplane.
Zone 2 contains the 3 connectors P20, P21 and P23. P20 is used to support
telephony clocking. P21 and P23 are used to connect the blade to the standard
ATCA interfaces. All these connectors are standard and therefore are not
documented in this guide.
Zone 3 contains the 3 connectors P30 to P32. They are used to connect an
RTM to the blade and carry the following signals:
Serial (RS232)
Serial ATA
USB
Keyboard/Mouse
IPMI
Power
PMC user I/O.
In case of MFS application only the JBXSSW blades use the RTM.

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4.3 JBXSSW
4.3.1 Introduction
The blade provides the following features:
Advanced TCA compliant switch
Managed 24-port Layer 2 Gigabit switch for the base interface
Gigabit Ethernet support for 14 payload slots
Eight base and one fabric Gigabit Ethernet uplinks via the rear transition
module
16-port Layer 2 Gigabit Ethernet switch for the fabric interface
ATCA Management Controller (IPMI version 1.5) which communicates
with Shelf Management controllers
SNMP agent for switch management
Option for TDM clock generation and synchronization via CGM module
Designed for NEBS level 3 and ETSI requirements.
The fabric interface and clock generation and synchronization module are not
used for MFS application.
The following figure shows the main function blocks of the blade.

Compact
Flash
Card

RTC

Boot
Flash
Processor

Base
Interface
Switch

PMC Slot for


Clock
Generation
Module

Base
Interface
Switch

Fabric
Interface
Switch

Power Module

Figure 19: Blade Functional Blocks

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4.3.2 Front Plate


The following figure shows:
Position of the Ethernet interface
LEDs
Reset key
Serial interface on the front plate.

JBXSSW

P
M
C
OOS

OK

ACT

F
A
B
R
I
C

I
N
T
E
R
F
A
C
E

B
A
S
E

1
2
3
4
5

I
N
T
E
R
F
A
C
E

ABC
1
2
3
4
5
6
7
8
E
T
H
1

S L A
H/S

ETH2
RESET
S
E
R
I
A
L

ABC
ST

Figure 20: JBXSSW Front Plate

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4.3.3 LEDs
The following LEDs are available on the front plate:
Status and Ethernet LEDs
Base interface LEDs.

4.3.3.1 Status and Ethernet LEDs


The following figure shows the location of the status and Ethernet LEDs.

OOS

OK

ACT

E
T
H
1

SLA
H/S

ETH2
RESET
S
E
R
I
A
L

ABC
ST

Figure 21: JBXSSW LED Location

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The following table describes the LEDs.


Name

Color

Description

OOS

Red

Out Of Service
Red: The blade is out of service
OFF: The blade is working properly

OK

Green

Power OK
Green: The blade is operating properly
OFF: Otherwise

ACT

Amber

Active
Amber: The blade is active
OFF: The blade is in standby mode

H/S

Blue

Blue: The blade is ready to be extracted


Blinking: The blade communicates with the
JAXSMM during insertion or notifies its request
to deactivate during extraction.
OFF: The blade is not ready to be extracted.
Do not remove the board during this state.

ETH2 S - Speed

10 BaseT

Orange
ETH2 L - Link

Green

100 Base Tx

Green

ON: Link up
OFF: Link down

ETH2 A - Activity

Orange

ON: Activity
OFF: No activity

During power-up
ST A

FPGA initialized

Red

Power good 2

Green

Power good of all DC/DCs

Red

Power good 1

Green

Power up command from IPMC

Orange

ST C

Power good 3

Green
ST B

Red

Power good 1 and power up command from


IPMC are indicated

During operation

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Name

Description

Color

ST A

Indicates general activity via UART between


both boards:
Green

No activity

Orange

Activity

ST B

Indicates the status at the Ethernet heartbeat


connection:
Red

Heartbeat connection is dead

Green

Active

Orange

Warning

ST C

Indicates the status at the UART heartbeat


connection:
Red

Heartbeat connection is dead

Green

Active

Orange

Warning

Table 5: JBXSSW LED Description

4.3.3.2 Base Interface (BIF) LEDs


There is one LED per physical port, located on the front plate.
This is shown in the following figure.

1
2
3
4
5
6
7
8

B
A
S
E

I
N
T
E
R
F
A
C
E

Figure 22: Base Interface LED Location


The following table describes the LEDs.

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Color

Description

Green

Port-performed linkup but no activity

Orange

Port-performed linkup and there is


activity

Table 6: Color Coding of Base Interface LEDs


The following table describes the mapping of the physical port to the front
plate LEDs.
LED

Interface/Port

LED

Interface/Port

LED

(RTM)

(BIF)

(BIF)

Interface/Port

A1

B1

C1

17

A2

B2

10

C2

18

A3

B3

11

C3

19

A4

B4

12

C4

20

A5

B5

13

C5

21

A6

B6

14

C6

22

A7

B7

15

C7

23

A8

B8

16

C8

24

Table 7: Base Interface and RTM LEDs

4.3.4 Connectors
The front plate provides the following connectors:
RJ-45, which is used for debugging only
Serial, which is used for factory settings.

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E
T
H
1
SLA

H/S

ETH2
RESET
S
E
R
I
A
L

Figure 23: Connector Location

4.3.5 Reset Key


The front plate provides one mechanical reset key. This is shown in the
following figure.

SLA

H/S

ETH2
RESET
S
E
R
I
A
L

Figure 24: Reset Key Location


A reset of all on-board I/O devices and the CPU is performed when the reset
key is set to the active position. The reset is maintained until the key is returned
to the inactive position, however at least 200 ms are guaranteed by a local timer.

4.3.6 Backplane
The backplane provides the following connectors:
Zone 1: power connector
Zone 1 connectors are used to implement the power supply interface.
Zone 2: data transport interface
Zone 2 connectors are used to implement the base and fabric interface.
Zone 3: access to RTM.
The Zone 3 connectors provide access to the JAXSSW rear transition
module.

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4.4 JAXSSW
4.4.1 Front Plate
The following figure shows the front plate of the blade.

JAXSSW

E
T1
H
E
T2
H
E
T3
H

O
O
S

E
T4
H

O
K

E
T5
H

A
C
T

E
T6
H
E
T7
H
E
T8
H

HS

Figure 25: Front Plate

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4.4.2 LEDs
The RTM provides four LEDs on the front plate, as shown in the following figure.
All LEDs are standard ATCA LEDs.
E
T3
H

O
O
S

E
T4
H

O
K

E
T5
H

A
C
T

E
T6
H
HS

Figure 26: JAXSSW Front Plate LEDs


The following table describes the LEDs.
LED

Description

OOS

Out Of Service
Red: The blade is out of service
OFF: The blade is working properly

OK

Power OK
Green: The blade is operating
properly
OFF: Otherwise

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LED

Description

ACT

Not used

H/S

Hot Swap
Blue: The blade is ready to be
extracted
OFF: The blade is not ready to be
extracted. Do not remove the board
during this state.

Table 8: Front Plate LED Description

4.4.3 Ethernet Uplink Connectors


The JAXSSW provides eight Ethernet uplink connectors (ETH1 to ETH8) on
the front plate. ETH1 to ETH8 are routed to the base channel switch located on
the JBXSSW, and provide access to the shelfs base channel interfaces.
ETH1 to ETH8 are available as RJ-45 connectors and constitute
10/100/1000BaseTX interfaces.
For Ethernet uplink connectors location refer to Figure 25.

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4.5 JBXGPU
4.5.1 Introduction
The JBXGPU board is installed in the MFS equipment designed to handle the
General Packet Radio Service (GPRS) in the BSS.
The MFS:
Receives Ater links from BSCs, carrying a mix of circuit (voice) and GPRS
packet channels
Transparently forwards circuit channels to the MSC through another Ater
interface
Processes GPRS packet channels and forwards them to the SGSN, directly
or through the MSC, on a Gb interface.
The Ater interface has an E1 structure (2,048 Mbit/s), with a 64 or 16 or 8
kbit/s sub-channeling.
For Gb interface, there are two posible configurations:
FR over E1, E1 structure bearing Nx64 kbit/s channels, each of which carry
GPRS packets on Frame Relay links
IP over Ethernet
The Ater and Gb interfaces can be on the same link between the MFS and
the transcoders.
The SGSN performs similar functions as the MSC in GSM, such as tracking
individual MS locations and providing security functions and access control.
The MFS equipment is housed in a new platform, based on standard Advanced
TCA shelves. The main shelf contains :
Two redundant shelf managers (JAXSMM) performing management
through redundant IPMI busses
Two redundant switches (JBXSSW) performing mainly Gigabit Ethernet
switching at the shelf level
Two redundant Operation and Maintenance Control Processing boards
(JBXOMCP) in charge of telecom control, and providing large capacity
storage
Up to 10 JBXGPU boards in one shelf and up to 22 JBXGPU boards in
case of two selves configuration.

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This is shown in the following figure.

External E1 links

JSXLIU Termination Shelf


JBXGPU P
JBXOMCP P

JBXGPU N
JBXGPU 1

JBXOMCP W

NE1oE
JBXSSW W
JBXSSW P

1 Gigabit Ethernet ATCA Base Interface

Figure 27: Single Shelf Environment

4.5.2 JBXGPU Architecture


The JBXGPU can be split into eight functional modules :
The OBC module, based on the Puma-Agx PrPMC and the JGXDBC EPLD,
provides processing power for GPRS packet handling
The HDLC Termination module ensures management of the Frame Relay
low layers for the Gb and GSL interfaces
The DSP module provides processing power for the management of the
Ater interface low layers
The TDM Termination module provides the physical termination of the
16 E1 interfaces of the board (Ater or Gb) interfaces and a spatial and
temporal switch
The IPMC module provides the IPMB interface for hardware management
services
The Ethernet switch module provides a switch between data and control
Ethernet frames

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The NE1OE module provides emission/reception of the E1 links over


Ethernet
The Power Supply module provides all of the required on-board power
supply.

4.5.2.1 OBC Module


The OBC module is composed of a micro controller and the JGXDBC EPLD.
In addition, it includes 1 Gbyte DDR SDRAM running at 166MHz, 512 Kbytes
Boot Flash, and 32 Mbytes User Flash.
Communication between the OBC and the JBXGPU "mother board" is via a
connector supporting a 32bit/33MHz PCI bus, a device bus, two serial links and
three Gigabit Ethernet links.
The JGXDBC EPLD controls:
The reset function for all the components
Access to some components through the device bus
Access to the Giga Ethernet switch through the SPI bus
PCI arbitration
JGXSRE FPGA downloading
Interrupt management
The ATCA H3
Two application LEDs.

4.5.2.2 HDLC Termination Module


This HDLC termination module provides the HDLC Termination used by the
low layers of the Frame Relay protocol. This protocol is used to carry the
GPRS packets on the Gb interfaces.
The main characteristics of this module are:
16 x 2 Mbit/s ports, across 64 kbit/s channels, connected to the TDM
Termination module
Termination of 128 Nx64kbit/s HDLC channels
The 32bit/33MHz PCI connection.

4.5.2.3 DSP Module


The DSP module is built around four DSPs, operating at 720 MHz.
Each DSP:
Provides 64 MBytes of SDRAM memory, operating at 133 MHz, accessible
from the OBC CPU
Provides a master interface to the PCI bus, for DMA transfers between
the DSPs and the OBC memory
Is connected to the TDM module through a 8,192Mbit/s TDM serial link
Is directly connected on the 32bit/33MHz PCI bus.

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4.5.2.4 TDM Termination Module


The TDM Termination module, associated with the NE1OE module, performs
the 16 x 2,048 Mbit/s E1 physical layer termination and related functions.
It is composed of:
Two octal-framers, connected to the JGXESD FPGA
An 192 Mbit/s port, non-blocking TDM switch, which dynamically switches
the Ater and Gb channels to the proper modules
A JGXSRE FPGA which performs the synchronization function of the E1
lines and 2,048 to 8,192 Mbit/s link multiplexing
A JGXESD FPGA which performs E1 multiplexing and bit stuffing for
asynchronous E1 transport
A LIU component managing eight E1 links, installed for test purpose
(without the NE1OE module). The E1 termination resistance is 120 ohm or
75 ohm for the eight E1.
The JGXESD and LIU components have a micro-controller interface for
configuration and status retrieval. This interface is under the control of the
OBC module.
The JGXSRE and JGXESD FPGAs are downloaded by the OBC and NE1OE
modules respectively.

4.5.2.5 IPMC Module


All Advanced TCA boards support an intelligent hardware management system,
based on the "Intelligent Platform Management Interface Specification". The
hardware management system provides the ability to manage power, cooling,
and interconnect needs to intelligent devices, in order to monitor events and to
log events to a central repository.
The IPMC module uses the Pigeon Point System reference design. It is based
on two processors (one master, one slave). On the JBXGPU board, the IPMC
module manages:
All the communication with the shelf manager
ATCA blue H4, H1 and H2
The RI EEPROM.
The IPMC module has a serial interface for configuration and status retrieval.
This interface is under the control of the OBC module.

4.5.2.6 Ethernet Switch Module


The Ethernet switch module provides a switch function between the data
frames and the control frames.
The data frames are managed by the NE1OE module, whereas the control
frames are managed by the OBC module.
This module is based on an eight port Gigabit switch. It has an SPI interface
for configuration and status retrieval. This interface is under the control of the
OBC module.

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4.5.2.7 NE1OE Module


The nE1 over Ethernet module provides the transport of the E1 links payload
over a Giga Ethernet link between JSXLIU/JSXLIUB shelf (256 E1) and
JBXGPU board (16 E1). This transport is made through a Giga Ethernet
switch (JBXSSW board).
The module is composed of:
JGXEOE FPGA, which performs the E1 links transport over Ethernet
JGXCLU EPLD performing the downloading of the JGXESD FPGA (TDM
termination module) and the JGXEOE FPGA. An attached flash contains
the code for these two FPGAs.
The configuration and status retrieval of this module is under the control of
the JBXOMCP.

4.5.2.8 Power Supply Module


The power supply module provides the secondary power supply for the overall
board. On-board DC/DC converters and regulators provide the necessary
power supply to the board from a received -48V DC redundant primary
power supply input.
The Power Supply module can be controlled (cut off) by the IPMC module.

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4.5.3 Front Plate


On the front panel:
ATCA LEDs H1, H 2, H3 and H4:
H1: Controlled by the IPMC
The H1 is a bi-color (RED/AMBER) to meet different geographic
requirements. It indicates a failure or other an out of service state. This
LED is controlled by the JGXTP EPLD and the status is as described
below:
ON : Board is out of service (OOS)
OFF: Board is operational
H2: The LED is GREEN and is controlled by the IPMC (not used)
H3: The LED is AMBER and is controlled by the OBC (not used)
H4: The LED is BLUE and is controlled by the IPMC
The Blue LED shines during the board insertion into Node Slot of
AdvancedTCA system. It serves as an indication of whether or not the
front board can be extracted. This LED is controlled by the IPM
Two "three-colors-LEDs" for MFS applications (L1 and L2). Their
significance and operational control are specific to the MFS application
One RJ45 connector (RS232) for three RS232 debug links (OBC,IPMC
master, NE1OE)
One RJ45 connector (ETH) for a 10/100Mbit/s Ethernet debug link.
Upper handle
Lower handle.

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This is shown in the following figure.

JBXGPU

Handle

H1
H2
H3
L1
L2

H4

Handle

R
S
2
3
2
E
T
H

Figure 28: Front Plate

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4.5.4 LEDs
LED

Color

Description

H1

Red/Amber

ON: The JBXGPU is out of service


OFF: The JBXGPU is operational

H2

Green

Not used

H3

Amber

Not used

H4

Blue

Hot swap
During blade installation:
Permanently blue: On-board IPMC
powers up
Blinking blue: Blade communicates with
the Shelf Management controller
OFF: Blade is active
During blade removal:
Blinking blue: Blade notifies the Shelf
Management controller of its desire to
deactivate.
Permanently blue: Blade is ready to be
extracted.

L1

JBXGPU board is active:


OFF: All PCM-TTP ar not installed
No change of the current color: At least
one PCM-TTP is not installed
Green: All PCM-TTP are available
Red: All equipped PCM-TTP are in fault
Yellow: At least one PCM-TTP is in fault,
but not all
JBXGPU board is standby:
LED is OFF.

L2

JBXGPU board is active:


LED is green.
JBXGPU board is standby:
LED is green blinking.

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4.6 JAXSMM
4.6.1 Introduction
The JAXSMM is a 2U shelf manager board used in AdvancedTCA systems. It
plugs into a dedicated shelf management slot of an advancedTCA system. The
board provides management for up to 16 advancedTCA front blades as well as
for blowers, power entry modules, alarm modules, and shelf FRU info modules
that are used in an advancedTCA system. In a redundant configuration the
JAXSMM are used as redundant shelf manager.
The JAXSMM is a main component of the shelf management system. The shelf
management system is used in AdvancedTCA systems and its purpose is to
ensure proper operation of AdvancedTCA blades and other system components
like blowers, power entry modules (PEMs) and rear transition modules (RTMs).
The shelf manager board possesses a backplane connector and is plugged
into a 2U slot.
The alignment protrusion offers a guide rail to the slot and a coding mechanism
to ensure the installation of the board in the matching slot. It also prevents bent
pins, which can occur during installation.
The following figure shows the JAXSMM hardware architecture.
Front Plate

Backplane

Ethernet

Ethernet

Ethernet
Serial
Interface

Payload

Serial
Interface
Block Transfer
Interface
Hardware
Address
IPMB0 A

ATCA LEDs
Shelf Management
Controller

IPMB0 B

Handle
Switch

48V
48V

Figure 29: JAXSMM Hardware Architecture


The shelf manager JAXSMM hardware consists of:
Payload hardware with:
Ethernet interfaces to the backplane and to the front plate
Redundant connection between two shelf managers via the backplane
Block transfer interface to the JAXSMM

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Shelf management controller with:


IPMB0-A and IPMB0-B interface to the backplane
Handle switch and status LED interface to the front plate
Option signals to the backplane
Support logic for testing and debugging as well as local and remote
programming of all programmable devices on the board
Power supply with 3.3V feed to the backplane for external devices

4.6.2 Payload Hardware


The payload hardware on the shelf manager board is always powered when
power supply is present. During power on, the JAXSMM keeps the payload in a
reset state. The following interfaces are available:
Three Ethernet interfaces
Two redundancy interfaces (serial)
Block transfer interface.

4.6.2.1 Ethernet Interfaces


The shelf manager board has three Ethernet ports which are available
concurrently.
One 10/100 BaseT out-of-band interface is accessible via a RJ45 connector at
the front plate. Link and activity status LEDs are integrated into the connector.
Two 10 BaseT interfaces are connected to the backplane connector at the pins
Eth1-Hub Tx/Rx and Eth2-Hub Tx/Rx.
These ports connect to the base interface of up to two AdvancedTCA switch
boards (e.g. SSW) in the hub slots of an AdvancedTCA shelf.
The green LEDs (Ethernet LEDs) on the front plate indicate the link status of
the Ethernet ports.

4.6.2.2 Redundancy Interfaces


JAXSMM uses a private, redundant, high-speed, full duplex serial connection
for heart beating and data replication between the two shelf manager boards.
The redundancy interface is routed to the backplane via differential line LVDS
transceivers. The physical interface of both channels are compliant with the
AdvancedTCA specifications for the update interface.
Each of the serial inputs of the redundancy interface triggers an interrupt to the
PowerQUICC when the other shelf manager board:
Initiates a break-in condition on the serial line
Experiences a power failure
Switches in the reset state
Is extracted.

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4.6.2.3 Block Transfer Interface


The payload CPU is connected to the JAXSMM via a parallel interface with
interrupt support implemented in a FPGA.
The block transfer (BT) interface is compliant with IPMI specification v1.5.

4.6.3 Shelf Management Controller


The JAXSMM part is derived from IPMC building block and consists of two
coupled microcontrollers:
IPMC master controller (IMC)
IPMC Slave Controller (ISC).

4.6.3.1 IPMB0 Interface


IPMB0-A is connected to the I2C controller of the IMC.
IPMB0-B is connected to the I2C controller of the ISC of the JAXSMM. Both
have their own I2C controller and handle message transmission and reception
independently, including bus error handling and bus arbitration.
Received messages from both the IMC and the ISC channels are collected by
the IMC. The IMC dispatches messages which have to be sent either to its
own I2C interface or to the ISC for transmission.

4.6.3.2 IPMC Standard Functions


The following functions of the IPMCs are available on the IPMC of the JAXSMM:
Hardware address input from the backplane connector (HA 0 ...7)
Handle switch.
The handle switch is generally activated by a lever which moves when one
of the front plate fastening screws is loosened or fastened.

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4.6.4 Power Supply


The JAXSMM is powered by:
A dual redundant -48V to -60V from the backplane connector
48V-A, 48V-ARTN
48V-B, 48V-BRTN
Each of the 4 power connections is separately fused.
The fuse rating is 1 Amp. An EME filter at the power input ensures conducted
emission levels below EN 55022 class B.

4.6.4.1 Onboard and External Supply


The JAXSMM makes no provision for switching OFF the power input. The
board is powered when the power input is in the operating range of -36 to -72V.
An on-board DC/DC converter supplies all on-board circuitry, and provides:
A 3.3V power supply to external circuits with a consumption of no more
than 4W
V3.4 management on the backplane pins
GND on the backplane pins.
Output voltage is slightly above 3.3V to compensate for losses caused by
ORing circuits, which may be present on the external load.
The board satisfies the standby power limit of 10W for AdvancedTCA FRUs,
even when supplying 4W to external loads. Typical power consumption of
the JAXSMM board is 2W.

4.6.4.2 Power Supply Holdup


The JAXSMM complies with the requirements for board level voltage transients.
It meets the requirements for uninterrupted operation during a power failure of
5ms, while supplying 4W to external circuits.

4.6.5 Frame Ground and ESD


The frame ground connection is provided by the FrameGND backplane
connector.
The front plate mounting holes of the board are connected to frame ground.
An ESD strip, for rear transition modules (RTMs), is provided on one edge of
the PCB.

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4.6.6 Front Plate


The following figure shows the position of connector and LEDs on the front
plate of the board.

JAXSMM
OOS

OK

ACT

Eth 3 Activity
Eth 2
Eth 3 Linkup
Eth 1

H/S

Figure 30: JAXSMM Front Plate

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4.6.7 LEDs
The following LEDs are used on the front plate of the board.
LED

Color

Description

OOS

Red

Failure
Red: The shelf manager board is out of service
OFF: The shelf manager board is working properly

OK

Green

Power
Green: The shelf manager board is operating
properly
Green blinking: The board bots up
OFF: Otherwise

ACT

Amber

Active
Amber: The shelf manager board is active
OFF: The shelf manager board is in standby mode

H/S

Blue

Blue: The shelf manager board is ready to be


extracted
OFF: The shelf manager board is not ready to be
extracted. Do not remove the board during this state.

Eth 2: Ethernet Uplink

Green

Green: Link to backplane Ethernet 2 is available


OFF: Otherwise

Eth 1

Green

Green: Link to backplane Ethernet 1 is available


OFF: Otherwise

Ethernet 3 Activity

Green

Green: Link to Ethernet is available


OFF: Otherwise

Ethernet 3 Linkup

Amber

Amber: Activity
OFF: No activity

Table 9: JAXSMM LEDs

4.6.8 Ethernet Connector


One 10/100 Mbps Ethernet port is provided via the Ethernet connector on the
front plate. It allows external system managers to access the shelf manager.

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4.7 JAXPC
4.7.1 Introduction
The JAXPC is a shelf configuration and alarm board used with AdvancedTCA
systems. The JAXPC alarm board is a 4 Horizontal Pitch (HP) wide x 87 mm
high card and is designed for rear access applications. It is located below the
Rear Transition Module (RTM) area. The communication with the JAXPC alarm
board takes place via Intelligent Platform Management Bus (IPMB).
The JAXPC is a general purpose device providing the functions not
implemented by the other Field Replaceable Units (FRUs).
The JAXPC alarm board:
Contains the Shelf FRU Information Store
Contains rotary switches for setting SGAs
Provides HA, SGA and configuration bit inputs
Visualizes the states and alarms via LEDs on the front panel
Provides interface to IPMB0-A and IPMB0-B.
The following figure shows the JAXPC board.

Figure 31: JAXPC Hardware

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4.7.2 Front Panel


The following figure shows the position of connectors and LEDs on the front
panel of the board.

Telco Alarms & Relays

JAXPC

Alarm I/O Connector

Alarm Reset Push Button


Alarm/
Reset

Hot Swap LED

Closed
Open

Handle

H/S

Failure LED
Power LED
OOS
OK

Figure 32: JAXPC Front Panel

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4.7.3 LEDs
The following LEDs are used on the front plate of the board.
LED

Color

Description

OOS

Red

Failure
ON: The JAXPC alarm board is out of service
Red blinking: the shelf FRU information is invalid
OFF: The JAXPC alarm board is working properly

OK

Green

Power
ON: The IPMC has initialized properly
OFF: Otherwise

H/S

Blue

ON steady: The JAXPC alarm board is ready to be


extracted
Blue blinking: The IPMC is attempting to
communicate with the JAXSMM
OFF: The JAXPC alarm board is operating and not
ready to be extracted. Do not remove the board
during this state.

Table 10: JAXPC LEDs

4.7.4 Alarm I/O Connector


The DB15 connector on the front panel provides access to the dry contact
inputs and outputs.

4.7.5 Handle Toggle Switch


There is one handle toggle switch located on the front panel. It mimics the
function of the ejector handle on a front panel, as described in the following
table.
Switch Position

Function

Upper position

Handle is closed

Lower position

Handle is open

Table 11: Handle Toggle Switch

4.7.6 Alarm Reset Push Button


The JAXPC provides an alarm reset push button on the front panel. It is used
to reset a cleared alarm condition.

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4.7.7 Shelf Addressing


On an ATCA system there are 8 bits allocated for a Shelf Geographic Address
(SGA). The SGA on the JAXPC alarm board is set via two SGA rotary switches.
The two JAXPC in the same shelf must always be set to the same SGA.
S1 (bottom switch in the figure below) sets the lower nibble and S2 (top switch
in the figure below) sets the upper nibble. Use a screwdriver to set the switches
by turning them. A little arrow on the switch shows you the value to which the
switch is set.

S2

S1

Figure 33: Rotary Switches on JAXPC


Optionally, the Shelf Geographic Address can be set by the backplane.

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4.8 JBXPS
Four field maintainable intelligent Power Entry Modules (JBXPS) are installed
beneath the rear slots of the backplane. The JBXPSs A1 and B1 supply the odd
numbered slots, and the JBXPSs A2 and B2 supply the even numbered slots.
Each feed has two power attachment points, each of which is capable of
supplying 50 A.
At the minimum operating voltage (-39.5V), this power entry supports 3950W,
which is beyond the limit of 200W per slot.
The JBXPSs provide the following features and functions:
Redundancy so that a single JBXPS failure will still provide full power
to the system
Hot-swap
Providing monitoring information to the shelf manager
Power feed voltage and current measurement
Temperature sensing
Power filtering
IPMC for input power monitoring within the power distribution path. IPMC
is located on both IPMB-A and IPMB-B buses.
Each JBXPS connects to the distribution board via a Positronic PLC series 3x6
connector and a 3x10 connector. The DIN connector has multiple levels of
mating to allow hot insertion and removal. The panel I/O is comprised of a
power feed input and a hot swap toggle switch, and hot swap and status LEDs.
All JBXPSs are a single width module with dual M6 insulated studs and power
filtering. The four-JBXPS system includes a full IPM interface for 50A.
A toggle switch is provided to allow supervision interruption for maintenance
reasons.
The following figure shows the functional blocks of the JBXPS.

48V DC

48V DC

Filter

LEDs
Curr/Voltg
LEDs, Switch
Switch

TEMP

GA

Distribution Board

Front Plate

Breaker

Current
Sensing

IPMC
IPMB_0

Figure 34: JBXPS Functional Blocks

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4.8.1 JBXPS Specifications


4.8.1.1 Power Input
The external power is connected to the JBXPS via dual, isolated power studs.
The studs are sized to support a maximum of 90 A when derated for a 30
C temperature rise.
The JBXPS is designed to operate from 36V to 75V and can withstand 100V
transients for at least 100ms, 200V transients for at least 5s, and 1500V
fast transients. A breaker (depending on the model) is used to provide shelf
protection. The breaker is equipped with finger guards and a push-to-reset
feature to avoid accidental tripping.

4.8.1.2 Power Filtering


The JBXPS is equipped with input power filtering. The filter is designed to
support 50A in the four-JBXPS system.
The filter provides transient voltage immunity, in accordance with the IEC
1000-4-4 Part 4 for electronic fast transient/burst immunity specifications, and
test level 1 in accordance with generic EMC requirements.
For details about power distribution system refer to Power Distribution System
(Section 4.1.6).

4.8.2 Front Plate

closed
open
H/S

OOS

(POWER)

handle

The following figure shows the front plate of the JBXPS.

Rev. Power
OK

ON
I

+(RETURN)

O
OFF

Operating Voltage 44V to 72 VDC


Maximum Current 50A
Torque Nut 7.12 Nm (8 lbf.in) Max

Figure 35: JBXPS Front Plate

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4.8.3 LEDs
The following LEDs are used on the front plate of the board.
LED

Color

Description

OOS

Red

Out of Service
ON: The JBXPS is out of service
OFF: The JBXPS is working properly

OK

Green

Power
ON: The JBXPS is powered properly
OFF: The JBXPS is not powered.

Rev. Power

Red

Polarity
ON: Power-feed cables of the JAXPS is
reversed connected.
OFF: Power-feed cables of the JAXPS are
correct connected.

H/S

Blue

Hot Swap
On JBXPS insertion:
ON: On boards IPMC poweres up
Blue blinking: The JBXPS communicates
with the JAXSMM
OFF: The JBXPS is active
On JBXPS extraction:
Blue blinking: The JBXPS notifies the
JAXSMM its request to deactivate
OFF: The JBXPS can be removed.

Table 12: JBXPS LEDs

4.8.4 Handle Switch


The handle switch is located on the front plate in the left upper corner. It has
two positions as described in the following table.
Position

Description

Open

Out of JAXSMM control

Closed

Under JAXSMM control

Table 13: Handle Switch Positions

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4.9 JBXFAN
The JSXATCA shelf is equipped with four fan modules, JBXFAN.

4.9.1 Front Plate


The following figure shows the JBXFAN font plate.

CLOSED / OPEN

H/S OOS

Figure 36: JBXFAN Front Plate

4.9.2 LEDs
The following LEDs are used on the front plate of the JBXFAN unit.
LED

Color

Description

OOS

Red

Out of Service
ON: The JBXFAN is out of service
OFF: The JBXFAN is working properly

H/S

Blue

Hot Swap
On JBXFAN insertion:
ON: On board IPMC powers up
Blue blinking: The JBXFAN communicates with the
JAXSMM
OFF: The JBXFAN is active
On JBXFAN extraction:
ON: The JBXFAN is ready to be removed.
Blue blinking: The JBXFAN notifies the JAXSMM its
request to deactivate
OFF: The JBXFAN is active

Table 14: JBXFAN LEDs

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4.9.3 Handle Switch


The handle switch is located on the front plate in the left upper corner. It has
two positions as described in the following table.
Position

Description

Open

Out of JAXSMM control

Closed

Under JAXSMM control

Table 15: Handle Switch Positions

4.10 ATCA Fillers


All unused slots are covered with filler blades. These blades ensure a
consistent airflow per slot whether or not the neighboring slot contains an
AdvancedTCA blade.
The system comes delivered with unused slots at the systems rear covered
with RTM filler blades. These RTM filler blades are necessary to provide
proper airflow.
Front and rear filler blades must be removed before RTM or AdvancedTCA
blade installation.

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4.10.1 JBXFILL
Front unused slots are covered with font fillers, JBXFILL. The following figure
shows the front filler.

Figure 37: JBXFILL View

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4.10.2 JAXFILL
Rear unused slots are covered with rear fillers, JAXFILL. The following figure
shows the rear filler.

Figure 38: JAXFILL View

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5 JSXLIU/JSXLIUB Shelf
JSXLIU/JSXLIUB shelf provides basic information about the:
JSXLIU/JSXLIUB shelf
JBXLIU/JBLIU75 board
JBXMUX
JBXPS
Dummy panel.

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5.1 JSXLIU/JSXLIUB Shelf Description


5.1.1 Introduction
The JSXLIU/JSXLIUB shelf ensures the concentration of 256 E1 on a 1 Giga
Ethernet link.
The JSXLIU/JSXLIUB shelf hosts:
Two JBXPS boards supporting the connection from - 40 up to 72VDC
secondary voltage, the EMI filtering, the down conversion in a 12V SELV
voltage, and collects the alarms through a I2C link
Two JBXMUX boards which collect the E1 links from the 16 JBXLIU/JBLIU75
boards on 16 serial links at 36.864 Mbit/s and build packets sent towards up
to 32 directions (125ms each) on a Giga Ethernet link
Up to 16 JBXLIU/JBLIU75 boards converting 16 plesiochronous E1 links
into a synchronous link at 36.864 Mbits (4B/5B coded).

5.1.2 Shelf Position in the System


The JSXLIU/JSXLIUB shelf is located between the DDF and the ATCA shelf
hosting the MFS functions.
It is connected to the DDF through up to 16 cables, each in 32 pairs. The PCM
interfaces are balanced 120 or unbalanced 75 , in accordance with G703
standards. The unbalanced 75 is not supported on the LIU itself. In this case,
the adaption is done at DDF side.
It is powered from two sources (48/60VDC).
The JSXLIU/JSXLIUB shelf has its own EMI enclosure and fire protection. It
can be hosted in the same cabinet as the ATCA shelf or can be stand-alone.
This is shown in the following figures.

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External E1 Links

O&M + TELECOM
JSXLIU Shelf

JNXGPU P
JBXOMCP P

JBXGPU N

JBXOMCP W

JBXGPU 1

NE1oE
JBXSSW W

JBXSSW P

1 Gigabit Ethernet ATCA Base Interface

Figure 39: JSXLIU/JSXLIUB Shelf in the MFS


Power
Source A

Power
Source B

JBXPEM A JBXPEM B
32 pairs cable
DDF

JBXLIU
X 16

JBXMUX A

JSXATCA SHELF

NE1OE

JBXSSW A

16 cables

JBXMUX B

NE1OE

JBXSSW B

Figure 40: JSXLIU/JSXLIUB Shelf Environment

5.1.3 Main Features


The LIU is composed of:
A mechanical housing designed to hold the JBXMUX, the LIU and the
JBXPS pluggable items:
Width compatible with a standard 19 cabinet
Overall height : 3U
Depth : to accommodate the pluggable boards depth of 160 mm.
Two JBXPS slots

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Two JBXMUX slots


16 LIU slots
One unused position referred to as the shelf address slot.
The power input is -48/60VDC, redundant with the A + B power feed. The
consumption is less than 100W (fully loaded).
For thermal requirements, natural convection is sufficient. This assumes that
there is 1U free space up one side and down the other side of the shelf.
A single backplane provides all the internal connections between the hosted
boards. All the external accesses to the JSXLIU/JSXLIUB shelf are made
through the front plate of the boards.
This is shown in the following figure.
JBXPEM

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXMUX JBXDUM JBXMUX JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXLIU

JBXPEM

48 / 60
VDC

48 / 60
VDC

4A

4A

Figure 41: JSXLIU/JSXLIUB Shelf Front View

5.1.4 Mechanical Housing Description


21 slots are available (20 are required) and the spacing is 20.32 mm. The slot
numbering marking is added on a 1U filler on top of the shelf , including the
slot numbers from 1 to 21.
Board guides are plastic and are made with an ESD clip. The boards
mechanical size is a 3U small form factor.
This is shown in the following figure.

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JBXLIU
Power/Fail

JBXMUX

JBXPEM

Power/Fail

JBXDUM

Power/Fail

Active

TEST

E
1
/
T
1

48/60VDC
4A

GbE

Figure 42: LIU Hosted Strips and Marking


The following table lists the backplane sizes.
JSXLIU/JSXLIUB Shelf Backplane

Weight and Dimensions

Length

426.72 mm

High

128.7 mm

Thickness

3.2 mm

Weight

Less than 10 Kg

Table 16: JSXLIU/JSXLIUB Shelf Backplane Weight and Dimensions


JBXMUX slots position are fitted with a P1 connector and a P2 connector .
Other slots (LIU & JBXPEM) are fitted with only one P1 connector. On the slot
address shelf (slot #11), the P2 connector is replaced by a set of eight jumpers
used to configure the shelf address. Sub-equipment of JBXLIU/JBLIU75 board
is possible and requires no specific recommendations. The JBXDUM filler for
EMI compliance is used to close the unused slot. In terms of hot insertion, the
design of the boards takes account the inrush current.

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10

11

12

13

14

15

16

17

18

19

20

JBXPEM B

JBXMUX A

JBXLIU 16

JBXLIU 8

JBXLIU 15

JBXLIU 7

JBXLIU 14

JBXLIU 6

JBXLIU 13

JBXLIU 5

JBXLIU 12

JBXLIU 4

JBXLIU 11

JBXLIU 3

JBXLIU 10

JBXLIU 2

JBXLIU 9

JBXLIU 1

JBXMUX B

JBXPEM A

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Figure 43: JSXLIU/JSXLIUB Shelf Back-Plane Front View

5.1.5 JSXLIU/JSXLIUB Shelf Internal Connection


5.1.5.1 - 48/60 Volts Power Supply
The power supply is in the range -38.4/-72V. It is composed of two independent
lines (VBATA and VBATB), and a common return VBATR. The battery return
is normally not connected to the mechanic ground but to a jumper on each
JBXPEM which can provide the link if requested. The logical ground GND and
the mechanic ground MGND are connected together on the backplane by
screws in a basic configuration. For specific markets, it is possible to separate
them by removing the dedicated screws.

5.1.5.2 VBAT Power Supply Distribution


VBAT power supply enters the front panel of each JBXPEM on the left and
right sides of the shelf . It also is distributed to the other JBXPEM boards. The
VBATO of JBXPEMA is connected to the VBATI of JBXPEMB (and reciprocally).

5.1.5.3 12 Volts Power Supply Distribution


12 V power supply is distributed by each JBXPEM to all the other boards
via a complete plan.
P12VA is the +12 voltage generated by the left JBXPEM. It is connected to
P12Vi on the right JBXPEM.
P12VB is the +12 voltage generated by the right JBXPEM. It is connected to
P12Vi on the left JBXPEM.

5.1.5.4 Serial Data Interface Between JBXMUX and JBXLIU/JBLIU75 Boards


The serial link carrying data and control between JBXLIU/JBLIU75 boards and
JBXMUX board is encoded 4B/5B. It needs only one pair for each direction.
Two additional pairs are provided for any future use.
The upward interface is composed of UDATPxx and UDATNxx pairs carrying
uplinks A and B from the LIU to the corresponding input or JBXMUX board
A and B.
The downward interface is composed of DDATPxx and DDATNxx pairs carrying
the downlink from JBXMUX A and B to the corresponding LIU input A and B.

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5.1.5.5 I2C Link


This link allows the JBXMUX to read the RI EEPROM, the alarm register and
the temperature on the adjacent JBXPEM board. It is composed of the SCL
and SDL signals. Arbitration of I2C master is performed via the active/standby
signal.
The LIU RI data is read by the JBXMUX board through the serial 4B/5B
interface.

5.1.5.6 Active/Standby Control JBXMUX


This link allows selection of the active JBXMUX, depending on the JBXMUX A
and B help and software requests.

5.1.5.7 Board Presence and Reset Links


This link allows each JBXMUX (A or B) to detect whether a LIU is plugged
into a slot, and to restart it.

5.1.5.8 Slot Address


Each slot in the JSXLIU/JSXLIUB shelf backplane is individually identified by a
specific polarization of the SLA signals. X indicates that the jumper is present
and lowers the corresponding SLA pin of JBX* board. It is left open, so that the
selected board will detect a logical level 1 via the adequate pull up resistor.

5.1.5.9 Shelf Address


Each JSXLIU/JSXLIUB shelf belonging to a given system can be individually
identified by a specific polarization of SHA signals on the JSXLIU/JSXLIUB
shelf backplane. X indicates the jumper is present and lowers the
corresponding SHA (0 to 3) pin of the two JBXMUX boards.

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5.2 JBXLIU/JBLIU75 Board


There are two version of LIU boards, identical from functional point of view but
different by the type of cables that can be conncted on it. JBXLIU supports
the 120 Ohm cables connection and JBLIU75 supports the 75 Ohm cables
connection.

5.2.1 Introduction
The JBXLIU/JBLIU75 board ensures the interfacing of 16 plesiochronous E1
links in the JSXLIU/JSXLIUB shelf. The JSXLIU/JSXLIUB shelf hosts 16
JBXLIU/JBLIU75 boards.
The JBXLIU/JBLIU75 board functions are:
In the ingress direction:
2048 kHz clock recovery
HDB3 decoding
LOS detection
Stuffing
Multiplexing 16 lines and board control into a serial signal at 36.864 Mbit/s
Encoding the serial signal 4B/5B at 46.08 Mbauds.
In the egress direction:
46.08 MHz clock recovery
5B/4B decoding
De-multiplexing
De-stuffing
HDB3 encoding.
The E1 interface is compliant with the G.703 recommendations in 120
or 75 termination.

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5.2.1.1 System Description


The JBXLIU/JBLIU75 board is part of the JSXLIU/JSXLIUB shelf which
belongs to the ATCA based platform. It is shown in the following figure in an
MFS environment.

External E1/T1 Links

JBXLIU

JSXLIU Shelf

GPU
JBXGPU P
GPU
JBXGPU N

JBXOMCP P
JBXOMCP W

JBXGPU 1

NE1oE
JBXSSW W
JBXSSW P

1 Gigabit Ethernet ATCA Base Interface

Figure 44: Platform Architecture

5.2.1.2 LIU Environment


The JBXLIU/JBLIU75 board is hosted in the JSXLIU/JSXLIUB shelf. It is
powered from two redundant +12 V from two JBXPEM boards.
The interface with the two JBXMUX boards through the backplane is composed
of:
One point to point bi-directional encoded serial link 4B/5B carrying both
payload and control data. This link is supported by two pairs with LVDS
signals.
One point to point bi-directional link for board presence indication and
reset functions
Two point to multipoint signals to indicate which is the active JBXMUX (SELA
and SELB). SELA and SELB signals always display a complementary state,
and only SELA is used.

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The JBXLIU/JBLIU75 board provides 16 balanced E1 interfaces on its front


panel via one 68 pin sub-D connector.
This is shown in the following figure.
48V B

48V A

JSXLIU Shelf
ATCA Shelf

JBXPEM

+12 V

+12 V

4B/5B up

4B/5B down

16 E1/T1

JBXLIU

JBXMUX

GE Link

GE S witch

PRSET

MUX Select

Figure 45: JBXLIU/JBLIU75 Board Environment

5.2.2 Hardware Architecture


The JBXLIU/JBLIU75 board provides the following functions:
Power supply
Line Interface
LIU reference clock generation
Mux selection
E1/T1 configuration
Stuffing
Multiplexing
Serialization
4B/5B encoding
Loop-back facilities
RI.

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This is shown in the following figure.

RI

RI
EEPROM
EEPROM

Electrical

Electrical
protection
Protection &&
Transformer
Transformer

Electrical
Electrical
Protection &
Transformer

I2C
SELA/B

SELASELB

OCTAL
OCTAL
LIU E1/T1
LIU E1/T1

Control Bus

E1 MUX
MUX
E1
+
+
Bit stuffing
Bit stuffing

Serial link 1

OCTAL
OCTAL
LIU E1/T1
LIU E1/T1

Data + Clock
Data + Clock

E1 MUX
MUX
E1
+
+
Bit stuffing
Bit stuffing

Serial link 2

Control Bus

JGXESD

E1/T1 selection
E1/T1 selection

2048
2048
kHz

1544
1544
kHz
kHz

Board presence
and reset

EPLD
EPLD
EEPROM
EEPROM

DC/DC
DC/DC
converters
Converters

12V (A)
12V (B)

JSXLIU Board
JSXLIU Board

Figure 46: JBXLIU/JBLIU75 Board Architecture

5.2.2.1 Power Supply


The board is powered from two separated +12 V inputs. The + 3.3 voltage
is obtained via a non isolated converter (the isolation is performed on the
JBXPEM board). The 1.5 voltage required for the JGXESD FPGA is provided
via a linear regulator.

5.2.2.2 Line Interface


The JBXLIU/JBLIU75 provides 16 balanced 120
lines, compliant with G.703.

or unbalanced 75

E1

The line interface is provided by two octal E1 short hall JBXLIU/JBLIU75s in


the PBGA package. These LIUs are associated with four octal transformers
ensuring the galvanic isolation.
Tripolar protection is provided on the PCB to prevent difficulties with regard to
meeting K41 requirements. It is assumed that if this protection is not required, it
will not be equipped.

5.2.2.3 LIU Reference Clock


For clock recovery and jitter attenuation, the E1/T1 LIU needs a 2048 kHz
reference clock when used in E1 mode, and a 1544 kHz reference clock
when used in T1. In order to permit the dual mode, two crystal free running
oscillators are implemented on the board. On the current board, only the 2048
kHz oscillator is equipped.

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5.2.2.4 E1/T1 Configuration


The LIU functions are as follows:
In the ingress direction:
Clock recovery
HDB3 decoding
LOS detection.
In the egress direction:
HDB3 encoding
Jitter attenuation.
The configuration of the LIU is achieved via the non-multiplexed bus type
emulated by the JGXESD. Depending on the configured mode, the LIU
reference clock is switched to 2048 kHz or 1544 kHz. In the current design,
the JGXESD only provides E1 capability. This configuration is downloaded
into the LIU upon hardware reset.
The LIUs are configured as follows:
AIS disabled on LOS
LOS criteria is G.775
HDB3 coding enabled
Jitter attenuator depth 32 bits
Jitter transfer bandwidth 1.7 Hz
Jitter attenuator in transmit path.
In the egress direction, the JGXESD extracts the orders of local or a remote
loop-back on each E1 link from the serial link. It transfers these orders into the
LIU loop-back configuration register. In the ingress, it reads the loop-back and
LOS status registers of the LIU and inserts the information in the serial link.

5.2.2.5 JGXESD Reference Clock


The JGXESD component requires a 36864 kHz transport clock for the 4B/5B
recovery clock function. It is provided via a VCXO used in free run mode.

5.2.2.6 JBXMUX Selection


Depending on the status of the SELA input, the E1 or T1 output signal comes
from the serial link A or B. This function is performed inside the JGXESD
component. The link A is active when SELA is low.
In the ingress direction, the 16 E1 are converted and sent on both serial links.

5.2.2.7 Stuffing
33 bytes of payload are allowed to each E1 or T1 link every 125 ms. Depending
on the phase relationship between each line clock and transport clock, these
33 bytes carry 255, 256, or 257 bits. This function is performed inside the
JGXESD component.

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5.2.2.8 Multiplexing and Serialization


In the ingress direction, the JGXESD multiplexes the data coming from the
16 lines, RI data, and LIU status information on a serial link at 36864 kbit/s.
In the egress direction, the JGXESD extracts the data from the 16 lines and
controls the LIU of the serial link

5.2.2.9 4B/5B Encoding


In the ingress direction, the serial link is encoded 4B/5B. In the egress direction,
the clock is recovered from the received signal, the frame alignment is checked
and the data is decoded 5B/4B. This function is performed by the JGXESD
component.

5.2.2.10 Remote Inventory


An EEPROM with I2C access is dedicated to RI data. It can be read by the
JGXESD component. A specific connector allows the factory to write the
data when the board is not powered.

5.2.2.11 Board Presence


A pull down indicates the presence of the JBXLIU/JBLIU75 board to the
JBXMUX boards. The active JBXMUX board can reset the JBXMUX board
by driving this access high.

5.2.2.12 Hot Insertion


The JBXLIU/JBLIU75 board can be plugged into the JSXLIU/JSXLIUB shelf
without perturbing the other boards of the shelf.

5.2.2.13 ESD Discharge Circuit


An ESD discharge circuit allows a progressive discharge of the board before
complete insertion.

5.2.2.14 Start Policy


The board starts when powered ON.

5.2.2.15 Reset Policy


The board is reset at power ON, or by the active JBXMUX by PRSET access.
The LIU can be reset through the serial egress link.

5.2.2.16 Boundary Scan Chain (JTAG)


The boundary scan chain includes the JGXESD and the two octal LIU. The
chain is accessible on a dedicated connector for factory use. For future
improvements, a Firecron scan path component is implemented (not
equipped). This component can provide access to the boundary scan chain
from a backplane bus reserved for this application.

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5.2.3 Interfaces
5.2.3.1 Internal Interfaces
The following internal interfaces are available:
Data + clock interface between the LIU and JGXESD
Ingress data + clock interface between the LIU and JGXESD
Egress data + clock interface between JGXESD and the LIU.
Control interface between the LIU and JGXESD
I2C interface
Board type interface.

5.2.3.2 External Interfaces


The following external interfaces are available:
Line interface (X6)
Backplane Interface (X1)
Visual interface (H0201)
Remote inventory interface (X2)
JTAG Interface (X4)
Programming Interface (X3).

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5.2.4 Front Panel


The following figure shows the LIU board front panel for the 120 ohm and 75
ohm solutions.

JBXLIU

JBLIU75

Power/Fail

E
1
/
T
1

E
1
/
7
5

Power/Fail

Figure 47: LIU Front Panel

5.2.5 Safety
The JBXLIU/JBLIU75 board belongs to the JSXLIU/JSXLIUB shelf and meets
the required safety specifications.
The E1 accesses are TNV1 voltages.
Other circuits are SELV voltage.
Mechanical ground and logic ground are separated on the board. These two
ground types can be connected together at the backplane level.

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5.3 JBXMUX Board


5.3.1 Introduction
The JBXMUX board, which is part of the JSXLIU/JSXLIUB shelf, ensures the
concentration of 256 E1 PCM links on a Gb Ethernet external interface.
This board performs the following functions:
Multiplexing and de-multiplexing of up to 16 E1 trunks (1 per LIU card)
for a total capacity of 256 E1 lines
Overall timing synchronization generation via the nE1oE mechanism
NE1oE packing/ unpacking
Control, supervision and data frame management through the GbE link
Control management and supervision of LIU cards
One GbE physical interface
Active/ standby communication link with the second JBXMUX card for 1+1
protection purpose
Debug interface
RI data storage
Hot insertion.

5.3.2 JBXMUX Hardware Architecture


The JBXMUX card architecture can be described as follows:
The NE1OE block, which provides emission/reception of the E1 links over
Ethernet, along with control management (also over Ethernet). It also
performs Active/ Standby JBXMUX control.
The NE1oE master clock, which provides synchronization timing for the
overall MX platform
One Gb Ethernet physical interface
Control management and supervision of JBXLIU/JBLIU75 cards
Active/ standby communication link with the second JBXMUX card for
1+1 protection purposes
One Flash memory block for FPGA bit stream, and boot firmware
FPGA configuration
One 16MX32 bit SDRAM block attached to the nE1oE system on the
chip processor
One RS232 test interface for the nE1oE SOC processor
One I2C interface for RI data storage
The reset module, which provides the reset logic for the FPGA (JGXEOE
and JGXCLU) and the GbE transceiver

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The power supply module, which provides all the required on-board power
from the backplane 12V A and B rails. It also manages the power/failure
front plate LED.
This is shown in the following figure.
12V A/B

Power
Supply

Reset

Front
panel
access

JGXEOE
Serial data links

Back
plane
access

Timing
generation

Active/ standby
LIU cards presence

SMbus

I2C

nE1oE / User &


Control planes
management

TWSI

RGMII
JGXCLU
RI
EEPROM
FPGA /
configuration

Ethernet
Physical interface
module

RS232
transceiver

System On
Chip

Debug

RAM
16MX32b

FLASH
8 MB

Address/ data/ ctrl

Address/ data/ ctrl

Figure 48: JBXMUX Architecture

5.3.2.1 NE1OE Block


The nE1oE function constitutes the main part of the JBXMUX card and is
housed in the JGXEOE FPGA. This function provides, along with the E1
interface/ alignment/ Mux function setting on each LIU card, an overall E1
cross-connect capability for 512 E1 PCM links (limited by hardware capabilities
to 256 E1 links) over Ethernet transport.
The nE1oE can be split into the following sub-blocks:
16E1 data interfaces 4B-5B coding
Each of the 16 serial data links in connection with the 16 LIU cards in
the shelf are 4B-5B coded/decoded for reducing the backplane access
connector pin-count and ultimately simplifying the backplane physical
design. The nominal bit rate before coding is 36.864Mbps and the line
bit-rate is 46.08Mbps. Data out and data in signals are conveyed to/from
each LIU card after single to differential signal conversion (100 Ohm
balanced pairs), ending up with a two pair backplane interconnection per
data stream. Data and synchronization signals are recovered from the 4B5B
code itself via an over-sampling technique.
Ethernet frames packing/ unpacking and E1 cross-connect with physical
entities within the MX platform perimeter (JBXGPU, JBXOMCP)
Gb Ethernet MAC/Physical interfacing, with auto-negotiation 10/100/1000
base-T with Reduced Pin count GMII (RGMII) interfacing on the MAC side
Communication with the second JBXMUX card for mutual active/ standby
switching-over process control
Control and user plane management to/from the Gb Ethernet link.

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This part is achieved by an embedded processor (SOC) also in charge of


the SDRAM, the Flash, the I2C, the RS232 debug link, the in-band reset
and shelf address management.

5.3.2.2 Timing Generation


NE1oE Master clock: The designated active JBXMUX card in the
selected JSXLIU/JSXLIUB shelf is by definition also the master, in terms of
synchronization for the entire nE1oE function on the MX platform. As a result,
all other entities present in the system are necessarily synchronized with the
8kHz rhythm sent by the JBXMUX through the nE1oE framing mechanism.
A 36.864MHz VCXO used as a free run oscillator is dedicated to this end, and
provides the clock signal used by the JGXEOE as the reference for all nE1oE
sub-blocks. The 8KHz frame synchronization signal is also internally built
from this reference.
Given that the JGXEOE architecture is common to the different applications
(JBXGPU or JBXMUX), the internal PLL tracking is disabled in the JBXMUX
case and the phase comparator output pulse width is set to its mid-range value.
An analog low pass filter (cut-off at approximately 10Hz) provides the VCXO
with a DC voltage, setting the output frequency to its mid-range value.
System clock: A 25MHz system clock signal is produced by a free run
oscillator for the JGXEOE, the JGXCLU and the GbE transceiver. The
JGXEOE Mac interface sub-block uses the 25MHz input clock to produce the
125MHz reference clock necessary for the 10/100/1000base-T application. The
frequency multiplication is managed via an internal broadband PLL embedded
in the FPGA matrix. The same artifact is used on the transceiver Mac side.

5.3.2.3 Ethernet Physical Interface Module


The gigabit Ethernet physical access is performed via the Marvell 88E1111
transceiver. This transceiver use a Reduced pin count GMII (RGMII) interface
with the JGXEOE, and has its MDI interface connected directly to an
1000base-T RJ45 module integrating the filtering magnetics and two LEDs .
RGMII interface:
Upward: TXD[3:0], TXEN, GTX CLK
Downward: RXD[3:0], RXDV, XCLK.
For alarm collection and register programming, the transceiver TWSI interface
is also connected to the JGXEOE.

5.3.2.4 Active/ Standby Communication


In the 1+1 protection scheme philosophy adopted on the MX platform, the
active/ standby switchover provides a very important function of the JBXMUX. It
gives each of the 16 LIU cards in the shelf clear information as to which of the
incoming data streams (from either JBXMUX card A or B) is the valid one.
The active/ standby communication link concerns the two JBXMUX cards
present in the JSXLIU/JSXLIUB shelf as part of a shared RS flip-flop function).
This function provides each JBXMUX with an exclusive mechanism for
triggering one JBXMUX in Active or Standby modes, whereas the second
JBXMUX is automatically set to the opposite state.
Switchover triggering events:

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Master request from the MX platform management entity. The order is


received from the JBXOMCP through the Ethernet and is decoded as such
by the JGXEOE control plane management.
Card in error (see below).
These two events are processed in an autonomous fashion vis-a-vis the MX
platform management entity. In both cases, a report of the JBXMUX state
change is sent to the MX platform management entity through the Ethernet
control frames.
A JBXMUX card is declared in error after any of the following events:
Card currently in reset mode (nE1oE functions are unavailable until the end
of this sequence)
FPGA download sequence NOK (monitoring of JGXEOE init done signal
along with watchdog time-out) or card absent
Boot operational status not validated (specific bit and watchdog time-out
monitoring)
No supervision frame received for more than n X T seconds, whereby T =
mX100 ms and n is a positive integer.

5.3.2.5 Flash Memory Block


The Flash memory contains the FPGA configuration files and the boot code of
the processor embedded in the JGXEOE.
The Flash is accessed via a data path of 8 bits wide at a frequency of 12,5
MHz. The Flash is performed with two components (8Mx8 (M29DW640D
from ST, 70ns access time).
The Flash is split in two main areas
A permanent area programmed in the factory (write protected)
An update area which can be programmed by the SoC processor.
The programming process is controlled by the JGXCLU EPLD but the update
configuration is managed by the embedded processor of the JGXEOE FPGA
and is received through the Ethernet communication.

5.3.2.6 SDRAM Memory Block


The SDRAM is used by the SoC processor to store its executable program
and eventually to store data (constants, variables) if the JGXEOE internal
memory is not sufficient.
The SDRAM capacity is 512 Mbits. It is organized in 16 Mega words of 32
bits each and is accessed via a data bus of 32 bits at the frequency of the
processor (i.e. 66 MHz). The SDRAM memory is built with two 16Mbit*16
memory components.

5.3.2.7 RS232 Test Interface


Connected to the JGXEOE, this serial interface provides test access through a
dedicated RJ45 connector setting on the front plate.
Communication port settings:
Speed : 115200 baud

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Parity : No
Data bits: 8
Stop bit: 1
Flow control: No.

5.3.2.8 LIU Cards Presence Detection


The JGXEOE is in charge of collecting, via the I2C interface, card presence
information for each LIU card slot in the JSXLIU/JSXLIUB shelf. In order to do
so, a I2C decoder able to manage 16 I/O is used (PCA9555) to detect the 16
signals PRST_1 to 16 present on the backplane connectors.
LIU present: PRST_xx = Voltage logic level low (LVTTL)
LIU absent: PRST_xx = Voltage logic level high (forced on the JBXMUX card
input by a pull-up resistor to 3.3V).

5.3.2.9 I2C Interface


A single master I2C interface managed by the JGXEOE is used to communicate
with the :
RI component (EEPROM 512X8, 10ms)
JBXPEM in the JSXLIU/JSXLIUB shelf (local RI and alarms polling)
External components in charge of detecting the JBXLIU/JBLIU75 boards
presence.
For the different I2C items to be accessed properly, each item of the same
type (i.e. RI EEPROM, temperature controller, I2C GPIO) have a unique
hardware address code within this type.

5.3.2.10 Reset Logic


Two types of reset are implemented on the JBXMUX:
Power-ON reset
This is a global hardware reset of the entire card. A power supply
supervisory circuit supervisor monitors the main power supply rail (3.3V).
As soon as it reaches a certain threshold, it maintains the JGXEOE, the
JGXCLU and the GbE transceiver (PHY) in reset. As soon as the JGXCLU
reset is released, it performs the JGXEOE download operation from the
FLASH down to the FPGA. As soon as the JGXEOE bit stream is loaded,
the component Init-done signal is activated and the JGXEOE master reset
is released, followed by the boot loader execution
JBXMUX reset
This is a single reset bit carried out by the nE1oE control frames. It is
also used as a global hardware reset for the JBXMUX card. This reset
being conveyed by the FPGA, which is a target for this reset action, the
FPGA JBXMUX reset output falling edge is detected and converted into a
calibrated negative pulse driving the power supply supervisory circuit
(MAX708S) responsible of delivering the master reset pulse. A discrete
component (TLC7701) is responsible for performing this function.

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5.3.2.11 FPGA Download


The FPGA download is performed by the JGXCLU EPLD. This device is also
used on the JBXGPU card. The behavior of the JGXCLU depends on the type
of the board. Selection of the board type is made with the BRD_SEL(1:0)
input pin.

5.3.2.12 Power Supply Module


The power supply module provides the secondary power supply for the overall
board. On-board DC/DC converters and regulators provide the necessary
voltage rails from two 12V DC redundant primary feeds.
Start-up, shut-down and supervisory voltage rails are provided via a dedicated
EPLD.

5.3.3 Front Panel Interface


5.3.3.1 RS232 Test Interface (X5)
The connector type is a 10/100/1000 base T-RJ45 single port.

5.3.3.2 GbE Interface (X6)


The GbE interface provides:
Connector type: 10/100/1000 base T-RJ45 single port with integrated
LEDs and magnetics.
The mechanical ground is connected via the PCB to the connector shield.
This is shown in the following figure.
Top LED (Link Satus
up/down)
PCB pin side
Bottom LED (1000 base T
link activity)

Figure 49: 1000 Base-T RJ45 Connector Front View

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5.3.3.3 LEDs
Four LEDs are visible on the front panel (from the top to the bottom):
Power ON/OFF/failure LED (L1)
This is a bi-colour, red/green LED. When the card is powered ON and all the
monitored power supply rails voltages are at least at 0.9xVcc, the green
LED is turned ON. If any of the power supply rails drop below 0.9xVcc, the
green LED is turned OFF and the red LED is turned ON
Active/ standby LED (L2)
This is a yellow LED driven by the JGXEOE SEL signal. When the JBXMUX
card is in active mode, the signal SEL is set to 3.3V, saturating a switching
transistor and turning the LED ON. When the JBXMUX card is back in
standby mode, the LED is turned OFF.
Two additional LEDs are associated with the GbE RJ45 front panel connector:
Upper LED (L3): Link status. Green LED:
LED ON: Link up
LED OFF: Link down.
When up, the link is operational, in either idle or transmission modes.
Lower LED (L4): 1000 base-T Link activity. Yellow LED
LED ON: Transmitting
LED OFF: Not transmitting or negotiated mode is 10base-T or 100base-T.

5.3.4 Backplane Interface


Two connectors share the overall height of the card on the back.
The backplane accesses are as follows:
JBXLIU/JBLIU75/ JBXMUX 16E1 serial differential links
JBXMUX active/ standby link
I2C link
Slot address
Shelf address
12V Power supply A & B
JBXLIU/JBLIU75 card presence
Provision for JSXLIU/JSXLIUB shelf unused slot communication.

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5.3.5 Front Panel


The following figure shows the JBXMUX front panel.

JBXMUX
GREEN/ RED Led
YELLOW Led

TEST

Test access

GbE
Link status (L3)
GbE access
Link activity (L4)

Figure 50: JBXMUX Front Panel

5.3.6 Power Supply Description


This block is responsible for converting the incoming 12V A and 12V B DC
voltages to the following DC voltage rails:
+3.3V / GND powers the RAM, the Flash, the JGXCLU, the JGXEOE I/O,
the ISPPAC and all the discrete components
+1.5V / GND is for the JGXEOE core
+1.2V / GNDis for the GbE transceiver core
+2.5V / GND is for the GbE transceiver I/O and the JGXEOE I/O.

5.3.6.1 TNV/ SELV Galvanic Isolation


The incoming 12V rails are provided by each JBXPEM card in the
JSXLIU/JSXLIUB shelf. The -48V to +12V DC/DC converters used for this

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purpose feature a galvanic isolation between the two classes of voltages


handled in the system. For this reason, the DC/DC converter block used on
the JBXMUX card does not have to exhibit any galvanic isolation, thereby
reducing its overall cost.

5.3.6.2 Power Supply Management


A specialized IC monitors and controls each secondary power supply voltage
rail used by the card:
Card plug-in (hot insertion) whereby all the secondary voltages rails are
enabled at the same time and a smooth start is programmed to limit the
inrush current
DC rail voltage failure, whereby any secondary power supply rail whose
voltage value is below 10% of its nominal value ( factory programmable
threshold) triggers a global disabling of all the secondary rails.

5.3.7 Safety
The JBXMUX board belongs to the JSXLIU/JSXLIUB shelf, and meets the
safety specifications, according to the LIU Product Integration Qualification
Specification:
The Gigabit Ethernet access is TNV1 voltage class
Other circuits are SELV voltage class.
Mechanical ground and logic ground are kept separated on the board. These
two ground types can be connected together at the backplane level by addition
of dedicated screws.
With regard to the ESD discharges for the front plate and the electrical ground
planes. The Compact PCI standard [16] ensures a soft discharge of any
hazardous ESD buildup by the use of 3 copper stripes laid down the PCB card,
and one metallic card guide clip placed within mechanical rails in the shelf.
When the card is plugged into its slot, the stripes are successively in contact
with the clip, ensuring an electrical path towards the mechanical ground.
Consequently, the front plate is connected to stripe 1 (nearest to the front plate)
through a 10M Ohm resistance, the ground planes are connected to the second
stripe, and the third stripe (nearest to the back side) connects the front plate
directly to the mechanical ground (no resistance).
This is shown in the following figure.
Card enclosure

Chassis

ESD Stripes
10 M Ohm
Font plate
GND planes

1
2
3

Card guide clip

Mechanical ground

Figure 51: ESD Mitigation Mechanism

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5.4 JBXPEM Board


5.4.1 Introduction
The JBXPEM board handles the power for the JSXLIU/JSXLIUB shelf. Each
JBXPEM receives front input from - 40V up to - 72 VDC, redundant A + B
power feeds. Each JBXPEM board distributes the +12VDC supply to the
JBXLIU/JBLIU75 and JBXMUX boards. The global consumption is less than
100W (fully loaded).
The JBXPEM board is part of the JSXLIU/JSXLIUB shelf, which belongs
to the MX platform.
The JBXPEM board is hosted in the JSXLIU/JSXLIUB shelf in slots 1 and 21.
Each JBXPEM board receives -48/60 VDC on the front panel. The redundant
function between both JBXPEMs is provided through the backplane.
This is shown in the following figure.
JSXLIU Shelf

48V
A Input

Redundant
link

JBXPEM A

48V
B Input

JBXPEM B

+12V

JBXLIU
1 to 16

I2C
link

+12V

JBXMUX A&B
+ unused slot

Figure 52: JBXPEM Environment

5.4.2 JBXPEM Architecture and Functions


The JBXPEM board functions are as follows:
EMI filter
DC/DC converter with basic insulation (-40/72VDC into +12Vdc)
Alarm connection
Temperature detection
RI EEPROM
Current limitation device for hot insertion.

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The following figure shows the JBXPEM board architecture.

48V
front input

48V Back input


to the other PEM B

EMI filter
Power coupling
+
Current limitation
+
Protection
+
Input monitoring

48V Back input


from other PEM B

Local +12V
Remote + 12V

Logic alim

+3.3V

Power Entry Module

DC/DC
isolated converter

12V (A or B)

ALA12
ALA48

Alarm
collection

Slot Address

Temperature
sensor

RI
EEPROM

I2C
I2C

Figure 53: JBXPEM Board Architecture

5.4.2.1 Hot Insertion Device


The JBXPEM board can be plugged into the JSXLIU/JSXLIUB shelf without
disturbing the other boards in the shelf. A specific device suppresses the
inrush input current.

5.4.2.2 EMI Filter


An EMI filter is required in order to be compliant with the 73/23/EEC directive,
to obtain the CE marking label.

5.4.2.3 48V / 12V Conversion


Two incoming separated input power supplies feed each board:
Front input -48/60Vdc
Back panel input -48/60Vdc (VBATI).
12 V power supply is distributed by each JBXPEM to all the other boards
via a complete plan.
P12VA is the +12 voltage generated by the left JBXPEM. It is connected to
P12Vi on the right JBXPEM.
P12VB is the +12 voltage generated by the right JBXPEM. It is connected to
P12Vi on the left JBXPEM.

5.4.2.4 12V /3.3V Conversion


The 12V to 3.3V conversion is made by a bipolar low drop device to feed the
logical alarm supervision. The regulator is powered by two 12V. The first is the
local 12V of the JBXPEM and the second is the 12V of the second JBXPEM.

5.4.2.5 Hardware Management


A multi-master I2C interface, managed by the JGXEOE of the JBXMUX,
is used to communicate with the:
RI component (EEPROM 512X8, 10ms)
JBXPEM in the JSXLIU/JSXLIUB shelf (local RI and alarms polling)

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External components in charge of detecting the JBXLIU/JBLIU75 boards


presence.
Each item of the same type (i.e. RI EEPROM, temperature controller, I2C
GPIO) has a single hardware address code within this type.
Slot Address: Each slot in the JSXLIU/JSXLIUB shelf backplane is individually
identified by a specific polarization of the SLA signals. X indicates that
the jumper is present and drives the corresponding SLA pin of JBX* board.
When it is left open, the selected board will detect a logical level 1 via an
adequate pull up resistor.
The address number of the JBXPEM board is:
1 for JBXPEM A
21 for JBXPEM B.
RI EEPROM: An EEPROM with I2C access is dedicated to RI data. It can be
read by the active JBXMUX board component. A specific connector allows the
factory to write the data when the board is not powered.
Alarm Collection: The different alarms come from:
-48/60Vdc of JBXPEM board A
-48/60Vdc of JBXPEM board B
12V
The temperature sensor.
All the alarms are connected to a IC/SMBus device. This I2C link allows the
JBXMUX to read the RI EEPROM, the alarm register and the temperature on
the adjacent JBXPEM board. It is composed of the SCL and SDL signals.
Arbitration of the I2C master is performed via active/standby signals.
Temperature Sensor: The LM75 temperature sensor provides the local
temperature at all times to the JBXPEM board. When the temperature exceeds
80C, the device generates a temperature alarm.

5.4.2.6 Redundant A+B Power Feed


The VBAT power supply enters the front panel of each JBXPEM on left and
right sides of the shelf . It is also distributed to the other JBXPEM board. The
VBATO of JBXPEM A is connected to VBATI of JBXPEM B (and reciprocally).
Each JBXPEM board generates 12V (A & B). All the other boards are powered
by two 12V:
P12VA from JBXPEM A
P12VB from JBXPEM B.

5.4.2.7 ESD Discharge Circuit


An ESD discharge circuit allows a progressive discharge through a resistor
(10 MW) on the board before complete insertion.

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5.4.3 Front Panel


The front panel shows the:
Front board connector
Visual interface
RI.
This is shown in the following figure.

JBXPEM

Power/Fail

48/60VDC
4A

Figure 54: JBXPEM Front Panel

5.4.3.1 Front Board Connector


The front board connector (X3) type UPI has three pins:
Pin 1 for -48/60VDC input (VBAT)
Pin 2 for 0VCR input (VBATR)
Pin 3 for MMECA (or MGND) input (shelf ground).

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5.4.3.2 Visual Interface


A LED indicator on the front plate shows the boards status, as described in
the following table.
Color

Description

OFF

The board is not powered.

Green

The board is powered and OK.

Amber

One input -48/60VDC is missing.

Red

Board failure is detected (local +12V failure).

5.4.3.3 Remote Inventory


The interface for RI factory access is via a CONAN 9-pin connector.

5.4.4 Back Plane Connector


The board connector (J1) is a compact PCI type A.
This is shown in the following figure.

100 mm

160 mm

3U board format

J1
X3

Figure 55: JBXPEM Side View

5.4.5 Safety
The JBXPEM board meets safety standards.
The front input -48/60VDC access is a classified TNV2 circuit. The output of
the DC/DC and the other circuits are classified as SELV.
Mechanical ground (MGND) and logic ground (GND) are separated on the
board. These two grounds can be connected together through the backplane,
depending on the equipment.

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5.5 Dummy Panel (JBXDUM)


Each unsed slot in JSXLIU/JSXLIUB shelf is closed by a dummy panel,
JBXDUM
The following figure shows the front and side view of the dummy panel.

JBXDUM

Figure 56: JBXDUM Front and Side Views

5.6 LIU Filler (JMXF1U)


Above each JSXLIU shelf, JMXF1U filler is used to give the physical slot
number for the blades. It is not part of JSXLIU shelf.
The following figure shows the front view of the filler.

10 11 12 13 14 15 16 17 18 19 20 21

Figure 57: JMXF1U Front View

5.7 LIUB Label


On top of the front side of each JSXLIUB shelf, a label is used to give the
physical slot number for the blades. It is part of JSXLIUB shelf.
The following figure shows the JSXLIUB label.
JSXLIUB

10

11

12

13

14 15

16

17

18

19

20

Figure 58: JSXLIUB Label

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