Applied Rec GCT

1
VHDL
PROGRAMMING
USING IMAGE
and XILINX
SOFTWARE

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3

EXP NO: 1 LCD DISPLAY
16.01.2013
AIM
To write a VHDL program to simulate lcd display and implement it on an FPGA
kit.
APPARATUS REQUIRED
Image software, Xilinx Spartan 3E FPGA Trainer Kit
THEORY
In recent years LCD is finding wide spread use replacing LEDs due to its low
price, ability to display numbers, characters etc, ease of programming for
characters and graphics. There are two very important registers inside the LCD.
The RS, Register Select pin is used for selecting command code register (RS=0) or
data register (RS=1). R/W, Read/write pin allows the user to write
information(R/W=0) to LCD or read information (R/W=1) from it .Enable pin is
used by the LCD to latch information presented to its data pins. When data is
supplied to the data pins, a high to low pulse must be applied to this pin in order
for the LCD to latch the data present at the data pins. There are 8 data pins D0-D7
are used to send information to LCD or reads the contents of the LCDs internal
registers. To display letters and numbers, we send ASCII codes for the letters A-Z,
a-z and numbers 0-9 to these pins while making RS=1.

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5

LCD COMMANDS
CODE(HEX) COMMAND TO LCD INSTRUCTION REGISTER
01 CLEAR DISPLAY SCREEN
02 RETURN HOME
04 DECREMENT CURSOR
06 INCREMENT CURSOR
05 SHIFT DISPLAY RIGHT
07 SHIFT DISPLAY LEFT
08 DISPLAY OFF,CURSOR OFF
0A DISPLAY OFF,CURSOR ON
0C DISPLAY ON,CURSOR OFF
0E DISPLAY ON,CURSOR BLINKING
0F DISPLAY ON,CURSOR BLINKING
10 SHIFT CURSOR POSITION TO LEFT
14 SHIFT CURSOR POSITION TO RIGHT
18 SHIFT THE ENTIRE DISPLAY TO THE LEFT
1C SHIFT THE ENTIRE DISPLAY TO THE RIGHT
80 FORCE CURSOR TO BEGINNING OF FIRST LINE
C0 FORCE CURSOR TO BEGINNING OF SECOND LINE
38 TWO LINES AND 5*7 MATRIX

6

TESTBENCH
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture test of
testbench is
signal s1:std_logic:='0';
signal s2,s3,s4:std_logic;
signal d:std_logic_vector(7 downto 0);
component lc is
port(clk:in std_logic;
lcde:out std_logic;lcdrw,lcdrs:out std_logic;
lcddata:out std_logic_vector(7 downto 0));
end component;
begin
dut:lc port map(s1,s2,s3,s4,d);
s1<=not s1 after 5 ns;
end test;

7

a)SOURCE CODE FOR SIMULATION USING IMAGE TOOL
library ieee;
entity lc is
port(clk:in std_logic;
lcde:out std_logic;lcdrw,lcdrs:out std_logic;
lcddata:out std_logic_vector(7 downto 0));
end lc;
architecture Behavioral of lc is
begin
process(clk)
variable count: integer :=0;
variable delay:integer :=0;
variable wait1 :integer :=0;
variable flag :std_logic :='0';
variable regsel:std_logic :='0';
variable lcrw:std_logic :='0';
variable lce:std_logic :='0';
variable lcdata: std_logic_vector (7 downto 0) :="00000000";
begin
if(clk'event and clk='1') then
if (wait1 <=1) then
wait1:=wait1+1;
end if;
if(delay=3 and wait1>1)then
if (flag='0') then
count:=count+1;
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if count<27 then flag:='0';
else flag:='1';
end if;
else
flag:='1';
end if;
delay:=0;
end if;
delay:=delay+1;
end if;
case count is
when 0=>
flag:='0';regsel:='0';lcrw:='0';lce:='1';lcdata:="00000000";
when 1=>
when 2=>
when 3=>
when 4=>
when 5=>
when 6=>
when 7=>
10

SIMULATION RESULT

11

when 8=>
when 9=>
when 10=>
when 11=>
when 12=>
when 13=>
when 14=>
when 15=>
when 16=>
when 17=>
when 18=>
when 19=>
when 20=>
when 21=>
12

13

when 22=>
when 23=>
when 24=>
when 25=>
when 26=>
when others=>
flag:='1';
lce:='1';
end case;
if(count<=27)then
lcdrs<=regsel;
lcdrw<=lcrw;
lcde<=lce;
lcddata<=lcdata;
end if;
end process;
end Behavioral;

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b)SOURCE CODE FOR IMPLEMENTATION USING XILINX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--en is enable signal of 7 seg
--data ,dr,wr are the o/ps.
entity lcd is
Port ( data : out std_logic_vector(3 downto 0);
dr : out std_logic; en : out std_logic;
clk1 : in std_logic;
wr : out std_logic));
end lcd;
architecture Behavioral of lcd is
type state is (state1,state2,state3,state4,state5,state6,state7,state8, state9,state10,
state11,state12,state13,state14,state15,state16,state17,state18,state19,state20,
state21,state22, state 23,state24,state25,state26,state27,state28,state29,
state30,state31,endmsg,endmsg1,endmsg2,endmsg3);
signal current_state,next_state:state;
constant init : std_logic_vector(3 downto 0) := "0010";
constant init1 : std_logic_vector(3 downto 0) := "1000";
constant cldisp : std_logic_vector(3 downto 0) := "0000";
constant cldisp1 : std_logic_vector(3 downto 0) := "0001";
constant cronblink: std_logic_vector(3 downto 0):= "0000";
16

PIN ASSIGNMENT (UCF)
net "clk" loc="p80";
net "lcddata<3>" loc="p18";
net "lcde" loc="p11";
net "lcdrw" loc="p9";
net "lcdrs" loc="p8";

17

constant cronblink1: std_logic_vector(3 downto 0):= "1100";
constant A: std_logic_vector(3 downto 0):="0100";
constant A1: std_logic_vector(3 downto 0):="0001";
constant P: std_logic_vector(3 downto 0):="0101";
constant P1: std_logic_vector(3 downto 0):="0000";
constant 2P: std_logic_vector(3 downto 0):="0101";
constant 2P1: std_logic_vector(3 downto 0):="0000";
constant L: std_logic_vector(3 downto 0):="0100";
constant L1: std_logic_vector(3 downto 0):="1100";
constant I: std_logic_vector(3 downto 0):="0100";
constant I1: std_logic_vector(3 downto 0):="1001";
constant E: std_logic_vector(3 downto 0):="0100";
constant E1: std_logic_vector(3 downto 0):="0101";
constant D: std_logic_vector(3 downto 0):="0100";
constant D1: std_logic_vector(3 downto 0):="0100";
constant SPACE: std_logic_vector(3 downto 0):="0010";
constant SPACE1: std_logic_vector(3 downto 0):="0000";
constant G: std_logic_vector(3 downto 0):="0100";
constant G1: std_logic_vector(3 downto 0):="0111";
constant C: std_logic_vector(3 downto 0):="0100";
constant C1: std_logic_vector(3 downto 0):="0011";
constant T: std_logic_vector(3 downto 0):="0101";
constant T1: std_logic_vector(3 downto 0):="0100";
constant initreg : std_logic_vector(3 downto 0):= "0011";
constant initreg1 :std_logic_vector(3 downto 0):= "0010";
18

IMPLEMENTATION RESULT

19

signal sen: std_logic:='1';
signal el: std_logic:='1';
signal sdr: std_logic:='0';
signal ln2: std_logic:='0';
signal sdata: std_logic_vector(3 downto 0);
signal temp: std_logic_vector(3 downto 0):= "0000";
signal bclk: std_logic;
signal bclk1: std_logic;
signal swr: std_logic;
--sub component declaration of testcount
component testcnt is
port(clk : in std_logic;
one : inout std_logic);
end component;
begin
u1:testcnt port map(clk =>clk1,one =>bclk);
u2:testcnt port map(clk =>bclk,one =>bclk1);
wr <= swr;
dr <= sdr;
data <= sdata;
pp2: process(bclk1)
begin
if bclk1'event and bclk1 = '1' then
current_state <= next_state;
if sen = '1' then
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en <= el;-- after 10 ns;--100 ns;
el <= not el;-- after 600 ns;
else
en <= not el;
end if;
case current_state is
--lcd intialization
when state1 =>
if el = '0' then
sdr<='0';
swr<='0';
sdata <= initreg;
next_state <= state2;
end if;
when state2 =>
sdata <= initreg;
if el = '0' then
end if;
when state3 =>
sdata <= initreg1;
if el = '0' then
end if;
when state4 =>
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sdata <= init;
if el = '0' then
end if;
when state5 =>
sdata <= init1;
if el = '0' then
end if;
--lcd cursor blink
when state6 =>
sdata <= cronblink;
if el = '0' then
end if;
when state7 =>
sdata <= cronblink1;
if el = '0' then
end if;
--lcd clear display
when state8 =>
sdata <= cldisp;
if el = '0' then
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25

end if;
when state9 =>
sdata <= cldisp1;
if el = '0' then
end if;
--sending A character higher nibble
when state10 =>
sdata <= A;
sdr <= '1' after 200 ns;
if el = '0' then
end if;
--sending A character lower nibble
when state11 =>
sdata <= A1;
if el = '0' then
end if;
--sending P character higher nibble
when state12 =>
sdata <= P;
if el = '0' then
end if;
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--sending P character lower nibble
when state13 =>
sdata <= P1;
if el = '0' then
end if;
--sending P character higher nibble
when state14 =>
sdata <= 2P;
if el = '0' then
end if;
--sending P character lower nibble
when state15 =>
sdata <= 2P1;
if el = '0' then
end if;
--sending L character higher nibble
when state16=>
sdata <= L;
if el = '0' then
end if;
--sending L character lower nibble
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when state17=>
sdata <= L1;
if el = '0' then
end if;
--sending I character higher nibble
when state18=>
sdata <= I;
if el = '0' then
end if;
--sending I character lower nibble
when state19=>
sdata <= I1;
if el = '0' then
end if;
--sending E character higher nibble
when state20=>
sdata <= E;
if el = '0' then
end if;
--sending E character lower nibble
when state21=>
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sdata <= E1;
if el = '0' then
end if;
--sending D character higher nibble
when state22=>
sdata <= D;
if el = '0' then
end if;
--sending D character lower nibble
when state23=>
sdata <= D1;
if el = '0' then
end if;
--giving SPACE higher nibble
when state24 =>
sdata <= SPACE;
if el = '0' then
end if;
--giving SPACE lower nibble
when state25=>
sdata <= SPACE1;
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if el = '0' then
end if;
--sending G character higher nibble
when state26=>
sdata <= G;
if el = '0' then
end if;
--sending G character lower nibble
when state27 =>
sdata <= G1;
if el = '0' then
end if;
--sending C character higher nibble
when state28 =>
sdata <= C;
if el = '0' then
end if;
--sending C character lower nibble
when state29 =>
sdata <= C1;
if el = '0' then
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35

end if;
--sending T character higher nibble
when state30 =>
sdata <= T;
if el = '0' then
end if;
--sending T character lower nibble
when state31 =>
sdata <= T1;
if el = '0' then
next_state <= endmsg;
end if;
when endmsg =>
sdata <= SPACE;
if el = '0' then
next_state <= endmsg1;
end if;
when endmsg1=>
sdata <= SPACE1;
if el = '0' then
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end if;
when endmsg2 =>
sdata <= SPACE;
if el = '0' then
end if;
when endmsg3=>
sdata <= SPACE1;
if el = '0' then
end if;
end case;
end if;
end process pp2;
end Behavioral;

RESULT
The VHDL program to simulate lcd display is written, simulated and implemented
it on an FPGA kit.

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39

EXP NO: 2 DIGITAL CLOCK
23.01.2013
AIM
To write a program in vhdl for digital clock , simulate it using IMAGE software
and implement in FPGA kit using Xilinx software.
APPARATUS REQUIRED
Image software, Xilinx software and Spartan3E FPGA kit.
THEORY
A digital clock is a type of clock that displays the time digitally, ie, in
numerals or other symbols as opposed to an analog clock, where the time is
indicated by the positions of rotating hand. To represent time ,digital clock use
seven segment display. The Spartan 3E FPGA starter kit has four character, seven
segment LED display. Each digit shares eight common control signals to light
individual LED segments. Each character has a separate anode control input. To
light an individual signal, drive the individual control signal low along with the
associated anode control signal for the individual character.
Minutes and seconds are displayed in each of this by selecting appropriate
segments. Clock divider or prescalar is used to divide the frequency(clock).
Because digital clocks can be very small and inexpensive devices that
enhance the popularity of product designs, they are often incorporated into all
kinds of devices such as cars, radios, televisions, microwave ovens, standard
ovens, computers and cell phones.

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SOURCE CODE FOR SIMULATION
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity digi_clk is
port(clk1 : in std_logic;
seconds:out std_logic_vector(5 downto 0);
minutes:out std_logic_vector(5 downto 0);
hours:out std_logic_vector(4 downto 0));
end digi_clk;
architecture ad of digi_clk is
signal sec,min, hour: integer range 0 to 60:=0;
signal count:integer:=1;
signal clk:std_logic:='0';
begin
seconds<= conv_std_logic_vector(sec,6);
minutes<= conv_std_logic_vector(min,6);
hours<= conv_std_logic_vector(hour,5);
process(clk1)
begin
if(clk1'event and clk1='1')then
count<=count+1;
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if(count=5)then
clk<= not clk;
count<=1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
sec<=sec+1;
if(sec=59)then
sec<=0;
min<=min+1;
if(min=59)then
hour<=hour+1;
min<=0;
if(hour=23)then
hour<=0;
end if;
end if;
end if;
end if;
end process;
end ad;
44

RTL SCHEMATIC

45

SOURCE CODE FOR KIT IMPLEMENTATION
library IEEE;
entity digiclock is
port(clk:in bit;
en:in bit;
unit0,unit1,unit2, unit3: inout bit_vector(7 downto 0);
dataout:out bit_vector(7 downto 0);
sel:out bit_vector(3 downto 0));
end digiclock;
architecture Behavioral of digiclock is
subtype nat4 is integer range 15 downto 0;
subtype nat3 is integer range 7 downto 0;
signal clk1:bit;
signal count1,count2:integer:=1;
signal c1:integer range 0 to 4:=0;
begin
process(clk)
begin
if(clk'event and clk='1')then
count1<=count1+1;
if(count1=20000)then
clk1<= not clk1;
count1<=1;
end if;
46

UCF FILE
NET "clk" LOC ="p80";
NET "en" LOC ="p101";
NET "dataout<7>" LOC ="p19";
NET "sel<0>" LOC ="p5";

47

end if;
end process;
process(clk1)
variable secs,mins :nat4:=0;
variable tsecs,tmins :nat3:=0;
begin
if(clk1'event and clk1='1')then
case secs is
when 0 => unit0 <= "11000000";
when 1 => unit0 <= "11111001";
when 2 => unit0 <= "10100100";
when 3 => unit0 <= "10110000";
when 4 => unit0 <= "10011001";
when 5 => unit0 <= "10010010";
when 6 => unit0 <= "10000010";
when 7 => unit0 <= "11111000";
when 8 => unit0 <= "10000000";
when 9 => unit0 <= "10010000";
when others => unit0 <= "11111111";
end case;
case tsecs is
when 0 => unit1 <= "11000000";
when 1 => unit1 <= "11111001";
when 2 => unit1 <= "10100100";
when 3 => unit1 <= "10110000";
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49

when 4 => unit1 <= "10011001";
when 5 => unit1 <= "10010010";
end case;
case mins is
when 0 => unit2 <= "01000000";
when 1 => unit2 <= "01111001";
when 2 => unit2 <= "00100100";
when 3 => unit2 <= "00110000";
when 4 => unit2 <= "00011001";
when 5 => unit2 <= "00010010";
when 6 => unit2 <= "00000010";
when 7 => unit2 <= "01111000";
when 8 => unit2 <= "00000000";
when 9 => unit2 <= "00010000";
end case;
case tmins is
when 0 => unit3 <= "11000000";
when 1 => unit3 <= "11111001";
when 2 => unit3 <= "10100100";
when 3 => unit3 <= "10110000";
when 4 => unit3 <= "10011001";
when 5 => unit3 <= "10010010";
50

SIMULATION OUTPUT

51

end case;
c1<=c1+1;
if(c1=1)then
dataout<=unit0;
sel<="1110";
end if;
if(c1=2)then
dataout<=unit1;
sel<="1101";
end if;
if(c1=3)then
dataout<=unit2;
sel<="1011";
end if;
if(c1=4)then
dataout<=unit3;
sel<="0111";
c1<=0;
end if;
count2<=count2+1;
if(count2=300)then
if en='1' then
if secs = 9 then
secs := 0;
if tsecs =5 then
52

IMPLEMENTATION RESULT

53

tsecs := 0;
if mins =9 then
mins := 0;
if tmins=5 then
tmins:=0;
else tmins:=tmins+1;
end if;
else mins:=mins+1;
end if;
else tsecs:=tsecs+1;
end if;
else secs:=secs+1;
end if;
end if;
count2<=0;
end if;
end if;
end process;
end Behavioral;

RESULT
The vhdl program for digital clock has been written and simulated successfully
using image software and implemented on fpga kit.

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55

EXP NO: 3 ENCRYPTION & DECRYPTION
06.02.2013
AIM
To write a VHDL program for 32 encryption & decryption and to execute the
same in image software.
APPARATUS REQUIRED
Image software
THEORY
Encryption is the conversion of data into a form, called a ciphertext, that cannot be
easily understood by unauthorized people. Decryption is the process of converting
encrypted data back into its original form, so it can be understood. Simple ciphers
include the substitution of letters for numbers, the rotation of letters in the
alphabet, and the "scrambling" of voice signals by inverting the sideband
frequencies. More complex ciphers work according to sophisticated computer
algorithms that rearrange the data bits in digital signals. In order to easily recover
the contents of an encrypted signal, the correct decryption key is required. The key
is an algorithm that undoes the work of the encryption algorithm. Alternatively, a
computer can be used in an attempt to break the cipher. The more complex the
encryption algorithm, the more difficult it becomes to eavesdrop on the
communications without access to the key. Encryption/decryption is especially
important in wireless communications. This is because wireless circuits are easier
to tap than their hard-wired counterparts. Nevertheless, encryption/decryption is a
good idea when carrying out any kind of sensitive transaction, such as a credit-card
purchase online, or the discussion of a company secret between different
departments in the organization. The stronger the cipher -- that is, the harder it is
for unauthorized people to break it -- the better, in general. However, as the
strength of encryption/decryption increases, so does the cost.
There are two types of encryption techniques. Cryptography and stegnography.
Cryptography is processing of data into unintelligible form, reversibly, without
data loss.

56

BLOCK DIAGRAM

57

Stegnography is xc a secret message within a larger one in such a way that others
cannot discern the presence or contents of the hidden message. Cryptography uses
two types of keys. Public key and symmetric key. Public key or asymmetric key is
utilizes two keys - a public key to encrypt messages and a private key to decrypt
them. Symmetric key or secret-key cryptography is An encryption system in
which the sender and receiver of a message share a single, common key that is
used to encrypt and decrypt the message. Here, we are employing encryption of a
Four letter word which is represented using ASCII code. The encryption is
implemented by XOR operation with an eight bit key. On the Decryption part, we
again XOR the received data to retrieve the original data. Cryptography provides
means for secure data communication through a wireless channel.

SOURCE CODE
library IEEE;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encr_1 is
port(input,key: in bit_vector(7 downto 0);
output: out bit_vector(7 downto 0));
end encr_1;
architecture Behavioral of encr_1 is
begin
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59

output(0)<= input(0) xor key(0);
end Behavioral;
library IEEE;
entity encrptn_4 is
port(input_4: in bit_vector(31 downto 0);
key: in bit_vector(7 downto 0);
output_4: out bit_vector(31 downto 0));
end encrptn_4;
architecture Behavioral of encrptn_4 is
component encr_1 is
port(input,key: in bit_vector(7 downto 0);
output: out bit_vector(7 downto 0));
end component;
begin
x0: encr_1 port map(input_4(31 downto 24),key,output_4(31 downto 24));
60

TEST BENCH
library IEEE;
entity test bench is
end test bench;
Architecture test of test bench is
Signal s1: std_logic_vector(31 down to 0);
Signal s2: std_logic_vector(7 down to 0);
Signal s3, s4, s5: std_logic_vector(31 down to 0);
Component encr_decr is
Port(input_4: in std_logic_vector(31 down to 0);
Key : in std_logic_vector(7 down to 0);
Output_4: inoutstd_logic_vector(31 down to 0);
Din_4: inoutstd_logic_vector (31 down to 0);
Dout_4: out std_logic_vector (31 down to 0));
End component
Begin
Dut: encr_decrportmap (s1, s2, s3, s4, s5);
Process
Begin
Wait for 100nS;
S1<=010110010011000101001101001001;
S2<=00000001;
End process;
End test;
61

end Behavioral;
--decr;
entity decr_1 is
port(din,key: in bit_vector(7 downto 0);
dout: out bit_vector(7 downto 0));
end decr_1;
architecture Behavioral of decr_1 is
begin
dout(0)<= din(0) xor key(0);
end Behavioral;
library IEEE;
entity decr_4 is
port(din_4: in bit_vector(31 downto 0);
dout_4: out bit_vector(31 downto 0));
end decr_4;
62

SIMULATION OUTPUT

63

architecture Behavioral of decr_4 is
component decr_1 is
port(din,key: in bit_vector(7 downto 0);
dout: out bit_vector(7 downto 0));
end component;
begin
x0: decr_1 port map(din_4(31 downto 24),key,dout_4(31 downto 24));
end Behavioral;
entityencr_decr is
output_4: inoutbit_vector(31 downto 0);
din_4: inoutbit_vector(31 downto 0);
endencr_decr;
architecture Behavioral of encr_decr is
component encrptn_4 is
output_4: out bit_vector(31 downto 0));
end component ;
component decr_4 is
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65

port(din_4: in bit_vector(31 downto 0);
end component;
begin
f0: encrptn_4 port map( input_4,key,output_4);
din_4<=output_4;
f1: decr_4 port map( din_4,key,dout_4);
end Behavioral;

RESULT
Thus the program for 32-bit encryption and decryption using image software has
been executed succesfully.

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67

EXP NO: 4 FINITE STATE MACHINE
20.02.2013
AIM
To write a source code for FSM mealy and moore machine by using image
software.
APPRATUS REQUIRED
Image Tools
THEORY
A finite-state machine (FSM) or finite-state automaton or simply a state
machine, is a mathematical model of computation used to design both computer
programs and sequential logic circuits. It is conceived as an abstract machine that
can be in one of a finite number of states. The machine is in only one state at a
time; the state it is in at any given time is called the current state. It can change
from one state to another when initiated by a triggering event or condition; this is
called a transition. A particular FSM is defined by a list of its states, and the
triggering condition for each transition. The behavior of state machines can be
observed in many devices in modern society which perform a predetermined
sequence of actions depending on a sequence of events with which they are
presented. Simple examples are vending machines, elev Moore machine
The FSM uses only entry actions, i.e., output depends only on the state.
Mealy machine
The FSM uses only input actions, i.e., output depends on input and state. The use
of a Mealy FSM leads often to a reduction of the number of states.

68

STATE DIAGRAM FOR MEALY MACHINE

TEST BENCH FOR MEALY MACHINE
library ieee;
entity test is
end test;
architecture tt of test is
signal clk,rst,i:std_logic:='0';
signal o:std_logic;

component me is
port(clk,rst,i:in std_logic;
o:out std_logic);
end component;
begin
clk <= not clk after 5 ns;
rst<='0' after 5 ns;
i<='0'after 2 ns;
dut: me port map(clk => clk, rst => rst, i => i, o => o);
end tt;

S1
S0 S3
S2
69

SOURCE CODE FOR MEALY MACHINE
library ieee;
entity me is
port(clk,rst,i:in std_logic;
o:out std_logic);
end me;
architecture ame of me is
type st_type is (s0,s1,s2,s3);
signal cu_s,nx_s: st_type;
begin
process(clk,rst)
begin
if(rst='1')then
cu_s<=s0;
elsif(rising_edge(clk))then
cu_s<=nx_s;
end if;
end process;
process(cu_s,i)
begin
case cu_s is
when s0=>
if(i='0')then
o<='0';
nx_s<=s1;
else
o<='1';
nx_s<=s2;
end if;

70

OUTPUT WAVEFORM (MEALY MACHINE)

71

when s1=>
if(i='0')then
o<='0';
nx_s<=s3;
else
o<='1';
nx_s<=s1;
end if;

when s2=>
if(i='0')then
o<='1';
nx_s<=s2;
else
o<='0';
nx_s<=s3;
end if;

when s3=>
if(i='0')then
o<='1';
nx_s<=s3;
else
o<='1';
nx_s<=s0;
end if;
end case;
end process;
end ame;

72

S0/
00
STATE DIAGRAM FOR MOORE MACHINE
X=0

Y=1 x=1
Z=1

Y=1 z=0
Y=0
TESTBENCH FOR MOORE MACHINE
library ieee;
entity test is
end test;
architecture tt of test is
signal clk,rst,x,y,z:std_logic:='0';
signal o1,o2:std_logic;
component mo is
port(clk,rst,x,y,z:in std_logic;
o1,o2:out std_logic);
end component;
S1/
10
S3
/11
S2/
01
73

SOURCE CODE FOR MOORE MACHINE
library ieee;
entity mo is
port(clk,rst,x,y,z:in std_logic;

o1,o2:out std_logic);
end mo;
architecture amo of mo is
type st is (s0,s1,s2,s3);
signal state,nst:st;
begin
sc:process(state,x,y,z)
begin
nst<=s1;
case state is
when s0=>
nst<=s1;
when s1=>
if(x='1')then
nst<=s2;
else
nst<=s1;
end if;
when s2=>
nst<=s3;
when s3=>
if(y='0')then
nst<=s3;

74

begin
clk <= not clk after 5 ns;
rst<='1' after 5 ns;
x<='1'after 10 ns;
y<='0' after 20 ns;
z<='1' after 30 ns;
dut: mo port map(clk => clk, rst => rst, x => x, y => y,z=>z,o1=>o1,o2=>o2);
end tt;

75

elsif(z='0')then
nst<=s2;
else
nst<=s0;
end if;
end case;
end process sc;
sr:process(rst,clk)
begin
if(rst='0')then
state<=s0;
elsif(clk'event and clk='1')then
state<=nst;
end if;
end process sr;
sd:process(state,x,y,z)
begin
case state is
when s0=>
o1<='0';
o2<='0';
when s1=>
o1<='1';
o2<='0';
when s2=>
o1<='0';
o2<='1';
when s3=>
if(y='0')then
o1<='1';
o2<='1';
76

OUTPUT WAVE FORM (MOORE MACHINE)

77

elsif (z='0')then
o1<='0';
o2<='1';
else
o1<='0';
o2<='0';
end if;
end case;
end process sd;
end amo;

RESULT
Thus the VHDL code for FSM Mealy and Moore machine using image software
has been executed and verified.
78

Applied Rec GCT

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