1

Design for Test

Wen Ching Wu
STC/ITRI
(03) 591-3488
wcwuitri.org.tw
90.09.28
NTHU_DTC
P.2
Outline
Basic Concept of Testing
Testability Analysis and Fixing
DfT Flow for Digital Circuits
DfT for Mixed-Signal Circuits
Summary
2
P.3
Validation, Verification, Testing and Diagnosis
! Design Verification: Ascertain the design perform its specified
behavior
! Testing: Exercise the system and analyze the response to
ascertain whether it behaves correctly
! Diagnosis: To locate the cause of misbehavior after the
incorrect behavior is detected
P.4
Testing
" Testing is a process of sorting DUTs to determine their
acceptability
DUT Response Stimulus
Pass
Fail

Bin sorting
Bin sorting
Application of
stimulus
1udgement of
response
Decision
Best
Better
Good
...
Power consumption
Linearity
Dynamic range
...
Quality: Defective parts per million (DPM)
Over-killing
Missing
3
P.5
Good
Faulty
Pass
Fail Good/Fail
Faulty/Pass
Over-killing
Missing
Over-killing v.s. Missing
Yield
FC
DL
P.6
Fault Coverage v.s. Test Coverage
FC =

#of detected faults
#of total faults
TC =

#of detected faults
#of total faults - #of untestable faults
G Redundant faults
G Design untestable faults
Unused outputs, constant inputs, floating inputs,
non-scan registers, blocking faults due to them.
G ATPG untestable faults
Test mode, scan enable, clock generation circuit,
blocking faults due to them
Untestable Faults:
4
P.7
The Infamous Design/Test Wall
Test after design
Functionally correct!
We're done!
Oh no!
What does this chip do?!
Design Engineering
Test Engineering
P.8
Goals and Roles of DfT
Goals
Quality: a high degree of confidence during testing
Cost-to-Test: efficiently and economically measuring coverage
Time-to-Volume: test automation for product manufacturing
Current Roles
DFT ranks as one of the top concerns for SoC design
DFT becomes an integral part of the high level deign process
5
P.9
Cost of Time-to-Market
! ! D Delay of the product lifetime reduces revenue
! Missed opportunities for short stagnation time
! Moores Law: IC gate counts double every 18 months
4% more gates every month
Stagnation Decline
Time
Growth Stagnation Decline
$
Sales
Investment
Cumulative profit
Delay in
reaching
market
Time
Growth
Stagnation Decline
$
Sales
Investment
Cumulative profit
P.10
Evaluating Mixed-Signal DfT/BIST
! Evaluating criteria
! Silicon area & pins
! Fault coverage
! Design impact (performance, complexity, schedule,)
! Test time
! Test yield impact
! Re-usability
6
P.11
DfT Tools for Semiconductor Devices
Note: Advantest, Agilent, Credence, IMS, Schlumberger, Teradyne
Rick Nelson, 'DFT Lets ATE Work Magic, Test & Measurement World, May 2001
,zqpy
[(}|
,;q(}|;z
,$,
|z,||;};|y
}y,;,
,|[( |z(,;y
-,z
;,z;|;z
,$,
,z
;,z;|;z
[z_;z
|$|
zqz;y
|$|
;z,-
,;_}
|$|
(|jz;
[zv;zz
|$|
,z;z
|$|
|z,|z;
zq(}|;z
(v;;|(} |z,|)
,v|! $y,|zq,
LTX
Teradyne
,,zzz [z,;_ $y,|zq, O O O
[;_z} $y,|zq,
[}(zzz |zzjz}z_y O O O O O O O
ADC
DAC
PLL
(zz,y, |z,|w;z O O O O, note
$ V;;|(} |z,| [;v;,;z
[z_;zV;,;z O O O O PLL O
z|z; (;pj;z, O O O O O o O
[;zv;, O
SynaptiCAD
Synopsys O O O O
$y|z,| |zzjz}z_;z, o O O O O O O
P.12
Scan
MUX-D Scan Flip-Flop (MDSFF) Scan Design for Sequential Circuit
D
D
Q
clk
SDI
SE
clk
SDO
Q
0
1
Combinational Logic

PI
PO

SDI
SE
SDO
clk
TM
Q. How about partial scan?
7
P.13
ATE v.s. BIST
Bandwidth (data transfer)
Overall Timing Accuracy(OTA)
At speed
Test time
SoC test
High number of internal functions
High-speed internal signals
Problems extend to system level
Cost of multi-function testing in one ATE soars
Over 1/3 of engineering costs: test development and debug
Built In Self Test
P.14
Scan-Based BIST Architecture
Primary
Inputs
Scanned Circuit
Under Test
BIST Controller
Pattern
Generator
Bist_on
Bist_done
Response
Analyzer
Primary
Outputs
SDO
SDI, TM, SE
MUX
Pass/Fail
8
P.15
Random Pattern Generator(RPG)

set
1
2 3
111
110
011
100
010
001
101
111
Q. Why not start from all zero ?
Linear Feedback Shift Register(LFSR)
P.16
Divider Polynomial: P(x) = x
5
+ x
4
+ x
2
+ 1
Input Output
+
3 4 5
+
1 2
+
Response Analyzer
Prob. of fault aliasing (missing faults) = 1 / 2
n
where n is the number of Flip-Flops
Input Output
+
3 4
+
1 2
+ +
In1 In2 In3 In4
Multiple Input Signature Register(MISR)
9
P.17
Improvement of Fault Coverage
FC
100%
?
Test point insertion
With ATPG pattern
10~30 of faults are typically
random pattern resistant
#Patterns
P.18
Testability Analysis and Fixing
Combinational
Logic
D Q
clk
D Q

Hard to control
to 1
A N D
10
P.19
Testability Analysis and Fixing
G RTL Coding Rules for Test
G RTL Coding and Fixing for Test
G Gate-Level Netlist Fixing for Test
P.20
DfT Violations
V01-Combinational Loop
V02-Clock as Data
V03-Bi-Direction
V04-Tri-State Buffer
V05-Latch
V06-Preset or Clear
V07-Unresolved Clock
V08-Multiple Path from Clock
V09-Different Clock Phases
V10-Clock Used as Output
V11-Constant or Floating
Inputs of Modules
V12-Incomplete Assignment
11
P.21
Unresolved Clock
SDI
D Q
D Q

sela
selb
SE
clk2
SDO
clk1
D Q
D Q

sela
selb
SE
clk2
SDI
SDO
clk1

TM
Asynchronous Clock or Uncontrollable Clock
P.22
Combinational
Logic
D Q
preset/clear
SDI
Data
clk
SE

SDO
D Q
Unexpected Preset or Clear
Combinational
Logic
D Q
preset/clear
SDI
Data
clk
SE

SDO
D Q
TM
12
P.23
Combinational Loop
c b
a
TM
a
b
c
Eault
Propagation
Eault
Propagation
a
b c
TM
P.24
Clock as Data
Combinational
Logic
D Q Data
clk
Combinational
Logic
D Q Data
clk
TM
13
P.25
Combinational
Logic
D Q
Data as Clock
clk
Combinational
Logic
D Q
TM

Note: If you do not fix this violation,

the flip-flop can not be scanned.
P.26
RTL Coding and Fixing for Test
! Y.1.Chang, K.L.Luo and W.C.Wu,
~Code Fixing for Improvement of Fault Coverage,
12th VLSI/CAD Symposium, 2001
14
P.27
Pre-Process
Flow Chart
DfT Process
Post-Process
DfT Flow
P.28
! Checking list
! Constrains
! IO PAD insertion
! Verification methods for function and timing
! Clock domains
! Shared IO for scan
!
! Core_BIST
! Memory BIST
Pre-Process(1/3)
15
P.29
Combinational
Logic
D Q
clk
Testability Analysis in RTL Code
D Q

Combinational
Logic
D Q
clk
D Q
TM
Pre-Process(2/3)
P.30
Scan Replacement in Synthesis
(Timing and Area Optimization)

Combinational
Logic
D Q
clk
D Q
TM

Combinational
Logic
D Q
clk
TM
D Q

SE
Pre-Process(3/3)
16
P.31
DfT Flow Chart(1/2)
Library Setup
Testability
Report
Gate-Level Netlist
Testability Analysis
Fixing by DfT tool
or by manual
Yes
DfT Flow
Fix DfT Rule
Violations?
No
P.32
Clock Domain
and DfT Plan
Scan Select
Scan Synthesis
ATPG and Pattern Translation
Scan Number
and Scan Chain
Scan-Ready
Netlist
Test Patterns
End of DfT Flow
Full-Scan Verification
DfT Flow Chart(2/2)
17
P.33

Combinational
Logic
D Q
clk
TM
D Q

Fixing in the Gate-Level Netlist

(Critical DfT Violation)
SE
Clear

Combinational
Logic
D Q
clk
TM
D Q

SE
Clear
DfT Process(1/2)
P.34
Scan Select and Scan Synthesis

Combinational
Logic
D Q
clk
TM
D Q

SE

Combinational
Logic
D Q
clk
TM
D Q

SE
SDI
SDO
DfT Process(2/2)
18
P.35
Post-Process
! Place
! Scan Chain Optimizion
! Clock Tree / Scan Enable Synthesis
! Routing
! RC Extraction
! Delay Calculation
! Fixing for timing
! Test Pattern Re-generation
! Function Verification
! Test Pattern Verification
P.36
Scan Chain Optimization
! Scan chain reordering
! Reorder the scan chains to reducing their wire lengths
! The placement is remain unchanged
! There might be hold time violations after scan chain reordering
! Make sure that the new chains are routable
,zz z;
,zz j ,zz j
,zz z;
19
P.37
BeIore Scan Insert Scan Overhead
Area 12,886,100 13,604,310 5.50
Gate Counts 746k 787k 5.50
Critical Path Delay (Include Setup Time)
clk Domain 14.50ns 14.97ns 3.24
rxclk Domain 13.15ns 13.61ns 3.50
txclk Domain 15.63ns 16.09ns 2.94
Unit Area: NAND2X1 = 17.28
! Overhead
! Over spec. design
! 0.5~0.6 ns 0.1~0.2 ns
Case I Study
P.38
Case II Study
73.16%
Add OB2
(Gated Clock)
92.23%
Bi-Direction
75.46% 73.95%
C-Loop
75.76% 75.60% 74.16%
Add OB1
(Reset)
91.81%
Latch
84.39% 80.41% 77.60%
Tri-State Bus
87.09% 84.31% 77.56%
Tools Default Fix
Our Fix Tools Fix
20
P.39
Case III Study
Before Optimization
Wire length of scan chain: 1 0.2 (case dependent)
After Optimization
P.40
Reconfiguration
Isolation
! Most used currently (Bypass)
! Challenge
! Switch (multiplexer) in signal path (Loading, Degradation)
Analog
Function
Block 1
Analog
Function
Block 2
SW1 SW2 SW3 SW4
S.J.Chang
Analog
Function
Block 1
Analog
Function
Block 2
SW1 SW2 SW3 SW4
Analog
Function
Block 1
Analog
Function
Block 2
SW1 SW2 SW3 SW4
! Normal
! Test functional block 1
! Test functional block 2
21
P.41
Reconfiguration
DfT for Switched Capacitor Filter |Soma, VTS`94]
! In test mode, bypass a filter stage by converting it to an
all-pass gain stage
! Open grounding switches
! Close signal path switches
! Operate in continuous fashion, not in sampled-data mode

,,

=
Bandwidth
Controllability
Observability
P.42
Reconfiguration
SW-OPAMP |Huertas, VTS`96]
! SW-OPAMP
! With additional inputs: Test, VT
! = 0: regular opamp
! = 1: unit buffer
! VT is connected to the output of
previous stage
! In test mode
! = 0 for stage under test
! = 1 for others
22
P.43
Reconfiguration
Oscillation Test (1/2) |Kaminska, VTS`96]
! In test model
! Partitioning CUT into functional building blocks
! Converting each building block to an oscillator
! Shift poles on the imaginary axis (natural oscillation)
! Adding a feedback loop to the CUT
! Combine various building blocks to forman oscillator
! Defects cause deviations in oscillation frequency
P.44
Reconfiguration
Oscillation Test (2/2)
! Example
! Continuous-time
state-variable filter
! Excellent for hard and large deviation faults
! Adopted by Fluence
! Challenges
! No universal rules to transfer DUT into oscillator
! No trivial relationship between the oscillation frequency and the
specification under test
! Soft faults, small deviation faults
23
P.45
Test Point Insertion
IDDQ / IDDT Test
! Insert current sensor between CUT
and Vdd (Vss)
! Use current signature to make
pass/fail decision
! Compare to:
! DC threshold (IDDQ) [Stopjakova, 96]
! Expected spectrum (IDDT) [Lopez, 97]
! Challenges
! Resistance in Vdd Path
! Aliasing
P.46
Test Point Insertion
Output Response Compaction |Bertrand, EDTC`97]
! Summing or weighted-summing the internal node voltage
or branch current
! During Testing
! C=0, output is initialized to 0
! C=1, performs the integration function
! The analog signature provided by the =RC of the integrator
! Challenge -- Aliasing
24
P.47
Test Point Insertion
Analog Checksum |Chatterjee, D&T`96]
! Smart output response compaction for linear analog
circuit
! Reconstruct the input signal
! The signature (analog checksum) is the difference
between the input stimuli and reconstruct signal
! Checksum=0, Fault free
! Checksum 0, Faulty
! Example
! Biquadratic Filter
P.48
Test Point Insertion
Sub-Band Filtering (1/2) |Abraham, ITC`99]
! Reduce aliasing probability of integrator scheme by
analyzing signature for each frequency band
! Nonlinear faults
! Signature Analysis Scheme
25
P.49
Test Point Insertion
Sub-Band Filtering (2/2)
! Recursive Architecture of Filter Banks
! Pros -- More immune from fault aliasing problems
! Cons -- Requires on-chip ADC (digitized output)
Sub-Band Filtering
Wavelet
P.50
DSP-Based Analog Test - Present
! Perform signal synthesis & response analysis in digital
domain
! Pros: single setup for multiple types of tests
! Cons: limited measurement resolution
26
P.51
Functional BIST
DSP Based BIST
! On-chip software tester
! On-chip ADC and DAC for signal generation and response
acquisition
! On-chip programmable cores for signal synthesis and response
analysis
! More immune from external noise
P.52
Functional BIST
ADC & DAC BIST (1/3) |K.T. Cheng, DATE`2000]
! Many BIST schemes for ADC and DAC were proposed previously
! Need both on-chip ADC and DAC (spec. performance)
! Vulnerable to analog imperfections
! One BIST strategy does not require the existence of both on-chip
ADC and DAC
27
P.53
Functional BIST
PLL BIST (Logic Vision) (1/2) |Sunter, ITC '99]
! Applying a phase shift ( or M ) in the input of PLL
! Measure the oscillation frequency deviation of VCO output
! Open loop gain

=
(M is number of cycles of
input phase shift )
Open loop gain
Freq / Phase
P.54
Functional BIST
PLL BIST (Logic Vision) (2/2)
A
B
Q
A
B
Q
A
B
Q
Error Count: 0 E/2 E
! The error counter has a maximum
value E
! Every E cycles, the counter output
is latched and then reset
! Cumulative Distribution Function
1itter
Mapping point:
(1) Mean(50)
(2) 1 (16, 84)
28
P.55
Functional BIST
PLL BIST (Fluence) (1/2)
! Implement 2X ring oscillators
! Control the 2X ring oscillators frequency
Period P t
1
-t
2

M* P
1
-N*P
2
(

P
1
-P
2
) * 6
t

P
Signal
1 2 3 4 5 6
P

Osc. 1
Osc. 2 1 2 3 4 5 6
P

CoIncIdence PoInt
P.56
Functional BIST
PLL BIST (Fluence) (2/2)
PLL Out
Jitter Measurement
PLL Out
PLL In
Delay Measurement
Trigger Osc. 2
Trigger Osc. 1
29
P.57
Fault-Based BIST
Histogram Based BIST (HABIST) (1/3) (Fluence)
! Histogram (used to test ADC & DAC)
! A statistical number of samples of the input signa are taken and
stored as a record
! The frequency of code occurrence in the record is plotted as a
function of code
t
Code
Bin
255
0
1
Code
Bin
255
0
1
t
t
Code
Bin
255
127
Code
Bin
255
t
127
Code
Number of
Occurence
Number of
Occurence
Code
0 255
0 255
[Frisch, ITC97]
P.58
Fault-Based BIST
Histogram Based BIST (HABIST) (2/3)
! Block diagram
of HABIST
implementation
Stimulus
Vectors
(Optional)
Histogram
Generator
D/A
(Optional)
CUT
S&H,
A/D
Difference
Expected
Histogram
Compress,
Encode
Signature of
Circuit Under Test
! Signature
Analysis
30
P.59
Fault-Based BIST
Pseudo-Random BIST |K.T. Cheng, ICCAD`95]
! Digital white noise stimulus
! Using the cross-correlation
function as a signature to verify
the transfer function of CUT
P.60
Fault-Based BIST
Oscillation BIST (OBIST) (Opmaxx, Fluence)
! Translate CUT into
oscillator
! Built-in frequency
counter
! The di gi tal output val ue
is given by
Analog
CUT
Added
circuitry
Oscillator
Built-in
Frequency
Counter
B
1
B
2
B
M
LCD
(Level -Crossi ng
Detector)
Counter
Reset

enable

=
[Kaminsak, ITC97]
31
P.61
Outline
Basic Concept of Testing
Testability Analysis and Fixing
DfT Flow for Digital Circuits
DfT for Mixed-Signal Circuits
Summary
P.62
Potential DfT Strategies
! Reduce redundancy
! Reduce probabilities of undetectable (or hard to
detected) faults at the layout level
! Improve test access (controllability and observability)
! Reduce demands on production test equipment
! Increase resolution of parameter measurement
! Provide support for on-line monitoring and diagnostics
32
P.63
General DfT Guidelines (1/2)
! Incorporate DfT features at a early design stage
! Incorporated circuits must be testable
! Obey the rules of ad-hoc and scan when you use them
! Partition the circuit in simple and ease to treat macro
blocks
! Disable feedback paths
! Use digital test access port to select test mode
P.64
General DfT Guidelines (2/2)
! Separate analog and digital circuits (include the built-in
test circuits)
! If possible, BIST structures have to be based on
reconfiguration of already existing cells
! Consider the limitation (speed, accuracy, memory, ) of
ATE
! Eliminate difficult to detect faults by layout optimization
! If possible, incorporate digital circuit rather than analog
one when using DfT techniques
33
P.65
DfT Strategies
! Layout level
! Decrease the fault probability
! Increase the fault detectability
! Schematic, Block levels
! Classify fault difficult to detect
! Add/change circuitry to increase detectability
! Structures to support specific measurements (Iddx, Reconfiguration)
! Test access techniques ( IEEE 1149.4 test bus)
! DSP
! Oscillation test
! BIST (Embedded ATE)
! System level
! Partition of system
! Increase controllability and observability
P.66
Summary
! DfT and testing become more and more important
! Trade-off on timing, area, test cost and quality
! Trade-off on design cycle for test and debug time
! Early consideration on DfT reduces much test cost.
! Analog testing is more difficult than digital testing, because of
the continuous range of analog circuit parameters, and the lack of
well accepted fault models
V. D. Agrawal in Essentials of Electronic Testing for Digital,
Memory & Mixed-Signal VLSI Circuits, 2000
! Company with leading test technology will revenue and survive.
! DfT holds very exciting prospects
34
P.67
Acknowledgements and Reference
! Yong-Ja Chang
Section manager, STC/ITRI
! Soon-Chi Chang
Ph.D student, VLSI Testing and DFT group, NCTU
! S. K. Sunter
IC Techniques for Mixed-Signal DfT and BIST , 2000
Director, Mixed-Signal Testing, LogicVision
! ITRI Technical Report, 2000~2001, DfT team/STC/ITRI
Testable Design Guideline for Digital Circuits
Testable Design Guideline for Mixed-Signal Circuits
Memory-BIST Design Automation
0.25~0.18um DfT Flow
RTL Coding and Fixing for Test
P.68