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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO.

7, JULY 2004 1119

Digital Circuit Capacitance and Switching


Analysis for Ground Bounce in ICs
With a High-Ohmic Substrate
Mustafa Badaroglu, Student Member, IEEE, Geert Van der Plas, Member, IEEE, Piet Wambacq, Member, IEEE,
Lakshmanan Balasubramanian, Member, IEEE, Kris Tiri, Student Member, IEEE,
Ingrid Verbauwhede, Senior Member, IEEE, Stéphane Donnay, Member, IEEE, Georges G. E. Gielen, Fellow, IEEE,
and Hugo J. De Man, Fellow, IEEE

Abstract—Substrate noise is a major obstacle for mixed-signal There have been only few works addressing the generation
integration. Ground bounce is a major contributor to substrate mechanisms of substrate noise. In most cases only the propaga-
noise generation due to the resonance caused by the inductance tion mechanisms have been measured. A good overview of the
and the admittance that consists of the on-chip dig-
ital circuit capacitance of the MOS transistors, the decoupling, and
substrate noise models and experiments is given in [1]. Most
the parasitics arising from the interconnect. In this paper, we ad- substrate noise experiments reported in the literature have been
dress: 1) the dependence of the admittance on the dif- carried out on test chips with dedicated digital substrate noise
ferent states of the circuit, the supply voltage, and the interconnect, generators [3], [4] or with small test circuits [5]. In these exper-
and 2) the computation of the total supply current with ground iments, fewer reasons have been given on how substrate noise
bounce. By using a fast and accurate macromodeling approach, is generated. In [3] and [4], only substrate contacts are used as
the admittances of several test circuits are computed
with 2%–3% error relative to the values simulated from the com-
the access ports in order to measure the noise generated from
plete SPICE level netlist, but several orders of magnitude faster in another substrate contact while the substrate is the conductive
CPU time and with 10% maximum error relative to the measure- medium in between. In [5] and [6], voltage-comparator-based
ments on a test ASIC fabricated in a 0.18- m CMOS process on a measurements are used to characterize the substrate noise gen-
high-ohmic substrate with 18

cm resistivity. The measurements erated from a set of parallel-connected inverters on the same
also show that this admittance mainly depends only on the connec- power line.
tivity of the gates to the supply rail rather than their connectivity
among each other. Substrate noise measurements from mixed-signal systems
provide valuable guidelines for reducing the noise generation
Index Terms—Crosstalk, decoupling, integrated circuit [7], [8]. In [7], several parallel-connected tri-state buffers with
modeling, MOS capacitors, mixed analog–digital ICs, power
different driving capabilities are operated with an internal/ex-
distribution, substrate noise, system-on-a-chip.
ternal clock in order to measure the substrate noise and to
quantify its impact on the performance of a low-noise-am-
I. INTRODUCTION plifier (LNA). The outputs of these tri-state buffers have
binary-weighted loads to the substrate. The measurements
W ITH THE increase of the complexity and switching
speed of digital circuits and of the resolution require-
ments of analog circuits, substrate noise will become more and
show that the substrate noise is scaling with the number of
switching buffers. Also it is shown that the substrate noise
more a major obstacle for single-chip integration of the digital spectrum bandwidth decreases as the rise/fall time of the output
and analog circuits together [1], [2]. switching increases. However, this work only considers the
capacitive coupling of the outputs, which are connected to the
relatively large junction capacitances. Since in the experiments
Manuscript received November 1, 2003; revised January 16, 2004. these capacitances are in the picofarad range, the substrate noise
M. Badaroglu is with IMEC/DESICS, B-3001 Leuven, Belgium, and also can be dominated by the capacitive coupling, which is mostly
with the Department of Elektrotechniek, Katholieke Universiteit Leuven, the case in I/O buffers. In this case, the noise can be reduced
B-3001 Heverlee, Belgium (e-mail: badar@imec.be).
G. Van der Plas, P. Wambacq, and S. Donnay are with IMEC, B-3001 Leuven, by equalizing the rise and fall transitions. In reality, only a
Belgium. small portion of the digital circuitry can drive such large loads
L. Balasubramanian was with IMEC, B-3001 Leuven, Belgium. He is now simultaneously. The modeling of the transfer function from
with Nulife Semiconductor, 600018 Chennai, India.
K. Tiri is with the Department of Electrical Engineering, University of Cali- the power supply to the substrate or equivalently to the circuit
fornia, Los Angeles, CA 90095 USA. ground as well as the modeling of the power supply become
I. Verbauwhede is with the Katholieke Universiteit Leuven, B-3001 Heverlee, more crucial in order to derive the conditions of the resonance
Belgium, and also with the University of California, Los Angeles, CA 90095
USA.
and the amount of noise that flows between the circuit, the
G. G. E. Gielen is with the Department of Elektrotechniek, Katholieke Uni- power supply, and the substrate. This will be addressed in this
versiteit Leuven, B-3001 Heverlee, Belgium. paper.
H. J. De Man is with IMEC, B-3001 Leuven, Belgium, and also with the De- The measurements up to now have also lacked an important
partment of Elektrotechniek, Katholieke Universiteit Leuven, B-3001 Heverlee,
Belgium. insight, which is how to scale the measurement results from
Digital Object Identifier 10.1109/JSSC.2004.829393 these small circuits to large and complex digital systems. The
0018-9200/04$20.00 © 2004 IEEE

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1120 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

coupling from the substrate contacts of the power rail is more


dominant in the noise generation for large-scale integrated
circuits [9]. Therefore, careful selection of the test circuits
is necessary to study the scalability aspects of the measured
substrate noise to large and complex digital systems. For this
purpose, dedicated simple test circuits are fabricated in a
0.18- m six-metal CMOS process on a high-ohmic substrate
with a resistivity of 18 cm in order to: 1) demonstrate the
state-dependent transfer functions; 2) verify that these transfer
functions are topology-independent; and 3) show that these
transfer functions as well as the supply current can be linearly
superposed in order to form the models of large digital systems
[10]. Topology-independent transfer functions indicate that
modeling only the connectivity to the supply network is more
important rather than the connectivity between the gates. The
results of these measurements will give insight and prove the
assumptions in the modeling efforts of substrate noise coupling.
For the demonstration of the experimental results a high-ohmic
substrate has been used. The choice of the substrate is mostly Fig. 1. Chip-level ground bounce generation macromodel.
driven by the cost, application, and isolation requirements. The
bulk-type (high-ohmic) substrates are less expensive and good is also taken into account as a part of the capacitance
for substrate noise isolation but have less latchup immunity [12]. models the power-supply current used by the gate
in comparison to EPI-type substrates. These substrates are during switching.
mostly preferred for the analog circuits and the DRAM devices. Assuming that all gates under consideration belong to a single
Due to decreasing supply voltages, the availability of graded power domain (therefore package impedance is higher than the
doping profiles, and shallow trench isolation (STI), the latchup impedance of the on-chip power grid), it is possible to combine
immunity of bulk-type substrates has increased in recent years. the admittances of each gate in the same
Therefore, high-ohmic substrates are currently a valuable power network to a single admittance (Fig. 1). Whenever the
alternative to EPI-type substrates for high-performance logic chip is partitioned into different supply regions, they each have
ICs. their own admittance. For a large mixed-mode system-on-chip
This paper is organized as follows. In Section II, we introduce (SoC) with multiple supplies, a modeling approach to estimate
a lumped model for ground bounce and briefly describe its de- the substrate noise frequency spectrum is described in [8]. As
pendencies. In Section III, the impact of ground bounce on the will be illustrated later, the effective admittance will be the same
supply current is described. In Section IV, we describe the test for two different circuits, which contain the same number and
circuits used in our experiments and present the measurements. type of gates in a single power region. It will also be shown
In Section V, conclusions are given. that these circuits at different supply voltages have the same
admittance.
II. CHIP-LEVEL GROUND BOUNCE MACROMODEL The contribution of the substrate in the overall
is negligible for the high-ohmic substrates. For a two-input
Fig. 1 shows the ground bounce generation macromodel for NAND gate (NAND2) in a 0.18- m CMOS technology on a
a network of digital gates on a bulk substrate. In this model, the high-ohmic substrate with 18 cm resistivity. Fig. 2 shows
supply line inductance and its series resistance are represented due to the substrate as well as due to the circuit
by and , respectively. Additional on-chip decoupling and the substrate. The latter is clearly dominant. For the plot
capacitance and its series damping resistance are represented by shown in the figure, the logic state of the NAND2 gate is AB
and , respectively. For each gate, the circuit admittance (both inputs are logic level LOW). There is no resonance
is represented by a capacitance in series with a parallel behavior in the figure since the NAND2 gate is connected
combination of a resistance and a capacitance . The to an ideal 1.8-V power supply with no package parasitics.
series resistance from the contact to the substrate is The substrate netlist is extracted by using SubstrateStorm
represented by . The capacitance due to the reverse-biased [13]. The figure shows that the substrate can be neglected in
n-well junction diode and the resistive path are represented the overall admittance. The results are repeated
by and , respectively. A resistive network models the also for other digital gates without loss of generality. Besides
coupling through the bulk. By taking the substrate into account, this impedance division in the substrate, the high ratio of the
the well capacitance and the substrate contact resistance total drain-source current to the substrate current
are computed as a part of the admittance. For through the nMOS transistor further justifies the assumption of
lightly doped (bulk-type) substrates with resistivities around neglecting the substrate in . The effect from the pMOS
10–20 cm, this resistive simplification of the substrate is devices inside the n-well is negligible due to the shielding of
valid up to 5–10 GHz [11]. This frequency increases further the reverse-biased n-well. The ratio is around 10.47 on
beyond 10 GHz in heavily doped (EPI-type) substrates. The average for this technology due to smaller drain/source area as
capacitive coupling from the interconnect into the substrate a result of 45 poly lines and due to STI (which reduces the

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BADAROGLU et al.: DIGITAL CIRCUIT CAPACITANCE AND SWITCHING ANALYSIS FOR GROUND BOUNCE 1121

Fig. 2. Contribution of the substrate in the V dd 0


V ss admittance
(Y 11(j! )) of a NAND2 gate implemented in a 0.18-m CMOS technology
1
on a high-ohmic substrate with 18-
cm resistivity. The logic state of the
NAND2 gate is AB = 00 (both inputs are logic level LOW).

Fig. 4. (a) Relative difference (in %) in the magnitude value of the NAND2
V dd 0 V ss admittance for each logic state (jY 11(j!)Statej) with respect
Fig. 3. The magnitude and phase of the average admittance Y 11(j! ), to the one obtained by averaging over the logic states (jY 11(j! )Averagej).
simulated in SPICE, over the logic states for the NAND2 gate in a 0.18-m (b) NAND2 circuit capacitance (Cc) versus supply voltage for different logic
CMOS technology including its substrate model as a function of frequency. states.

drain-bulk capacitances). This ratio tends to decrease slightly ficiency. On the other hand, a change at the node voltages will
with technology scaling due to the increase in doping level in cause deviations in the linear behavior especially in the admit-
the wells with technology scaling, which increases the unit tance . The significance of these deviations as well as
area/perimeter junction capacitance slightly. On the other hand, the switched capacitance between and can be reduced
the resistive ratio tends to increase much faster due to the by adding fixed decoupling capacitance between the supplies at
increase in doping level in the wells with technology scaling, the expense of extra chip area [9], [14].
which decreases the resistance from the bulk to the substrate The most important change is caused by a change in the
contact. Therefore, the substrate current going to the sensitive pull-up and pull-down current paths as a result of different input
circuits gets much smaller for more advanced technologies. logic states. A gate has characteristics that depend on the state
We compute the voltage swing at the node with the of the circuit [15]. For each logic state, we simulate a different
supply current as the excitation to an equivalent RLC net- complex admittance and then compute an average complex ad-
work of Fig. 1. This equivalent RLC network is constructed by mittance by summing these complex admittances weighted by
summing the individual frequency-domain admit- the probability of occurrence of each logic state. Fig. 3 shows
tances of each gate (Fig. 1) and then converting the overall ad- the magnitude and phase of the average admittance ,
mittance into an equivalent parallel RLC network. As it will be simulated in SPICE, over the logic states for the NAND2 gate in
illustrated later using experimental results, the effective admit- the above technology process including its substrate model as a
tance will be the same for two different circuits, which contain function of frequency. For the average admittance shown in the
the same number and type of gates in a single power region. figure, each logic state has an equal probability of occurrence.
Fig. 4(a) shows the percentage difference in the magnitude
A. Logic-State Dependence of the Circuit Admittance value of the NAND2 admittance for
Linear substrate models are preferable in an effort to decouple each logic state with respect to the one obtained by averaging
it from the nonlinear behavior of the circuits for simulation ef- over the logic states. For medium-sized circuits (from 1 Kgate

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1122 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

TABLE I
MEAN VALUES OF THE MACROMODEL ELEMENTS, THE VARIATION OF THE
CIRCUIT CAPACITANCE AND RESONANCE FREQUENCY OF THE GATES IN A
0.18-m CMOS PROCESS ON A HIGH-OHMIC SUBSTRATE

to 1 Mgate), the ground bounce resonance occurs between


10 MHz and 2 GHz [8]. In this frequency region, there is a
maximum variation of 45% over the mean value of ,
which results in a 25% variation on the resonance frequency
with no extra on-chip decoupling. For this gate, the input(s) has
(have) been connected to the positive power supply for a logic
level HIGH at the input(s), and to ground for a logic level LOW
at the input(s) when both input and load share the same power
network. The values of (computed using plots) for
the NAND2 gate are 9.88, 9.50, 6.59, and 10.73 fF for the logic
states 00, 01, 10, and 11, respectively [Fig. 4(b)]. By omitting
the influence of the interconnect capacitances inside the gate,
these values become 9.44, 8.49, 5.54, and 9.42 fF, respectively.
Note that interconnect capacitance is also logic-state-depen-
dent. For example, the effective capacitance seen between the
two interconnects (including the supply line) is zero when
these two interconnects are at the same potential, which can
be set by a logic state of the gate. The interconnect will be
a more dominant contributor to for large digital circuits
with dense interconnects and a complex power grid and also
for future technologies with smaller devices. Table I lists for Fig. 5. Logic-state-dependent capacitance network in the inverter. (a) For input
different logic gates the average values of the elements together LOW and output HIGH. (b) For input HIGH and output LOW.
as well as the maximum (max-min) and standard variations
(normalized to the mean value) of the circuit capacitance respectively. These capacitances are nonlinear and their value
and of the resonance frequency with 0.1-nH inductance depends on the operating region of the transistor. is
nH . The compilation of element values given in the capacitance between the gate and the bulk. and
the table represents values assuming that all logic states have are the junction (diffusion) bottom-plate and sidewall
equal probabilities. In fact, it is possible to take into account capacitances due to the reverse-biased pn-junctions formed
the probability of each state, which can be simulated by using at the source-bulk (well) and drain-bulk (well) boundaries,
a switching activity simulator [8], and then these probabilities respectively. This capacitance decreases when the reverse-bias
can be used to compute the expected value of a particular voltage across the junction increases. The resistance
element as well as its variation. The variations for a high-ohmic is the resistance due to the channel and parasitic drain/source
technology are quite high due to the small admittance values resistance when the p(n)MOS transistor is ON. The resistance
to the backside node, as discussed previously. To reduce the models the resistance seen from the bulk of the tran-
variations on the circuit capacitance, one can employ a set of sistor to the well contact in the p(n)MOS transistor. is the
digital gates with less variability or increase the amount of sidewall capacitance of the n-well.
decoupling. The capacitance values of the pMOS transistor are larger than
For example, in the case of the inverter, the capacitance the ones of the nMOS transistor since the pMOS is designed
network due to the two different logic states at the input is given larger than the nMOS in order to compensate the lower mobility
in Fig. 5. The circuit capacitance is dominated by the junction, of the carriers in the pMOS for the performance and the dc op-
channel, and overlap capacitances. and erating point of the gate. Fig. 6 shows the simplification of the
correspond to the drain and the source overlap capacitance capacitance network from Fig. 5 for the two logic states of the
beside the gate, respectively. and corre- inverter. When the input is LOW/HIGH, the gate capacitance
spond to the capacitances from the gate to the source and drain, is split into equal proportions to the source

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BADAROGLU et al.: DIGITAL CIRCUIT CAPACITANCE AND SWITCHING ANALYSIS FOR GROUND BOUNCE 1123

Fig. 7. (Non)-Switching cells and their decoupling between V dd and V ss


rails.

III. SUPPLY CURRENT ANALYSIS WITH GROUND BOUNCE


Fig. 6. Simplification of the capacitance network of the inverter for the two
different logic states.
In large digital circuits, high peaks and fast slew rates on
the supply current create power-supply noise (so-called
and drain . The comparison of the two noise) in the supply network due to the RLC network formed
logic states gives by the on-chip capacitance between and , the package
inductance and the series resistance in the supply connection
(Fig. 7). There is also resistive power-supply noise (so-called
IR drop) due to the series resistance of the supply line. In a
p-type substrate, this supply noise couples into the substrate re-
(1)
sistively via the substrate contacts from and capacitively
from via the n-well junction capacitance. The noise in the
Equation (1) shows that the circuit capacitance will take power supply consists of two parts: common-mode and differ-
its maximum value when the input is LOW since the junction ential-mode noise.
capacitances and are smaller than the sum of the
Common-mode noise is caused by the imbalance between
oxide and gate-source overlap capacitances. Eventually, the ca-
supply current and ground return current due to the sig-
pacitances attain their minimum value when the
naling current between circuits of different power domains.
input is LOW/HIGH since the reverse-bias voltage across the
Common-mode noise will not affect the operation of local
junction becomes .
circuits (that have inputs coming from a local circuit and that
have its power and ground connected to the internal power
B. Supply Voltage Dependence of the Circuit Admittance ring). On the other hand, it changes the signal levels used for
Fig. 4(b) shows the simulated circuit capacitance of a NAND2 inter-chip communication and will increase the electromagnetic
gate as a function of the supply voltage. The circuit admittance interference (EMI) due to sharp changes on the power and
in a nonswitching gate does not change significantly over the ground voltages. The timing behavior changes only for the gate,
variations of the supply voltage around its nominal value (here, which causes common-mode noise, since the supply current
1.8 V) due to ground bounce since the transistors in this gate are of that gate will be affected by unexpected shift between its
either in cutoff or in the linear region. This weak dependence of input(s) and its reference affected by common-mode noise.
the circuit admittance to the supply voltage is applicable to all Common-mode noise is defined by
static CMOS gates without loss of generality.
The supply-voltage dependence of the circuit admittance for
(2)
an inverter for instance can be explained as follows. When the
inverter input is LOW, the following is obtained: for nMOS
, and for pMOS , The voltage transients and are the bounces
. When the input is HIGH, the following is ob- on the ground rail and the positive supply rail, respectively.
tained: for nMOS , and for pMOS They are measured on the die, referred to external power supply,
, . Around the nominal values of the which is assumed to be a clean one. Common-mode noise is
supply voltage, the change in the circuit capacitance (Fig. 1) negligible if the input to the circuit is coming from a driver con-
is only due to the junction capacitances (when the input is nected to the same supply line of the circuit.
LOW) and (when the input is HIGH). These two capaci- The second component of the power-supply noise, differen-
tances change by a sublinear dependence with respect to the bias tial-mode noise, is caused by the oscillations of the damped LC
across the junction (in this case, ) [16], therefore, resulting tank formed between the circuit capacitance and the supply par-
in a small change in the circuit capacitance . On the other asitics (Fig. 7). The initial energy of differential-mode noise is
hand, a sudden increase is observed in the circuit capacitance generated from the charge sharing in the switching capacitance
when the supply voltage is around when the input ( and in Fig. 7) and the nonswitching capacitance
is HIGH since the gate-bulk capacitance is becoming zero and ( and in Fig. 7). The equivalent switching ca-
the charge is evenly divided between the source and drain. In this pacitance is represented by , which is the average capaci-
case, the circuit capacitance increases by . tance computed using the times when the capacitance or
Similar results are applicable when the input is LOW. In this is (dis)charged. We define the equivalent nonswitching
case, the circuit capacitance increases by . capacitance of the circuit ( ) in a similar way using the

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1124 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

Fig. 9. Simulated common/differential-mode power-supply noise versus the


number of simultaneously switching inverters with the supply voltage as a
parameter (PP=2: half of the difference between maximum and minimum
values of the noise voltage). All inverters in the network are switching
(0.18-m CMOS). The inputs are external (from independent voltage sources
without any package parasitics) while the inverters are connected to a supply
line with Lp = Lg = 1 nH and Rp = Rg = 0:1
.

The common-mode noise voltage is independent of the


number of nonswitching gates and directly proportional to the
number of identical switching gates. Equalizing the number of
falling-edge and rising-edge inputs has a cancellation impact
on the common-mode noise. Almost linear proportionality
between the peak-to-peak value of common-mode noise and the
number of switching gates is shown in Fig. 9. The saturation of
Fig. 8. Simulated waveforms of (a) V dd=V ss noise and (b) common/diff-
common-mode noise occurs around the supply voltage levels
erential-mode power-supply noise for a circuit having 20 switching inverters due to the fact that the difference between its input(s) and its
with rising inputs and 100 nonswitching inverters (0.18-m CMOS process). reference is decreasing, therefore, decreasing the amplitude of
The inputs are external (from independent voltage sources without any package the supply current generated by the gate causing common-mode
parasitics) while the inverters are connected to a supply line with Lp = Lg = 1
nH and Rp = Rg = 0:1
. noise. When the number of inverters is relatively small, the lin-
earity is also degraded since the damping of the circuit, which
also scales down by the number of inverters, dominates the
durations when the nonswitching circuits have a HIGH (LOW)
fixed damping of the power-supply line. In a large digital circuit
output. Here the term is the switching activity factor that is de-
where most of the signaling occurs within the core cells sharing
fined as the ratio of the equivalent switching circuit capacitance
the same supply region, the common-mode noise component of
to the total circuit capacitance . The voltage difference across
the power-supply noise can be ignored. Since differential-mode
the switching capacitance is transferred back and forth into the
noise changes the supply voltage of local circuits, it can have
magnetic energy in the parasitic inductance of the loop ground
a significant impact on the peak value of the supply current.
path. This process is damped by the resistors of bondwires, con-
Due to this, the linearity is not preserved for the peak value of
tacts, decoupling, wells, and the circuit. Differential-mode noise
the supply current and thus on the power-supply noise (Fig. 9).
changes the supply voltage of the local circuits, and hence, seri-
As a result, predicting supply bounce by the superposition
ously affects the timing of the circuits [17]. During this ringing,
of the bounce values caused by every individual gate is no
the waveforms on power and ground rails are 180 out of phase
longer valid. Decreasing the ratio between nonswitching and
with respect to each other. Differential-mode noise is defined by
switching gates reduces differential-mode noise. Equalizing the
(3) number of falling-edge and rising-edge inputs does not have a
cancellation impact on differential-mode noise (only a slight
Fig. 8 shows the waveforms (simulated in SPICE) of (a) change due to different supply currents for rising versus falling
noise and (b) common/differential-mode noise of a edge signals). Please note that in Fig. 9, the switching activity
circuit consisting of 120 inverters, of which 20 are switching A is maximal (100%) and all gates are driven externally to
inverters with rising inputs having 100-ps rise time and 100 are clearly demonstrate the nonlinearity.
nonswitching inverters. Further, nH The negative feedback from the ground bounce on the supply
and . Each inverter has current of the I/O buffers was previously addressed in [18]. That
m and m work only considers long-channel devices and inputs from an
for the used 0.18- m CMOS process. external source with a clean ground. In fact, it is more common

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BADAROGLU et al.: DIGITAL CIRCUIT CAPACITANCE AND SWITCHING ANALYSIS FOR GROUND BOUNCE 1125

Fig. 11. Microphotograph of the test circuits.

2) has a package ( nH, ) and has the input


from an external source with a clean supply;
3) has a package ( nH, ) and has the input
from an internal source on the same supply line with the
circuit.
In the case of no ground bounce, namely for case 1), the peak
value of the supply current due to the switching circuits can be
derived using the line derived by linear superposition with re-
spect to the number of simultaneous switching inverters [see
Fig. 10(a)]. On the other hand, for case 3) the peak value of the
supply current deviates by 20% when the number of switching
inverters is 200, which corresponds to a switching activity factor
of 0.2 (a typical value in many digital system chips today).
Above this value the deviation increases further. In the case of
a serially cascaded inverter chain, the switching activity factor
Fig. 10. (a) Supply-current peak value and (b) ground-bounce voltage is greater than 0.2, therefore the linear superpositioning is not
peak-to-peak values versus the number of simultaneous switching inverters for
a circuit in a 0.18-m CMOS process. The circuit consists of 1000 inverters applicable to this circuit when all the cells in the circuit share
and has Lb = 1 nH and Rb = 1
. P: Peak value; PP: Peak-to-peak value. the same power-supply line with the package parasitics. The
switching activity factor is typically less than 0.2 for telecom-
to have the inputs from an on-chip driver in the same power line munication circuits and state machines. In the example shown
as the switching circuit. The saturation current of a switching above, the values of the package parasitics ( nH,
inverter for a rising input is defined by ) were chosen high in order to demonstrate the worst-case
(minimum) switching activity factor. In fact, the 20% deviation
(4) occurs at a larger switching activity ratio when the values of
the package parasitics become smaller. To illustrate this, for the
where is a process- and geometry-dependent coefficient and same circuit above, we decrease the package parasitics down
is the short-channel velocity saturation coefficient, which is to ( pH, ) and keep the other parame-
between 1 and 2 [19]. is the input voltage, which may ters the same. With these parameters, the 20% deviation occurs
contain on/off-chip noise, and is the ground voltage, when the number of switching inverters is 450, namely when
which has a ground bounce component. In the case of an the switching activity factor is 0.45.
on-chip driver, the negative feedback effect is much larger than
for an external signal with a clean ground since the logic level IV. EXPERIMENTAL RESULTS
HIGH at the input is the circuit positive supply having a
supply bounce, which becomes out of phase with during A. Description of the Test Circuits
the transition. Fig. 10 shows the peak of the supply current of The above analysis of the supply current and ground bounce
the switching current and ground bounce voltages versus the has been verified experimentally with test circuits that have been
number of simultaneous switching inverters in a circuit con- fabricated in a 0.18- m six-metal CMOS process on a high-
sisting of 1000 inverters (each inverter has ohmic substrate with 18 cm resistivity. The chip micropho-
m and m) implemented in a 0.18- m tograph is shown in Fig. 11. These circuits have the following
CMOS process, having V and with characteristics.
an input rise time of 100 ps, for the following three cases when 1) Parallel connection of 16 inverters (Circuit T1 in Fig. 12):
the circuit: It is composed of inverters connected in parallel. The
1) has no package parasitics; circuit is controllable with four inputs in order to operate

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1126 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

TABLE II
MEAN VALUES OF THE V dd 0
V ss CAPACITANCE FOR THE TEST CIRCUITS
(FROM SPICE SIMULATIONS, SUPERPOSITION OF THE MACROMODELS, AND MEASUREMENTS)

Fig. 12. Schematic of the circuits T1 and T3.

Fig. 13. Schematic of the circuits T4 and L1.


the parallel combinations of one, two, four, and eight
inverters. Each set is driven by a buffer (BUF). To
surements. There is a checksum comparator circuit com-
have equal input slope at each set, each buffer output
paring the output of the data path with the expected output
is balanced with several parallel connections of a load
in order to check whether the circuit is running properly
capacitance that corresponds to the input capacitance
or not. Whenever the circuit functions correctly the signal
of the inverter m. Circuit T1 has
(FUNCOK) becomes logic level HIGH continuously, oth-
an equivalent area of 135 gates.
erwise it stays at logic level LOW.
2) Serially cascaded inverters in parallel (Circuit T3 in
Fig. 12): It is composed of serially cascaded inverters.
B. Measurements
T3 is controllable with four inputs in order to operate
the parallel combinations of one, two, four, and eight We compute the value of the admittance (Table II)
serially cascaded inverters. Each set of serially cascaded of the test circuits either by simulating the complete transistor-
inverters is driven by the buffer, which is loaded with the level (SPICE) description or by combining the macromodels
same load capacitance as in T1 in order to preserve the described in Section II. The table shows the average capacitance
same input slope as in T1. values, which are weighted by the probability of occurrence of
3) A 256-gates sequential circuit (Circuit T4 in Fig. 13): It each logic state over all logic states during the simulation time.
is composed of an 8-bit maximum-length-sequence pseu- The simulation data have been generated:
dorandom binary sequencer (PRBS) circuit in cascade 1) using all possible input switchings for the circuits T1 and
with a 4-bit comparator. The circuit generates a trigger T3;
signal (TRIGOK) in order to synchronize the measure- 2) using all 256 states of the PRBS circuit for the circuit T4;
ments. The RESETGEN module generates a synchronous 3) using only the reset state for the circuit L1 since the simu-
reset for the circuit during the first three clock cycles after lation requires a long time for the extraction of the circuit
external reset. capacitance using the complete transistor-level (SPICE)
4) A 40-Kgate telecom circuit (Circuit L1 in Fig. 13): It is netlist in order to enable the comparison to the result ob-
composed of a 20-bit maximum-length-sequence PRBS tained by the macromodeling approach.
circuit driving the two-cascaded sets of the IQ modulator The interconnect and substrate are taken into account in the
and demodulator chains [8]. The PRBS circuit generates a model extraction. The values are computed for all cases, distin-
trigger signal (TRIGOK) in order to synchronize the mea- guished based on interconnect as follows:

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BADAROGLU et al.: DIGITAL CIRCUIT CAPACITANCE AND SWITCHING ANALYSIS FOR GROUND BOUNCE 1127

TABLE III
GROUND-BOUNCE MACROMODEL PARAMETERS WITHOUT/WITH THE LOCAL
INTERCONNECT EFFECTS FOR ITC’99 BENCHMARK CIRCUITS (LEFTMOST
COLUMN) SYNTHESIZED IN A 0.18-m CMOS PROCESS

Fig. 14. Measured circuit capacitance (Cc) of the 40Kgates telecom circuit
(L1) as a function of the supply voltage.

1) no interconnect;
2) local: interconnect within the gate (metal 1);
3) local + signal: interconnect between the gates (metals 1
to 4);
4) local + signal + global: interconnect between the I/O pads
(global) and the circuit (metals 1 to 6).
The first two cases can be computed by directly using the
netlist before the layout, while the latter requires a postlayout
extraction procedure for the values of the interconnect capaci-
tances connecting the gates to each other as well as the I/O pads.
Table II also shows the circuit capacitance obtained from
the wafer probe measurements using the HP8510 network Fig. 15. Measured ground-bounce peak-to-peak value for the circuits T1 and
T3 versus the number of simultaneous switching inverters in T1 (for T3 this
analyzer (45 MHz to 50 GHz). The results show that the corresponds to the same switching inputs).
macromodel circuit capacitances are computed within 2%–3%
error with respect to SPICE and within 10% error with respect to
measurements. On the other hand, the computation of the circuit Table II also shows that the signaling interconnects become
capacitance of a 40-Kgate telecom circuit (L1) by using SPICE more significant in the overall admittance with the
is too time-consuming: six hours for the netlist extraction from increasing circuit size: 5% in T1, 5% in T2, 15% in T4, and
the layout and around five days for the ac simulation performed 11% in L1. Omitting all the interconnects will cause an error
by SPICE. The netlist of circuit L1 contains 119 762 transistors of 14%, 13%, 11%, and 15% for T1, T3, T4, and L1, respec-
and 58 939 interconnect capacitances. With our method, on the tively, in the resonance frequency estimation. For future tech-
other hand, the computation of the same circuit capacitance by nologies, this error will be even more pronounced. Note that
superposition of the one-time characterized macromodels takes the admittances of T1 and T3 are the same even
less than a second. The macromodels are constructed in around when local interconnect is taken into account. This shows that
ten minutes, including the time for the netlist extraction from the connectivity of the gates to the supply rail is important rather
the layout of each gate. But the cases 3 and 4 still require a than the connectivity of gates to each other. The overall differ-
post-layout extraction procedure in order to combine the signal ence is limited to 5% from the measurements. Further, Table III
and global interconnect capacitances with the macromodel, lists the extracted ground bounce macromodel parameters for
which only includes the effect of the local interconnects. On ITC’99 benchmark circuits [21] with and without the local in-
the other hand, the methodologies of predicting the interconnect terconnect effects (only at the prelayout level). The data show
capacitances before the layout is still not applicable to a complete that ignoring the interconnect overestimates the resonance fre-
interconnect network of a large digital system [20]. Fig. 14 quency by about 5%–6%.
shows the circuit capacitance of circuit L1 as a function of Fig. 15 shows the measured AC peak-to-peak value of the
the supply voltage. The figure clearly shows that the supply supply voltage ( ) on the die for T1 and T3 versus the
voltage variation across the nominal supply voltage (1.8 V) number of simultaneous switching inverters. The comparison
does not have any significant impact on the circuit capacitance. of the noise generated by the parallel logic to the noise gen-
The capacitance decreases slightly with the increasing supply erated by the serial logic shows that the difference becomes
voltage. significant for the cases with two, four, and eight switching

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1128 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

in a short CPU time. We have shown that the contribution of


the resistive substrate in the impedance of the gates
is negligible for the high-ohmic substrates. The logic-state
dependence of the inputs and interconnects on the ground
bounce should be taken into account. Both measurements and
simulations show that the assumption of linear superposition
of the supply currents of individual switching gates to obtain
the total supply current is valid with an error of 20% when the
switching activity factor is less than 0.2 for circuits sharing the
same supply and with the package parasitics. In the case of an
on-chip driver the negative feedback effect of the power-supply
noise on the peak value of the supply current is much more
severe (therefore, creating much more speed penalty) than the
case of an off-chip driver. From the measurements of a test
ASIC fabricated in a 0.18- m CMOS process on a high-ohmic
substrate with a resistivity of 18 cm, we have verified that
it is possible to derive the overall chip-level model for ground
Fig. 16. Measured variations in the magnitude of the V dd 0 V ss admittance bounce by directly summing the admittances of
(jY 11(j!)j) of the circuit T4 over a frequency band from 400 MHz to 1 GHz. the individual gates. This sum is independent of the overall
circuit topology. Using this topology-independent computation
inverters. In other cases, T3 does not behave like a serial logic for a more complex sequential circuit estimates the circuit
since more than one inverter switches simultaneously in those capacitance only within 10% error relative to the measurements
cases. T3 is 33% and 40% less noisy at four and eight switching while within 2%–3% error with respect to SPICE, but several
inverters, respectively, than T1. However, at two switching orders of magnitude faster in CPU time. Measurements have
inverters, T3 is 12% more noisy than T1. The case of two verified that the supply voltage variation does not have any
switching inverters is due to the fact that the depth of the serial impact on this admittance. Measurements have also verified
logic is not sufficient enough such that it still behaves like a that serial logic, when it has a sufficient depth in combinatorial
parallel logic. When the number of switching inverters is less
delay, generates less ground bounce.
than seven, it is difficult to judge that T3 generates less noise
than the noise generated from T1. On the other hand, for 12
switching inverters, T3 has two parallel switching rows of four ACKNOWLEDGMENT
and eight serially cascaded inverters. In this case, T3 is 33%
The authors would like to thank V. Gravot for his help in the
less noisy than T1. From these measurements, we conclude
extraction of the substrate network of the standard cells.
that whether three inverters switch in series or in parallel does
not make any difference on the ground bounce generation. The
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BADAROGLU et al.: DIGITAL CIRCUIT CAPACITANCE AND SWITCHING ANALYSIS FOR GROUND BOUNCE 1129

[9] M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, M. Geert Van der Plas (S’01–M’03) was born in
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synchronous digital circuits,” IEEE J. Solid-State Circuits, vol. 37, pp. Leuven, Belgium, in 1992 and 2001, respectively.
1383–1395, Nov. 2002. From 1992 to 2001, he was a Research Assistant
[10] M. Badaroglu, L. Balasubramanian, K. Tiri, V. Gravot, P. Wambacq, G. with the ESAT-MICAS Laboratory of the Katholieke
Van der Plas, S. Donnay, G. Gielen, and H. De Man, “Digital circuit Universiteit Leuven, where he worked in the field of
capacitance and switching analysis for ground bounce in IC’s with a analog modeling and design automation. In 2002, he
high-ohmic substrate,” in Proc. Eur. Solid-State Circuits Conf., Sept. was appointed as a Postdoctoral Research Assistant
2003, pp. 257–260. in the same research group. Since 2003, he has
[11] R. Singh, “A review of substrate coupling issues and modeling been with the design technology division of the
strategies,” in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. Interuniversitary Microelectronics Center (IMEC/DESICS), Belgium, where
491–499. he is working on substrate noise coupling in mixed-signal ICs. His current
[12] F. Martorell, D. Mateo, and X. Aragones, “Modeling and evaluation of research interests include deep-submicron signal integrity analysis and design
of mixed-signal circuits.
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and Test in Europe Conf., Mar. 2003, pp. 524–529.
[13] SubstrateStorm [Online]. Available: http://www.cadence.com
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[16] S. M. Sze, Semiconductor Devices: Physics and Technology, 2nd Piet Wambacq (S’89–M’91) was born in Asse,
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[17] P. Larsson, “Resonance and damping in CMOS circuits with on-chip electrical and mechanical engineering and the Ph.D.
decoupling capacitance,” IEEE Trans. Circuits Syst. I, vol. 45, pp. degree from the Katholieke Universiteit Leuven,
849–858, Aug. 1998. Belgium, in 1986 and 1996, respectively.
[18] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise From 1986 to 1996, he was a Research Assistant
calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits, at the ESAT-MICAS Laboratory, Katholieke Univer-
vol. 26, pp. 1724–1728, Nov. 1991. siteit Leuven. Since 1996, he has been with IMEC,
[19] T. Sakurai and R. Newton, “Alpha-power law MOSFET model and its Heverlee, Belgium, as a Principal Scientist working
applications to cmos inverter delay and other formulas,” IEEE J. Solid- on design methodologies for mixed-signal and RF in-
State Circuits, vol. 25, pp. 584–594, Apr. 1990. tegrated circuits. He is also a Lecturer at the Univer-
[20] Y. Cao, C. Hu, X. Huang, A. B. Kahng, I. L. Markov, M. Oliver, D. sity of Brussels (Vrije Universiteit Brussel). He has authored or coauthored two
books and more than 70 papers in edited books, international journals, and con-
Stroobandt, and D. Sylvester, “Improved a priori interconnect predic-
ference proceedings. He is the coinventor of two patents. He is an Associate
tions and technology extrapolation in the GTX system,” IEEE Trans.
Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I. He is
VLSI Syst., vol. 11, pp. 3–14, Feb. 2003.
regularly a member of the program committees of international conferences, in-
[21] ITC99 Benchmark Circuits [Online]. Available: http://www.cad.polito. cluding DATE. His research interests are design and CAD of mixed-signal and
it/tools/itc99.html RF integrated circuits.

Lakshmanan Balasubramanian (M’03) received


the B.Sc. degree in physics from the University
of Madras, India, in 1995, the B.Tech. degree in
electronics engineering from the Madras Institute
Mustafa Badaroglu (S’02) received the B.Sc. of Technology, Anna University, India, in 1998,
degree in electrical engineering from Bilkent and the M.Tech. degree in electronics design and
University, Ankara, Turkey, in 1995, and the M.Sc. technology from the Indian Institute of Science
degree in electrical engineering from Middle East in 2000. His B.Tech. and M.Tech. theses were on
Technical University, Ankara, in 1998. He did his the implementation of FPGA-based GPS baseband
Master’s thesis on design, verification, and VLSI processors and active noise reduction in a pilot’s
implementation of embedded microcontrollers. headset, respectively.
He is finalizing the Ph.D. degree in electrical He is currently with Nulife Semiconductor, Chennai, India. His current
engineering at the Katholieke Universiteit Leuven research is on low-power design of flip-flops, register files, and embedded
(K.U. Leuven), Belgium. memories. From 2001 to 2003, he was a Researcher working jointly
He is currently a Researcher in the Wireless Re- with the Interuniversity Microelectronics Center (IMEC), Belgium, and the
search group of IMEC, Leuven, Belgium. From 1996 to 1998, he worked as a Department Elektrotechniek, Katholieke Universiteit Leuven (K.U.Leuven),
Researcher in the VLSI design group of the Information Technologies and Elec- Belgium. During that period, his research was on analysis and design
tronics Research Institute (BILTEN) of the Scientific and Technical Research techniques for reduced switching noise in mixed-signal ICs. From 2000 to
Council of Turkey (TUBITAK) focusing on design and VLSI implementation 2001, he was an IC Design Engineer with the DSP Product Development
of digital signal processing blocks, mixed-signal voice/data CODEC ICs, base- Center of Texas Instruments India, Ltd. During that period, he worked on
band modems, and microprocessors. At IMEC, he is currently working on sub- design for testability and ATPG for DSP and broadband communication
strate noise coupling in mixed-signal ICs focusing on gate-level characterization ICs. His areas of interest include deep-submicron signal integrity analysis,
and reduction of substrate noise in integrated digital circuits. He also works on low-power circuit design, mixed-signal design, high-speed digital design,
ultra-low-power digital design. He has also worked on design and VLSI imple- and design for testability.
mentation of OFDM-based wireless LAN modems and UWB transceivers. His Mr. Balasubramanian is a member of the Institute of Electrical Engineers. He
current research interests include deep submicron signal integrity analysis, de- has been a Certified Engineer with the Engineering Council of the U.K. since
sign of low-noise digital circuits, and supply and clock distribution networks. December 2000.

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1130 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004

Kris Tiri (S’99) was born in Bree, Belgium, in 1976. Georges G. E. Gielen (S’87–M’92–SM’99–F’02)
He received the M.S. degree in electrical engineering received the M.Sc. and Ph.D. degrees in electrical
from the Katholieke Universiteit Leuven, Belgium, engineering from the Katholieke Universiteit
in 1999. He is currently working toward the Ph.D. Leuven, Belgium, in 1986 and 1990, respectively.
degree at the University of California, Los Angeles. In 1990, he was appointed as a Postdoctoral
His doctoral research focuses on design methodolo- Research Assistant and Visiting Lecturer with the
gies to reduce leakage of confidential information in Department of Electrical Engineering and Computer
cryptographic designs and substrate noise generation Science, University of California, Berkeley. From
in mixed-signal designs. 1991 to 1993, he was a Postdoctoral Research
He has been a Research Assistant with the Elec- Assistant with the Belgian National Fund of Scien-
trical Engineering Department of University of Cali- tific Research at the ESAT Laboratory, Katholieke
fornia, Los Angeles, since 1999. During the spring of 1999, he was with COM- Universiteit Leuven. In 1993, he was appointed as a Tenure Research Associate
ELEC of Ecole Nationale Superieure des Telecommunications, Paris, France. with the Belgian National Fund of Scientific Research and, at the same time,
During 2001–2002, he was with IMEC, studying substrate noise modeling and as an Assistant Professor at the Katholieke Universiteit Leuven, where, in
reduction. 2000, he was promoted to full Professor. His research interests are in the
Mr. Tiri was awarded a Franqui Foundation Fellowship by the Belgian Amer- design of analog and mixed-signal integrated circuits, and especially in analog
ican Educational Foundation in 1999. and mixed-signal CAD tools and design automation (modeling, simulation
and symbolic analysis, analog synthesis, analog layout generation, analog
and mixed-signal testing). He is coordinator or partner of several (industrial)
research projects in this area. He has authored or coauthored two books and
more than 200 papers in edited books, international journals, and conference
proceedings. He regularly is a member of the program committees of inter-
national conferences, including DAC, ICCAD, ISCAS, DATE, and CICC.
He is Deputy Editor in Chief of the IEEE TRANSACTIONS ON CIRCUITS AND
Ingrid Verbauwhede (M’93–SM’00) received the SYSTEMS—PART II, and Editor in Chief of the Elsevier Integration journal, and
Electrical Engineering degree and the Ph.D. degree he is a member of the Editorial Board of the Kluwer international journal on
in electrical engineering from the Katholieke Uni- Analog Integrated Circuits and Signal Processing.
versiteit Leuven (K.U. Leuven), Leuven, Belgium, Dr. Gielen received the 1995 Best Paper Award of the Wiley international
in 1991. journal on Circuit Theory and Applications, and was the 1997 Laureate of the
She was a Lecturer and Visiting Research Engi- Belgian Royal Academy on Sciences, Literature and Arts in the discipline of
neer at the University of California at Berkeley from Engineering. He received the 2000 Alcatel Award from the Belgian National
1992 to 1994. From 1994 to 1998, she was a Prin- Fund of Scientific Research for his innovative research in telecommunications.
cipal Engineer, first with TCSI and then with Atmel He is a member of the Board of Governors of the IEEE Circuits and Systems
in Berkeley. She joined the faculty of the University (CAS) society and Chairman of the IEEE Benelux CAS chapter.
of California at Los Angeles (UCLA) in 1998 as an
Associate Professor and the K.U. Leuven in 2003. Her interests include cir-
cuits, processor architectures, and VLSI design methodologies for real-time,
embedded systems in application domains such as cryptography, digital signal Hugo J. De Man (M’81–SM’81–F’86) received the
processing, wireless and high-speed communications. electrical engineering degree and the Ph.D. degree
in applied sciences from the Katholieke Universiteit
Leuven, Heverlee, Belgium, in 1964 and 1968,
respectively.
He has been a Professor in electrical engineering
at the Katholieke Universiteit Leuven since 1976. He
was a Visiting Associate Professor at the University
of California, Berkeley, in 1975, teaching semicon-
Stéphane Donnay (M’00) received the M.Sc. and ductor physics and VLSI design. His early research
Ph.D. degrees in electrical engineering from the was devoted to the development of mixed-signal,
Katholieke Universiteit Leuven (K.U.Leuven), switched-capacitor, and DSP simulation tools as well as new topologies for
Belgium, in 1990 and 1998, respectively. high-speed CMOS circuits, which lead to the invention of NORA CMOS. In
He was a Research Assistant in the ESAT-MICAS 1984, he was one of the cofounders of IMEC (Interuniversity Microelectronics
Laboratory of the K.U.Leuven from 1990 to 1996, Center), which today is the largest independent semiconductor research
where he worked in the field of analog and RF institute in Europe with over 1200 employees. From 1984 to 1995, he was Vice
modeling and design automation. In 1997, he joined President of IMEC, responsible for research in design technology for DSP and
IMEC, where he is now Manager of the Wireless telecom applications. In 1995, he became a Senior Research Fellow of IMEC,
Research group. His current research interests working on strategies for education and research on design of future post-PC
are ultra-low-power radios for sensor networks, systems. His research at IMEC has lead to many novel tools and methods in
software defined radios for broadband digital telecommunication applications, the area of high level synthesis, hardware–software codesign, and C++ based
system-in-a-package integration of RF front-ends, modeling and simulation design. Many of these tools are now commercialized by spin-off companies
of substrate noise coupling in mixed-signal ICs, and modeling and simulation like Coware and Target Compilers or have been used by major IP providers and
of communication systems. He is responsible for several projects in these system design industries. His work and teaching has also resulted in a cluster
areas and has authored or coauthored more than 100 papers in books, journals, of DSP-oriented companies in Leuven now known as DSP Valley, where more
and conference proceedings. He is coeditor of Substrate Noise Coupling in than 1500 DSP engineers work on design tools and on telecom, networking,
Mixed-Signal ASICs (Kluwer, 2003). and multimedia integrated system products.
Dr. Donnay has been a member of the Technical Program Committee of the In 1999, Dr. De Man received the Technical Achievement Award of the IEEE
European Solid-State Circuits Conference (ESSCIRC) since 2001. He was a Signal Processing Society, The Phil Kaufman Award of the EDA Consortium,
corecipient of the Best Paper Award at the Design, Automation and Test (DATE) and the Golden Jubilee Medal of the IEEE Circuits and Systems Society. He is
Conference in 2002. a member of the Royal Academy of Sciences in Belgium.

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