2040
9, SEPTEMBER 2006
Modeling of Substrate Noise Generation, Isolation,
and Impact for an LC-VCO and a Digital Modem on
a Lightly-Doped Substrate
Charlotte Soens, Member, IEEE, Geert Van der Plas, Member, IEEE, Mustafa Badaroglu, Member, IEEE,
Piet Wambacq, Member, IEEE, Stéphane Donnay, Member, IEEE, Yves Rolain, Fellow, IEEE, and
Maarten Kuijk, Member, IEEE
Abstract—Substrate noise generated by the digital circuits on a
mixed-signal IC can severely disturb the analog and RF circuits
sharing the same substrate. Simulations at the circuit level of the
substrate noise coupling in large systems-on-chip (SoCs) do not
provide the necessary understanding in the problem. Analysis at a
higher level of abstraction gives much more insight in the coupling
mechanisms. This paper presents a physical model to estimate and
understand the substrate noise generation by a digital modem, the
propagation of this noise and the resulting performance degrada-
tion of LC tank VCOs. The proposed linearized model is fast to de-
rive and to evaluate, while remaining accurate. It is validated with
measurements on two test structures: a reference design and a de-
sign with a p+ /n-well (digital) guard ring. Both structures contain
a functional 40k gate digital modem and a 0.18 m 3.5 GHz CMOS
LC-VCO on a lightly-doped substrate. In both cases, the model ac-
curately predicts the level of the spurious components appearing
at the VCO output due to the digital switching activity. The error
remains smaller than 3 dB. Finally, we demonstrate how the pro-
posed model enables a systematic and controlled isolation strategy
to suppress substrate noise coupling problems. As an example, the
model is used to determine suitable dimensions for a digital guard
ring.
Index Terms—CMOS integrated circuits, crosstalk, mixed-
signal integrated circuits, modeling, voltage-controlled oscillator.
I. INTRODUCTION
A N IMPORTANT problem that arises during the design of
a single-chip mixed-signal radio is the crosstalk from dig-
ital to analog. Simulation of this crosstalk at the circuit level for
large systems-on-chip (SoCs) does not provide the necessary in-
sight to resolve it. Moreover, performing circuit simulations to
investigate the crosstalk in a large SoC is not a workable solu-
tion. First, the number of digital gates is so large that it is not
practical to include them in analog circuit simulations. In addi-
tion, the crosstalk occurs via the silicon substrate, the printed
circuit board (PCB), the bonding wires, the package, and via
Manuscript received September 30, 2005; revised March 20, 2006. This work
was supported in part by the Institute for the Promotion of Innovation through
Science and Technology in Flanders (IWT-Flanders).
C. Soens is with IMEC, 3001 Leuven, Belgium, and also with the Department
ELEC-ETRO, Vrije Universiteit Brussel (VUB), Belgium, and the IWT (e-mail:
soens@imec.be).
G. Van der Plas, M. Badaroglu, and S. Donnay are with IMEC, 3001 Leuven,
Belgium.
P. Wambacq and M. Kuijk are with IMEC, 3001 Leuven, Belgium, and also
with the Vrije Universiteit Brussel (VUB), Belgium.
Y. Rolain is with the Vrije Universiteit Brussel (VUB), Belgium.
Digital Object Identifier 10.1109/JSSC.2006.880595
0018-9200/$20.00 © 2006 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
the ground and supply lines. All these parasitic paths have to
be included in the circuit simulations as well, resulting in ex-
tremely large simulation models. Analysis at a higher level of
abstraction is more practical and gives much more insight in the
coupling mechanisms.
The problem of reducing the impact of substrate noise on
analog/RF circuits has already received much attention in liter-
ature. Because of the lack of systematic and reliable simulation
methods designers are left with an intuitive and ad hoc approach
to solve the substrate noise coupling problems. For example, in
the single-chip Bluetooth system of [1], the radio has been care-
fully isolated with a 300 m wide p guard ring connected to
ground with 13 low-impedance bumps. It is estimated that the
isolation structure reduces substrate noise coupling by 25 dB at
2.5 GHz. Although the system is functional, it is not clear if this
guard ring is performing as intended. Similarly, in [2] the inte-
gration of a radio onto a Pentium die is investigated. A noise
transfer function analysis reveals that the use of deep n-well
biasing based isolation in conjunction with differential circuit
design is sufficient for radio integration. However, no functional
system has been built to verify this analysis.
The biggest modeling challenge for substrate noise impact is
in lightly-doped substrates which are nowadays used in almost
any bulk CMOS technology. Unlike the epi-type substrates,
modeled as a single equipotential node, lightly-doped sub-
strates have to be modeled as a three-dimensional RC-mesh.
Hence, propagation of noise in a lightly-doped substrate is a
distributed and layout dependent phenomenon. Lightly-doped
substrates are preferred for wireless applications because they
offer high- inductors, and feature higher isolation. In [3], [4],
and [5], macromodels for the generation of digital switching
noise are presented and validated with measurements, both
for epi-type and lightly-doped substrates. However, the prop-
agation towards and resulting impact on analog/RF circuits
is not included. Concerning the impact on analog circuits,
mostly circuit level simulations ([6], LNA) and interpretation
of measurements ([7], ADC) have been reported. Refs. [8] and
[9] derive an analytical model for substrate noise impact on
ring oscillators. The analytical model is validated for epi-type
substrates only and does not include a model for the digital
noise generation. Moreover, the analytical model does not
provide much information on the exact coupling mechanisms.
To the authors’ best knowledge, this work is the first to present
a linearized physical model that successfully predicts both the
substrate noise generation by a digital modem and the resulting
SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM 2041

Fig. 1. Schematic showing the generation, propagation, and impact of substrate noise on an LC-tank VCO via the ground interconnect, inductors, and nMOS
back-gates.

performance degradation for LC-tank VCOs on a lightly-doped in two equal power tones around the local oscillator signal at a
substrate. This model is valid for both epi-type and lightly- frequency ( is local oscillator frequency). The am-
doped substrates. The model is validated with measurements on plitude of these tones depends linearly on the (small) amplitude
a system containing a functional 40k gate digital modem and of the disturbance. For a VCO, this frequency translation is the
a 3.5 GHz LC-VCO on the same lightly-doped substrate. Two result of the modulation of the voltage over the variable circuit
designs are used: a reference design and a design containing capacitances and thus of the oscillation frequency. In the fre-
a p /n-well guard ring. In both cases, the model accurately quency domain, spurious components that appear around
predicts the level of the spurious components appearing at the the LO signal can be expressed as a linear sum over the sen-
voltage-controlled oscillator (VCO) output due to the digital sitive spots in the VCO [13]:
switching activity. The error remains smaller than 3 dB.
This paper is organized as follows. Section II describes the
linearized model in more detail. In Section III, the experimental
measurement setup is described and the model is validated on (1)
the reference design. In Section IV, the model is used to study
the p / n-well guarding of the second design. Section V demon- The assumption of linearity, and thus also superposition, holds
strates how the proposed model allows us to use isolation tech- since the substrate noise signals reaching the VCO are typically
niques as part of a systematic and controlled approach to solve orders of magnitude smaller than the LO signal. In Section II-A,
substrate noise coupling problems. the noise generation model is described, yielding a value for
in (1). In Section II-B, the model for the propa-
II. SUBSTRATE NOISE GENERATION AND IMPACT MODEL gation and for the resulting impact on LC-VCOs is explained.
The switching of digital circuits creates noise, ,
on the digital ground labeled (Fig. 1). The resistive cou- A. Digital Noise Generation Model
pling of the noise on the digital ground into the substrate is The digital ground bounce voltage, , is mod-
the dominant mechanism for substrate noise generation in eled as the response of a resonant circuit, formed by the circuit
lightly-doped substrates [5], [10], [11]. The digital ground capacitance and the package impedance, excited by the digital
bounce, , propagates to the sensitive analog cir- switching current (Fig. 2). One finds
cuits through the substrate (Fig. 1) and affects their operation.
For the VCO, this occurs as spurious components next to the
wanted local oscillator (LO) signal (see Fig. 11, right plot).
To study this effect, we split the problem in three parts (2)
(Fig. 1): the generation of noise ( ), the propa-
gation ( ) of noise through the resistive substrate to the
sensitive spots labeled (e.g., analog circuit ground, nMOS
back-gate) in the analog circuit, and the impact inside the (3)
analog circuit ( ) from the sensitive spots to the output.
With respect to the small substrate noise disturbance, a VCO Here and are the inter-
can be treated as an LPTV system. According to [12], a signal connect and bonding wire impedances, from, respectively, the
injected in an LPTV system at some frequency results in a spec- on-chip digital ground to the PCB ground and from the on-chip
tral component at another frequency. The injection of a single digital supply to the external supply. Further, is the capac-
tone disturbance with a small amplitude and frequency results itance of the digital circuit.

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2042 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

Fig. 2. The ground bounce is modeled as the response of a resonant tank excited by the digital switching current.

Fig. 3. Representation of the digital ground bounce model in the frequency domain.

is the current drawn by the digital circuit from noise. The propagation in the substrate and the coupling to the
the digital power supply during switching. It can be approxi- different entry points is characterized with a substrate transfer
mated by a train of triangular waveforms, a larger one at the function . is obtained from AC simulation
clock rising edge and a smaller one at the clock falling edge results on a model of the substrate and the VCO extracted with
[11], [3]. A part of this current, labeled , flows through Substratestorm and DIVA. As said previously, a substrate noise
the digital ground impedance . The impedance, labeled signal that enters the VCO will modulate the variable capac-
, that creates the ground bounce for a certain itances in the circuit and thus the oscillation frequency. Only
switching current is found to be FM is considered because, in a radio, AM will most likely be
removed by a switching mixer. Since the substrate disturbances
are small compared to the LO signal, narrowband FM can be as-
sumed. This assumption is confirmed by the measurements. The
expression of the amplitude of the spurious tones resulting from
narrowband FM shown in (1) can be further detailed as follows:

(4)

has a resonance at a frequency : (7)

Here is the LO amplitude, the dependency is due to the
narrowband FM, and is the FM sensitivity function
(5) related to the entry point defined similarly as the VCO gain
:
with a quality factor given by
(8)
(6)
The function is derived from Spectre pss simulations
on the circuit model (without substrate). The model of (7) is
To obtain , is multiplied
represented schematically in Fig. 4.
with (Fig. 3). The latter has a like shape with
is further modeled as a simple voltage division be-
notch frequency [3] ( : rise time; : fall
tween two resistors: and . The coupling to the VCO
time).
ground, for example, can be expressed as follows:
B. Propagation and Analog Impact Model
The digital ground bounce travels from the VSS on-chip node (9)
through the substrate and enters the VCO through different entry
points labeled . The nMOS back-gate, the on-chip ground in- Here is the equivalent resistance of the VCO ground
terconnect, the inductors and the devices inside n-wells via a plane, the resistance between the digital circuit ground
capacitive coupling are all prone to the influence of substrate and the VCO ground, and is the impedance of the

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SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM
Fig. 4. Schematic representation of the model for substrate noise propagation
and impact.
Fig. 5. Microphotograph of LC-VCO and digital IQ modem (20
cm 1P6M
0.18 m CMOS).
VCO ground bonding wire. models the distributed cur-
rent flow in both the substrate and the VCO ground plane as
explained in the Appendix.
In the remainder of this paper, the proposed model is eval-
uated using MATLAB and compared to measurements for dif-
ferent situations. The relative importance of the different com-
ponents of the model give insight into the coupling and impact
problem.
III. EXPERIMENTAL VERIFICATION OF MODEL
ON REFERENCE DESIGN
In order to build up trust for a model that describes substrate
noise coupling, validation with measurements is mandatory. In
this section, the relevant parameters of the experiment (test chip
and PCB) and the measurement setup are described.
Both the digital IQ modulator/demodulator, with a com-
plexity of 40k gates, and the LC-VCO have been realized in
a lightly-doped (20 cm / cm doping level, 305 m
wafer thickness) twin-well one-poly six-metal (1P6M) 0.18 m
CMOS technology (Fig. 5). Two layouts of the modem have
been designed: a reference design without guard ring and a
design with a p /n-well guard ring (see Fig. 5). Section III-A
describes the 3.5 GHz LC-tank VCO and the digital modem in
more detail. Section III-B shows the validation of the generation
model with measurements. Finally, in Section III-C, the model
for the propagation and the resulting impact on the LC-tank
VCO is validated with measurements.
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2043
A. Experimental Setup
The digital circuit consists of a 20-bit pseudorandom binary
sequencer (PRBS) with maximum-length sequence sourcing
input into two cascaded sets of IQ modulator and demodulator
chains. The PRBS circuit provides an output signal in order to
synchronize the measurement system with the circuit operation.
The operational clock frequency of the IQ modem can be varied
from DC to 60 MHz. Its current consumption is 5 mA @ 10
MHz clock and increases linearly with clock frequency.
A 3.5 GHz LC-VCO (schematic in Fig. 1, microphotograph
in Fig. 5) is integrated next to the digital circuit and serves as a
substrate noise victim. The VCO uses an nMOS/pMOS cross-
coupled pair ( m and m) with
an LC-tank formed by two on-chip inductors (without patterned
ground shield) of 1.2 nH each (realized in metal six) and two
accumulation mode nMOS varactors (1.2 pF to 2.5 pF each).
It operates from 3 GHz to 4.4 GHz by changing the (control)
tuning voltage at the varactor back gate node from 0 to 1.8 V.
The VCO gain is related to this voltage. The phase noise
is 100 dBc Hz @ 100 kHz offset at a current consumption
of 5 mA (VCO core only) and the supply voltage is set at 1.8 V.
The n-wells have a sheet resistance of 400 sq and the p-wells
have a sheet resistance of 800 sq. The 20 kA top metal layer
has a sheet resistance of 20 m sq and the metal 1 layer has a
sheet resistance of 77 m sq.
The chip has been bonded on a PCB using nonconductive
epoxy isolating the die from the PCB ground. Connections be-
tween chip and PCB have been realized using bonding wires.
The bonding wires have a length of approximately 1.5 mm and
a diameter of 25 m. Simulation with FastHenry and calcula-
tion according to the formula of Greenhouse [14] both estimate
an inductance of approximately 1.5 nH. The bonding wire re-
sistance calculated with FastHenry equals approximately 0.1 .
Decoupling has been placed on the PCB as close as possible to
the chip.
The following measurements are performed. The digital IQ
modem is powered and the clock and reset signals are applied
from a digital pattern generator. While the digital circuit is
operational, the power of the spurious tones appearing at both
sides of the LO signal are measured and modeled. The LC-VCO
is powered from a different source and its tuning voltage
is set externally to 1 V (largest impact). The VCO output
spectrum is measured (after limiting to remove AM) with a
HP8565ES spectrum analyzer. The ground bounce is measured
with a HP8565ES spectrum analyzer and an oscilloscope.
B. Digital Ground Bounce
On the reference design described in previous section, the
digital ground bounce model is first verified separately. The
measured digital ground bounce is shown in Fig. 6.
This signal is modeled as the response of the resonant circuit
formed by the package inductance and the digital circuit capac-
itance by the digital switching current (Fig. 2). As explained in
[5] and [11], the power of the clock harmonics is determined by
the average switching current (over multiple clock cycles). This
can be determined using SWAN [20]. In our example, the av-
erage switching current corresponds to a 490 pC pulse at the
rising clock edge with 1 ns rise and 5.5 ns fall times and a
2044
Fig. 6. Measured digital V (f = 20 MHz).
Fig. 7. Ground bounce model matches the measured spectrum (f
10 MHz).
65 pC pulse at the falling edge with 0.3 ns rise and 1 ns fall
times. The factor of the resonance circuit computed with (6)
equals only 1.2 due to the large resistance in the on-chip inter-
connect and bonding wires ( , nH,
, nH, pF). The resonance
frequency of is determined with (5) to be
127 MHz. The switching current notch frequency is 180 MHz.
In Fig. 7, a measurement of the digital ground bounce spec-
trum for a 10 MHz clock frequency is compared to the model.
At this low clock frequency the spectrum envelope can clearly
be seen. The ground bounce is measured indirectly. Using the
RC-model of the substrate, it is derived from a noise measure-
ment on a substrate contact located between the digital modem
and the VCO. The ground bounce spectrum is computed with
the model by multiplying the switching current spectrum with
the ground impedance. As said before, the resistive coupling of
the noise on the digital ground into the substrate is the dominant
mechanism for substrate noise generation in lightly-doped sub-
strates [5], [10], [11]. Both the ground impedance and supply
current have a finite bandwidth and both are approximately
equal to 130 MHz. This explains the drop in the ground bounce
power spectrum above 130 MHz. For the low-frequency har-
monics, the error compared to measurement is very small (in the
order of 1 dB). At higher frequencies (which are less important
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
Fig. 8. Ground bounce spectrum (f = 10 MHz) when reset signal is con-
tinuously high. The circuit resonance can clearly be observed.
Fig. 9. Impact model of 3.5 GHz LC-VCO: ground and inductor impact are the
dominant mechanisms.
=
Fig. 10. Substrate transfer functions to dominant entry points on reference de-
sign: on-chip VCO ground and inductors.
in this application), the noise is lower and the error increases.
This is due to the crude modeling of the switching current. This
can be improved by using a more detailed waveform derived
as described in [3]. It is interesting to note that the power of
the even harmonics is slightly higher than the power of the
odd harmonics. This is due to the fact that besides the large
triangular current peak drawn from the external supply at the
clock rising edge, a second, much smaller, peak is drawn at the
clock falling edge.
In normal operation, a signal is fed to the computational logic
at the clock falling edge, requiring a small current from the ex-
ternal supply. At the clock rising edge, the circuit performs a
computation on this input, which requires a larger current from
the external supply. Fig. 8 shows the measurement of the ground
bounce spectrum for a 10 MHz clock frequency when the reset
signal is continuously high. When the reset signal is continu-
ously high, no data is input into the computational logic. In this
mode, only the clock buffer is switching both at the falling and
SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM 2045

Fig. 11. Left: model of digital ground bounce matches measurement within 1 dB. Right: model for spurious tones at VCO output matches measurements within
3 dB over the full clock range (here: f = 20 MHz).

the rising clock edge. This explains the power in Fig. 8 present at between the substrate and the inductor, and flows into the
. Since the rise and fall times of this small switching cur- tank nodes A and B (Fig. 1) with impedance (mean
rent are very short, its bandwidth is very high and the shape of transconductance of nMOS–pMOS cross-coupled pair). These
the spectrum is completely determined by . tank nodes have a sensitivity equal to . Combining (10)
Indeed, around 120 MHz the resonance of and (11) yields
is visible.
After determining the digital ground bounce, we apply this
noise source to the VCO.

C. Impact of Digital Noise on the LC-VCO (12)

In general, the proposed model, equation (1), is used to in-

Fig. 10 shows the coupling from the digital ground to the VCO
vestigate where the weak spots in the analog circuit are located.
ground, , and the inductors, . and are
When these are identified, isolation techniques can be applied
determined from AC simulations on the RC substrate model.
to shield these weak spots/entry points. In our experiment two
Since the on-chip ground interconnect is connected to the off-
coupling mechanisms reveal dominant: resistive coupling to the
chip (PCB) ground with an inductive bonding wire, can,
non-ideal ground interconnect and capacitive coupling to the in-
for example, be expressed as
ductors (without patterned ground shield in this technology).
Hence, according to (7), when taking only the dominant im-
pact mechanisms into account, the level of the spurious tones
can be approximated by (according to model in Fig. 9)
(13)
Hence, increases above 37 MHz (
nH) (Fig. 10).
Using the ground bounce as predicted by the model of (2),
(10) the transfer functions, and (Fig. 10), and the FM
sensitivities, , the spectrum calculated with the model (1)
matches the measured output spectrum of the VCO on the ref-
Here is the transfer in the substrate from the source of
erence design within 3 dB for the entire clock range (Fig. 11).
noise to the VCO ground interconnect, and the transfer
The lower harmonics of the clock frequency are the most detri-
of noise to the substrate under the inductors. [defined
mental since they result in spurs closest to the carrier. The spu-
in (8)] is the ground FM sensitivity function and is the
rious level is almost flat because for the impact via the inductors,
inductor sensitivity function. Further, the FM sensitivity
the frequency dependence of the frequency modulation
can be expressed as a function of as follows (verified
is compensated by the behavior of the inductor FM sensi-
with simulations) [13]:
tivity, . For the coupling to the ground, a flat response is
obtained as well because the frequency dependence of
(11) the frequency modulation is compensated by the inductive
behavior of the ground network (Fig. 10). With this model, one
This relation can be explained as follows. The substrate noise can evaluate the efficiency of the guard rings and interpret how
current couples capacitively through , the capacitance they work.

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2046
Fig. 12. Level of spurious components when the p guard ring is kept floating (left), and (right) with a grounded p guard ring (f
Fig. 13. Transfer to on-chip analog ground interconnect and inductors decreases with 12 dB for a grounded (right) compared to a floating p guard ring (left).
IV. STUDY OF GUARDING STRATEGY FOR SECOND
MIXED-SIGNAL DESIGN WITH AN N-WELL SHIELD
AND A P+ GUARD RING
In the second version of the mixed-signal IC, a standard
double isolation structure, an n-well shield and a p guard
ring, surrounds the digital circuit (Fig. 5). Both have a width
of 5 m. These dimensions were chosen arbitrarily (within the
limited available area) since the goal is not to obtain a specified
isolation but to model and verify experimentally the isolation
provided by a guard ring in general. With measurements, we
compared this design in two modes: p guard ring left floating
or p guard ring connected to the PCB ground. The n-well
shield is always connected to a separate digital supply on the
PCB.
The effect of grounding the p guard ring is a decrease of the
substrate noise impact by approximately 12 dB (i.e., a factor
of 4), which is predicted by the model within 1 dB (Fig. 12).
This is explained by the reduction in noise transfer between the
on-chip digital ground and the dominant VCO entry points, the
VCO on-chip ground interconnect and the inductors. Both entry
points experience this reduction (Fig. 13).
Let us, for instance, investigate this decrease in the noise
transfer function for the coupling to the on-chip VCO ground.
For the inductors, a similar reasoning applies. Fig. 14 shows a
cross section of the test structure with, from left to right, the
analog ground, the p guard ring, the n-well shield, and the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
= 60 MHz).
digital ground. From the layout, an abstract view is extracted
(by means of the Substrate Noise Analyst (SNA) [15] software)
from which an equivalent circuit is derived. The circuit is shown
in Fig. 15. It contains only the nodes that are relevant for the
problem: the p guard ring labeled GR, the digital ground la-
beled VSS and the VCO ground labeled VCO GND. The equiv-
alent circuit consists of the three substrate impedances between
these nodes, , , and , completed with the parasitic im-
pedances (both inductance and resistance) of the interconnect
and bonding wires connecting them to the PCB ground, ,
, and . The bonding wire inductance and resis-
tance are estimated with the FastHenry software and using the
Greenhouse formula [14]. Since the studied frequency range is
far below 7 GHz, the 20 cm substrate can be modeled as a
mesh containing only resistive components [16]. Hence, we can
approximate the impedances , , and by the resistances
, , and (Figs. 15 and 16). Resistance models the
current escaping the influence of the guard ring and reaching
the VCO ground by diving deeper into the lightly-doped sub-
strate. Resistance models the current flow from the digital
ground to the guard ring. This current is pushed deeper into the
substrate by the n-well barrier. Resistance models the cur-
rent flow from the guard ring to the VCO ground via two par-
allel paths: the lightly-doped substrate and the p-well. These re-
sistances are both determined with the SNA software [15] and
measured. Measured values for , , and are 1088 ,
70 , and 328 , respectively, and extracted values 1200 ,
SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM 2047

Fig. 14. Cross section of test structure.

Fig. 17. Resistance values for equivalent model (Fig. 15) of test structure in a
function of guard ring width.

Fig. 15. Equivalent circuit of the test structure containing three external nodes:
the p guard ring (GR), the digital ground (VSS) and the analog ground (VCO
GND).

Fig. 18. Comparison of total (tot), direct (direct) and noise transfer via the
guard ring (GR) at 1 MHz.

The first term represents the coupling directly from the dig-
ital ground node to the VCO ground when the guard ring is
ideally grounded. It results from the voltage division between
and (Fig. 16). The second term represents the
noise transferred from the digital ground via the (not ideally
grounded) guard ring to the VCO ground (considered
). It results from the voltage division between
Fig. 16. Extracted substrate and analog ground network. The values in paren- and followed by the division between and .
theses are for a model without n-well.
For our test case, the digital modem and VCO had to be placed
relatively close to each other for reasons of limited chip area,
and the direct coupling via [first term in (14)] is dominant
60 , and 299 . The error on [ in (13)], which dom- over the coupling via the guard ring [second term in (14)]. When
inantly determines the coupling, is only 10%, which is within the coupling via is reduced, the guard ring ground impedance
the processing variation of the substrate resistivity. starts playing an important role, as was already pointed out by
In the case of a floating p guard ring, the ground bounce [17]. What is the effect of the n-well shield in our isolation struc-
charge on the on-chip digital ground (VSS) flows both directly ture? The n-well used in our isolation structure was used as part
to the on-chip analog ground (VCO GND) via , and indirectly of a standard isolation method. Its actual effect was not verified
through the guard ring node (GR) via and (Fig. 16). This beforehand. The only significant change it brings in the model
results in an effective resistive path for the noise current of 270 of Fig. 16 is that increases from 14 to 60 . and re-
(1 k in parallel with 370 ). In the case of a grounded p guard main unchanged. Since in this specific case, coupling via is
ring, the path passing through the guard ring node is shorted to dominant, the n-well shield does not bring additional shielding
ground through the guard ring bonding wire (both resistive and when combined with the p guard ring (below 100 MHz). Only
inductive). The current flows through only, hence the 12 dB when the coupling via is negligible and the main coupling
reduction in coupling. occurs via the guard ring will the n-well help to reduce the im-
From the model in Fig. 16, a simplified expression is derived pact. Note that the insights presented here can only be obtained
for the coupling from the digital to the analog ground (simplified with this type of model.
assuming , , ):
V. GUARDING GUIDELINES BASED ON MODEL
Due to the lack of reliable simulation tools, actual guarding
(14) strategies [1], [18] are often based on the application of rules

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2048
Fig. 19. Total (tot), direct (direct) and noise transfer via guard ring (GR) for 100 and 200 MHz noise.
of thumb and intuition, leading to overengineered solutions or
even system failure. In [18], a large isolation structure is used
to isolate the digital modem from the analog front-end. How-
ever, the authors do not mention the additional columns of pads
placed at both sides of the isolation structure used to connect the
analog and digital part with bonding wires on chip. This clearly
offers the possibility of a two-chip back-up solution and shows
that the effects of substrate noise coupling are not under control.
In this section, we demonstrate how the proposed model al-
lows us to apply isolation techniques as part of a systematic and
controlled approach to solve substrate noise coupling problems.
The reduction of the impact provided by a digital guard ring de-
pending on its dimensions is determined.
The model is applied to a test structure containing the digital
modem and the 3.5 GHz LC-tank VCO described above, but
placed approximately 1000 m apart. The coupling of digital
noise to the VCO ground is considered, but a similar analysis
can be made for any entry point in the VCO that has been iden-
tified as a “weak spot.” To extract the parameters of the model
an “abstract view” of the system is generated with SNA. The re-
sistances , , and of the equivalent circuit (Fig. 16) are
determined for a guard ring width varying from 5 m to 600 m
(Fig. 17). For a grounded guard ring and a given noise voltage
on the digital ground the total noise current is
(15)
For a width of 5 m approximately 97%
of this current will flow to
the PCB ground via and the guard ring and only 3%
via and the
VCO ground. When the guard ring dimensions are increased,
the amount of current taken out of the path to the VCO
ground and lead via the path to the guard ring will result in a
large relative change of but only a small relative change of .
This is reflected in a large change in (since ) ductance lowers its efficiency. The developed model opens the
and a small change in (since ) as can be
seen in Fig. 17.
From these resistances, the coupling from the digital to the
analog ground can be estimated according to (14). In Figs. 18
and 19, the total coupling, labeled tot and given by (14), is
plotted, as well as the coupling via , labeled direct and given
by the first term in (14), and the coupling via the non-ideal guard
ring labeled GR and given by the second term in (14). This is
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
done for noise frequencies of 1 MHz, 100 MHz, and 200 MHz.
For noise frequencies in the 1 MHz range, the impedance of the
bonding wire connecting the guard ring to the PCB ground is
only 0.01 and the transfer of noise via and is thus negli-
gible compared to the coupling via . For a noise frequency of
100 MHz and 200 MHz, the second term in (14) becomes equal
to the first term at a guard ring width of 380 m and 300 m,
respectively. From this point on, increasing the guard ring di-
mensions is useless. It can be concluded that for large isolation
structures, as used by [1] and [18], the bonding wire parasitics
can become the bottleneck for substrate noise coupling reduc-
tion. Hence, for high-frequency noise it is advised to verify that
the guard ring is not made unnecessarily large. To diminish the
influence of the guard ring parasitics, multiple bonding wires
or bumps can be used for grounding. The required amount of
bonding wires can be predicted by the model, taking into ac-
count the allowed spurious power and the available chip area
(number of ground pads available for bonding).
VI. CONCLUSION
This paper reports a model to predict, prior to processing, the
substrate noise generation, propagation, and resulting LC-VCO
performance degradation. The proposed model is both fast to ex-
tract and evaluate, while remaining accurate. It is validated with
measurements on two test structures, a reference design and a
design with a /n-well (digital) guard ring structure, both con-
taining a functional 40k gate digital modem and an LC-VCO
in a 0.18 m CMOS process on a lightly-doped substrate. In
both cases, the model accurately predicts the level of the spu-
rious components appearing at the VCO output due to the dig-
ital switching activity with an error smaller than 3 dB. Finally,
we demonstrate how the model allows the application of isola-
tion techniques as part of a systematic and controlled approach
to solve substrate noise coupling problems. As an example, we
demonstrate for a digital guard ring how the model allows us to
determine suited dimensions and how the guard ring parasitic in-
way to solve and understand substrate noise coupling problems
for analog and RF circuits.
APPENDIX
This Appendix explains the derivation of the equivalent
ground resistance, . A similar reasoning applies for
the derivation of the equivalent resistances of the other sen-
sitive spots in the VCO such as the inductors. Typically, a
SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM 2049

Fig. 20. Drawing of VCO with distributed current flow in the on-chip ground interconnect.

The distributed effect is further modeled by means of an equiv-

alent ground resistance, . This simplifies the model de-
scribing the coupling from the noisy digital ground node, ,
to the VCO ground node, , as shown in Fig. 21.
This model replaces the distributed ground plane by one node
such that the coupling from the aggressor node to the victim
node can be expressed as
Fig. 21. Macromodel describing the coupling of noise from the digital to the
VCO ground.

(17)
lightly-doped substrate is tied to ground by means of many p
contacts that are connected to the off-chip ground with a metal
Here is the noise present on the digital ground labeled
interconnect and bonding wires or flip-chip connections. These
, is the noise on the VCO ground determined ac-
contacts and interconnect draw part of the harmful substrate
cording to (16) and is the substrate resistance between
noise currents out of the substrate. This is only effective if
the noisy digital ground, and the VCO ground. This resistance
the voltage drop, resulting from these currents flowing in the
is both measured performing two-point measurements and de-
ground interconnect parasitic resistance, is not sensed by the
termined from the RC-mesh extracted with SubstrateStorm. The
devices in the circuit. Otherwise, ground contacts originally
transfer function is obtained
meant to remove substrate noise currents, form a path via which
from AC simulation results using Spectre on a simulation model
substrate noise enters an analog circuit. Moreover, the on-chip
built with SNA [15] for the substrate modeling in combination
ground is often implemented as a metal plane over which p
with DIVA for the extraction of the parasitic resistance of the
contacts are distributed. For the studied VCO, impact occurs
distributed ground plane. is determined from and
when substrate noise currents are picked up by the ground
the transfer function using (17).
plane, and result in a voltage fluctuation at the circuit ground
that modulates the oscillator frequency. Currents are picked up ACKNOWLEDGMENT
at different locations and follow a different path in the ground
The authors wish to thank C. De Tandt, M. Libois, and
plane towards the bonding wire to go off-chip as described in
H. Suys for the help with the realization of the PCBs, and
Fig. 20.
D. Linten for the design of the VCO.
This distributed current flow in the parasitic resistance of the
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[12] T. H. Lee and A. Hajimiri, “Oscillator phase noise: A tutorial,” IEEE
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[13] C. Soens, “Performance degradation of LC-tank VCOs by impact of
digital switching noise in lightly doped substrates,” IEEE J. Solid-State
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[14] H. M. Greenhouse, “Design of planar rectangular microelectronic
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Charlotte Soens (S’02–M’05) received the M.Sc.
degree in electrical engineering (Burgerlijk In-
genieur) and the Ph.D. degree from the Vrije
Universiteit Brussel (VUB), Brussels, Belgium, in
2001 and 2006, respectively.
She was a Research Assistant with the Department
ELEC/ETRO from 2001 to 2006. Since 2001, she
has also been with the design technology division
of the Interuniversitary Microelectronics Center
(IMEC/DESICS), Belgium. Her current research
includes the physical modeling of substrate noise
impact on RF circuits and the design of RF circuits for flexible front-ends.
Geert Van der Plas (S’01–M’03) received the M.Sc.
and Ph.D. degrees from the Katholieke Universiteit
Leuven, Belgium, in 1992 and 2001, respectively.
From 1992 to 2001, he was a Research Assistant
with the ESAT-MICAS Laboratory of the Katholieke
Universiteit Leuven, where he worked in the field of
analog modeling and design automation. In 2002, he
was appointed as a Postdoctoral Research Assistant
in the same research group. Since 2003, he has been
with the design technology division of the Interuni-
versitary Microelectronics Center (IMEC/DESICS),
Belgium, where he is working on substrate noise coupling in mixed-signal ICs.
His current research interests include deep-submicron signal integrity analysis
and design of mixed-signal circuits.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
Mustafa Badaroglu (S’00–M’05) received the B.Sc.
degree from Bilkent University, Ankara, Turkey, in
1995, the M.Sc. degree from Middle East Technical
University, Ankara, Turkey, in 1998, and the Ph.D.
degree from the Katholieke Universiteit Leuven, Bel-
gium, in 2004, all in electrical engineering.
Since 1999, he has been with IMEC, Leuven,
Belgium, where he is now a Senior Researcher.
From 1996 to 1998, he was a Researcher in the
Scientific and Technical Research Council of Turkey
(TUBITAK), Ankara, where he worked on de-
sign/implementation of embedded microcontrollers, digital signal processors,
and several mixed-signal integrated circuits. At IMEC, he has worked on
deep-submicron design automation, low-power design, and design/imple-
mentation of WLAN and UWB transceivers. His research interests include
deep-submicron effects analysis/suppression, low-noise/power design, and
supply/clock networks.
Dr. Badaroglu was the recipient of the 2004 European Design and Automa-
tion Association (EDAA) Doctoral Dissertation Award and of the Best Paper
Award at the Design, Automation and Test Conference in 2004.
Piet Wambacq (S’89–M’91) received the M.Sc.
degree in electrical and mechanical engineering and
the Ph.D. degree from the Katholieke Universiteit
Leuven, Belgium, in 1986 and 1996, respectively.
From 1986 to 1996, he was a Research Assistant
at the ESAT-MICAS Laboratory, Katholieke Univer-
siteit Leuven. Since 1996, he has been with IMEC,
Belgium, as a Principal Scientist working on design
methodologies for mixed-signal and RF integrated
circuits. He is also a Lecturer at the University
of Brussels (Vrije Universiteit Brussel). He has
authored or coauthored two books and more than 70 papers in edited books,
international journals, and conference proceedings. He is the coinventor of two
patents. His research interests are design and CAD of mixed-signal and RF
integrated circuits.
Dr. Wambacq is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—PART I. He is regularly a member of the program committees
of international conferences, including DATE.
Stéphane Donnay (M’00) received the M.Sc. and
Ph.D. degrees in electrical engineering from the
Katholieke Universiteit Leuven (K.U.Leuven),
Belgium, in 1990 and 1998, respectively.
He was a Research Assistant in the ESAT-MICAS
Laboratory of the K.U.Leuven from 1990 to 1996,
where he worked in the field of analog and RF
modeling and design automation. In 1997, he joined
IMEC, where he is now Manager of the Wireless
Research group. His current research interests
are ultra-low-power radios for sensor networks,
software defined radios for broadband digital telecommunication applications,
system-in-a-package integration of RF front-ends, modeling and simulation
of substrate noise coupling in mixed-signal ICs, and modeling and simulation
of communication systems. He is responsible for several projects in these
areas and has authored or coauthored more than 100 papers in books, journals,
and conference proceedings. He is a coeditor of Substrate Noise Coupling in
Mixed-Signal ASICs (Kluwer, 2003).
Dr. Donnay has been a member of the Technical Program Committee of the
European Solid-State Circuits Conference (ESSCIRC) since 2001. He was a
corecipient of the Best Paper Award at the Design, Automation and Test (DATE)
Conference in 2002.
SOENS et al.: MODELING OF SUBSTRATE NOISE GENERATION, ISOLATION, AND IMPACT FOR AN LC-VCO AND A DIGITAL MODEM
Yves Rolain (M’90–SM’96–F’06) received the Elec-
trical Engineering (Burgerlijk Ingenieur) degree in
July 1984, the degree of computer sciences in 1986,
and the Ph.D. degree in applied siences in 1993, all
from the Vrije Universiteit Brussel (VUB), Brussels,
Belgium.
He is currently a Senior Research Assistant with
the Electrical Measurement Department (ELEC),
Vrije Universiteit Brussel (VUB), Brussels, Belgium.
His main interests are microwave measurements and
modelling, applied digital signal processing, and
parameter estimation/system identification.
Dr. Rolain was the recipient of the 2004 IEEE Instrumentation and Measure-
ment Society Award.
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2051
Maarten Kuijk (S’90–M’95) received the Ph.D.
degree (cum laude) in electrical engineering from the
Vrije Universiteit Brussels (VUB), Belgium, in 1993
with felicitations of the jury. The work was done in
close collaboration with IMEC, Europe’s leading
independent research center for microelectronics.
The subject was the optoelectronic thyristor device
in III-V semiconductor and the differential pair
of thyristors resulting in fast and sensitive optical
digital transceivers.
In 1994, he became an Assistant Professor at the
VUB in the field of integrated electronics and optoelectronics and was addition-
ally appointed Research Associate for the Fund for Scientific Research Flanders
(FWO-V) in 1997. His current research topics include electrical and optical in-
terconnects devices, optical components, CMOS and SiGe-BICMOS circuits,
and alternatives for flip-chip technology. He has authored or coauthored more
than 40 international refereed publications and holds nine international patents
with four patents pending.