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  • JNTU Analog IC Design Exam Questions on Modeling Concepts, Op-Amp Compensation, Sample and Hold Circuits

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    This document appears to be an exam paper for an Analog IC Design course. It consists of 8 questions related to topics in analog and mixed-signal integrated circuit design. The questions cover topics such as modeling concepts for microcircuit design, op-amp compensation, switched capacitor circuits, analog-to-digital converters, noise shaping, and short channel effects in CMOS transistors. It also asks students to calculate various circuit parameters and design components like sample and hold circuits.

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    Analog Ic Design

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    This document appears to be an exam paper for an Analog IC Design course. It consists of 8 questions related to topics in analog and mixed-signal integrated circuit design. The questions cover topics such as modeling concepts for microcircuit design, op-amp compensation, switched capacitor circuits, analog-to-digital converters, noise shaping, and short channel effects in CMOS transistors. It also asks students to calculate various circuit parameters and design components like sample and hold circuits.

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    38 tayangan2 halaman

    JNTU Analog IC Design Exam Questions on Modeling Concepts, Op-Amp Compensation, Sample and Hold Circuits

    Diunggah oleh

    IbmWasuser
    This document appears to be an exam paper for an Analog IC Design course. It consists of 8 questions related to topics in analog and mixed-signal integrated circuit design. The questions cover topics such as modeling concepts for microcircuit design, op-amp compensation, switched capacitor circuits, analog-to-digital converters, noise shaping, and short channel effects in CMOS transistors. It also asks students to calculate various circuit parameters and design components like sample and hold circuits.

    Hak Cipta:

    © All Rights Reserved
    Unduh sebagai PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    dari 2

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    Code No: A5707
    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
    M.Tech I SEMESTER EXAMINATIONS, APRIL/MAY-2013
    ANALOG IC DESIGN
    (VLSI SYSTEM DESIGN)
    Time: 3hours Max.Marks:60
    Answer any five questions
    All questions carry equal marks
    - - -

    1.a) State and explain the three advanced modeling concepts that a microcircuit
    designer uses.
    b) In a common source amplier with a current mirror active load circuit, all the
    transistors are assumed to have

    Calculate the gain of the amplier.
    2.a) Design a first-order model of closed loop amplier and discuss in detail about
    compensation in two stage op-amp.
    b) Assume for a 0.8 -

    m technology that K
    3
    =2.5, V
    o
    = 10mV, V
    logic
    =2V,
    V
    ef f
    =0.5V and
    n
    =0.05 m
    2
    /V.S. Calculate the maximum clocking frequency of
    the comparator.

    3. Design and explain a switched capacitor sample and hold circuit. If combined
    with Low pass lter how does this circuit work?

    4. A Full Scale sinusoidal waveform is applied to a 12-bit ADC and the output is
    digitally analyzed. If the fundamental has a normalized power of 1W while the
    remaining power being 0.5W, what is the eective number of bits of the
    converter?

    5. Calculate the discrete-time transfer function of the switched capacitor circuit
    shown in Figure. Ignore the eect of parasitic capacitances.




    NR
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    6. Compare and contrast dierent types of ADCs and explain the ow graph
    for a successive-approximation approach.

    7.a) State the concept of oversampling with noise shaping and explain a noise-shaped
    delta-sigma modulator.
    b) Given that a 1-bit ADC has a 6-dB SNR, what sample rate is required to obtain a
    96-dB SNR (or 16 bits) if f
    o
    = 25KHz for straight oversampling as well as rst and
    second-order noise shaping?


    8. Write short notes on:
    a) Short channel eects in CMOS.
    b) Correlated double sampling technique.
    c) Single stage digital decimation lter.




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