Introduction to Peripheral Interface Controllers (PIC)

Peripheral Interface Controllers (PIC) is one of the advanced microcontrollers developed by

microchip technologies. These microcontrollers are widely used in modern electronics
applications. A PIC controller integrates all type of advanced interfacing ports and memory
modules. These controllers are more advanced than normal microcontroller like INTEL
8051. The first PIC chip was announced in 1975 (PIC1650). As like normal microcontroller,
the PIC chip also combines a microprocessor unit called CPU and is integrated with
various types of memory modules (RAM, ROM, EEPROM ,etc), I/O ports, timers/counters,
communication ports, etc.

Overview of PIC 16F877
PIC 16F877 is one of the most advanced microcontroller from Microchip. This controller is
widely used for experimental and modern applications because of its low price, wide range
of applications, high quality, and ease of availability. It is ideal for applications such as
machine control applications, measurement devices, study purpose, and so on. The PIC
16F877 features all the components which modern microcontrollers normally have. The
figure of a PIC16F877 chip is shown below.

Features of PIC16F877
The PIC16FXX series has more advanced and developed features when compared to its
previous series. The important features of PIC16F877 series is given below.

General Features
High performance RISC CPU.
ONLY 35 simple word instructions.
All single cycle instructions except for program branches which are two cycles.
Operating speed: clock input (200MHz), instruction cycle (200nS).
Up to 3688bit of RAM (data memory), 2568 of EEPROM (data memory), 8k14
of flash memory.
Pin out compatible to PIC 16C74B, PIC 16C76, PIC 16C77.
Eight level deep hardware stack.
Interrupt capability (up to 14 sources).
Different types of addressing modes (direct, Indirect, relative addressing modes).
Power on Reset (POR).
Power-Up Timer (PWRT) and oscillator start-up timer.
Low power- high speed CMOS flash/EEPROM.
Fully static design.
Wide operating voltage range (2.0 5.56)volts.
High sink/source current (25mA).
Commercial, industrial and extended temperature ranges.
Low power consumption (<0.6mA typical @3v-4MHz, 20A typical @3v-32MHz
and <1 A typical standby).

Peripheral Features
Timer 0: 8 bit timer/counter with pre-scalar.
Timer 1:16 bit timer/counter with pre-scalar.
Timer 2: 8 bit timer/counter with 8 bit period registers with pre-scalar and post-
scalar.
Two Capture (16bit/12.5nS), Compare (16 bit/200nS), Pulse Width Modules (10bit).
10bit multi-channel A/D converter
Synchronous Serial Port (SSP) with SPI (master code) and I2C (master/slave).
Universal Synchronous Asynchronous Receiver Transmitter (USART) with 9 bit
address detection.
Parallel Slave Port (PSP) 8 bit wide with external RD, WR and CS controls
(40/46pin).
Brown Out circuitry for Brown-Out Reset (BOR).
Key Features
Maximum operating frequency is 20MHz.
Flash program memory (14 bit words), 8KB.
Data memory (bytes) is 368.
EEPROM data memory (bytes) is 256.
5 input/output ports.
3 timers.
2 CCP modules.
2 serial communication ports (MSSP, USART).
PSP parallel communication port
10 bit A/D module (8 channels)
Pin Diagrams

PIC16F877 chip is available
in different types
of packages. According to the
type of applications and
usage, these packages are
differentiated.


Input/output ports

PIC16F877 has 5 basic input/output ports. They are usually denoted by PORT A (R A),
PORT B (RB), PORT C (RC), PORT D (RD), and PORT E (RE). These ports are used for
input/ output interfacing. In this controller, PORT A is only 6 bits wide (RA-0 to RA-5),
PORT B , PORT C,PORT D are only 8 bits wide (RB0 to RB7, RC0 to RC7, RD0 to
RD7), PORT E has only 3 bit wide (RE0 to RE2).
PORT-A RA-0 to RA-5 6 bit wide
PORT-B RB-0 to RB-7 8 bit wide
PORT-C RC-0 to RC-7 8 bit wide
PORT-D RD-0 to RD-7 8 bit wide
PORT-E RE-0 to RE-2 3 bit wide
All these ports are bi-directional. The direction of the port is controlled by using TRIS(X)
registers (TRIS A used to set the direction of PORT-A, TRIS B used to set the direction for
PORT-B, etc.). Setting a TRIS(X) bit 1 will set the corresponding PORT(X) bit as input.
Clearing a TRIS(X) bit 0 will set the corresponding PORT(X) bit as output.
(If we want to set PORT A as an input, just set TRIS(A) bit to logical 1 and want to set
PORT B as an output, just set the PORT B bits to logical 0.)
o Analog input port (AN0 TO AN7) : these ports are used for interfacing analog inputs.
o TX and RX: These are the USART transmission and reception ports.
o SCK: these pins are used for giving synchronous serial clock input.
o SCL: these pins act as an output for both SPI and I2C modes.
o DT: these are synchronous data terminals.
o CK: synchronous clock input.
o SD0: SPI data output (SPI Mode).
o SD1: SPI Data input (SPI mode).
o SDA: data input/output in I2C Mode.
o CCP1 and CCP2: these are capture/compare/PWM modules.
o OSC1: oscillator input/external clock.
o OSC2: oscillator output/clock out.
o MCLR: master clear pin (Active low reset).
o Vpp: programming voltage input.
o THV: High voltage test mode controlling.
o Vref (+/-): reference voltage.
o SS: Slave select for the synchronous serial port.
o T0CK1: clock input to TIMER 0.
o T1OSO: Timer 1 oscillator output.
o T1OS1: Timer 1 oscillator input.
o T1CK1: clock input to Timer 1.
o PGD: Serial programming data.
o PGC: serial programming clock.
o PGM: Low Voltage Programming input.
o INT: external interrupt.
o RD: Read control for parallel slave port.
o CS: Select control for parallel slave.
o PSP0 to PSP7: Parallel slave port.
o VDD: positive supply for logic and input pins.
o VSS: Ground reference for logic and input/output pins.
Architecture and Memory Organization of PIC 16F877
The basic building block of PIC 16F877 is based on Harvard architecture. This
microcontroller also has many advanced features as mentioned in the previous post. Here
you can see the basic internal architecture and memory organisation of PIC16F877.

Architecture of PIC16F877
The figure below shows the internal architecture of a PIC16F877A chip.

CPU
The function of CPU in PIC is same as a normal microcontroller CPU. A PIC CPU consists of
several sub units such as instruction decoder, ALU, accumulator, control unit, etc. The CPU
in PIC normally supports Reduced Instruction Set Computer (RISC) architecture (Reduced
Instruction Set Computer (RISC), a type of microprocessor that focuses on rapid and
efficient processing of a relatively small set of instructions. RISC design is based on the
premise that most of the instructions a computer decodes and executes are simple. As a
result, RISC architecture limits the number of instructions that are built into the
microcontroller but optimizes each so it can be carried out very rapidly (usually within a
single clock cycle.). These RISC structure gives the following advantages.
The RISC structure only has 35 simple instructions as compared to others
The execution time is same for most of the instructions (except very few numbers).
The execution time required is very less (5 million instructions/second (approximately).

Memory
The memory in a PIC chip used to store the data and programs temporary or permanently.
As like normal microcontrollers, the PIC chip also has certain amount of RAM, ROM,
EEPROM, other flash memory, etc.
ROM memory is used for permanent storage. The ROM memory also called as n program
memory. A PI chip has certain amount of ROM memory. EEPROM memory is another
category of ROM memory. The contents in the EEPROM changes during run time and at
that time it acts like a RAM memory. But the difference is after the power goes off , the
data remains in this ROM chip. This is the one of the special advantages of EEPROM. In the
PIC chip the function of EPROM is to store the values created during the runtime.
RAM memory is the one of the complex memory module in a PIC chip. This memory
associated with various type of registers (special function registers and general purpose
registers) and memory BANK modules (BANK 0, BANK 1, etc.). Once the power goes off, the
contents in the RAM will be cleared. As like normal microcontrollers, the RAM memory is
used to store temporary data and provide immediate results.
Flash memory
This is a special type of memory where READ, WRITE, and ERASE operations can be done
many times. This type of memory was invented by INTEL corporation in 1980. A PIC Chip
normally contains a certain amount of flash memory.




Registers
Information is stored in a CPU memory location called a register. Registers can be thought
of as the CPUs tiny scratchpad, temporarily storing instructions or data. Registers basically
classified into the following.
1) General Purpose Register (GPR)
A general purpose register (or processor register) is a small storage area available on a CPU
whose contents can be accessed more quickly than other storage that available on PIC. A
general purpose register can store both data addresses simultaneously.
2) Special Function registers (SFR)
These are also a part of RAM memory locations. As compared to GPR, their purpose is
predetermined during the manufacturing time and cannot be changed by the user. It is only
for special dedicated functions.

Interrupts
Interrupt is the temporary delay in a running program. These delays stop the current
execution for a particular interval. This interval/delay is usually called as interrupt. When
an interrupt request arrives into a current execution program, then it stops its regular
execution. Interrupt can be performed by externally (hardware interrupt) or internally (by
using software).

Bus
BUS is the communication or data transmission/reception path in a microcontroller unit. In
a normal microcontroller chip, two types of buses are normally available.
1) Data bus
Data bus is used for memory addressing. The function of data bus is interfacing all the
circuitry components inside the PIC chip.
2) Address bus
Address bus mostly used for memory addressing. The function of address bus is to transmit
the address from the CPU to memory locations.

USART or UART
These ports are used for the transmission (TX) and reception (RX) of data. These
transmissions possible with help of various digital data transceiver modules like RF, IR,
Bluetooth, etc. This is the one of the simplest way to communicate the PIC chip with other
devices.



Oscillators
Oscillator unit basically an oscillation/clock generating circuit which is used for providing
proper clock pulses to the PIC chip. This clock pulses also helps the timing and counting
applications . A PIC chip normally use various types of clock generators. According to the
application and the type of PIC used, the oscillators and its frequencies may vary. RC
(Resistor-Capacitor), LC (Inductor-Capacitor), RLC (Resistor-Inductor-capacitor), crystal
oscillators, etc are the normal oscillators used with A PIC chip.

STACK
The entire PIC chip has an area for storing the return addresses. This area or unit called
Stack is used in some Peripheral interface controllers. The hardware stack is not accessible
by software. But for most of the controllers, it can be easily accessible.

Input/output ports
These ports are used for the interfacing various input/output devices and memories.
According to the type of PIC, the number of ports may change.


Advanced functioning blocks
These sections include various advanced features of a PIC chip. According to the type of PIC,
these features may change. Various advanced features in a peripheral interface controller
are power up timer, oscillator start up timer, power on reset, watch dog timer, brown out
reset, in circuit debugger, low voltage programming, voltage comparator, CCP modules etc.

Limitations of PIC Architecture
Peripheral Interface Controller has only one accumulator.
Small instruction set.
Register banking switch required to access RAM of other devices.
Operations and registers are not orthogonal.
Program memory is not accessible.

Advantages of PIC Controlled System
Reliability
The PIC controlled system often resides machines that are expected to run continuously for
many years without any error and in some cases recover by themselves if an error
occurs(with help of supporting firmware).
Performance
Many of the PIC based embedded system use a simple pipelined RISC processor for
computation and most of them provide on-chip SRAM for data storage to improve the
performance.
Power consumption
A PIC controlled system operates with minimal power consumption without sacrificing
performance. Power consumption can be reduced by independently and dynamically
controlling multiple power platforms.
Memory
Most of the PIC based systems are memory expandable and will help in easily adding more
and more memory according to the usage and type of application. In small applications the
inbu

The use of each functional block inside this controller has already been explained in the
previous post. Now let us look in to the detailed explanation about each sections inside the
PIC 16F877.

Memory Organization of PIC16F877
The memory of a PIC 16F877 chip is divided into 3 sections. They are
1. Program memory
2. Data memory and
3. Data EEPROM
1. Program memory
Program memory contains the programs that are written by the user. The program counter
(PC) executes these stored commands one by one. Usually PIC16F877 devices have a 13 bit
wide program counter that is capable of addressing 8K14 bit program memory space. This
memory is primarily used for storing the programs that are written (burned) to be used by
the PIC. These devices also have 8K*14 bits of flash memory that can be electrically erasable
/reprogrammed. Each time we write a new program to the controller, we must delete the old
one at that time. The figure below shows the program memory map and stack.

Program counters (PC) is used to keep the track of the program execution by holding the
address of the current instruction. The counter is automatically incremented to the next
instruction during the current instruction execution.
The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space is
not a part of either program or data space and the stack pointers are not readable or
writable. In the PIC microcontrollers, this is a special block of RAM memory used only for
this purpose.
Each time the main program execution starts at address 0000 Reset Vector. The address
0004 is reserved for the interrupt service routine (ISR).
2. PIC16F87XA Data Memory Organization
The data memory of PIC16F877 is separated into multiple banks which contain the general
purpose registers (GPR) and special function registers (SPR). According to the type of the
microcontroller, these banks may vary. The PIC16F877 chip only has four banks (BANK 0,
BANK 1, BANK 2, and BANK4). Each bank holds 128 bytes of addressable memory.

Data Memory Organization

The banked arrangement is necessary because there are only 7 bits are available in the
instruction word for the addressing of a register, which gives only 128 addresses. The
selection of the banks are determined by control bits RP1, RP0 in the STATUS registers
Together the RP1, RP0 and the specified 7 bits effectively form a 9 bit address. The first 32
locations of Banks 1 and 2, and the first 16 locations of Banks2 and 3 are reserved for the
mapping of the Special Function Registers (SFRs).
A bit of RP1 & RP0 of the STATUS register selects the bank access.
3. Data EEPROM and FLASH
The data EEPROM and Flash program memory is readable and writable during normal
operation (over the full VDD range). This memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the Special Function Registers. There are
six SFRs used to read and write this memory:
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
The EEPROM data memory allows single-byte read and writes. The Flash program memory
allows single-word reads and four-word block writes. Program memory write operations
automatically perform an erase-before write on blocks of four words. A byte write in data
EEPROM memory automatically erases the location and writes the new data (erase-before-
write). The write time is controlled by an on-chip timer. The write/erase voltages are
generated by an on-chip charge pump, rated to operate over the voltage range of the device
for byte or word operations.

INPUT/OUTPUT PORTS OF PIC 16F877

PIC 16F877 series normally has five input/output ports. They are used for the input/output
interfacing with other devices/circuits. Most of these port pins are multiplexed for handling
alternate function for peripheral features on the devices. All ports in a PIC chip are bi-
directional. When the peripheral action is enabled in a pin, it may not be used as its general
input/output functions. The PIC 16F877 chip basically has 5 input/output ports. The five
input/output ports and its functions are given below.


BANK RP0 RP1
0 0 0
1 1 0
2 0 1
3 1 1
PORT A and the TRIS A Registers
PORT A is a 6-bit wide bi-directional port, the direction of this port is controlled by TRIS A
data direction register. Setting a TRIS A (=1) makes corresponding PORT A pin as an input,
clearing the TRIS A (=0) making the corresponding PORT A pin as an output
Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI
pin and functioning either input/output operation or Timer 0 clock functioning module.
The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. All other PORT A
pins have TTL input levels and full CMOS output drivers.
Other PORT A pins in this microcontroller multiplexed with analog inputs and the analog
VREF input for both the A/D converters and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON
registers. The TRIS A register controls the direction of the PORT pins even when they are
being used as analog inputs. The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
The block diagram of PORTA register is shown in the figures below.
The functions and the registers associated with PORT A register is given in the table below.
PORT B and the TRIS B Registers
PORT B is also an 8 bit bi-directional PORT. Its direction controlled and maintained by
TRIS B data direction register. Setting the TRIS B into logic 1 makes the
corresponding PORT B pin as an input. Clearing the TRIS B bit make PORT B as an
output. Three pins of PORT B are multiplexed with the In-Circuit Debugger and Low-
Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD for performing its
alternate functions.
The block diagram of PORT B register is given in the figure below.
PORT B functioning table and the registers associated with PORT B is given in the table
below.
PORT C and the TRIS C Registers
PORT C is an 8-bit wide, bidirectional PORT which controlled and maintained by TRIS C
data direction register. Setting a TRIS C bit (= 1) will make the corresponding PORT C pin
an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a
TRIS C bit (= 0) will make the corresponding PORT C pin an output PORT C is also
multiplexed with several peripheral functions. PORT C pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, more care should be taken in defining TRIS bits for
each PORT C pin as compared to other. Some peripherals override the TRIS bit to make a
pin an output, while other peripherals override the TRIS bit to make a pin an input. Since
the TRIS bit override is in effect while the peripheral is enabled, read-modify write
instructions (BSF, BCF, and XORWF) with TRISC as the destination, should be avoided.
The user should refer to the corresponding peripheral section for the correct TRIS bit
settings.
The block diagram of PORT C register is shown in the figures below.
The functions and registers associated with PORT C register is given in the table below.
PORT D and TRIS D Registers
PORT D is an 8-bit PORT with bi-directional nature. This port also with Schmitt Trigger
input buffers, each pin in this PORT D individually configurable as either input or output.
PORT D can be configured as an 8-bit wide microprocessor PORT (functioning as Parallel
Slave PORT) by setting control bit, PSPMODE ((TRISE<4>). In this mode, the input buffers
are TTL.
Block diagram of PORT D is shown in the figure below.
The functions and register associated with PORTD is given in table below.
PORT E and TRIS E Registers
PORT E has only three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are
individually configurable as inputs or outputs. These pins controllable by using its
corresponding data direction register TRIS E. These pins also have Schmitt Trigger input
buffers. The PORT E pins become the I/O control inputs for the microprocessor PORT when
bit PSPMODE is set. In this mode, the user must make certain that the TRIS E bits are set
and that the pins are configured as digital inputs. Also, ensure that ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
TRISE register which also controls the Parallel Slave PORT operation. PORT E pins are
multiplexed with analog inputs. When selected for analog input, these pins will read as 0s.
TRIS E controls the direction of the RE pins, even when they are being used as analog
inputs. The user must make sure to keep the pins configured as inputs when using them as
analog inputs.
The block diagram of PORT E (in input/output mode) is shown in the figure below.
PORT E functions and registers associated with PORT E is given in the table below.




















Timer modules in PIC 16F877
The PIC 16F877 basically has three timer modules. These timer module terminals are also
multiplexed with other functions for handling alternate functions. These timer modules are
usually denoted by the symbols TIMER-0, TIMER-1, and TIMER-2.These modules help to
perform various timing and counting functions inside the chip.

TIMER-0 module
The main timing/counting features of Timer-0 module are given below.
Timer-0 module has built in 8 bit timer/counter
It can be easily readable/writable
Built in 8 bit software programmable pre-scalar functions
Easily select internal/external clock pulses
Interrupt with overflow from the value FFh to 00h
Edge selection for external clock pulse
The block diagram of timer-0 module is given in the figure below. The timer mode is
normally selected by clearing the T0CS bit in the register. In Timer mode, when the Timer
0 Module increases with every instruction cycle, the TMR0 register is written, the increment
is inhibited for the following two instruction cycles. The user can work around this by
writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit
T0CS in Counter mode. Timer 0 will increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by the Timer 0 Source Edge Select bit,
T0SE. Clearing bit T0SE selects the rising edge. The pre-scaler is mutually exclusively
shared between the Timer0 module and the Watchdog Timer.

Timer-0 Interrupt
TMR0 interrupt is activated only when the TMR0 register overflows from the value FFh to
00h. This overflow sets bit TMR0IF .The interrupt can be masked by clearing bit TMR0IE.
Bit TMR0IF must be cleared in software by the Timer 0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt cannot awaken the Processor from
Sleep since the timer is shut-off during Sleep. The main registers associated with timer 0
module is shown in the below table.

Register Memory Organization in Timer 0
TIMER 1 MODULE
Timer 1 module is a 16 bit timer/counter unit. That is, it consists of two 8 bit (8+8) registers
(TMR1H, TMR1L) which read and write easily. TMR1 register is a pair of TMR1H and
TMR1L and also its value increment its value from 0000h to FFFFh and rolls over to
0000h.
Timer 1 module basically operates in two different modes. They are
1) Timer mode
2) Counter mode
The operating mode of timer 1 module is selected by using the clock select bit (TMR1CS), in
timer mode. The timer 1 increases on every instruction cycle. But in counter mode, it
increases on every rising edge of the external clock input. Timer 1 pin can be
enabled/disabled easily by setting/clearing the control bit (TMR1ON). This timer1 pin also
has an internal reset input function. It can be generated by either of the two CCP modules.
The block diagram of timer1 module I given in the image below.

Timer-1 Block Diagram
Timer 1 Operation in Timer Mode
The Timer mode can be easily selected by clearing the TMR1CS bit. In this mode, the input
clock to the timer is FOSC/4. The synchronize control bit, T1SYNC, has no effect since the
internal clock is always in sync. Timer1 Operation in Synchronized
Counter Mode
The synchronized Counter mode is selected by setting timer 1 synchronized counter select
bit (TMR1CS). In this mode, the timer increments on every rising edge of clock input on pin
RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit
T1OSCEN is cleared.
Timer1 Counter Operation
Timer 1 generally operates in two modes. Timer 1 may operate in either a Synchronous, or
an Asynchronous mode, depending on the setting of the timer 1 synchronized counter select
(TMR1CS) bit. When Timer1 is being incremented with an external source, increments
occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment. Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on
every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin
RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external
clock input is synchronized with internal phase clocks. The synchronization is done after the
prescaler stage. The prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not increment even if the external
clock is present since the synchronization circuit is shut-off. The prescaler, however, will
continue to increment.
Timer1 Operation in Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The
timer continues to increment asynchronous to the internal phase clocks. The timer will
continue to run during Sleep and can generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in software are needed to read/write the timer.
In Asynchronous Counter mode, Timer 1 cannot be used as a time base for capture or
compare operations.
Timer 1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-
power oscillator, rated up to 200 kHz. It will continue to run during Sleep. It is primarily
intended for use with a 32 kHz crystal. Below table shows the capacitor selection for the
Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator.

TIMER 2 Module
Timer 2 is an 8-bit timer with a prescaler and a postsaler. It can be used as the PWM (pulse
width modulation) time base for the PWM mode of the CCP module(s). The block diagram
of timer 2 module is given in the figure below.

Timer-2 Block Diagram
The TMR2 register is readable and writable and is cleared on any device Reset. The input
clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer 2 module has an 8-bit period register, PR2.
The value of Timer 2 increments from 00h until it matches PR2 and then resets to 00h on
the next increment cycle. PR2 is a readable and writable register. The PR2 register is
initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler
(which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1<1>)). Timer 2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.