Real Time Edge Detection Modelling With Fpga

Vol 04, Article 06103; June 2013
International Journal of VLSI and Embedded Systems-IJVES

http://ijves.com ISSN: 2249 6556

2010-2013 IJVES
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449
REAL TIME EDGE DETECTION MODELLING WITH FPGA
B.MURALIKRISHNA
1
, P.SUJITHA
2
, HABIBULLA KHAN
3
1
Assistant professor,
2
M TECH VLSI,
3
HOD, Department of ECE, K L University, Vaddeswaram, AP
boppana.muralikrishna@gmail.com, sujithareddy58@yahoo.com, habibulla@kluniversity.in

ABSTRACT
A methodology for implementing the real time image processing applications on Field programmable gate
Arrays is presented in this paper. In this we proposed the algorithms for image edge detection in which variable
scene illumination make edges and object detection difficult. Edge detection is the first step in many computer
vision applications. Edge detection significantly reduces the amount of data and filters out unwanted or
insignificant information and gives the significant information in an image. This information is used in image
processing to detect objects. There are some problems like false edge detection, problems due to noise, missing
of low contrast boundaries etc. This paper presents a comparison between various edge detectors to identify
which edge detector performs better results. These edge detection algorithms are based on MATLAB
simulation and FPGA implementation using Xilinx platform studio and Xilinx ISE.
Keywords: Image Processing, Image Edge Detection, illumination, object Detection, MATLAB, FPGA.

[1] INTRODUCTION
Edge detection is a low level operation used in image processing and computer vision applications. The main
goal of edge detection is to locate and identify sharp discontinuities from an image. These discontinuities are
due to abrupt changes in pixel intensity which characterizes boundaries of objects in a scene. Edges give
boundaries between different regions in the image. These boundaries are used to identify objects for
segmentation and matching purpose .These object boundaries are the first step in many of computer vision
algorithms like edge based face recognition, edge based obstacle detection, edge based target recognition, image
compression etc. So the edge detectors are required for extracting the edges. There are many edge detection
operators available. These operators identifying vertical, horizontal, corner and step edges. The quality of edges
detected by these operators is highly dependent on noise, lighting conditions, objects of same intensities and the
density of edges in the scene. These problems can be solved by adjusting various parameters in the edge detector
and changing the values of threshold for what an edge is considered. These operators are very sensitive to noise
and edges that contain high frequency contents. So removal of noise is required that may result in blurred and
distorted edges. A wide range of operators are available that can extract the edges from noisy image .But these
edges are less accurate. That is due to the presence of noise that they extract false edges. They do not find the
boundaries of object having small change in intensities values. That result in poor localization of edges. So the
operator is required that identify such a gradual change in intensities. So there are problems of false edge
detection, problem due to noise, missing of low contrast boundaries, high computational time etc. Therefore,
objective is to do the comparison between various edge detectors and analyze which edge detector performs
better. The paper is organized as follows: Section 1 explains the introduction of Edge detection.Section 2
presents an overview of related work and background.Section 3 explicates the design flow for image processing.
Section 4 explains the design methodology. Section 5 explains the Experimental Setup.The experimental results
are given in Section 6. Section 7 makes the concluding remarks.

2. RELATED WORK AND BACKGROUND
There are various types of operators available for edge detection. In First order derivative the input
image is convolved by an adapted mask to generate a gradient image in which edges are detected by
thresholding. Most classical operators like Sobel, Prewitt, and Robert are the first order derivative operators.
These operators are also said as gradient operators. These gradient operators detect edges by looking for
maximum and minimum intensity values. These operators examine the distribution of intensity values in the
neighborhood of a given pixel and determine if the pixel is to be classified as an edge. The gradient based
detectors like Sobel, Robert, Prewitt, convolve the input image with their respective convolution mask as shown
in fig 1 to generate a gradient image. Threshold values are used to detect edges. The output of these edge
detectors is very much sensitive to the threshold. The Matlab implementation of these operators uses an
adaptive threshold. These thresholds are dependent on the Root mean square (RMS) estimate of noise in the
image. The predefined kernel matrices for Roberts, Prewitt and Sobel operators are given as
0 0 0 0 0 0 -1 0 1 1 1 1 -1 0 1 -1 -2 -1
Gx= 0 -1 0 Gy= 0 0 -1 Gx= -1 0 1 Gy= 0 0 0 Gx= -2 0 2 Gy= 0 0 0
0 0 1 0 1 0 -1 0 1 -1 -1 -1 -1 0 1 1 2 1

Fig 1: Kernel Matrices for Roberts, Prewitt and Sobel Algorithms


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The Canny edge detection algorithm is known to many as the optimal edge detector. The first and most obvious
is low error rate. It is important that edges occurring in images should not be missed and that there should be
no responses to non-edges. The second criterion is that the edge points be well localized. A third criterion is to
have only one response to a single edge.

3. DESIGN FLOW FOR IMAGE PROCESSING
Fig 2: Using IPIF module in your peripheral Fig 3: Design Flow for Image Processing

The Xilinx Embedded Development Kit (EDK) comes with a large number of commonly used peripherals.
Many different kinds of systems can be created with these peripherals, but it is likely that you may have to
create our own custom peripheral to implement functionality not available in the EDK peripheral libraries and
taruse it in our processor system.EDK uses Intellectual-Property Interface (IPIF) library to implement common
functionality among various processor peripherals. It is verified, optimized and highly parameterizable. It also
gives you a set of simplified bus protocol called IP Interconnect (IPIC) which is much easier to use rather than
operate on OPB or PLB bus protocol directly. Using the IPIF module with parameterization suits our needs
which will greatly reduce our design and test effort.
Base System Builder (BSB) is used from XPS to generate a simple processor system that may use our custom
peripheral. Create and Import Peripheral Wizard (create mode) is used to generate the HDL templates, BFM
Simulation platform, ISE support files and software driver templates under the EDK project that we created.
Project Navigator is used to open the .npl file generated in below step (Create and import peripheral Wizard), to
implement our custom functionality in user_logic.vhd file can or we add extra generics or user I/O to the
peripheral top template file.
Xilinx IP CORE Generator System accelerates design time by providing access to highly parameterized
Intellectual Properties (IP) for Xilinx FPGAs and is included in the ISE Design Suite. These user-customizable
IP functions range in complexity from commonly used functions such as memories and FIFOs to system-level
building blocks such as filters and transforms. The highly optimized IP allows FPGA designers to focus efforts
on building designs quicker. We can also generate HDL to quickly configure FPGA architectural elements
such as MGTs and Ethernet and PCI Express hard blocks using the integrated LogiCORE GUI-based
customizers and Core Generator Architecture Wizards. Specific IP from the CORE Generator IP catalog can be
used in the designer methodology for Logic designers using Project Navigator ,for DSP algorithm designers
using Xilinx System Generator and for Embedded designers using Xilinx Platform Studio (XPS).In IP core
generator wizard we have to store our image in block RAM in .COE format and after storing the image we
have to generate the core.
After generating the IP core synthesize the top module and implement the design i.e Translate, Map, Place and
Route has to be done. After that generate the Bit file, this bitfile has to be downloaded into the target FPGA
board. We can observe the outputs in VGA monitor.
The term Video Graphics Array (VGA) refers either to an analog computer display standard, or the 640480
resolution. A VGA video signal contains 5 active signals. They are HSYNC, VSYNC, RED, BLUE,
GREEN.By changing the analog levels of the three RGB signals all other colors are produced. The screen
refresh process begins in the top left corner and paints 1 pixel at a time from left to right. At the end of the first
row, the row increments and the column address is reset to the first column. Once the entire screen has been
painted, the refresh process begins again. The video signal must redraw the entire screen 60 times per second to
provide motion in the image and to reduce flicker,this period is called the refresh rate(60HZ,25MHZ Clock
Frequency).


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Fig 4: VGA Screen Fig 5:640x480 Resolution VGA Screen
The vertical sync signal tells the monitor to start displaying a new image or frame, and the monitor starts in the
upper left corner with pixel (0,0) The horizontal sync signal tells the monitor to refresh another row of 640
pixels After 480 rows of pixels are refreshed with 480 horizontal sync signals, a vertical sync signal resets the
monitor to the upper left corner and the process continues.

Fig 6: Core Schematic Symbol

4. DESIGN METHODOLOGY
First of all in Xilinx platform studio we have to generate a base system builder(BSB) to generate a processor by
creating a new folder .In order to create our own peripheral according to our application goto to Hardware in
tool bar of XPS and Click Create and import peripheral wizard , so this wizard will guide us with the necessary
steps to build the required files and connect our new peripheral (both hardware and software) and so will be
able to add our own VHDL code into the new design to implement the required function.The new peripheral is
stored in our project local directory and so it will be accessible only in our project.In the next step we have to
enter a required peripheral name which allows us to create different revisions of the same core and the last step
in create or import peripheral wizard is to generate the user_logic module in Verilog or VHDL This option is
used to generate an ISE project which help in the implementation of the core. The generated ISE project can be
used to verify the core before integrating to the EDK. The steps are now completed and the template for our
design will be created. The wizard creates all necessary files required for the core and these files are located in
the local directory of our project. The files created are stored in two main directories pcores and drivers.
The first includes all the files for the hardware build while the second contains the software drivers created by
the wizard. In both directories we will find another directory for our core with the name mycore Open
pcores mycore ,we find three directories in that. They are data which contains the files required to define
the core to the EDK.
The EDK reads the files inside this directory to identify the bus connections of the core, and the hardware files
required to build the core devl which contains the files for the ISE project and hdl which contains the HDL
files for the core .Next open the folder devl in which there will be the directory named as projnav which
contains the files of the ISE project navigator to edit the source files of our core. In Projnav we find the ISE
project file mycore.vhd ,open that ISE project in XILINX ISE..In XILINX ISE,mycore.vhd will get opened
which contains USER_LOGIC.vhd.Open USER_LOGIC.vhd which contains entity and architecture
declarations.
The entity declaration contains the required ports for data and control signals. The signals Bus2IP_Data and
IP2Bus_Data are 32-bits data signals that are used to transfer data from/to the core. The signals
Bus2IP_RdCE and Bus2IP_WeCE are the read enable and write enable signals for each register of the
created core. The architecture block contains several signals like signal declarations, register selection signals
etc.In the architecture declaration we have to develop our code according to the application. After completion of
writing code create the IP core generator in which an image has to be stored (.COE format) in block RAM and
we have to specify the width and depth of an image. After specifying the widths and depth of an image
generate the IP core. After generating the IP core synthesize the top module and we have to generate the bit file
(.bit).We have to download that bit file into SPARTEN 3E FPGA (XC3S500E).We can observe outputs on
VGA monitor.


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5. EXPERIMENTAL SETUP
A) Create and Import Peripheral Wizard:

Fig 7: Create and Import Peripheral Wizard flow

Fig 8: Create and Import Peripheral Wizard flow

Fig 9: Successful Creation of Template for our Design Fig 10: ISE Project for for mycore

Fig 11: Selecting IP from Core Fig 12: Selection of Memory Fig 13: Selection of Block Fig 14: Block Memory
Generator Wizard Storage Elements Memory IP core IP Wizard


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Fig15: Initializing .COE File Fig 16: Successful Creation of IP Core

6. RESULTS:

Fig 17:Original Image Fig 18: Thresholded Image Fig 19: Negative Image Fig 20: Roberts
Algorithm

Fig 21: Prewitt Algorithm Fig 22: Sobel Algorithm Fig 23: Canny Algorithm

Fig 24 Efficiency of Roberts Algorithm Fig 25 Efficiency of Prewitt Algorithm

Fig 26 Efficiency of Sobel Algorithm Fig 27 Efficiency of Canny Algorithm


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Logic Utilization Roberts Prewitt Sobel Canny
No of Slice FFs 598 345 322 70
No of 4 input LUTs 896 343 343 128
No of Slices 776 234 221 88
No of bonded IOBs 123 87 87 19
No of RAMB 16s 17 13 13 11
No of BUFGMUXs 9 6 4 2
Tab 1 Device Utilization Summary and comparison of various Edge Detection Algorithms

CONCLUSION
Edge Detection is the first step in Object recognition, so in this paper we compare different Edge Detection
algorithms. In this we created our own IP Core for our application i.e. edge Detection and this core is added to
the Xilinx Library and integrates into our design and we add VHDL code according to our functionality. Finally
we will able to build our own embedded system and we add our own design to that system and we execute the
complete system on FPGA.From all the four implemented Edge detection algorithms Canny Edge Detection
algorithm provides best results with no losses in the edges and it also consumes less hardware resources.

REFERENCES
[1] Jain, Anil K. (1989). Fundamentals of Digital Image Processing, Prentice-Hall, Inc.
[2] Chanda, B. and Dutta, D. Majumdar. (2001). Digital Image Processing and Analysis, Prentice-Hall of India.
[3] Gonzalez, Rafael C. and Woods, Richard E. (2002). Digital Image Processing, Pearson Education, Inc.
[4] Pratt, W. K. (2004). Digital Image Processing, John Wiley & Sons, Inc.
[5] Spartan FPGA Complete Data Sheet Xilinx Inc.
[6] B.Murali Krishna, Gnana deepika (2012),Image Processing Using IP Core Generator through FPGA.
[7] M. Wen and C. Zhong, Application of Sobel Algorithm in Edge Detection of Images, China High-tech
Enterprise, pp.57-62, Jun. 2008,(in Chinese).
[8]Xilinx Inc. MicroBlaze Reference Manual, version 10.1. [9] Xilinx Inc. Xilinx ISE and Xilinx EDK tools.
[10] Arrigo Benedetti, Andrea Prati, Nello ScarabottoloImage convolution on FPGAs: the implementation of a
multi-FPG FIFO structure. Euromicro Conference, 1998.
[12] Gan Jinlai. Comparative study of the image edge detection algorithm University of electronic science and
technology, 2005.
[13]Steve Kilts, Advanced FPGA Design: Arichitecture Implementation, and Optimization, John Tiley & Sons

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Vol 04, Article 06103; June 2013

International Journal of VLSI and Embedded Systems-IJVES

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