Data Sheet
High Performance
Digital Signal Controllers
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
UART
SPI™
I2C™
CAN
SRAM EEPROM Timer Input A/D 10-bit Quad
Device Pins Mem. Bytes/ Comp/Std Control
Bytes Bytes 16-bit Cap 500 Ksps Enc
Instructions PWM PWM
* This table provides a summary of the dsPIC30F6010 peripheral features. Other available devices in the dsPIC30F
Motor Control and Power Conversion Family are shown for feature comparison.
40-Pin PDIP
MCLR 1 40 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 39 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 38 PWM1L/RE0
AN2/SS1/CN4/RB2 4 37 PWM1H/RE1
AN3/INDX/CN5/RB3 5 36 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 35 PWM2H/RE3
dsPIC30F4011
AN5/QEB/IC8/CN7/RB5 7 34 PWM3L/RE4
AN6/OCFA/RB6 8 33 PWM3H/RE5
AN7/RB7 9 32 VDD
AN8/RB8 10 31 VSS
VDD 11 30 C1RX/RF0
VSS 12 29 C1TX/RF1
OSC1/CLKIN 13 28 U2RX/CN17/RF4
OSC2/CLKO/RC15 14 27 U2TX/CN18/RF5
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 PGD/EMUD/U1TX/SDO1/SCL/RF3
FLTA/INT0/RE8 17 24 SCK1/RF6
EMUD2/OC2/IC2/INT2/RD1 18 23 EMUC2/OC1/IC1/INT1/RD0
OC4/RD3 19 22 OC3/RD2
VSS 20 21 VDD
44-Pin TQFP
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
SCK1/RF6
OC3/RD2
OC4/RD3
VDD
VSS
NC
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 NC
U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15
CTX1/RF1 4 30 OSC1/CLKIN
CRX1/RF0 5 29 VSS
VSS 6 28 VDD
VDD
dsPIC30F4011 AN8/RB8
7 27
PWM3H/RE5 8 26 AN7/RB7
PWM3L/RE4 9 25 AN6/OCFA/RB6
PWM2H/RE3 10 24 AN5/QEB/IC8/CN7/RB5
PWM2L/RE2 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
AN2/SS1/CN4/RB2
NC
NC
PWM1L/RE0
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN3/INDX/CN5/RB3
PWM1H/RE1
AVDD
AVSS
44-Pin QFN
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUD2/OC2/IC2/INT2/RD1
EMUC2/OC1/IC1/INT1/RD0
FLTA/INT0/RE8
SCK1/RF6
OC4/RD3
OC3/RD2
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
U2TX/CN18/RF5 2 32 OSC1/CLKIN
U2RX/CN17/RF4 3 31 VSS
CTX1/RF1 4 30 VSS
CRX1/RF0 5 29 VDD
VSS 6 dsPIC30F4011 28 VDD
VDD 7 27 AN8/RB8
VDD 8 26 AN7/RB7
PWM3H/RE5 9 25 AN6/OCFA/RB6
PWM3L/RE4 10 24 AN5/QEB/IC8/CN7/RB5
PWM2H/RE3 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
EMUC3/AN1/VREF-/CN3/RB1
PWM2L/RE2
MCLR
NC
PWM1L/RE0
AVSS
AVDD
AN2/SS1/CN4/RB2
PWM1H/RE1
EMUD3/AN0/VREF+/CN2/RB0
AN3/INDX/CN5/RB3
28-Pin SPDIP
28-Pin SOIC
MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 PWM1L/RE0
AN2/SS1/CN4/RB2 PWM1H/RE1
dsPIC30F4012
4 25
AN3/INDX/CN5/RB3 5 24 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 23 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 22 PWM3L/RE4
VSS 8 21 PWM3H/RE5
OSC1/CLKIN 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
VDD 13 16 FLTA/INT0/SCK1/OCFA/RE8
EMUD2/OC2/IC2/INT2/RD1 14 15 EMUC2/OC1/IC1/INT1/RD0
44-Pin QFN
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
FLTA/INT0/SCK1/OCFA/RE8
EMUD2/OC2/IC2/INT2/RD1
EMUC2/OC1/IC1/INT1/RD0
VDD
VDD
VSS
NC
NC
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 1 33 OSC2/CLKO/RC15
NC 2 32 OSC1/CLKIN
NC 3 31 VSS
NC 4 30 VSS
NC 5 29 VDD
VSS 6 28 VDD
dsPIC30F4012 NC
VDD 7 27
VDD 8 26 NC
PWM3H/RE5 9 25 NC
PWM3L/RE4 10 24 AN5/QEB/IC8/CN7/RB5
PWM2H/RE3 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
PWM2L/RE2
NC
PWM1L/RE0
AVSS
AVDD
MCLR
PWM1H/RE1
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Y Data Bus
X Data Bus
16 16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table Y Data
Data Access X Data
24 Control Block 8 16 RAM RAM
(1 Kbyte) (1 Kbyte)
Address Address
24 Latch Latch
16 16 16
24 X RAGU AN0/EMUD3/VREF+/CN2/RB0
Y AGU
PCU PCH PCL X WAGU AN1/EMUC3/VREF-/CN3/RB1
Program Counter AN2/SS1/CN4/RB2
Address Latch Stack Loop AN3/INDX/CN5/RB3
Control Control AN4/QEA/CN6/IC7/RB4
Program Memory Logic Logic
AN5/QEB/CN7/IC8/RB5
(48 Kbytes)
AN6/OCFA/RB6
Data EEPROM AN7/RB7
(1 Kbyte) Effective Address AN8/RB8
Data Latch 16 PORTB
ROM Latch 16
24
IR
EMUD1/SOSCI/CN1/T2CK/U1ATX/RC13
16 16 EMUC1/SOSCO/T1CK/CN0/U1ARX/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array PORTC
Decode
Instruction
Decode and 16 16
Control
Input Output
CAN 10-bit ADC Capture Compare I2C
PWM1L/RE0
Module Module
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
Motor Control UART1, FLTA/INT0/RE8
SPI1 Timers QEI
PWM UART2
PORTE
C1RX/RF0
C1TX/RF1
U1RX/PGC/EMUC/SDI1/SDA/RF2
U1TX/PGD/EMUD/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
SCK1/RF6
PORTF
Y Data Bus
X Data Bus
16 16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV & Table Y Data
Data Access X Data
24 Control Block 8 16 RAM RAM
(1 Kbyte) (1 Kbyte)
Address Address
24 Latch Latch
16 16 16
24 X RAGU
Y AGU
PCU PCH PCL X WAGU
AN0/CN2/VREF+/EMUD2/RB0
Program Counter
AN1/CN3/VREF-/EMUC3/RB1
Address Latch Stack Loop AN2/SS1/CN4/RB2
Control Control
Program Memory Logic Logic AN3/INDX/CN5/RB3
(48 Kbytes) AN4/QEA/CN6/IC7/RB4
AN5/QEB/CN7/IC8/RB5
Data EEPROM
(1 Kbyte) Effective Address PORTB
Data Latch 16
ROM Latch 16
24
IR
EMUD1/SOSCI/CN1/T2CK/U1ATX/RC13
16 16 EMUC1/SOSCO/T1CK/CN0/U1ARX/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array PORTC
Decode
Instruction
Decode and 16 16
Control
Input Output
CAN 10-bit ADC Capture Compare I2C
PWM1L/RE0
Module Module
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
SPI1, Motor Control UART1, FLTA/INT0/SCK1/OCFA/RE8
Timers QEI
SPI2 PWM UART2
PORTE
U1RX/PGC/EMUC/SDI1/SDA/RF2
U1TX/PGD/EMUD/SDO1/SCL/RF3
PORTF
D15 D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
PC22 PC0
0 Program Counter
7 0
TABPAG
TBLPAG Data Table Page Address
7 0
PSVPAG Program Space Visibility Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter
22 0
DOSTART DO Loop Start Address
22
DOEND DO Loop End Address
15 0
CORCON Core Configuration Register
SRH SRL
S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder
Negate
40
40 40
Barrel
16
Shifter
X Data Bus
40
Sign-Extend
Y Data Bus
32 16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16 16
To/From W Array
User Memory
incremented by two between successive program Alternate Vector Table 000084
Space
0000FE
words, in order to provide compatibility with data space User Flash 000100
addressing. Program Memory
(16K instructions)
User program space access is restricted to the lower 007FFE
4M instruction word address range (0x000000 to 008000
Reserved
0x7FFFFE), for all accesses other than TBLRD/TBLWT, (Read 0’s)
which use TBLPAG<7> to determine user or configura- 7FFBFE
tion space access. In Table 3-1, Read/Write instruc- 7FFC00
Data EEPROM
tions, bit 23 allows access to the Device ID, the User ID (1 Kbytes)
and the configuration bits. Otherwise, bit 23 is always 7FFFFE
clear. 800000
Reserved
Configuration Memory
8005BE
Space
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
F7FFFE
Device Configuration F80000
Registers F8000E
F80010
Reserved
FEFFFE
DEVID (2) FF0000
FFFFFE
23 bits
Using
Program 0 Program Counter 0
Counter
Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits
EA
User/ Byte
Configuration 24-bit EA
Space Select
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDL.B (Wn<0> = 0)
Program Memory TBLRDL.W
‘Phantom’ Byte
TBLRDL.B (Wn<0> = 1)
(Read as ‘0’).
TBLRDH.W
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’) TBLRDH.B (Wn<0> = 1)
3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each pro-
MEMORY USING PROGRAM gram memory word, the LS 15 bits of data space
SPACE VISIBILITY addresses directly map to the LS 15 bits in the corre-
sponding program space addresses. The remaining
The upper 32 Kbytes of data space may optionally be bits are provided by the Program Space Visibility Page
mapped into any 16K word program space page. This register, PSVPAG<7:0>, as shown in Figure 3-5.
provides transparent access of stored constant data
from X data space, without the need to use special Note: PSV access is temporarily disabled during
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Table Reads/Writes.
Program space access through the data space occurs For instructions that use PSV which are executed
if the MS bit of the data space EA is set and program outside a REPEAT loop:
space visibility is enabled, by setting the PSV bit in the • The following instructions will require one instruc-
Core Control register (CORCON). The functions of tion cycle in addition to the specified execution
CORCON are discussed in Section 2.4, DSP Engine. time:
Data accesses to this area add an additional cycle to - MAC class of instructions with data operand
the instruction being executed, since two program pre-fetch
memory fetches are required. - MOV instructions
Note that the upper half of addressable data space is - MOV.D instructions
always part of the X data space. Therefore, when a • All other instructions will require two instruction
DSP operation uses program space mapping to access cycles in addition to the specified execution time
this memory region, Y data space should typically con- of the instruction.
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient For instructions that use PSV which are executed
(constant) data. inside a REPEAT loop:
Although each data space address, 0x8000 and higher, • The following instances will require two instruction
maps directly into a corresponding program memory cycles in addition to the specified execution time
address (see Figure 3-5), only the lower 16-bits of the of the instruction:
24-bit program word are used to contain the data. The - Execution in the first iteration
upper 8 bits should be programmed to force an illegal - Execution in the last iteration
instruction to maintain machine robustness. Refer - Execution prior to exiting the loop due to an
to the dsPIC30F Programmer’s Reference Manual interrupt
(DS70030) for details on instruction encoding.
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
15 PSVPAG(1)
EA<15> = 0 0x00
8
Data 16
Space 0x8000
EA 15 23 15 0
Address
EA<15> = 1 0x001200
15 Concatenation 23
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2 Data Address Space When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64
The core has two data spaces. The data spaces can be Kbyte data address space (including all Y addresses).
considered either separate (for some DSP instruc- When executing one of the MAC class of instructions,
tions), or as one unified linear address range (for MCU the X block consists of the 64 Kbyte data address
instructions). The data spaces are accessed using two space excluding the Y address block (for data reads
Address Generation Units (AGUs) and separate data only). In other words, all other instructions regard the
paths. entire data memory as one composite address space.
The MAC class instructions extract the Y address space
3.2.1 DATA SPACE MEMORY MAP from data space and address it using EAs sourced from
The data space memory is split into two blocks, X and W10 and W11. The remaining X data space is
Y data space. A key element of this architecture is that addressed using W8 and W9. Both address spaces are
Y space is a subset of X space, and is fully contained concurrently accessed only with the MAC class
within X space. In order to provide an apparent linear instructions.
addressing space, X and Y spaces have contiguous A data space memory map is shown in Figure 3-6.
addresses.
Figure 3-7 shows a graphical summary of how X and Y
data spaces are accessed for MCU and DSP
instructions.
MS Byte LS Byte
Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
0x0FFF 0x0FFE
0x1001 0x1000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE
X SPACE
UNUSED
X SPACE
X SPACE
UNUSED
Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11
DS70135C-page 32
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
dsPIC30F4011/4012
Preliminary
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000
TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000
PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Preliminary
DS70135C-page 33
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
Byte
Address MOV #0x1100,W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
0x1100 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
0x1163
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
2. The stack pointer is loaded with a value which is Math Error Trap Vector
Priority
DS70135C-page 46
IFS1 0086 — — — — C1IF — U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — — FLTAIF — — QEIIF PWMIF — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E — — — — C1IE — U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — — FLTAIE — — QEIIE PWMIE — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100
dsPIC30F4011/4012
Preliminary
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
The dsPIC30F family of devices contains internal 6.3 Table Instruction Operation Summary
program Flash memory for executing user code. There
are two methods by which the user can program this The TBLRDL and the TBLWTL instructions are used to
memory: read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
1. In-Circuit Serial Programming™ (ICSP™)
Word or Byte mode.
2. Run Time Self-Programming (RTSP)
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
6.1 In-Circuit Serial Programming
and TBLWTH can access program memory in Word or
(ICSP) Byte mode.
dsPIC30F devices can be serially programmed while in A 24-bit program memory address is formed using
the end application circuit. This is simply done with two bits<7:0> of the TBLPAG register and the effective
lines for Programming Clock and Programming Data address (EA) from a W register specified in the table
(which are named PGC and PGD respectively), and instruction, as shown in Figure 6-1.
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). this allows customers to manu-
facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
24 bits
Using
Program 0 Program Counter 0
Counter
NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits
Working Reg EA
Byte
User/Configuration Select
Space Select 24-bit EA
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Read TRIS
I/O Cell
TRIS Latch
Data Bus D Q
WR TRIS CK
Data Latch
D Q I/O Pad
WR LAT +
CK
WR Port
Read LAT
Read Port
PIO Module 1
Output Data
0
Read TRIS
I/O Pad
Data Bus D Q
WR TRIS CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
8.2 Configuring Analog Port Pins 8.2.1 I/O PORT WRITE/READ TIMING
The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port
operation of the A/D port pins. The port pins that are direction change or port write operation and a read
desired as analog inputs must have their correspond- operation of the same port. Typically this instruction
ing TRIS bit set (input). If the TRIS bit is cleared (out- would be a NOP.
put), the digital output level (VOH or VOL) will be
converted. EXAMPLE 8-1: PORT WRITE/READ
When reading the PORT register, all pins configured as EXAMPLE
analog input channel will read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
Pins configured as digital inputs will not convert an ana- MOV W0, TRISBB ; and PORTB<7:0> as outputs
log input. Analog levels on any pin that is defined as a NOP ; Delay 1 cycle
digital input (including the ANx pins), may cause the btss PORTB, #13 ; Next Instruction
input buffer to consume current that exceeds the
device specifications.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
DS70135C-page 59
dsPIC30F4011/4012
TABLE 8-2: dsPIC30F4012 PORT REGISTER MAP
SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
TRISB 02C6 — — — — — — — — — — TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111
PORTB 02C8 — — — — — — — — — — RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB — — — — — — — — — — LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
DS70135C-page 60
TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000
PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000
TRISD 02D2 — — — — — — — — — — — — — — TRISD1 TRISD0 0000 0000 0000 0011
PORTD 02D4 — — — — — — — — — — — — — — RD1 RD0 0000 0000 0000 0000
LATD 02D6 — — — — — — — — — — — — — — LATD1 LATD0 0000 0000 0000 0000
TRISE 02D8 — — — — — — — TRISE8 — — TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0001 0011 1111
PORTE 02DA — — — — — — — RE8 — — RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
LATE 02DC — — — — — — — LATE8 — — LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000
TRISF 02EE — — — — — — — — — — — — TRISF3 TRISF2 — — 0000 0000 0000 1100
dsPIC30F4011/4012
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
8.3 Input Change Notification Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This module is capable of
detecting input change-of-states even in Sleep mode,
when the clocks are disabled. There are 10 external
signals (CN0 through CN7, CN17 and CN18) that may
be selected (enabled) for generating an interrupt
request on a change-of-state.
Please refer to the Pin Diagrams for CN pin locations.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
PR1
Equal
Comparator x 16 TSYNC
1 Sync
(3)
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
SOSCO/ TON 2
1X
T1CK
SOSCI
TCY 00
C1
SOSCI
C1 = C2 = 18 pF; R = 100K
DS70135C-page 66
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the LS
Word and Timer3 is the MS Word of the 32-bit timer.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete Note: For 32-bit timer operation, T3CON control
reference source. For more information on the CPU, bits are ignored. Only T2CON control bits
peripherals, register descriptions and general device are used for setup and control. Timer 2
functionality, refer to the dsPIC30F Family Reference clock and gate inputs are utilized for the
Manual (DS70046).
32-bit timer module, but an interrupt is
This section describes the 32-bit General Purpose generated with the Timer3 interrupt flag
(GP) Timer module (Timer2/3) and associated opera- (T3IF) and the interrupt is enabled with the
tional modes. Figure 10-1 depicts the simplified block Timer3 Interrupt Enable bit (T3IE).
diagram of the 32-bit Timer2/3 module. Figure 10-2 16-bit Mode: In the 16-bit mode, Timer2 and Timer3
and Figure 10-3 show Timer2/3 configured as two can be configured as two independent 16-bit timers.
independent 16-bit timers; Timer2 and Timer3, Each timer can be set up in either 16-bit Timer mode or
respectively. 16-bit Synchronous Counter mode. See Section 9.0,
Note: Timer2 is a ‘Type B’ timer and Timer3 is a Timer1 Module, for details on these two operating
‘Type C’ timer. Please refer to the appro- modes.
priate timer type in Section 24.0 Electrical The only functional difference between Timer2 and
Characteristics of this document. Timer3 is that Timer2 provides synchronization of the
The Timer2/3 module is a 32-bit timer, which can be clock prescaler output. This is useful for high frequency
configured as two 16-bit timers, with selectable operat- external clock inputs.
ing modes. These timers are utilized by other 32-bit Timer Mode: In the 32-bit Timer mode, the timer
peripheral modules such as: increments on every instruction cycle up to a match
• Input Capture value, preloaded into the combined 32-bit period regis-
• Output Compare/Simple PWM ter PR3/PR2, then resets to 0 and continues to count.
The following sections provide a detailed description, For synchronous 32-bit reads of the Timer2/Timer3
including setup and control registers, along with asso- pair, reading the LS word (TMR2 register) will cause
ciated block diagrams for the operational modes of the the MS word to be read and latched into a 16-bit
timers. holding register, termed TMR3HLD.
The 32-bit timer has the following modes: For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
• Two independent 16-bit timers (Timer2 and a write to the TMR2 register, the contents of TMR3HLD
Timer3) with all 16-bit operating modes (except will be transferred and latched into the MSB of the
Asynchronous Counter mode) 32-bit timer (TMR3).
• Single 32-bit Timer operation
32-bit Synchronous Counter Mode: In the 32-bit
• Single 32-bit Synchronous Counter Synchronous Counter mode, the timer increments on
Further, the following operational characteristics are the rising edge of the applied external clock signal,
supported: which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
• ADC Event Trigger
combined 32-bit period register PR3/PR2, then resets
• Timer Gate Operation to ‘0’ and continues.
• Selectable Prescaler Settings
When the timer is configured for the Synchronous
• Timer Operation during Idle and Sleep modes Counter mode of operation and the CPU goes into the
• Interrupt on a 32-bit Period Register Match Idle mode, the timer will stop incrementing, unless the
These operating modes are determined by setting the TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
appropriate bit(s) in the 16-bit T2CON and T3CON module logic will resume the incrementing sequence
SFRs. upon termination of the CPU Idle mode.
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3 TMR2 Sync
MSB LSB
ADC Event Trigger
Comparator x 32
Equal
PR3 PR2
0
T3IF
Event Flag 1 Q D TGATE(T2CON<6>)
Q CK
TGATE
(T2CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Prescaler
Gate 1, 8, 64, 256
Sync 01
TCY
00
Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
PR2
Equal
Comparator x 16
TMR2 Sync
Reset
0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR3
TMR3
Reset
0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
Sync 1X
Prescaler
01 1, 8, 64, 256
TCY 00
Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER3. In these devices the following
modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)
Preliminary
DS70135C-page 71
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
Data Bus<15:0>
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
TMR5 TMR4 Sync
MSB LSB
Comparator x 32
Equal
PR5 PR4
0
T5IF
Event Flag 1 Q D TGATE(T4CON<6>)
Q CK
TGATE
TGATE
(T4CON<6>)
TCS
TCKPS<1:0>
TON 2
1X
Prescaler
Gate 1, 8, 64, 256
Sync 01
TCY 00
Note: Timer Configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All
control bits are respective to the T4CON register.
The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices the following modes should not be used: (1) TCS = 1, (2) TCS = 0 and (3) TGATE = 1 (gated
time accumulation)
PR4
Equal
Comparator x 16
TMR4 Sync
Reset
0
T4IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
1X
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices the following modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)
PR5
TMR5
Reset
0
T5IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
Sync 1X
Prescaler
01 1, 8, 64, 256
TCY 00
Note: The dsPIC30F4011/4012 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices the following modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)
DS70135C-page 76
PR5 011C Period Register 5 1111 1111 1111 1111
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 0000 0000 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
12.0 INPUT CAPTURE MODULE The key operational features of the Input Capture
module are:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• Simple Capture Event mode
reference source. For more information on the CPU, • Timer2 and Timer3 mode selection
peripherals, register descriptions and general device • Interrupt on input capture event
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). These operating modes are determined by setting the
appropriate bits in the ICxCON register (where x =
This section describes the Input Capture module and
1,2,...,N). The dsPIC30F4011/4012 devices have 4
associated operational modes. The features provided
capture channels.
by this module are useful in applications requiring
Frequency (Period) and Pulse measurement. Note: The dsPIC30F4011/4012 devices have
Figure 12-1 depicts a block diagram of the Input four capture inputs: IC1, IC2, IC7 and IC8.
Capture module. Input capture is useful for such modes The naming of these four capture chan-
as: nels is intentional and preserves software
• Frequency/Period/Pulse Measurements compatibility with other dsPIC devices.
• Additional sources of External Interrupts
16 16
ICx ICTMR
Pin 1 0
Edge FIFO
Prescaler Clock Detection R/W
1, 4, 16 Synchronizer Logic Logic
3 ICM<2:0> ICxBUF
Mode Select
ICBNE, ICOV
ICI<1:0>
Interrupt
ICxCON Logic
Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.
IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
DS70135C-page 80
IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
13.0 OUTPUT COMPARE MODULE The key operational features of the Output Compare
module include:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• Timer2 and Timer3 Selection mode
reference source. For more information on the CPU, • Simple Output Compare Match mode
peripherals, register descriptions and general device • Dual Output Compare Match mode
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). • Simple PWM mode
• Output Compare during Sleep and Idle modes
This section describes the Output Compare module
and associated operational modes. The features pro- • Interrupt on Output Compare/PWM Event
vided by this module are useful in applications requiring These operating modes are determined by setting the
operational modes such as: appropriate bits in the 16-bit OCxCON SFR (where x =
• Generation of Variable Width Output Pulses 1,2,3,...,N). The dsPIC30F4011/4012 devices have 4/2
compare channels, respectively.
• Power Factor Correction
OCxRS and OCxR in the figure represent the Dual
Figure 13-1 depicts a block diagram of the Output
Compare registers. In the dual compare mode, the
Compare module.
OCxR register is used for the first compare and OCxRS
is used for the second compare.
OCxRS
3 Output Enable
OCM<2:0>
Comparator Mode Select OCFA
(for x = 1, 2, 3 or 4)
OCTSEL
0 1 0 1
Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
13.3 Dual Output Compare Match Mode The user must perform the following steps in order to
configure the output compare module for PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation:
or 101, the selected output compare channel is config-
1. Set the PWM period by writing to the appropriate
ured for one of two Dual Output Compare modes,
period register.
which are:
2. Set the PWM duty cycle by writing to the OCxRS
• Single Output Pulse mode register.
• Continuous Output Pulse mode 3. Configure the output compare module for PWM
operation.
13.3.1 SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1.
of a single output pulse, the following steps are
required (assuming timer is off): 13.4.1 INPUT PIN FAULT PROTECTION
• Determine instruction cycle time TCY. FOR PWM
• Calculate desired pulse width value based on TCY. When control bits OCM<2:0> (OCxCON<2:0>) = 111,
• Calculate time to start pulse from timer start value the selected output compare channel is again config-
of 0x0000. ured for the PWM mode of operation, with the addi-
• Write pulse width start and stop times into OCxR tional feature of input fault protection. While in this
and OCxRS compare registers (x denotes mode, if a logic 0 is detected on the OCFA/B pin, the
channel 1, 2, ...,N). respective PWM output pin is placed in the high imped-
ance input state. The OCFLT bit (OCxCON<4>) indi-
• Set timer period register to value equal to, or
cates whether a FAULT condition has occurred. This
greater than, value in OCxRS compare register.
state will be maintained until both of the following
• Set OCM<2:0> = 100. events have occurred:
• Enable timer, TON (TxCON<15>) = 1.
• The external FAULT condition has been removed.
To initiate another single pulse, issue another write to • The PWM mode has been re-enabled by writing
set OCM<2:0> = 100. to the appropriate control bits.
Duty Cycle
DS70135C-page 84
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
OC3RS* 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R* 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON* 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS* 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R* 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON* 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit, * = not available on dsPIC30F4012
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
14.0 QUADRATURE ENCODER The operational features of the QEI include:
INTERFACE (QEI) MODULE • Three input channels for two phase signals and
index pulse
Note: This data sheet summarizes features of this group • 16-bit up/down position counter
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU, • Count direction status
peripherals, register descriptions and general device • Position Measurement (x2 and x4) mode
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). • Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
This section describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes. • Quadrature Encoder Interface interrupts
The QEI module provides the interface to incremental These operating modes are determined by setting the
encoders for obtaining mechanical position data. appropriate bits QEIM<2:0> (QEICON<10:8>).
Figure 14-1 depicts the Quadrature Encoder Interface
block diagram.
TQCKPS<1:0>
Sleep Input TQCS
2
TCY
0
Synchronize
Prescaler
Det 1 1, 8, 64, 256
1
QEIM<2:0>
0
QEIIF
D Q
TQGATE Event
CK Q Flag
Programmable
QEB
Digital Filter
Programmable
INDX
Digital Filter
Up/Down
Note: In dsPIC30F4011/4012, the UPDN pin is not available. Up/Down logic bit can still be polled by software.
Note: QEI pins are multiplexed with analog inputs. User must insure that all QEI associated pins are set as digital
inputs in the ADPCFG register.
Preliminary
DS70135C-page 89
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
PWMCON1
PWM Enable and Mode SFRs
PWMCON2
PWM Manual
OVDCON
Control SFR
PWM Generator #3
PDC3 Buffer
16-bit Data Bus
PDC3
FLTA
PTPER Buffer
PTCON
SEVTCMP PTDIR
PWMxH
PWMxL
DS70135C-page 100
PWMCON1 01C8 — — — — — PTMOD3 PTMOD2 PTMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 1111 1111
PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — — OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC — — — — — — — — DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
16.0 SPI™ MODULE In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
Note: This data sheet summarizes features of this group value is written to SPI1BUF. The interrupt is generated
of dsPIC30F devices and is not intended to be a complete at the middle of the transfer of the last bit.
reference source. For more information on the CPU,
peripherals, register descriptions and general device In Slave mode, data is transmitted and received as
functionality, refer to the dsPIC30F Family Reference external clock pulses appear on SCK. Again, the inter-
Manual (DS70046). rupt is generated when the last bit is latched. If SSx
The Serial Peripheral Interface (SPI) module is a syn- control is enabled, then transmission and reception
chronous serial interface. It is useful for communicating are enabled only when SSx = low. The SDOx output
with other peripheral devices such as EEPROMs, shift will be disabled in SSx mode with SSx high.
registers, display drivers and A/D converters, or other The clock provided to the module is (FOSC/4). This
microcontrollers. It is compatible with Motorola's SPI clock is then prescaled by the primary (PPRE<1:0>)
and SIOP interfaces. and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
16.1 Operating Function Description tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
The SPI module consists of a 16-bit shift register, for the clock.
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. A control register, SPI1CON, 16.1.1 WORD AND BYTE
configures the module. Additionally, a status register, COMMUNICATION
SPI1STAT, indicates various status conditions.
A control bit, MODE16 (SPI1CON<10>), allows the
The serial interface consists of 4 pins: SDI1 (serial module to communicate in either 16-bit or 8-bit mode.
data input), SDO1 (serial data output), SCK1 (shift 16-bit operation is identical to 8-bit operation, except
clock input or output), and SS1 (active low slave that the number of bits transmitted is 16 instead of 8.
select).
The user software must disable the module prior to
In Master mode operation, SCK is a clock output, but changing the MODE16 bit. The SPI module is reset
in Slave mode, it is a clock input. when the MODE16 bit is changed by the user.
A series of eight (8) or sixteen (16) clock pulses shifts A basic difference between 8-bit and 16-bit operation is
out bits from the SPI1SR to SDO1 pin and simulta- that the data is transmitted out of bit 7 of the SPIxSR for
neously shifts in data from SDI1 pin. An interrupt is 8-bit operation, and data is transmitted out of bit 15 of
generated when the transfer is complete and the cor- the SPIxSR for 16-bit operation. In both modes, data is
responding Interrupt Flag bit (SPI1IF) is set. This inter- shifted into bit 0 of the SPIxSR.
rupt can be disabled through an Interrupt Enable bit
(SPI1IE). 16.1.2 SDO1 DISABLE
The receive operation is double buffered. When a A control bit, DISSDO, is provided to the SPI1CON
complete byte is received, it is transferred from register to allow the SDO1 output to be disabled. This
SPI1SR to SPI1BUF. will allow the SPI module to be connected in an input
If the receive buffer is full when new data is being only configuration. SDO can also be used for general
transferred from SPI1SR to SPI1BUF, the module will purpose I/O.
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF will 16.2 Framed SPI Support
not be completed and the new data will be lost. The
module will not respond to SCL transitions while The module supports a basic framed SPI protocol in
SPIROV is 1, effectively disabling the module until Master or Slave mode. The control bit FRMEN enables
SPI1BUF is read by user software. framed SPI support and causes the SS1 pin to perform
the frame synchronization pulse (FSYNC) function.
Transmit writes are also double buffered. The user The control bit SPIFSD determines whether the SS1
writes to SPI1BUF. When the master or slave transfer pin is an input or an output (i.e., whether the module
is completed, the contents of the shift register receives or generates the frame synchronization
(SPI1SR) is moved to the receive buffer. If any trans- pulse). The frame pulse is an active high pulse for a
mit data has been written to the buffer register, the single SPI clock cycle. When frame synchronization is
contents of the transmit buffer are moved to SPI1SR. enabled, the data transmission starts only on the
The received data is thus placed in SPI1BUF and the subsequent transmit edge of the SPI clock.
transmit data in SPI1SR is ready for the next transfer.
Note: Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
SPI1BUF SPI1BUF
Receive Transmit
SPI1SR
SDI1 bit0
SDO1 Shift
clock
SS & FSYNC Clock Edge
Control Select
SS1 Control
Secondary Primary
Prescaler Prescaler FCY
1,2,4,6,8 1, 4, 16, 64
SCK1
SDOx SDIy
Note: x = 1 or 2, y = 1 or 2.
DS70135C-page 104
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
17.0 I2C™ MODULE 17.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete • I2C Slave operation with 7-bit address
I2C Slave operation with 10-bit address
reference source. For more information on the CPU,
peripherals, register descriptions and general device
•
functionality, refer to the dsPIC30F Family Reference • I2C Master operation with 7 or 10-bit address
Manual (DS70046).
See the I2C programmer’s model in Figure 17-1.
2
The Inter-Integrated Circuit (I C) module provides
complete hardware support for both Slave and Multi- 17.1.2 PIN CONFIGURATION IN I2C MODE
Master modes of the I2C serial communication I2C has a 2-pin interface; pin SCL is clock and pin SDA
standard, with a 16-bit interface. is data.
This module offers the following key features:
17.1.3 I2C REGISTERS
• I2C interface supporting both Master and Slave
operation. I2CCON and I2CSTAT are control and status registers,
• I2C Slave mode supports 7 and 10-bit address. respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The
• I2C Master mode supports 7 and 10-bit address.
remaining bits of the I2CSTAT are read/write.
• I2C port allows bi-directional transfers between
master and slaves. I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
• Serial clock synchronization for I2C port can be
bytes are written, or from which data bytes are read.
used as a handshake mechanism to suspend and
I2CRCV is the receive buffer, as shown in Figure 17-1.
resume serial transfer (SCLREL control).
I2CTRN is the transmit register to which bytes are
• I2C supports Multi-Master operation; detects bus written during a transmit operation, as shown in
collision and will arbitrate accordingly. Figure 17-2.
The I2CADD register holds the slave address. A status
17.1 Operating Function Description bit, ADD10, indicates 10-bit Address mode. The
The hardware fully implements all the master and slave I2CBRG acts as the baud rate generator reload value.
functions of the I2C Standard and Fast mode specifica- In receive operations, I2CRSR and I2CRCV together
tions, as well as 7 and 10-bit addressing. form a double buffered receiver. When I2CRSR
Thus, the I2C module can operate either as a slave or receives a complete byte, it is transferred to I2CRCV
a master on an I2C bus. and an interrupt pulse is generated. During
transmission, the I2CTRN is not double buffered.
Note: Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
I2CRCV (8 bits)
bit 7 bit 0
I2CTRN (8 bits)
bit 7 bit 0
I2CBRG (9 bits)
bit 8 bit 0
I2CCON (16-bits)
bit 15 bit 0
I2CSTAT (16-bits)
bit 15 bit 0
I2CADD (10-bits)
bit 9 bit 0
Internal
Data Bus
I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB
SDA Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
Write
I2CSTAT
Start, Restart,
Stop bit Generate
Read
Control Logic
Collision
Detect
Write
I2CCON
Acknowledge
Read
Generation
Clock
Stretching Write
I2CTRN
Shift LSB Read
Clock
Reload
Control Write
If an address match occurs, an acknowledgement will I2CADD holds the entire 10-bit address. Upon receiv-
be sent, and the slave event interrupt flag (SI2CIF) is ing an address following a start bit, I2CRSR <7:3> is
set on the falling edge of the ninth (ACK) bit. The compared against a literal ‘11110’ (the default 10-bit
address match does not affect the contents of the address) and I2CRSR<2:1> are compared against
I2CRCV buffer or the RBF bit. I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
17.3.1 SLAVE TRANSMISSION indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
If the R_W bit received is a ‘1’, then the serial port will returns to the Idle state.
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to ‘0’ until the CPU responds by writ- The low byte of the address is then received and com-
ing to I2CTRN. SCL is released by setting the SCLREL pared with I2CADD<7:0>. If an address match occurs,
bit, and 8 bits of data are shifted out. Data bits are the interrupt pulse is generated and the ADD10 bit is
shifted out on the falling edge of SCL, such that SDA is set, indicating a complete 10-bit address match. If an
valid during SCL high (see timing diagram). The inter- address match did not occur, the ADD10 bit is cleared
rupt pulse is sent on the falling edge of the ninth clock and the module returns to the Idle state.
pulse, regardless of the status of the ACK received
from the master. 17.4.1 10-BIT MODE SLAVE
TRANSMISSION
Once a slave is addressed in this fashion, with the full
10-bit address (we will refer to this state as
"PRIOR_ADDR_MATCH"), the master can begin
sending data bytes for a slave reception operation.
As per the I2C standard, FSCK may be 100 kHz or The Master will continue to monitor the SDA and SCL
400 kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. be set.
A write to the I2CTRN will start the transmission of data
EQUATION 17-1: I2CBRG VALUE at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
I2CBRG = ( FFSCL
CY – FCY
1,111,111
) –1 In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
17.12.4 CLOCK ARBITRATION bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
Clock arbitration occurs when the master de-asserts cleared.
the SCL pin (SCL allowed to float high) during any
receive, transmit, or Restart/Stop condition. When the
17.13 I2C Module Operation During CPU
SCL pin is allowed to float high, the baud rate generator
(BRG) is suspended from counting until the SCL pin is Sleep and Idle Modes
actually sampled high. When the SCL pin is sampled
high, the baud rate generator is reloaded with the con-
17.13.1 I2C OPERATION DURING CPU
tents of I2CBRG and begins counting. This ensures SLEEP MODE
that the SCL high time will always be at least one BRG When the device enters Sleep mode, all clock sources
rollover count in the event that the clock is held low by to the module are shutdown and stay at logic ‘0’. If
an external device. Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
17.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly,
BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the
ARBITRATION reception is aborted.
Multi-Master operation support is achieved by bus
17.13.2 I2C OPERATION DURING CPU IDLE
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
MODE
master outputs a ‘1’ on SDA, by letting SDA float high For the I2C, the I2CSIDL bit selects if the module will
while another master asserts a ‘0’. When the SCL pin stop on Idle or continue on Idle. If I2CSIDL = 0, the
floats high, data should be stable. If the expected data module will continue operation on assertion of the Idle
on SDA is a ‘1’ and the data sampled on the SDA mode. If I2CSIDL = 1, the module will stop on Idle.
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
Preliminary
DS70135C-page 111
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
Write Write
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
‘0’ (Start)
UxTX
‘1’ (Stop)
Control
Signals
Note: x = 1 or 2.
dsPIC30F4012 only has UART1.
UxMODE UxSTA
LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control
FERR
PERR
Receive Shift Register Signals
UxRX
0 (UxRSR)
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
DS70135C-page 119
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
The module features are as follows: An Extended Data Frame is similar to a Standard Data
Frame, but includes an Extended Identifier as well.
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B • Remote Frame
• Standard and extended data frames It is possible for a destination node to request the data
• 0-8 bytes data length from the source. For this purpose, the destination node
sends a Remote Frame with an identifier that matches
• Programmable bit rate up to 1 Mbit/sec
the identifier of the required Data Frame. The appropri-
• Support for remote frames ate data source node will then send a Data Frame as a
• Double buffered receiver with two prioritized response to this Remote request.
received message storage buffers (each buffer
• Error Frame
may contain up to 8 bytes of data)
• 6 full (standard/extended identifier) acceptance An Error Frame is generated by any node that detects
filters, 2 associated with the high priority receive a bus error. An error frame consists of 2 fields: an Error
buffer, and 4 associated with the low priority Flag field and an Error Delimiter field.
receive buffer • Overload Frame
• 2 full acceptance filter masks, one each associ- An Overload Frame can be generated by a node as a
ated with the high and low priority receive buffers result of 2 conditions. First, the node detects a domi-
• Three transmit buffers with application specified nant bit during lnterframe Space which is an illegal
prioritization and abort capability (each buffer may condition. Second, due to internal conditions, the node
contain up to 8 bytes of data) is not yet able to start reception of the next message. A
• Programmable wake-up functionality with node may generate a maximum of 2 sequential
integrated low pass filter Overload Frames to delay the start of the next
• Programmable Loopback mode supports self-test message.
operation • Interframe Space
• Signaling via interrupt capabilities for all CAN Interframe Space separates a proceeding frame (of
receiver and transmitter error states whatever type) from a following Data or Remote
• Programmable clock source Frame.
• Programmable link to Input Capture module (IC2,
for both CAN1 and CAN2) for time-stamping and
network synchronization
• Low power Sleep and Idle mode
Acceptance Mask
BUFFERS RXM1
Acceptance Filter
RXF2
MESSAGE
MESSAGE
MTXBUFF
MTXBUFF
MTXBUFF
MSGREQ
MSGREQ
MSGREQ
TXLARB
TXLARB
TXLARB
c RXF0 RXF4 p
TXERR
TXERR
TXERR
TXABT
TXABT
TXABT
e t
Acceptance Filter Acceptance Filter
p
RXF1 RXF5
t
R R
X Identifier M Identifier X
Message B A B
Queue 0 B 1
Control
Transmit Byte Sequencer Data Field Data Field
Receive RERRCNT
Error
Counter
PROTOCOL TERRCNT
Protocol
Finite
CRC Generator CRC Check
State
Machine
Bit
Transmit
Timing Bit Timing
Logic
Logic Generator
C1TX C1RX
Input Signal
Sample Point
TQ
19.6.6 SYNCHRONIZATION
19.6.3 PROPAGATION SEGMENT
To compensate for phase shifts between the oscillator
This part of the bit time is used to compensate physical frequencies of the different bus stations, each CAN
delay times within the network. These delay times con- controller must be able to synchronize to the relevant
sist of the signal propagation time on the bus line and signal edge of the incoming signal. When an edge in
the internal delay time of the nodes. The Propagation the transmitted data is detected, the logic will compare
Segment can be programmed from 1 TQ to 8 TQ by the location of the edge to the expected time (Synchro-
setting the PRSEG<2:0> bits (C1CFG2<2:0>). nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
19.6.4 PHASE SEGMENTS mechanisms used to synchronize.
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit 19.6.6.1 Hard Synchronization
time. The sampling point is between Phase1 Seg and Hard Synchronization is only done whenever there is a
Phase2 Seg. These segments are lengthened or short- 'recessive' to 'dominant' edge during Bus Idle, indicat-
ened by re-synchronization. The end of the Phase1 ing the start of a message. After hard synchronization,
Seg determines the sampling point within a bit period. the bit time counters are restarted with the Synchro-
The segment is programmable from 1 TQ to 8 TQ. nous Segment. Hard synchronization forces the edge
Phase2 Seg provides delay to the next transmitted data which has caused the hard synchronization to lie within
transition. The segment is programmable from 1 TQ to the synchronization segment of the restarted bit time. If
8 TQ, or it may be defined to be equal to the greater of a hard synchronization is done, there will not be a
Phase1 Seg or the Information Processing Time re-synchronization within that bit time.
(2 TQ). The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (C1CFG2<5:3>), and Phase2 Seg is 19.6.6.2 Re-synchronization
initialized by setting SEG2PH<2:0> (C1CFG2<10:8>).
As a result of re-synchronization, Phase1 Seg may be
The following requirement must be fulfilled while setting lengthened or Phase2 Seg may be shortened. The
the lengths of the Phase Segments: amount of lengthening or shortening of the phase
• Propagation Segment + Phase1 Seg > = Phase2 buffer segment has an upper bound known as the Syn-
Seg chronization Jump Width, and is specified by the
SJW<1:0> bits (C1CFG1<7:6>). The value of the syn-
chronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The re-synchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
• Phase2 Seg > Synchronization Jump Width
DS70135C-page 128
C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF2SID 0310 — — — Receive Acceptance Filter 2 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF2EIDH 0312 — — — — Receive Acceptance Filter 2 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF3SID 0318 — — — Receive Acceptance Filter 3 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF4SID 0320 — — — Receive Acceptance Filter 4 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF4EIDH 0322 — — — — Receive Acceptance Filter 4 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
dsPIC30F4011/4012
C1RXF5SID 0328 — — — Receive Acceptance Filter 5 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM0SID 0330 — — — Receive Acceptance Mask 0 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM0EIDH 0332 — — — — Receive Acceptance Mask 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
Preliminary
C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM1SID 0338 — — — Receive Acceptance Mask 1 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM1EIDH 033A — — — — Receive Acceptance Mask 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1TX2SID 0340 Transmit Buffer 2 Standard Identifier <10:6> — — — Transmit Buffer 2 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX2EID 0342 Transmit Buffer 2 Extended Identifier <17:14> — — — — Transmit Buffer 2 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C1TX1SID 0350 Transmit Buffer 1 Standard Identifier <10:6> — — — Transmit Buffer 1 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX1EID 0352 Transmit Buffer 1 Extended Identifier <17:14> — — — — Transmit Buffer 1 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
Legend: u = uninitialized bit
Preliminary
C1RX0EID 0382 — — — — Receive Buffer 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RX0DLC 0384 Receive Buffer 0 Extended Identifier <5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 038E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1CTRL 0390 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000
C1CFG1 0392 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C1EC 039A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
DS70135C-page 129
dsPIC30F4011/4012
dsPIC30F4011/4012
NOTES:
AVDD AVSS
VREF+
VREF-
AN0 AN0
AN3 +
S/H CH1 ADC
AN6 -
Format
Data
AN7 -
16-word, 10-bit
Dual Port
Buffer
Bus Interface
AN2 AN2
AN5 +
S/H CH3
AN8 - CH1,CH2,
CH3,CH0 Sample/Sequence
sample Control
AN0
AN1 input
AN2 switches Input Mux
AN3 AN3 Control
AN4 AN4
AN5 AN5
*AN6 AN6
*AN7 AN7
*AN8 AN8 +
S/H CH0
AN1 -
CHOLD
VA CPIN I leakage = DAC capacitance
VT = 0.6V ± 500 nA = 4.4 pF
VSS
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
DS70135C-page 138
ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu
ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu
ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu
ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu
ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu
ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu
ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu
ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu
ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu
ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu
ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu
dsPIC30F4011/4012
Preliminary
ADPCFG 02A8 — — — — — — — PCFG8* PCFG7* PCFG6* PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA — — — — — — — CSSL8* CSSL*7 CSSL6* CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit
* Not available on dsPIC30F4012
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Wake-up Request
FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<1:0>
Primary Osc
NOSC<1:0>
Primary
Oscillator OSWEN
Stability Detector
Oscillator
POR Done Start-up
Clock
Timer
Switching
Programmable
Secondary Osc and Control Clock Divider System
Block
Clock
SOSCO
Secondary 2
32 kHz LP
Oscillator
SOSCI Oscillator
Stability Detector POST<1:0>
CF
Fail-Safe Clock
FCKSM<1:0> Monitor (FSCM)
2 Oscillator Trap
to Timer1
21.2.3 LP OSCILLATOR CONTROL Keeping the LP oscillator ON at all times allows for a
fast switch to the 32 kHz system clock for lower power
Enabling the LP oscillator is controlled with two
operation. Returning to the faster main oscillator will
elements:
still require a start-up time.
1. The current oscillator group bits COSC<1:0>.
2. The LPOSCEN bit (OSCON register).
The LP oscillator is ON (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
• COSC<1:0> = 00 (LP selected as main oscillator)
and
• LPOSCEN = 1
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
Illegal Opcode/
Uninitialized W Register
21.3.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is
nominally 10 µs and ensures that the device bias cir-
A power-on event will generate an internal POR pulse
cuits are stable. Furthermore, a user selected power-
when a VDD rise is detected. The Reset pulse will occur
up time-out (TPWRT) is applied. The TPWRT parameter
at the POR circuit threshold voltage (VPOR), which is
is based on device configuration bits and can be 0 ms
nominally 1.85V. The device supply voltage character-
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
istics must meet specified starting voltage and rise rate
device power-up TPOR + TPWRT. When these delays
requirements. The POR pulse will reset a POR timer
have expired, SYSRST will be negated on the next
and place the device in the Reset state. The POR also
leading edge of the Q1 clock, and the PC will jump to
selects the device clock source identified by the oscil-
the Reset vector.
lator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
21.3.1.2 Operating without FSCM and PWRT FIGURE 21-6: EXTERNAL POWER-ON
If the FSCM is disabled and the Power-up Timer RESET CIRCUIT (FOR
(PWRT) is also disabled, then the device will exit rap- SLOW VDD POWER-UP)
idly from Reset on power-up. If the clock source is VDD
FRC, LPRC, EXTRC or EC, it will be active
immediately. D R
If the FSCM is disabled and the system clock has not R1
MCLR
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s C dsPIC30F
perspective, the device will appear to be in Reset until
a system clock is available.
Note 1: External Power-on Reset circuit is
21.3.2 BOR: PROGRAMMABLE required only if the VDD power-up slope
BROWN-OUT RESET is too slow. The diode D helps discharge
the capacitor quickly when VDD powers
The BOR (Brown-out Reset) module is based on an down.
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a 2: R should be suitably chosen so as to
brown-out condition occurs. Brown-out conditions are make sure that the voltage drop across
generally caused by glitches on the AC mains (i.e., R does not violate the device’s electrical
missing portions of the AC cycle waveform due to bad specification.
power transmission lines or voltage sags due to exces- 3: R1 should be suitably chosen so as to
sive current draw when a large inductive load is turned limit any current flowing into MCLR from
on). external capacitor C, in the event of
The BOR module allows selection of one of the follow- MCLR/VPP pin breakdown due to Elec-
ing voltage trip points: trostatic Discharge (ESD) or Electrical
Overstress (EOS).
• 2.0V
• 2.7V
• 4.2V Note: Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
• 4.5V
used as an external Power-on Reset
Note: The BOR voltage trip points indicated here circuit.
are nominal values provided for design
guidance only.
21.5 Power Saving Modes If EC, FRC, LPRC or EXTRC oscillators are used, then
a delay of TPOR (~ 10 µs) is applied. This is the smallest
There are two power saving states that can be entered delay possible on wake-up from Sleep.
through the execution of a special instruction, PWRSAV.
Moreover, if LP oscillator was active during Sleep, and
These are: Sleep and Idle. LP is the oscillator used on wake-up, then the start-up
The format of the PWRSAV instruction is as follows: delay will be equal to TPOR. PWRT delay and OST
timer delay are not applied. In order to have the small-
PWRSAV <parameter>, where ‘parameter’ defines est possible start-up delay when waking up from Sleep,
Idle or Sleep mode. one of these faster wake-up options should be selected
before entering Sleep.
DS70135C-page 152
TABLE 21-8: DEVICE CONFIGURATION REGISTER MAP
File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOSC F80000 — FCKSM<1:0> — — — — FOS<1:0> — — — — FPR<3:0>
FWDT F80002 — FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 — MCLREN — — — — PWMPIN HPOL LPOL BOREN — BORV<1:0> — — FPWRT<1:0>
FGS F8000A — — — — — — — — — — — — — — — GCP GWRP
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
Preliminary
2005 Microchip Technology Inc.
dsPIC30F4011/4012
22.0 INSTRUCTION SET SUMMARY Most bit oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• The W register (with or without an address modi-
reference source. For more information on the CPU, fier) or file register (specified by the value of ‘Ws’
peripherals, register descriptions and general device or ‘f’)
functionality, refer to the dsPIC30F Family Reference • The bit in the W register or file register
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F (specified by a literal value, or indirectly by the
Programmer’s Reference Manual (DS70030). contents of register ‘Wb’)
The dsPIC30F instruction set adds many The literal instructions that involve data movement may
enhancements to the previous PICmicro® instruction use some of the following operands:
sets, while maintaining an easy migration from • A literal value to be loaded into a W register or file
PICmicro instruction sets. register (specified by the value of ‘k’)
Most instructions are a single program memory word • The W register or file register where the literal
(24-bits). Only three instructions require two program value is to be loaded (specified by ‘Wb’ or ‘f’)
memory locations. However, literal instructions that involve arithmetic or
Each single-word instruction is a 24-bit word divided logical operations use some of the following operands:
into an 8-bit opcode which specifies the instruction • The first source operand, which is a register ‘Wb’
type, and one or more operands which further specify without any address modifier
the operation of the instruction.
• The second source operand, which is a literal
The instruction set is highly orthogonal and is grouped value
into five basic categories: • The destination of the result (only if not the same
• Word or byte-oriented operations as the first source operand), which is typically a
• Bit-oriented operations register ‘Wd’ with or without an address modifier
• Literal operations The MAC class of DSP instructions may use some of the
• DSP operations following operands:
• Control operations • The accumulator (A or B) to be used (required
operand)
Table 22-1 shows the general symbols used in
describing the instructions. • The W registers to be used as the two operands
• The X and Y address space pre-fetch operations
The dsPIC30F instruction set summary in Table 22-2
lists all the instructions along with the status flags • The X and Y address space pre-fetch destinations
affected by each instruction. • The accumulator write back destination
Most word or byte-oriented W register instructions The other DSP instructions do not involve any
(including barrel shift instructions) have three multiplication, and may include:
operands: • The accumulator to be used (required)
• The first source operand, which is typically a • The source or destination operand (designated as
register ‘Wb’ without any address modifier Wso or Wdo, respectively) with or without an
• The second source operand, which is typically a address modifier
register ‘Ws’ with or without an address modifier • The amount of shift, specified by a W register
• The destination of the result, which is typically a ‘Wn’ or a literal value
register ‘Wd’ with or without an address modifier The control instructions may use some of the following
However, word or byte-oriented file register instructions operands:
have two operands: • A program memory address
• The file register specified by the value ‘f’ • The mode of the Table Read and Table Write
• The destination, which could either be the file instructions
register ‘f’ or the W0 register, which is denoted as All instructions are a single word, except for certain
‘WREG’ double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48-bits. In the second word, the
8 MSb’s are 0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
24.1 DC Characteristics
VDD
Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS 5 pF for OSC2 output
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKOUT
OS40 OS41
Param
Characteristic Min Typ Max Units Conditions
No.
Internal FRC Accuracy @ FRC Freq = 7.37 MHz(1)
FRC TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x4 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x8 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x16 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.
Param
Characteristic Min Typ Max Units Conditions
No.
Internal FRC Jitter @ FRC Freq = 7.37 MHz(1)
FRC TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x4 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x8 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
FRC with x16 PLL TBD % +25°C VDD = 3.0-3.6V
TBD % +25°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V
TBD % -40°C ≤ TA ≤ +85°C VDD = 4.5-5.5V
TBD % -40°C ≤ TA ≤ +125°C VDD = 4.5-5.5V
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.
I/O Pin
(Input)
DI35
DI40
VDD SY12
MCLR
Internal SY10
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
VBGAP
0V
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRX
QEB
TQ10 TQ11
TQ15 TQ20
POSCNT
ICX
IC10 IC11
IC15
OCx
(Output Compare
or PWM Mode) OC11 OC10
OC20
OCFA/OCFB
OC15
OCx
MP30
FLTA/B
MP20
PWMx
MP11 MP10
PWMx
TQ36
QEA
(input)
TQ31 TQ30
TQ35
QEB
(input) TQ41 TQ40
TQ31 TQ30
TQ35
QEB
Internal
QEA
(input)
QEB
(input)
Ungated
Index TQ50
TQ51
Index Internal
TQ55
Position
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SP36
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP20 SP21
SP40 SP30,SP31
SP41
SSX
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP72 SP73
SP35
SP30,SP31 SP51
SP41
SP40
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP72 SP73
SP52
SP30,SP31 SP51
SDIX
MSb IN BIT14 - - - -1 LSb IN
SP41
SP40
SCL
IM31 IM34
IM30 IM33
SDA
Start Stop
Condition Condition
SDA
Out
SCL
IS31 IS34
IS30 IS33
SDA
Start Stop
Condition Condition
SDA
Out
CA10 CA11
CXRX Pin
(input)
CA20
AD50
ADCLK
Instruction
Execution SET SAMP CLEAR SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 8 9 5 6 8 9
AD50
ADCLK
Instruction
Execution SET ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
XXXXXXXXXXXXXXXXX dsPIC30F4012
XXXXXXXXXXXXXXXXX 30I/SP e3
YYWWNNN 0510017
XXXXXXXXXXXXXXXXXXXX dsPIC30F4012
XXXXXXXXXXXXXXXXXXXX 30I/SO e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 0510017
XXXXXXXXXX dsPIC
XXXXXXXXXX 30F4012
XXXXXXXXXX 30I/ML e3
YYWWNNN 0510017
XXXXXXXXXXXXXXXXXX dsPIC30F4011
XXXXXXXXXXXXXXXXXX 30I/P e3
XXXXXXXXXXXXXXXXXX
YYWWNNN 0510017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXX dsPIC
XXXXXXXXXX 30F4011
XXXXXXXXXX 30I/PT e3
YYWWNNN 0510017
XXXXXXXXXX dsPIC
XXXXXXXXXX 30F4011
XXXXXXXXXX 30I/ML e3
YYWWNNN 0510017
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
E1
2
n 1 α
E
A2
L
c
β A1 B1
eB B p
E
E1
p
B
2
n 1
h
α
45°
c
A A2
φ
β L A1
E1
2 α
n 1
A A2
L
c
β B1
A1
eB B p
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45 °
α
A
φ
β A1 A2
L
(F)
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
d s P I C 3 0 F 6 0 1 0 AT- 3 0 I / P F - 0 0 0
Custom ID (3 digits) or
Trademark Engineering Sample (ES)
Architecture
Package
Flash PF = TQFP 14x14
S = Die (Waffle Pack)
W = Die (Wafers)
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K Temperature
5 = 49K to 96K I = Industrial -40°C to +85°C
6 = 97K to 192K E = Extended High Temp -40°C to +125°C
7 = 193K to 384K
8 = 385K to 768K
Speed
9 = 769K and Up
20 = 20 MIPS
30 = 30 MIPS
Device ID T = Tape and Reel
Example:
dsPIC30F6010AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A
10/20/04