Anda di halaman 1dari 1183

TMOS Power MOSFET Transistor Device Data

Alphanumeric Index of Part Numbers 1

Selector Guide

Introduction to Power MOSFETs


Basic Characteristics of Power MOSFETs

Data Sheets

Surface Mount Package Information and


Tape and Reel Specifications

Package Outline Dimensions and Footprints

Distributors and Sales Offices

Designers, SENSEFET, EFETs, ICePAK, HDTMOS, MiniMOS, SMARTDISCRETES,


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ii

TMOS Power MOSFET Transistor Device Data


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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
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Motorola, Inc. 1996


Previous Edition 1994
All Rights Reserved
Printed in U.S.A.

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Text to be entered:
M
C
6
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3
0
Two-digit codes:
61
23
06
05
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1 2 3
. /
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1 2 3
G H I
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1 2 3
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MN O
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1 2 3 4
P R S Q
7

1 2 3
T U V
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1 2 3 4
WX Y Z
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REV 1

Table of Contents
MMDF2C01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2C02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2C02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2C03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2N02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2P01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2P02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF2P03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF3N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF3N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF4N01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMDF4N01Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMFT1N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMFT2N02EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMFT2955E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMFT3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMFT3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF2P02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF3P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF3P02Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF3P03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF4P01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF4P01Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF5N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF5N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF5N03Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMSF7N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPIC2151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB1N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB2N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB2P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB3N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB3N120E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB4N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB6N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB8N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB9N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB10N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB16N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB20N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB23P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB30N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB30P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB33N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB35N06ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB36N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB50P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB52N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB52N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB55N06Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB60N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION ONE
Alphanumeric Index of Part Numbers
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Obsolete Part Numbers Cross Reference . . . . . . . . . . . . 13

SECTION TWO
Selector Guide
TMOS Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TMOS Power MOSFETs Numbering System . . . . . . 22
SO8 (MiniMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Micro8 HDTMOS Products . . . . . . . . . . . . . . . . . . . . 23
EZFET Power MOSFETs with Zener Gate
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
D3PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TO220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TO247 (Isolated Mounting Hole) . . . . . . . . . . . . . . . . 28
TO264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SOT227B (ISOTOP) . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IGBT Insulated Gate Bipolar Transistor . . . . . . . . 210
Power MOS Gate Drivers . . . . . . . . . . . . . . . . . . . . . . 210

SECTION THREE
Introduction to Power MOSFETs
Chapter 1: Introduction to Power MOSFETs
Symbols, Terms and Definitions . . . . . . . . . . . . . . . . . . 32
Basic TMOS Structure, Operation and Physics . . . . . 37
Distinct Advantages of Power MOSFETs . . . . . . . . . 310
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 313
Basic MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . 313
Temperature Dependent Characteristics . . . . . . . . . . 314
Drain-Source Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Chapter 3: The Data Sheet . . . . . . . . . . . . . . . . . . . . . . . 317

SECTION FOUR Data Sheets


MC33153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MGP20N14CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
MGP20N35CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
MGP20N40CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
MGW12N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
MGW12N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
MGW20N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
MGW20N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
MGW30N60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
MGY20N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
MGY25N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
MGY25N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
MGY30N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
MGY40N60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
MGY40N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
MLD1N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
MLD2N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
MLP1N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
MLP2N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
MMDF1N05E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4102

vi

4106
4115
4123
4132
4141
4147
4154
4160
4167
4174
4181
4187
4194
4196
4202
4208
4214
4216
4218
4224
4231
4238
4245
4252
4259
4266
4273
4280
4287
4291
4295
4299
4303
4308
4313
4317
4323
4329
4335
4341
4347
4354
4360
4366
4368
4374
4380
4386
4392
4398
4404
4410
4416
4422
4424
4430
4437
4439
4441
4443

Table of Contents (continued)


MTP9N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4783
MTP10N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4789
MTP10N10EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4795
MTP10N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4801
MTP12N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4807
MTP12P10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4813
MTP15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4818
MTP15N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4824
MTP16N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4826
MTP20N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4832
MTP20N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4834
MTP23P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4840
MTP27N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4846
MTP30N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4852
MTP30P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4858
MTP33N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4864
MTP35N06ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4870
MTP36N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4872
MTP50P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4878
MTP52N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4885
MTP52N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4887
MTP55N06Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4889
MTP60N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4891
MTP75N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4898
MTP75N05HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4905
MTP75N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911
MTP2955V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4918
MTP3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4920
MTP3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4926
MTSF1P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4932
MTSF2P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4940
MTSF3N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4943
MTSF3N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4951
MTV6N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4959
MTV10N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4965
MTV16N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4971
MTV20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4977
MTV25N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4983
MTV32N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4989
MTV32N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4995
MTW6N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41001
MTW7N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41007
MTW8N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41013
MTW10N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41019
MTW14N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41025
MTW16N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41031
MTW20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41037
MTW24N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41043
MTW32N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41049
MTW32N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41055
MTW35N15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41061
MTW45N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41067
MTY14N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41073
MTY16N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41079
MTY20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41085
MTY25N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41091
MTY30N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41097
MTY55N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41103
MTY100N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41109

SECTION FOUR Data Sheets (continued)


MTB75N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTB75N05HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD1N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD1N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD1N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD1P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD2N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD3N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD4N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD5N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD5P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD6N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD6N15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD6N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD6P10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD9N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD10N10EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD12N06EZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD15N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20N06HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD20P06HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD2955V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTD3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTDF1N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTDF1N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTE30N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTE53N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTE125N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTE215N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP1N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP1N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP1N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP1N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP2N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP2N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP2P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP3N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP3N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP3N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP3N120E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP4N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP4N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP4N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP5N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP5P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP6N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP6P20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP7N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP8N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4450
4457
4464
4470
4476
4482
4484
4490
4496
4502
4508
4514
4520
4526
4531
4537
4543
4549
4555
4561
4567
4569
4576
4583
4590
4592
4599
4606
4608
4614
4620
4628
4636
4642
4648
4654
4660
4666
4672
4678
4684
4690
4696
4702
4708
4714
4720
4726
4733
4735
4741
4747
4753
4759
4765
4771
4777

vii

SECTION FIVE
Surface Mount Package Information
and Tape and Reel Specifications
Surface Mount Package Information . . . . . . . . . . . . . . . .
Power Dissipation for a Surface Mount Device . . . . .
Solder Stencil Guidelines . . . . . . . . . . . . . . . . . . . . . . .
Soldering Precautions . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Solder Heating Profile . . . . . . . . . . . . . . . . . . .
Footprints for Soldering . . . . . . . . . . . . . . . . . . . . . . . . .
Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embossed Tape and Reel Data . . . . . . . . . . . . . . . . . .

SECTION SIX
Package Outline Dimensions and Footprints
Package Outline Dimensions and Footprints . . . . . . . . . 62
52
52
53
53
54
55
56
56
57

SECTION SEVEN
Distributors and Sales Offices
Distributors and Sales Offices . . . . . . . . . . . . . . . . . . . . . . 72

viii

Section One
Alphanumeric Index of Part Numbers

Alphanumeric Index of Part Numbers . . . . . . . . . . . . . . . 12


Obsolete Part Numbers Cross Reference . . . . . . . . . . . . 13

Motorola TMOS Power MOSFET Transistors Device Data

Alphanumeric Index of Part Numbers


11

Alphanumeric Index of Part Numbers

The following index provides you with a quick page number reference for complete data sheets. Contact your local Motorola
Sales Office for data sheets not referenced in this index.
Motorola
Part Number
MC33153
MGP20N14CL
MGP20N35CL
MGP20N40CL
MGW12N120
MGW12N120D
MGW20N60D
MGW20N120
MGW30N60
MGY20N120D
MGY25N120
MGY25N120D
MGY30N60D
MGY40N60
MGY40N60D
MLD1N06CL
MLD2N06CL
MLP1N06CL
MLP2N06CL
MMDF1N05E
MMDF2C01HD
MMDF2C02E
MMDF2C02HD
MMDF2C03HD
MMDF2N02E
MMDF2P01HD
MMDF2P02E
MMDF2P02HD
MMDF2P03HD
MMDF3N02HD
MMDF3N03HD
MMDF4N01HD
MMDF4N01Z
MMFT1N10E
MMFT2N02EL
MMFT2955E
MMFT3055V
MMFT3055VL
MMSF2P02E
MMSF3P02HD
MMSF3P02Z
MMSF3P03HD
MMSF4P01HD
MMSF4P01Z
MMSF5N02HD
MMSF5N03HD
MMSF5N03Z
MMSF7N03HD
MPIC2111
MPIC2112
MPIC2113
MPIC2117
MPIC2130
MPIC2131
MPIC2151

Data Sheet
Page Number
42
413
415
420
425
430
435
440
445
449
454
459
464
469
473
478
484
490
496
4102
4106
4115
4123
4132
4141
4147
4154
4160
4167
4174
4181
4187
4194
4196
4202
4208
4214
4216
4218
4224
4231
4238
4245
4252
4259
4266
4273
4280
4287
4291
4295
4299
4303
4308
4313

Alphanumeric Index of Part Numbers


12

Motorola
Part Number
MTB1N100E
MTB2N40E
MTB2N60E
MTB2P50E
MTB3N100E
MTB3N120E
MTB4N80E
MTB6N60E
MTB8N50E
MTB9N25E
MTB10N40E
MTB15N06V
MTB16N25E
MTB20N20E
MTB23P06V
MTB30N06VL
MTB30P06V
MTB33N10E
MTB35N06ZL
MTB36N06V
MTB50P03HDL
MTB52N06V
MTB52N06VL
MTB55N06Z
MTB60N06HD
MTB75N03HDL
MTB75N05HD
MTD1N50E
MTD1N60E
MTD1N80E
MTD1P50E
MTD2N40E
MTD2N50E
MTD3N25E
MTD4N20E
MTD5N25E
MTD5P06V
MTD6N10E
MTD6N15
MTD6N20E
MTD6P10E
MTD9N10E
MTD10N10EL
MTD12N06EZL
MTD15N06V
MTD15N06VL
MTD20N03HDL
MTD20N06HD
MTD20N06HDL
MTD20N06V
MTD20P03HDL
MTD20P06HDL
MTD2955V
MTD3055V
MTD3055VL

Data Sheet
Page Number
4317
4323
4329
4335
4341
4347
4354
4360
4366
4368
4374
4380
4386
4392
4398
4404
4410
4416
4422
4424
4430
4437
4439
4441
4443
4450
4457
4464
4470
4476
4482
4484
4490
4496
4502
4508
4514
4520
4526
4531
4537
4543
4549
4555
4561
4567
4569
4576
4583
4590
4592
4599
4606
4608
4614

Motorola
Part Number
MTDF1N02HD
MTDF1N03HD
MTE30N50E
MTE53N50E
MTE125N20E
MTE215N10E
MTP1N50E
MTP1N60E
MTP1N80E
MTP1N100E
MTP2N40E
MTP2N50E
MTP2N60E
MTP2P50E
MTP3N50E
MTP3N60E
MTP3N100E
MTP3N120E
MTP4N40E
MTP4N50E
MTP4N80E
MTP5N40E
MTP5P06V
MTP6N60E
MTP6P20E
MTP7N20E
MTP8N50E
MTP9N25E
MTP10N10E
MTP10N10EL
MTP10N40E
MTP12N10E
MTP12P10
MTP15N06V
MTP15N06VL
MTP16N25E
MTP20N06V
MTP20N20E
MTP23P06V
MTP27N10E
MTP30N06VL
MTP30P06V
MTP33N10E
MTP35N06ZL
MTP36N06V
MTP50P03HDL
MTP52N06V
MTP52N06VL
MTP55N06Z
MTP60N06HD
MTP75N03HDL
MTP75N05HD
MTP75N06HD
MTP2955V
MTP3055V

Data Sheet
Page Number
4620
4628
4636
4642
4648
4654
4660
4666
4672
4678
4684
4690
4696
4702
4708
4714
4720
4726
4733
4735
4741
4747
4753
4759
4765
4771
4777
4783
4789
4795
4801
4807
4813
4818
4824
4826
4832
4834
4840
4846
4852
4858
4864
4870
4872
4878
4885
4887
4889
4891
4898
4905
4911
4918
4920

Motorola TMOS Power MOSFET Transistor Device Data

ALPHANUMERIC INDEX OF PART NUMBERS (continued)


Motorola
Part Number
MTP3055VL
MTSF1P02HD
MTSF2P02HD
MTSF3N02HD
MTSF3N03HD
MTV6N100E
MTV10N100E
MTV16N50E
MTV20N50E
MTV25N50E
MTV32N20E

Data Sheet
Page Number
4926
4932
4940
4943
4951
4959
4965
4971
4977
4983
4989

Motorola
Part Number
MTV32N25E
MTW6N100E
MTW7N80E
MTW8N60E
MTW10N100E
MTW14N50E
MTW16N40E
MTW20N50E
MTW24N40E
MTW32N20E

Data Sheet
Page Number

Motorola
Part Number
MTW32N25E
MTW35N15E
MTW45N10E
MTY14N100E
MTY16N80E
MTY20N50E
MTY25N60E
MTY30N50E
MTY55N20E
MTY100N10E

4995
41001
41007
41013
41019
41025
41031
41037
41043
41049

Data Sheet
Page Number
41055
41061
41067
41073
41079
41085
41091
41097
41103
41109

Obsolete Part Numbers Cross Reference


Old Part
Number
BUZ11
BUZ71
BUZ71A
IRF510
IRF520
IRF530
IRF540
IRF610
IRF620
IRF630
IRF640
IRF720
IRF730
IRF740
IRF820
IRF840

New Part
Number
MTP36N06V
MTP15N06V
MTP15N06V
MTP10N10E
MTP10N10E
MTP12N10E
MTP27N10E
MTP7N20E
MTP7N20E
MTP20N20E
MTP20N20E
MTP4N40E
MTP5N40E
MTP10N40E
MTP3N50E
MTP8N50E

Old Part
Number
IRFZ20
MMFT3055E
MMFT3055EL
MTB15N06E
MTB23P06E
MTB30N06EL
MTB36N06E
MTB50N06E
MTB50N06EL
MTD5P06E
MTD8N06E
MTD10N05E
MTD2955E
MTD3055E
MTD3055EL
MTP3N25E

Motorola TMOS Power MOSFET Transistors Device Data

New Part
Number
MTP15N06V
MMFT3055V
MMFT3055VL
MTB15N06V
MTB23P06V
MTB30N06VL
MTB36N06V
MTB50N06V
MTB50N06VL
MTD5P06V
MTD15N06V
MTD15N06V
MTD2955V
MTD3055V
MTD3055VL
MTP9N25E

Old Part
Number
MTP8N06E
MTP15N05E
MTP15N05EL
MTP15N06E
MTP23P06
MTP30N06EL
MTP36N06E
MTP50N05E
MTP50N05EL
MTP50N06E
MTP2955E
MTP3055E
MTP3055EL
MTW20P10
MTW23N25E
MTW26N15E
MTW54N05E

New Part
Number
MTP15N06V
MTP15N06V
MTP15N06VL
MTP15N06V
MTP23P06V
MTP30N06VL
MTP36N06V
MTP50N06V
MTP50N06VL
MTP50N06V
MTP2955V
MTP3055V
MTP3055VL
MTP12P10
MTW32N25E
MTW35N15E
MTP50N06V

Alphanumeric Index of Part Numbers


13

Alphanumeric Index of Part Numbers


14

Motorola TMOS Power MOSFET Transistor Device Data

Section Two
TMOS Power MOSFETs
Products Selector Guide

In Brief . . .
Motorola continues to build a world class portfolio of
TMOS Power MOSFETs with new advances in silicon and
packaging technology. The following new advances have
been made in the area of silicon technology.
Additional high voltage devices with voltages up to
1200 volts.
The new High Cell Density (HDTMOS) Family of standard
and Logic Level devices in both N and P-channel are
available in SO8, DPAK and D2PAK surface mount
packages and in the industry standard TO-220 package.
The following new advances have been made in the area
of packaging technology.
Motorola has added Micro8, SO-8 (MiniMOS) and
SOT-223 packages to the surface mount portfolio.
New High Power packages capable of housing very large
die and higher power dissipation are now available in the
TO-264 (TO-3PBL) and SOT-227B (ISOTOP) packages.

Motorola TMOS Power MOSFET Transistors Device Data

Table of Contents
Page
TMOS Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TMOS Power MOSFETs Numbering System . . . . . . . 22
SO8 (MiniMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Micro8 HDTMOS Products . . . . . . . . . . . . . . . . . . . . . 23
EZFET Power MOSFETs with Zener Gate
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
D3PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TO220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TO247 (Isolated Mounting Hole) . . . . . . . . . . . . . . . . . 28
TO264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SOT227B (ISOTOP) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IGBT Insulated Gate Bipolar Transistor . . . . . . . . 210
Power MOS Gate Drivers . . . . . . . . . . . . . . . . . . . . . . 210

Selector Guide
21

TMOS
Power MOSFETs

TMOS Power MOSFETs Numbering System


Wherever possible, Motorola has used the following numbering systems for TMOS power MOSFET products.

MTP75N06HD
MOTOROLA
X FOR ENGINEERING SAMPLES
TMOS
T FOR TMOS
L FOR SMARTDISCRETES
G FOR IGBT
P FOR MULTIPLE CHIP PRODUCTS

OPTIONAL SUFFIX:
L FOR LOGIC LEVEL
E FOR ENERGY RATED
T4 FOR TAPE & REEL (DPAK/D2PAK)
RL FOR TAPE & REEL (DPAK/D3PAK)
HD FOR HIGH CELL DENSITY
V FOR TMOS V (FIVE)

PACKAGE TYPE
P FOR PLASTIC TO220
D FOR DPAK
A FOR TO220 ISOLATED
W FOR TO247
B FOR D2PAK
Y FOR TO264
E FOR SOT227B
V FOR D3PAK

VOLTAGE RATING DIVIDED BY 10


CHANNEL POLARITY, N OR P

Example of exceptions: MTD/MTP3055E


Example of exceptions: MTD/MTP2955E

CURRENT

SO8 (MiniMOS), Micro8 and SOT223 Power MOSFETs


MMSF4P01HDR1
MOTOROLA

R2 FOR TAPE & REEL MiniMOS, Micro8


T1 AND T3 FOR TAPE & REEL SOT223

PACKAGE TYPE
MMDF DUAL FET (SO8)
MMSF SINGLE FET (SO8)
MMFT FET TRANSISTOR (SOT223)
MTSF SINGLE FET (Micro8)
MTDF DUAL FET (Micro8)

OPTIONAL SUFFIX:
E FOR ENERGY RATED
HD FOR HIGH CELL DENSITY
L FOR LOGIC LEVEL
Z FOR ESD GATE PROTECTION

CURRENT

VOLTAGE RATING DIVIDED BY 10


CHANNEL POLARITY, N OR P
C FOR COMPLEMENTARY

Selector Guide
22

Motorola TMOS Power MOSFET Transistor Device Data

TM

SO8 (MiniMOS)
V(BR)DSS
(V)

RDS(on) @ VGS
10 V
(m)

ID

4.5 V
(m)

2.7 V
(m)

(A)
Device (5)

Package
Type

(3)PD (3)
(Watts)
Max

Table 1. SO8 NChannel


50

300

500

1.5

MMDF1N05E

SO8

2.0

40

80

100

3.4

MMDF3N04HD

SO8

2.0

30

28
40
70
70/200(11)

40
50
75
75/300

8
5
2.8
2

MMSF7N03HD
MMSF5N03HD
MMDF3N03HD
MMDF2C03HD

SO8
SO8
SO8
SO8

2.5
2.5
2.0
2.0

20

25
90
100
90/160(11)
100/250(11)

40
100
200
100/180(11)
200/400(11)

5
3
2
2
2

MMSF5N02HD
MMDF3N02HD
MMDF2N02E
MMDF2C02HD
MMDF2C02E

SO8
SO8
SO8
SO8
SO8

2.5
2.0
2.0
2.0
2.0

12

45
45/180

55
55/220(11)

4
2

MMDF4N01HD
MMDF2C01HD

SO8
SO8

2.0
2.0

Table 2. SO8 PChannel


30

100
200

110
300

3
2

MMSF3P03HD
MMDF2P03HD

SO8
SO8

2.5
2.0

20

75
160
250
250

95
180
400
400

3
2
2
2

MMSF3P02HD
MMDF2P02HD
MMDF2P02E
MMSF2P02E

SO8
SO8
SO8
SO8

2.5
2.0
2.0
2.0

12

100
180

110
220

4
2

MMSF4P01HD
MMDF2P01HD

SO8
SO8

2.5
2.0

1(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
1(5) Available in tape and reel only R1 suffix = 500/reel, R2 suffix = 2500/reel.
(11) NChannel/PChannel R
DS(on)

Micro8 HDTMOS Products


V(BR)DSS
(Volts)
Min

RDS(on)
(mW)
Max

VGS
(Volts)

ID
(cont)
Amps

Device

Product
Description

Table 3. N Channel and P Channel


20

190

2.7

200
30

75

4.5

225

MTSF1P02HD

Single P Channel

1.5

MTDF1N02HD

Dual N Channel

MTSF3N03HD

Single N Channel

1.5

MTDF1N03HD

Dual N Channel

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data

Selector Guide
23

EZFET Power MOSFETs with Zener Gate Protection


RDS(on)
(mW)
Max

V(BR)DSS
(Volts)
Min

Description

VGS
(Volts)

10 V

4.5 V

2.7 V

ID
(cont)
Amps

Device

Table 4. SO 8 N Channel
20

Single NChannel

22

27

MMSF6N02Z

30

Single NChannel

35

30

MMSF5N03Z

50

Dual NChannel

300

500

MMDF2N05Z

60

NChannel

18

55

MTP55N06Z
MTB55N06Z

26

28

35

MTP35N06ZL

VGS
(Volts)
Max

"10
"15
"20
"15

MTB35N06ZL

Package

PD(3)
(Watts)
Max

SO8

1.6

TO220
D2PAK

136

TO220
D2PAK

94

3
3

SOT223
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device (12)

ID
(cont)
Amps

PD(1)
(Watts)
Max

0.8(3)

Table 5. SOT223 NChannel


100

0.30

0.5

MMFT1N10E

60

0.14

0.75

MMFT3055VL(2)

1.5

0.13

0.85

MMFT3055V

1.7

0.15

20

MMFT2N02EL(2)

Table 6. SOT223 PChannel


60

0.30

MMFT2955E

0.6

1.2

0.8(3)

ID
(cont)
Amps

PD(1)
(Watts)
Max

1.75(3)

1(1) T = 25C
C
1(2) Indicates logic level
1(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(12) Available in tape and reel only T1 suffix = 1000/reel, T3 suffix = 4000/reel.

DPAK
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device (4)

Table 7. DPAK NChannel


800

12

0.5

MTD1N80E

600

0.5

MTD1N60E

500

0.5

MTD1N50E

3.60

MTD2N50E

400

3.50

MTD2N40E

250

1.40

1.5

MTD3N25E

2.5

MTD5N25E

200

1.5

1.5

MTD3N20E

1.20

MTD4N20E

0.70

MTD6N20E

0.30

MTD6N15

150

(1) T = 25C
C
(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel add T4 suffix to part number.

(continued)

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide
24

Motorola TMOS Power MOSFET Transistor Device Data

DPAK (continued)
RDS(on)
(Ohms)
Max

V(BR)DSS
(Volts)
Min

ID
(Amps)

Device (4)

ID
(cont)
Amps

PD(1)
(Watts)
Max

1.75(3)

Table 7. DPAK NChannel (continued)


100

60

0.40

MTD6N10E

0.25

4.5

MTD9N10E

0.22

MTD10N10EL

10

MTD14N10E

14

0.15

MTD3055V

0.18

MTD3055VL(2)

12

0.18

MTD12N06EZL(2)(13)

12

0.12

7.5

MTD15N06V

15

0.085

7.5

MTD15N06VL(2)

15

0.045

10

MTD20N06HD

20

0.045

10

MTD20N06HDL(2)

20

0.080

10

MTD20N06V

20

0.035

10

MTD20N03HDL(2)

20

500

15.0

0.5

MTD1P50E

100

0.66

MTD6P10E

60

0.45

2.5

MTD5P06V

0.30

MTD2955V

12

0.15

10

20

0.099

10

MTD20P06HDL(2)
MTD20P03HDL(2)

30

Table 8. DPAK PChannel

30

1.75(3)

19

(1) T = 25C
C
(2) Indicates logic level
(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel add T4 suffix to part number.
(13) ESD protected to 4 kV.

D2PAK
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device (4)

ID
(cont)
Amps

PD(1)
(Watts)
Max

2.5(3)

Table 9. D2PAK NChannel


1200

5.0

1.5

MTB3N120E

1000

0.5

MTB1N100E

1.5

MTB3N100E

800

MTB4N80E

600

1.20

MTB6N60E

4.16

MTB2N60E

500

0.80

MTB8N50E

400

3.50

MTB2N40E

0.55

MTB10N40E

10

0.50

4.5

MTB9N25E

0.25

MTB16N25E

16

250

(1) T = 25C
C
(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel add T4 suffix to part number.

(continued)

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data

Selector Guide
25

D2PAK (continued)
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device (4)

ID
(cont)
Amps

PD(1)
(Watts)
Max

2.5(3)

Table 9. D2PAK NChannel (continued)


200

0.16

10

MTB20N20E

20

100

0.060

16.5

MTB33N10E

33

60

0.12

7.5

MTB15N06V

15

0.05

15

MTB30N06VL(2)

30

0.026

17.5

MTB35N06ZL

35

0.04

18

MTB36N06V

32

0.032

21

MTB50N06VL(2)

42

0.028

21

MTB50N06V

42

0.024

26

52

0.018

27.5

MTB52N06VL(2)
MTB55N06Z (13)

0.022

26

MTB56N06V

52

0.014

30

MTB60N06HD

60

0.01

37.5

MTB75N06HD

75

0.0095

37.5

MTB75N05HD

75

37.5

MTB75N03HDL(2)

75

50
25

0.009

55

Table 10. D2PAK PChannel


500

MTB2P50E

60

0.12

11.5

MTB23P06V

23

0.080

15

MTB30P06V

30

0.025

25

MTB50P03HDL(2)

50

30

2.5(3)

(1) T = 25C
C
(2) Indicates logic level
(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel add T4 suffix to part number.
(13) ESD protected to 4 kV.

D3PAK
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device (4)

ID
(cont)
Amps

PD(1)
(Watts)
Max

Table 11. D3PAK NChannel


1.50

MTV6N100E

178

1.30

MTV10N100E

10

250

0.400

MTV16N50E

16

250

0.240

10

MTV20N50E

20

250

0.200

12.5

MTV25N50E

25

250

250

0.080

16

MTV32N25E

32

250

200

0.075

16

MTV32N20E

32

180

1000
500

(1) T = 25C
C
(4) Available in tape and reel add T4 suffix to part number.

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide
26

Motorola TMOS Power MOSFET Transistor Device Data

TO220AB
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device

ID
(cont)
Amps

PD(1)
(Watts)
Max

125

Table 12. TO220AB NChannel


1200

5.0

1.5

MTP3N120E

1000

0.5

MTP1N100E

75

4.0

1.5

MTP3N100E

125

12

MTP1N80E

48

MTP4N80E

125

0.5

MTP1N60E

50

3.80

MTP2N60E

2.20

1.5

MTP3N60E

75

1.20

MTP6N60E

125

0.5

MTP1N50E

50

3.60

MTP2N50E

75

1.5

MTP3N50E

50

1.50

MTP4N50E

75

0.80

MTP8N50E

125

3.50

MTP2N40E

50

1.80

MTP4N40E

800
600

500

400

250
200
100

60

50
25

2.5

MTP5N40E

75

0.55

MTP10N40E

10

125

0.5

4.5

MTP9N25E

75

0.25

MTP16N25E

16

125

0.70

3.5

MTP7N20E

75

0.16

10

MTP20N20E

20

125

0.25

MTP10N10E

10

75

0.22

MTP10N10EL

10

40

0.16

MTP12N10E

12

75

0.070

13.5

MTP27N10E

27

125

0.060

16.5

150

MTP33N10E
MTP3055VL(2)

33

0.18

12

48

0.15

MTP3055V

12

0.12

7.5

MTP15N06V

15

0.085

7.5

MTP15N06VL

15

0.080

10

MTP20N06V

20

0.05

15

MTP30N06VL(2)

30

0.026

17.5

MTP35N06ZL

35

0.04

18

MTP36N06V

32

90

0.032

21

MTP50N06VL(2)

42

150

0.028

21

MTP50N06V

42

0.022

26

MTP52N06V

52

0.024

26

MTP52N06VL

52

0.018

22.5

MTP55N06Z

55

0.014

30

MTP60N06HD

60

0.01

37.5

MTP75N06HD

75

0.0095

37.5

MTP75N05HD

75

37.5

MTP75N03HDL(2)

75

0.009

(1) T = 25C
C
(2) Indicates logic level

60
90
94

(continued)

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data

Selector Guide
27

TO220AB (continued)
RDS(on)
(Ohms)
Max

V(BR)DSS
(Volts)
Min

ID
(Amps)

Device

ID
(cont)
Amps

PD(1)
(Watts)
Max

75

Table 13. TO220AB PChannel


500

MTP2P50E

200

MTP6P20E

100

0.30

MTP12P10

12

88

60

0.45

2.5

MTP5P06V

40

0.30

MTP2955V

12

60

0.12

11.5

MTP23P06V

23

125

0.08

15

MTP30P06V

30

125

25

MTP50P03HDL (2)

50

150

30

0.025

(1) T = 25C
C
(2) Indicates logic level

TO247 (Isolated Mounting Hole)


V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)

Device

ID
(cont)
Amps

PD(1)
(Watts)
Max

Table 14. TO247 NChannel


1.50

MTW6N100E

180

1.30

MTW10N100E

10

250

800

3.5

MTW7N80E

180

600

0.55

MTW8N60E

180

500

0.40

MTW14N50E

14

180

0.24

10

MTW20N50E

20

250

0.24

MTW16N40E

16

180

0.16

12

MTW24N40E

24

250

250

0.08

16

MTW32N25E

32

250

200

0.075

16

MTW32N20E

32

180

150

0.05

17.5

MTW35N15E

35

180

100

0.035

22.5

MTW45N10E

45

180

1000

400

(1) T = 25C
C

TO264
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device

ID
(cont)
Amps

PD(1)
(Watts)
Max

Table 15. TO264 NChannel


7

MTY14N100E

14

568

0.50

MTY16N80E

16

568

0.21

12.5

MTY25N60E

25

568

500

0.26

10

MTY20N50E

20

300

0.15

15

MTY30N50E

30

568

200

0.028

27.5

MTY55N20E

55

568

100

0.011

50

MTY100N10E

100

568

1000

0.80

800
600

(1) T = 25C
C
Devices listed in bold, italic are Motorola preferred devices.

Selector Guide
28

Motorola TMOS Power MOSFET Transistor Device Data

SOT227B (ISOTOP)
V(BR)DSS
(Volts)
Min

RDS(on)
(Ohms)
Max

ID
(Amps)
Device

ID
(cont)
Amps

PD(1)
(Watts)
Max

30

250

Table 16. SOT227B (ISOTOP)


500

0.15

15

MTE30N50E

0.08

26.5

MTE53N50E

53

460

200

0.015

62.5

MTE125N20E

125

460

100

0.0055

107

MTE215N10E

215

460

(1) T = 25C
C
Indicates UL Recognition File #E69369

SMARTDISCRETES
Table 17. Ignition IGBTs
BVCES (Volts)
Clamped

VCE(on)
@ 10 A

Device

PD(1)
(Watts) Max

Package

140 V

1.8

MGP20N14CL

150

TO220AB

350 V

1.8

MGP20N35CL
MGB20N35CL

150
2.5(3)(4)

TO220AB
D2PAK

400 V

1.8

MGP20N40CL
MGB20N40CL

150
2.5(3)(4)

TO220AB
D2PAK

Table 18. TO220AB


V(BR)DSS
(Volts) Min

RDS(on)
(Ohms) Max

ID
(Amps)

Device

ID (cont)
Amps

PD(1)
(Watts) Max

60 Clamped Voltage

0.75

MLP1N06CL

Current Limited

40

62 Clamped Voltage

0.4

MLP2N06CL

Current Limited

40

V(BR)DSS
(Volts) Min

RDS(on)
(Ohms) Max

ID
(Amps)

Device

ID (cont)
Amps

PD(1)
(Watts) Max

60 Clamped Voltage

0.75

MLD1N06CL

Current Limited

1.75

62 Clamped Voltage

0.4

MLD2N06CL

Current Limited

1.75

Table 19. DPAK

(1) T = 25C
C
(3) Power rating when mounted on an FR4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel add T4 suffix to part number.

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data

Selector Guide
29

IGBT Insulated Gate Bipolar Transistor


Device

BVCES

IC90
(A)

IC
@ 25C
(A)

VCE(on) @ IC90
(V)
typ

Eoff @ IC90
(mJ)
typ @ 125C

(V)

Package

20

32

2.90

1.20

TO220

30

50

2.60

1.80

40

66

2.60

2.40

TO264

12

20

3.10

1.43

TO247

25

38

2.90

4.29

TO264

Table 20. IGBT NChannel


MGP20N60

600

MGW20N60D

TO247

MGW30N60

TO247

MGY30N60D

TO264

MGY40N60
MGY40N60D
MGW10N120

1200

MGW10N120D
MGY25N120
MGY25N120D
IC90 = Collector current rating at 90C case temperature

Power MOS Gate Drivers


Device

Description

Package

Table 21.
8 Pin SOIC

MC33153P

VCCVEE = 23 V, 1 A Source, 2 A Sink Low Side Driver


(Can be used as High Side Driver with Optocoupler)

MPIC2111D

600 V, 420 mA, Half Bridge Driver

8 Pin SOIC

MC33153D

MPIC2111P
MPIC2112DW

8 Pin PDIP
600 V, 420 mA, Half Bridge Driver

16 Pin SOICWide

MPIC2112P
MPIC2113DW

14 Pin PDIP
600 V, 2 A, Half Bridge Driver

16 Pin SOICWide

MPIC2113P
MPIC2117D

14 Pin PDIP
600 V, 420 mA, High Side Driver

8 Pin SOIC

MPIC2117P
MPIC2130P

8 Pin PDIP
600 V, 420 mA, Three Phase Driver

28 Pin PDIP

MPIC2130FN
MPIC2131P

44 Pin PLCC (modified)


600 V, 420 mA, Three Phase Driver

28 Pin PDIP

MPIC2131FN
MPIC2151D

8 Pin PDIP

44 Pin PLCC (modified)


600 V, 210 mA, Self Oscillating, Half Bridge Driver

MPIC2151P

8 Pin SOIC
8 Pin PDIP

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide
210

Motorola TMOS Power MOSFET Transistor Device Data

Section Three
Introduction to Power MOSFETs
Basic Characteristics of Power MOSFETs

Table of Contents
Chapter 1: Introduction to Power MOSFETs
Symbols, Terms and Definitions . . . . . . . . . . . . . . . . . . 32
Basic TMOS Structure, Operation and Physics . . . . . 37
Distinct Advantages of Power MOSFETs . . . . . . . . . 310
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 313
Basic MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . 313
Temperature Dependent Characteristics . . . . . . . . . . 314
Drain-Source Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Chapter 3: The Data Sheet . . . . . . . . . . . . . . . . . . . . . . 317

Motorola TMOS Power MOSFET Transistors Device Data

Introduction and Basic Characteristics


31

Chapter 1: Introduction to Power MOSFETs


Symbols, Terms and Definitions

The following are the most commonly used letter symbols, terms and definitions associated with Power MOSFETs.
Symbol

Term

Definition

Cds

drainsource capacitance

The capacitance between the drain and source terminals


with the gate terminal connected to the guard terminal of
a threeterminal bridge.

Cdg

draingate capacitance

The same as Crss See Crss.

Cgs

gatesource capacitance

The capacitance between the gate and source terminals


with the drain terminal connected to the guard terminal of
a threeterminal bridge.

Ciss

shortcircuit input capacitance,


commonsource

The capacitance between the input terminals (gate and


source) with the drain shortcircuited to the source for
alternating current. (Ref. IEEE No. 255)

Coss

shortcircuit output capacitance,


commonsource

The capacitance between the output terminals (drain and


source) with the gate shortcircuited to the source for
alternating current. (Ref. IEEE No. 255)

Crss

shortcircuit reverse transfer


capacitance, commonsource

The capacitance between the drain and gate terminals


with the source connected to the guard terminal of a
threeterminal bridge.

gFS

commonsource largesignal
transconductance

The ratio of the change in drain current due to a change in


gatetosource voltage.

ID

drain current, dc

The direct current into the drain terminal.

ID(on)

onstate drain current

The direct current into the drain terminal with a specified


forward gatesource voltage applied to bias the device to
the onstate.

IDSS

zerogatevoltage drain current

The direct current into the drain terminal when the


gatesource voltage is zero. This is an onstate current in
a depletiontype device, an offstate in an enhancement
type device.

IG

gate current, dc

The direct current into the gate terminal.

IGSS

reverse gate current, drain shortcircuited


to source

The direct current into the gate terminal of a junctiongate


fieldeffect transistor when the gate terminal is reverse
biased with respect to the source terminal and the drain
terminal is shortcircuited to the source terminal.

IGSSF

forward gate current, drain shortcircuited


to source

The direct current into the gate terminal of an insulated


gate fieldeffect transistor with a forward gatesource
voltage applied and the drain terminal shortcircuited to
the source terminal.

IGSSR

reverse gate current, drain shortcircuited


to source

The direct current into the gate terminal of an insulated


gate fieldeffect transistor with a reverse gatesource
voltage applied and the drain terminal shortcircuited to
the source terminal.

Introduction and Basic Characteristics


32

Motorola TMOS Power MOSFET Transistor Device Data

Symbol

Term

Definition

IS

source current, dc

The direct current into the source terminal.

PT, PD

total nonreactive power input to all


terminals

The sum of the products of the dc input currents and


voltages.

Qg

total gate charge

The total gate charge required to charge the MOSFETs


input capacitance to VGS(on).

RDS(on)

static drainsource onstate resistance

The dc resistance between the drain and source terminals


with a specified gatesource voltage applied to bias the
device to the on state.

RCA

thermal resistance, casetoambient

The thermal resistance (steadystate) from the device


case to the ambient.

RJA

thermal resistance, junctiontoambient

The thermal resistance (steadystate) from the semiconductor junction(s) to the ambient.

RJC

thermal resistance, junctiontocase

The thermal resistance (steadystate) from the semiconductor junction(s) to a stated location on the case.

RJM

thermal resistance, junctiontomounting


surface

The thermal resistance (steadystate) from the semiconductor junction(s) to a stated location on the mounting
surface.

TA

ambient temperature or freeair


temperature

The air temperature measured below a device, in an


environment of substantially uniform temperature, cooled
only by natural air convection and not materially affected
by reflective and radiant surfaces.

TC

case temperature

The temperature measured at a specified location on the


case of a device.

tc

turnoff crossover time

The time interval during which drain voltage rises from


10% of its peak offstate value and drain current falls to
10% of its peak onstate value, in both cases ignoring
spikes that are not chargecarrier induced.

TJ

channel temperature

The temperature of the channel of a fieldeffect transistor.

Tstg

storage temperature

The temperature at which the device, without any power


applied, may be stored.

td(off)

turnoff delay time

Synonym for current turnoff delay time (see Note 1)*.

td(off)i

current turnoff delay time

The interval during which an input pulse that is switching


the transistor from a conducting to a nonconducting state
falls from 90% of its peak amplitude and the drain current
waveform falls to 90% of its onstate amplitude, ignoring
spikes that are not chargecarrier induced.

td(off)v

voltage turnoff delay time

The time interval during which an input pulse that is


switching the transistor from a conducting to a nonconducting state falls from 90% of its peak amplitude and the
drain voltage waveform rises to 10% of its offstate
amplitude, ignoring spikes that are not chargecarrier
induced.

td(on)

turnon delay time

Synonym for current turnon delay time (see Note 1)*.

td(on)i

current turnon delay time

The time interval during which can input pulse that is


switching the transistor from a nonconducting to a
conducting state rises from 10% of its peak amplitude and
the drain current waveform rises to 10% of its onstate
amplitude, ignoring spikes that are not chargecarrier
induced.

Motorola TMOS Power MOSFET Transistors Device Data

Introduction and Basic Characteristics


33

Symbol

Term

Definition

td(on)v

voltage turnon delay time

The time interval during which an input pulse that is


switching the transistor from a nonconducting to a
conducting state rises from 10% of its peak amplitude and
the drain voltage waveform falls to 90% of its offstate
amplitude, ignoring spikes that are not chargecarrier
induced.

tf

fall time

Synonym for current fall time (see Note 1)*.

tfi

current fall time

The time interval during which the drain current changes


from 90% to 10% of its peak offstate value, ignoring
spikes that are not chargecarrier induced.

tfv

voltage fall time

The time interval during which the drain voltage changes


from 90% to 10% of its peak offstate value, ignoring
spikes that are not chargecarrier induced.

toff

turnoff time

Synonym for current turnoff time (see Note 1)*.

toff(i)

current turnoff time

The sum of current turnoff delay time and current fall time,
i.e., td(off)i + tfi.

toff(v)

voltage turnoff time

The sum of voltage turnoff delay time and voltage rise


time, i.e., td(off)v + trv.

ton

turnon time

Synonym for current turnon time (see Note 1)*.

ton(i)

current turnon time

The sum of current turnon delay time and current rise


time, i.e., td(on)i + tri.

ton(v)

voltage turnon time

The sum of voltage turnon delay time and voltage fall


time, i.e., td(on)v + tfv.

tp

pulse duration

The time interval between a reference point on the leading


edge of a pulse waveform and a reference point on the
trailing edge of the same waveform.
Note: The two reference points are usually 90% of the
steadystate amplitude of the waveform existing after the leading
edge, measured with respect to the steadystate amplitude
existing before the leading edge. If the reference points are 50%
points, the symbol tw and term average pulse duration should be
used.

tr

rise time

Synonym for current rise time (see Note 1)*.

tri

current rise time

The time interval during which the drain current changes


from 10% to 90% of its peak onstate value, ignoring
spikes that are not chargecarrier induced.

trv

voltage rise time

The time interval during which the drain voltage changes


from 10% to 90% of its peak offstate value, ignoring
spikes that are not chargecarrier induced.

tti

current fall time

The time interval following current fall time during which


the drain current changes from 10% to 2% of its peak
onstate value, ignoring spikes that are not chargecarrier
induced.

tw

average pulse duration

The time interval between a reference point on the leading


edge of a pulse waveform and a reference point on the
trailing edge of the same waveform, with both reference
points being 50% of the steadystate amplitude of the
waveform existing after the leading edge, measured with
respect to the steadystate amplitude existing before the
leading edge.
Note: If the reference points are not 50% points, the symbol tp
and term pulse duration should be used.

Introduction and Basic Characteristics


34

Motorola TMOS Power MOSFET Transistor Device Data

Symbol

Term

Definition

V(BR)DSR

drainsource breakdown voltage with


(resistance between gate and source)

The breakdown voltage between the drain terminal and the


source terminal when the gate terminal is (as indicated by
the last subscript letter) as follows:
R = returned to the source terminal through a specified
resistance.

V(BR)DSS

gate shortcircuited to source

S = shortcircuited to the source terminal.

V(BR)DSV

voltage between gate and source

V = returned to the source terminal through a specified


voltage.

V(BR)DSX

circuit between gate and source

X = returned to the source terminal through a specified


circuit.

V(BR)GSSF

forward gatesource breakdown voltage

The breakdown voltage between the gate and source


terminals with a forward gatesource voltage applied and
the drain terminal shortcircuited to the source terminal.

V(BR)GSSR

reverse gatesource breakdown voltage

The breakdown voltage between the gate and source


terminals with a reverse gatesource voltage applied and
the drain terminal shortcircuited to the source terminal.

VDD, VGG
VSS

supply voltage, dc (drain, gate, source)


voltage

The dc supply voltage applied to a circuit or connected to


the reference terminal.

VDG
VDS
VGD
VGS
VSD
VSG

draintogate
draintosource
gatetodrain
gatetosource
sourcetodrain
sourcetogate

The dc voltage between the terminal indicated by the first


subscript and the reference terminal indicated by the
second subscript (stated in terms of the polarity at the
terminal indicated by the first subscript).

VDS(on)

drainsource onstate voltage

The voltage between the drain and source terminals with


a specified forward gatesource voltage applied to bias the
device to the on state.

VGS(th)

gatesource threshold voltage

The forward gatesource voltage at which the magnitude


of the drain current of an enhancementtype fieldeffect
transistor has been increased to a specified low value.

ZJA(t)

transient thermal impedance,


junctiontoambient

The transient thermal impedance from the semiconductor


junction(s) to the ambient.

ZJC(t)

transient thermal impedance,


junctiontocase

The transient thermal impedance from the semiconductor


junction(s) to a stated location on the case.

Note 1: As names of time intervals for characterizing switching transistors, the terms fall time and rise time always refer to the change that is
taking place in the magnitude of the output current even though measurements may be made using voltage waveforms. In a purely resistive
circuit, the (current) rise time may be considered equal and coincident to the voltage fall time and the (current) fall time may be considered equal
and coincident to the voltage rise time. The delay times for current and voltage will be equal and coincident. When significant amounts of
inductance are present in a circuit, these equalities and coincidences no longer exist, and use of the unmodified terms delay time, fall time, and
rise time must be avoided.

Motorola TMOS Power MOSFET Transistors Device Data

Introduction and Basic Characteristics


35

100%

90%

Pulse
amplitude

Input Voltage
(Idealized wave shape)
10%

toff ton(i)

toff toff(i)

td(on) = td(on)i

Drain
Current
(Practical wave shape
including spikes caused
by currents that are
not chargecarrier
induced)

td(off) = td(off)i
tf tfi

tr tri

90%

ID(on)

Drain
Current
(Idealized wave shape)
10%

toff(v)

ton(v)

ID(off)

td(off)v

td(on)v
tfv

trv
90%

[VDD

Drain
Voltage
(Idealized wave shape)
10%

VDS(on)

Figure 11. Waveforms for ResistiveLoad Switching

90%
Input
Voltage

toff(i)
tfi
IDM
90%
Drain
Current

td(off)i

10%
ID(off)

2%
tc (or txo)
trv
90%

tti

VDSM
Vclamp or V(BR)DSX
(See Note)

td(off)v

Drain
Voltage

VDS(on)

10%

[VDD

toff(v)

NOTE: Vclamp (in a clamped inductiveload switching circuit) or V(BR)DSX (in an unclamped circuit) is the peak offstate voltage
excluding spikes.

Figure 12. Waveforms for Inductive Load Switching, TurnOff

Introduction and Basic Characteristics


36

Motorola TMOS Power MOSFET Transistor Device Data

Basic TMOS Structure, Operation and Physics

GATE + VG

Structures:

CURRENT

Motorolas TMOS Power MOSFET family is a matrix of diffused channel, vertical, metaloxidesemiconductor power
fieldeffect transistors which offer an exceptionally wide
range of voltages and currents with low RDS(on). The inherent
advantages of Motorolas power MOSFETs include:
Nearly infinite static input impedance featuring:
Voltage driven input
Low input power
Few driver circuit components

DEPLETION
REGION
NCHANNEL
(CURRENT PATH)

Very fast switching times


No minority carriers
Minimal turnoff delay time
Large reversed biased safe operating area
High gain bandwidth product
Positive temperature coefficient of onresistance
Large forward biased safe operating area
Ease in paralleling
Almost constant transconductance

PSUBSTRATE
AND BODY
SOURCE METAL
DRAIN METAL + VDD

Figure 13. Conventional SmallSignal MOSFET has


Long Lateral Channel Resulting in Relatively High
DraintoSource Resistance

High dv/dt immunity


Motorolas TMOS power MOSFET line is the latest step in
an evolutionary progression that began with the conventional
smallsignal MOSFET and superseded the intermediate lateral double diffused MOSFET (LDMOSFET) and the vertical
Vgroove MOSFET (VMOSFET).
The conventional smallsignal lateral Nchannel
MOSFET consists of a lightly doped Ptype substrate into
which two highly doped N+ regions are diffused, as shown in
Figure 13. The N+ regions act as source and drain which
are separated by a channel whose length is determined by
photolithographic constraints. This configuration resulted in
long channel lengths, low current capability, low reverse
blocking voltage and high RDS(on).
Two major changes in the smallsignal MOSFET structure
were responsible for the evolution of the power MOSFET.
One was the use of self aligned, double diffusion techniques
to achieve very short channel lengths, which allowed higher
channel packing densities, resulting in higher current capability and lower RDS(on). The other was the incorporation of a
lightly doped N+ region between the channel and the N+
drain allowing high reverse blocking voltages.
These changes resulted in the lateral double diffused
MOSFET power transistor (LDMOS) structure shown in
Figure 14, in which all the device terminals are still on the
top surface of the die. The major disadvantage of this configuration is its inefficient use of silicon area due to the area
needed for the top drain contact.

Motorola TMOS Power MOSFET Transistors Device Data

D
SiO2

N+

N+

P
Channel

Current

Figure 14. Lateral Double Diffused MOSFET


Structure Featuring Short Channel Lengths and High
Packing Densities for Lower On Resistance
The next step in the evolutionary process was a vertical
structure in which the drain contact was on the back of the
die, further increasing the channel packing density. The initial
concept used a Vgroove MOSFET power transistor as
shown in Figure 15. The channels in this device are defined
by preferentially etching Vgrooves through double diffused
N+ and P regions. The requirements of adequate packing
density, efficient silicon usage and adequate reverse blocking voltage are all met by this configuration. However, due to
its nonplanar structure, process consistency and cleanliness requirements resulted in higher die costs.

Introduction and Basic Characteristics


37

The cell structure chosen for Motorolas TMOS power


MOSFETs is shown in Figure 16. This structure is similar to
that of Figure 14 except that the drain contact is dropped
through the N substrate to the back of the die. The gate
structure is now made with polysilicon sandwiched between
two oxide layers and the source metal applied continuously
over the entire active area. This two layer electrical contact
gives the optimum in packing density and maintains the
processing advantages of planar LDMOS. This results in a
highly manufacturable process which yields low RDS(on) and
high voltage product.
S

X of

A1

SiO2

n+
p
n

n+

As the drain voltage is increased, the drain current saturates and becomes proportional to the square of the applied
gatetosource voltage, VGS, as indicated in Equation (2).
(2) ID

[ 2LZ

SOURCE SITE

SOURCE
METALIZATION

SILICON
GATE
NCHANNEL
DRAIN CURRENT
INSULATING OXIDE, SiO2
NEpi LAYER
NSUBSTRATE

DRAIN
METALIZATION

Figure 16. TMOS Power MOSFET Structure Offers


Vertical Current Flow, Low Resistance Paths and
Permits Compact Metalization on Top and Bottom
Surfaces to Reduce Chip Size

Operation:
Transistor action and the primary electrical parameters of
Motorolas TMOS power MOSFET can be defined as follows:
Drain Current, ID:
When a gate voltage of appropriate polarity and magnitude
is applied to the gate terminal, the polysilicon gate induces
an inversion layer at the surface of the diffused channel
region represented by rCH in Figure 17 (page A8). This
inversion layer or channel connects the source to the lightly
doped region of the drain and current begins to flow. For
small values of applied draintosource voltage, VDS, drain
current increases linearly and can be represented by Equation (1).
(1) ID

[ ZL

mCo

[VGSVGS(th)] VDS

Introduction and Basic Characteristics


38

[VGSVGS(th)]2

Where = Carrier Mobility


Co = Gate Oxide Capacitance per unit area
Z = Channel Width
L = Channel Length
These values are selected by the device design engineer
to meet design requirements and may be used in modeling
and circuit simulations. They explain the shape of the output
characteristics discussed in Chapter 2.
Transconductance, gFS:
The transconductance or gain of the TMOS power
MOSFET is defined as the ratio of the change in drain current and an accompanying small change in applied gateto
source voltage and is represented by Equation (3).

Figure 15. VGroove MOSFET Structure Has


Short Vertical Channels with Low
DraintoSource Resistance

mCo

(3) gFS

+ DDID(sat)
+ ZL
VGS

mCo

[VGSVGS(th)]

The parameters are the same as above and demonstrate


that drain current and transconductance are directly related
and are a function of the die design. Note that transconductance is a linear function of the gate voltage, an important
feature in amplifier design.
Threshold Voltage, VGS(th)
Threshold voltage is the gatetosource voltage required
to achieve surface inversion of the diffused channel region,
(r CH in Figure 17) and as a result, conduction in the
channel.
As the gate voltage increases the more the channel is
enhanced, or the lower its resistance (rCH) is made, the
more current will flow. Threshold voltage is measured at a
specified value of current to maintain measurement correlations. A value of 1.0 mA is common throughout the industry.
This value is primarily a function of the gate oxide thickness
and channel doping level which are chosen during the die
design to give a high enough value to keep the device off with
no bias on the gate at high temperatures. A minimum value
of 1.5 volts at room temperature will guarantee the transistor
remains an enhancement mode device at junction temperatures up to 150C.
OnResistance, RDS(on):
Onresistance is defined as the total resistance encountered by the drain current as it flows from the drain terminal to
the source terminal. Referring to Figure 17, RDS(on) is composed primarily of four resistive components associated with:
The Inversion channel, rCH; the GateDrain Accumulation
Region, rACC; the junction FET Pinch region, rJFET; and the
lightly doped Drain Region, rD, as indicated in Equation (4).
(4) RDS(on)

+ rCH ) rACC ) rJFET ) rD

Motorola TMOS Power MOSFET Transistor Device Data

POLY

N+

P+

rJFET
rACC

rCH

N+

P+

rD

N+

Figure 17. TMOS Device OnResistance


S

Cgs

Cgs

POLY

N+

Cgd
P+

n+

N+

P+
Cds

N
N+

resistance continues to decrease as VGS is increased toward


the maximum rating of the device.
Note: RDS(on) is inversely proportional to the carrier mobility. This
means that the RDS(on) of the PChannel MOSFET is approximately
2.5 to 3.0 times that of a similar NChannel MOSFET. Therefore, in
order to have matched complementary on characteristics, the Z/L ratio
of the PChannel device must be 2.53.0 times that of the NChannel
device. This means larger die are required for PChannel MOSFETs
with the same RDS(on) and same breakdown voltage as an NChannel
device and thus device capacitances and costs will be
correspondingly higher.

Breakdown Voltage, V(BR)DSS:


Breakdown voltage or reverse blocking voltage of the
TMOS power MOSFET is defined in the same manner as
V(BR)CES in the bipolar transistor and occurs as an avalanche
breakdown. This voltage limit is reached when the carriers
within the depletion region of the reverse biased PN junction acquire sufficient kinetic energy to cause ionization or
when the critical electric field is reached. The magnitude of
this voltage is determined mainly by the characteristics of the
lightly doped drain region and the type of termination of the
dies surface electric field.
Figure 19 shows a schematic representation of the
crosssection in Figure 18 and depicts the bipolar transistor
built in the epi layer. Point A shows where the emitter and
base of the bipolar is shorted together. This is why V(BR)DSS
of the power FET is equal to V(BR)CES of the bipolar. Also
note the short brings the base in contact with the source metal allowing the use of the basecollector junction. This is the
diode across the TMOS power MOSFET.

Figure 18. TMOS Device Parasitic Capacitances


Whereas the channel resistance increases with channel
length, the accumulation resistance increases with poly
width and the JFET pinch resistance increases with epi
resistivity and all three are inversely proportional to the channel width and gatetosource voltage. The drain resistance
is proportional to the epi resistivity, poly width and inversely
proportional to channel width. This says that the onresistance of TMOS power FETs with the thick and high resistivity
epi required for high voltage parts will be dominated by rD.
Low voltage devices have thin, low resistivity epi and rCH
will be a large portion of the total onresistance. This is
why high voltage devices are full on with moderate voltages
on the gate, whereas with low voltage devices the on

Motorola TMOS Power MOSFET Transistors Device Data

Figure 19. Schematic Diagram of all the Components


of the Cross Section of Figure 17

Introduction and Basic Characteristics


39

TMOS Power MOSFET Capacitances:


Two types of intrinsic capacitances occur in the TMOS
power MOSFET those associated with the MOS structure
and those associated with the PN junction.
The two MOS capacitances associated with the MOSFET
cell are:
GateSource Capacitance, Cgs
GateDrain Capacitance, Cgd
The magnitude of each is determined by the die geometry
and the oxides associated with the silicon gate.
The PN junction formed during fabrication of the power
MOSFET results in the draintosource capacitance, Cds.
This capacitance is defined the same as any other planar
junction capacitance and is a direct function of the channel
drain area and the width of the reverse biased junction depletion region.
The dielectric insulator of Cgs and Cgd is basically a glass.
Thus these are very stable capacitors and will not vary with
voltage or temperature. If excessive voltage is placed on the

gate, breakdown will occur through the glass, creating a resistive path and destroying MOSFET operation.
Optimizing TMOS Geometry:
The geometry and packing density of Motorolas
MOSFETs vary according to the magnitude of the reverse
blocking voltage.
The geometry of the source site, as well as the spacing between source sites, represents important factors in efficient
power MOSFET design. Both parameters determine the
channel packing density, i.e.: ratio of channel width per cell to
cell area.
For low voltage devices, channel width is crucial for minimizing RDS(on), since the major contributing component of
RDS(on) is rCH. However, at high voltages, the major contributing component of resistance is rD and thus minimizing
RDS(on) is dependent on maximizing the ratio of active drain
area per cell to cell area. These two conditions for minimizing
RDS(on) cannot be met by a single geometry pattern for both
low and high voltage devices.

Distinct Advantages of Power MOSFETs


Power MOSFETs offer unique characteristics and capabilities that are not available with bipolar power transistors. By
taking advantage of these differences, overall systems cost
savings can result without sacrificing reliability.

Speed
Power MOSFETs are majority carrier devices, therefore
their switching speeds are inherently faster. Without the
minority carrier stored base charge common in bipolar transistors, storage time is eliminated. The high switching
speeds allow efficient switching at higher frequencies which
reduces the cost, size and weight of reactive components.
MOSFET switching speeds are primarily dependent on
charging and discharging the device capacitances and are
essentially independent of operating temperature.

Input Characteristics
The gate of a power MOSFET is electrically isolated from
the source by an oxide layer that represents a dc resistance
greater than 40 megohms. The devices are fully biasedon
with a gate voltage of 10 volts. This significantly simplifies the
drive circuits and in many instances the gate may be driven
directly from logic integrated circuits such as CMOS and TTL
to control high power circuits directly.
Since the gate is isolated from the source, the drive
requirements are nearly independent of the load current.
This reduces the complexity of the drive circuit and results in
overall system cost reduction.

Safe Operating Area


Power MOSFETs, unlike bipolars, do not require derating
of power handling capability as a function of applied voltage.

Introduction and Basic Characteristics


310

The phenomena of second breakdown does not occur within


the ratings of the device. Depending on the application,
snubber circuits may be eliminated or a smaller capacitance
value may be used in the snubber circuit. The safe operating
boundaries are limited by the peak current ratings, breakdown voltages and the power capabilities of the devices.

OnVoltage
The minimum onvoltage of a power MOSFET is determined by the device onresistance RDS(on). For low voltage
devices the value of RDS(on) is extremely low, but with high
voltage devices the value increases. RDS(on) has a positive
temperature coefficient which aids in paralleling devices.

Examples of Advantages Offered by


MOSFETs
High Voltage Flyback Converter
An obvious way of showing the advantages of power
MOSFETs over bipolars is to compare the two devices in the
same system. Since the drive requirements are not the
same, it is not a question of simply replacing the bipolar with
the FET, but one of designing the respective drive circuits to
produce an equivalent output, as described in Figures 110
and 111.
For this application, a peak output voltage of about 700 V
driving a 30 k load (PO(pk) 16 W) was required. With the
component values and timing shown, the inductor/device
current required to generate this flyback voltage would have
to ramp up to about 3.0 A.

Motorola TMOS Power MOSFET Transistor Device Data

+VDD 36 V

1.6 mH

L
1N4725

MTP4N80E
Q1

15 V

Vo 800 V

RL
30 k

CL

68

0.5 F

0
PW 350 s
f = 1.7 kHz

1.0 k

Figure 110. TMOS Output Stage

+VCC 32 V

+V
150 pF

2.2
2.0 W

82

MJE200
Q1

VI
0
0.01 F

180

Vo 700 V

D1
D2
Q4

270

0.5 F

47
27

Q3

D3
MJ8505

MJE200

Q2
1N914

30 k

100
1.0 k
2N2905
V

Figure 111. Bipolar Driver and Output Stage


Figures 110 and 111. Circuit Configurations for a TMOS and
Bipolar Output Stage of a High Voltage Flyback Converter

Figure 110 shows the TMOS version. Because of its high


input impedance, the FET, an MTP4N80E, can be directly
driven from the pulse width modulator. However, the PWM
output should be about 15 volts in amplitude and for relatively fast FET switching be capable of sourcing and sinking
100 mA. Thus, all that is required to drive the FET is a resistor or two. The peak drain current of 3.2 A is within the
MTP4N80E pulsed current rating of 18.0 A (4.0 A continuous), and the turnoff load line of 3.2 A, 700 V is well within
the Switching SOA (18.0 A/800 V) of the device. Thus, the
circuit demonstrates the advantages of TMOS:
High input impedance
Fast Switching

Compare this circuit with the bipolar version of Figure


111.
To achieve the output voltage, using a high voltage Switchmode MJ8505 power transistor, requires a rather complex
drive circuit for generating the proper IB1 and IB2. This circuit
uses three additional transistors (two of which are power
transistors), three Baker clamp diodes, eleven passive components and a negative power supply for generating an off
bias voltage. Also, the RBSOA capability of this device is
only 3.0 A at 900 V and 4.7 A at 800 V, values below the
18.0 A/800 V rating of the MOSFET. A detailed description of
these circuits is shown in Chapter 8, Switching Power
Supplies.

No Second breakdown

Motorola TMOS Power MOSFET Transistors Device Data

Introduction and Basic Characteristics


311

+170 V

+170 V
VCC

1N4933

+10 F

MC34060
Q1 10 H
MC3406
PWM

Q1
MTP4N50E

200

47

56

Q2
MJE13005

MPSA55

Figure 112. TMOS Version

Figure 113. Bipolar Version

Figures 112 and 113. Comparison of Power MOSFET and Bipolar


in the Power Output Stage of a 20 kHz Switcher

20 kHz Switcher
An example of MOSFET advantage over bipolar that illustrates its superior switching speed is shown in the power output section of Figures 112 and 113. In addition to the drive
simplicity and reduced component count, the faster switching
speed offers better circuit efficiency. For this 35 W switching
regulator, using the same small heatsink for either device, a
case temperature rise of only 18C was measured for the
MTP4N50E power MOSFET compared to a 46C rise for the

Introduction and Basic Characteristics


312

MJE13005 bipolar transistor. Although the saturation losses


were greater for the TMOS, its lower switching losses predominated, resulting in a more efficient switching device.
In general, at low switching frequencies, where static
losses predominate, bipolars are more efficient. At higher
frequencies, above 50 kHz, the power MOSFETs are more
efficient.

Motorola TMOS Power MOSFET Transistor Device Data

Chapter 2: Basic Characteristics of Power MOSFETs


Output Characteristics
Perhaps the most direct way to become familiar with the
basic operation of a device is to study its output characteristics. In this case, a comparison of the MOSFET characteristics with those of a bipolar transistor with similar ratings is in
order, since the curves of a bipolar device are almost universally familiar to power circuit design engineers.
As indicated in Figures 21 and 22, the output characteristics of the power MOSFET and the bipolar transistor can be
divided similarly into two basic regions. The figures also
show the numerous and often confusing terms assigned to
those regions. To avoid possible confusion, this section will
refer to the MOSFET regions as the on (or ohmic) and
active regions and bipolar regions as the saturation and
active regions.

Basic MOSFET Parameters

POWER MOSFET
10

I D, DRAIN CURRENT (AMPS)

9.0
8.0

10 V
REGION A
9.0 V
REGION B

7.0
6.0

8.0 V

5.0
4.0
3.0

7.0 V

2.0
1.0
0

6.0 V
VGS = 5.0 V
4.0
8.0
12
16
VDS, DRAINSOURCE VOLTAGE (VOLTS)

Figure 21. IDVDS Output Characteristics of a Power


MOSFET. Region A is Called the Ohmic, On, Constant
Resistance or Linear Region. Region B is Called the
Active, Constant Current, or Saturation Region.
BIPOLAR POWER TRANSISTOR
10
9.0
8.0

One of the three obvious differences between Figures 21


and 22 is the family of curves for the power MOSFET is
generated by changes in gate voltage and not by base current variations. A second difference is the slope of the curve
in the bipolar saturation region is steeper than the slope in
the ohmic region of the power MOSFET indicating that the
onresistance of the MOSFET is higher than the effective
onresistance of the bipolar.
The third major difference between the output characteristics is that in the active regions the slope of the bipolar curve
is steeper than the slope of the TMOS curve, making the
MOSFET a better constant current source. The limiting of ID
is due to pinchoff occurring in the MOSFET channel.

100 mA
REGION A
REGION B

7.0

OnResistance
The onresistance, or RDS(on), of a power MOSFET is an
important figure of merit because it determines the amount of
current the device can handle without excessive power dissipation. When switching the MOSFET from off to on, the
drainsource resistance falls from a very high value to
RDS(on), which is a relatively low value. To minimize RDS(on)
the gate voltage should be large enough for a given drain
current to maintain operation in the ohmic region. Data
sheets usually include a graph, such as Figure 23, which
relates this information. As Figure 24 indicates, increasing
the gate voltage above 12 volts has a diminishing effect on
lowering onresistance (especially in high voltage devices)
and increases the possibility of spurious gatesource voltage
spikes exceeding the maximum gate voltage rating of
20 volts. Somewhat like driving a bipolar transistor deep into
saturation, unnecessarily high gate voltages will increase
turnoff time because of the excess charge stored in the input capacitance. All Motorola TMOS FETs will conduct the
rated continuous drain current with a gate voltage of 10 volts.
As the drain current rises, especially above the continuous
rating, the onresistance also increases. Another important
relationship, which is addressed later with the other temperature dependent parameters, is the effect that temperature
has on the onresistance. Increasing TJ and ID both effect an
increase in RDS(on) as shown in Figure 25.

6.0
5.0
4.0
3.0
2.0

IB = 20 mA
IB = 10 mA

1.0
0

0
4.0
8.0
12
16
VCE, COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 22. ICVCE Output Characteristics of a Bipolar


Power Transistor. Region A is the Saturation Region.
Region B is the Linear or Active Region.

Motorola TMOS Power MOSFET Transistors Device Data

Transconductance
Since the transconductance, or gFS, denotes the gain of
the MOSFET, much like beta represents the gain of the bipolar transistor, it is an important parameter when the device is
operated in the active, or constant current, region. Defined
as the ratio of the change in drain current corresponding to a
change in gate voltage (gFS = dID/dVGS), the transconductance varies with operating conditions as seen in Figure 26.
The value of gFS is determined from the active portion of the
VDSID transfer characteristics where a change in VDS no
longer significantly influences gFS. Typically the transconductance rating is specified at half the rated continuous drain
current and at a VDS of 15 V.

Introduction and Basic Characteristics


313

8.0

1.25
NORMALIZED ONRESISTANCE

I D, DRAIN CURRENT (AMPS)

1.20
VDS = 30 V
6.0

4.0

TJ = 100C

2.0

25C
55C

1.15
1.10
HIGH VOLTAGE
MOSFET

1.05
1.00
0.95
0.90
LOW
VOLTAGE
MOSFET

0.85
0.80

0
0

2.0
4.0
6.0
8.0
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.75
4.0

10

8.0
10
12
14
16
18
VGS, GATETOSOURCE VOLTAGE (VOLTS)

20

Figure 24. The Effect of GatetoSource


Voltage on OnResistance Varies with a
Devices Voltage Rating

0.5

3.0
gFS , FORWARD TRANSCONDUCTANCE
(SIEMENS)

RDS(on), DRAINTOSOURCE RESISTANCE (OHMS)

Figure 23. Transfer Characteristics

6.0

TJ = 100C

0.4

TJ = 25C
0.3
TJ = 55C

0.2

0.1

0
0

5.0

10
15
ID, DRAIN CURRENT (AMPS)

20

25

Figure 25. Variation of RDS(on) with Drain


Current and Temperature

For designers interested only in switching the power


MOSFET between the on and off states, the transconductance is often an unused parameter. Obviously when the device is switched fully on, the transistor will be operating in its
ohmic region where the gate voltage will be high. In that region, a change in an already high gate voltage will do little to
increase the drain current; therefore, gFS is almost zero.
Threshold Voltage
Threshold Voltage, VGS(th), is the lowest gate voltage at
which a specified small amount of drain current begins to
flow. Motorola normally specifies VGS(th) at an ID of one
milliampere. Device designers can control the value of the
threshold voltage and target VGS(th) to optimize device performance and practicality. A low threshold voltage is desired
so the TMOS FET can be controlled by low voltage chips
such as CMOS and TTL. A low value also speeds switching
because less current needs to be transferred to charge the
parasitic input capacitances. But the threshold voltage can
be too low if noise can trigger the device. Also, a positive
going voltage transient on the drain can be coupled to the
gate by the gatetodrain parasitic capacitances and can
cause spurious turnon of a device with a low VGS(th).
Introduction and Basic Characteristics
314

VDS = 15 V
TC = 25C
2.0
CURVE FALLS AS
DEVICE ENTERS
OHMIC REGION
(VDS DEPENDENT)
1.0

0
4.0

5.0

6.0
7.0
8.0
9.0
10
11
VGS, GATETOSOURCE VOLTAGE (VOLTS)

12

Figure 26. SmallSignal Transconductance


versus VGS

Temperature Dependent Characteristics RDS(on)


Junction temperature variations and their effect on the on
resistance, RDS(on), should be considered when designing
with power MOSFETs. Since RDS(on) varies approximately
linearly with temperature, power MOSFETs can be assigned
temperature coefficients that describe this relationship.
Figure 27 shows that the temperature coefficient of
RDS(on) is greater for high voltage devices than for low
voltage MOSFETs. A graph showing the variation of RDS(on)
with junction temperature is shown on most data sheets, Figure 25.
Switching Speeds are Constant with Temperature
High junction temperatures emphasize one of the most desirable characteristics of the MOSFET, that of low dynamic or
switching losses. In the bipolar transistor, temperature increases will increase switching times, causing greater dynamic losses. On the other hand, thermal variations have
little effect on the switching speeds of the power MOSFET.
These speeds depend on how rapidly the parasitic input capacitances can be charged and discharged. Since the magnitudes of these capacitances are essentially temperature
Motorola TMOS Power MOSFET Transistor Device Data

invariant, so are the switching speeds. Therefore, as temperature increases, the dynamic losses in a MOSFET are low
and remain constant, while in the bipolar transistors the
switching losses are higher and increase with junction temperature.
DrainToSource Breakdown Voltage
The draintosource breakdown voltage is a function of
the thickness and resistivity of a devices Nepitaxial region.
Since that resistivity varies with temperature, so does
V(BR)DSS. As Figure 28 indicates, a 100C rise in junction
temperature causes a V(BR)DSS to increase by about 10%.
However, it should also be remembered that the actual
V(BR)DSS falls at the same rate as TJ decreases.

NORMALIZED ONRESISTANCE

2.0

1.8

1.6
400 V MOSFET

1.4

Importance of TJ(max) and Heat Sinking


Two of the packages that commonly house the TMOS die
are the TO220AB and the TO204. The power ratings of
these packages range from 40 to 250 watts depending on
the die size and the type of materials used in construction.
These ratings are nearly meaningless, however, unless
some heat sinking is provided. Without heat sinking the
TO204 and the TO220 can dissipate only about 4.0 and
2.0 watts respectively, regardless of the die size.
Because long term reliability decreases with increasing
junction temperature, TJ should not exceed the maximum
rating of 150C. Steadystate operation above 150C also
invites abrupt and catastrophic failure if the transistor experiences additional transient thermal stresses. Excluding the
possibility of thermal transients, operating below the rated
junction temperature can enhance reliability. A TJ(max) of
150C is normally chosen as a safe compromise between
long term reliability and maximum power dissipation.
In addition to increasing the reliability, proper heat sinking
can reduce static losses in the power MOSFET by decreasing the onresistance. RDS(on), with its positive temperature
coefficient, can vary significantly with the quality of the heat
sink. Good heat sinking will decrease the junction temperature, which further decreases RDS(on) and the static losses.

60 V MOSFET
1.2

DrainSource Diode

1.0
25

50

75
100
TJ, JUNCTION TEMPERATURE

125

150

Figure 27. The Influence of Junction


Temperature on OnResistance Varies with
Breakdown Voltage
Threshold Voltage
The gate voltage at which the MOSFET begins to conduct,
the gatethreshold voltage, is temperature dependent. The
variation with TJ is linear as shown on most data sheets.
Having a negative temperature coefficient, the threshold
voltage falls about 10% for each 45C rise in the junction
temperature.

Inherent in most power MOSFETs, and all TMOS transistors, is a parasitic drainsource diode. Figure 29, the
illustration of cross section of the TMOS die, shows the PN
junction formed by the Pwell and the NEpi layer. Because
of its extensive junction area, the current ratings of the diode
are the same as the MOSFETs continuous and pulsed current ratings. For the NChannel TMOS FET shown in Figure
210, this diode is forward biased when the source is at a
positive potential with respect to the drain. Since the diode
may be an important circuit element, Motorola Designers
Data Sheets specify typical values of the forward onvoltage,
forward turnon and reverse recovery time. The forward
characteristic of the drainsource diode of a TMOS power
MOSFET is shown in Figure 211.

1.20
SOURCE
METALIZATION

NORMALIZED DRAINTOSOURCE
BREAKDOWN VOLTAGE

SOURCE SITE
1.15
1.10
1.05

SILICON
GATE

1.00

NCHANNEL

0.95

DRAIN CURRENT

0.90

INSULATING OXIDE, SiO2

0.85
0.80
50

NEpi LAYER
25

25

50

75

100

125

150

NSUBSTRATE

DRAIN
METALIZATION

TJ, JUNCTION TEMPERATURE

Figure 28. Typical Variation of


DraintoSource Breakdown Voltage with
Junction Temperature
Motorola TMOS Power MOSFET Transistors Device Data

Figure 29. Cross Section of TMOS Cell

Introduction and Basic Characteristics


315

DRAIN

GATE

SOURCE

Figure 210. NChannel Power MOSFET Symbol


Including DrainSource Diode
Most rectifiers, a notable exception being the Schottky
diode, exhibit a reverse recovery characteristic as depicted
in Figure 212. When forward current flows in a standard
diode, a carrier gradient is formed in the high resistivity side
of the junction resulting in an apparent storage of charge.
Upon sudden application of a reverse bias, the stored charge
temporarily produces a negative current flow during the reverse recovery time, or trr, until the charge is depleted. The
circuit conditions that influence trr and the stored charge are
the forward current magnitude and the rate of change of current from the forward current magnitude to the reverse current peak. When tested under the same circuit conditions,
the parasitic drainsource diode of a TMOS transistor has a
trr similar to that of a fast recovery rectifier.

100

In many applications, the drainsource diode is never


forward biased and does not influence circuit operation.
However, in multitransistor configurations, such as the
totem pole network of Figure 213, the parasitic diodes play
an important and useful role. Each transistor is protected
from excessive flyback voltages, not by its own drainsource
diode, but by the diode of the opposite transistor. As an
illustration, assume that Q2 of Figure 213 is turned on, Q1
is off and current is flowing up from ground, through the load
and into Q2. When Q2 turns off, current is diverted into the
drainsource diode of Q1 which clamps the loads inductive
kick to V+. By similar reasoning, one can see that D2 protects
Q1 during its turnoff.
As a note of caution, it should be realized that diode recovery problems may arise when using MOSFETs in multiple
transistor configurations. A treatment of the subject in Chapter 5 gives greater details.
TMOS power MOSFET intrinsic diodes also have forward
recovery times, meaning that they do not instantaneously
conduct when they are forward biased. However, since those
times are so brief, typically less than 10 ns, their effect on circuit operation can almost always be ignored. Package, lead
and wiring inductance are often at least as great a factor in
limiting current rise time.

Is = 0.5 A/div
0

50

I s , DS DIODE FORWARD CURRENT (AMPS)

t = 50 ns/div

10

Figure 212. Typical Reverse Recovery


Characteristics of a DrainSource Diode

5.0

TC + 25C
300 S Pulse 60 pps

+V

1.0
0.5

Q1

0.1

Q2

RL
0

1.0

2.0

3.0

4.0

5.0

6.0

VSD, DD DIODE FORWARD ONVOLTAGE (VOLTS)


V

Figure 211. Forward Characteristics of Power


MOSFETs DS Diodes

Introduction and Basic Characteristics


316

Figure 213. TMOS Totem Pole Network with


Integral DrainSource Diodes

Motorola TMOS Power MOSFET Transistor Device Data

Chapter 3: The Data Sheet


Introduction
Motorola prides itself in having one of the most complete
and accurate Power MOSFET data sheets in the industry.
For consistency, data sheet templates have been established for each technology and or application grouping. This
insures that the best approach is used in describing the performance characteristics of each device for the applications
they are used in. Additionally, this allows for the automation
of the data sheet generation process which has lead to a

reduction in new product introduction cycle time as well as


providing more accurate and repeatable data.

Headline Information
Motorolas TMOS Power MOSFET numbering system
contains coded information describing technology, package,
current and voltage information. A complete explanation of
the nomenclature used is contained in Figure 31.

MTP75N06HD
MOTOROLA
X FOR ENGINEERING SAMPLES
TMOS
T FOR TMOS
L FOR SMARTDISCRETES
G FOR IGBT
P FOR MULTIPLE CHIP PRODUCTS
PACKAGE TYPE
P FOR PLASTIC TO220
M FOR METAL TO204 (TO3)/ICePAK
D FOR DPAK
A FOR TO220 ISOLATED
W FOR TO247
B FOR D2PAK
Y FOR TO264
E FOR SOT227B

OPTIONAL SUFFIX:
L FOR LOGIC LEVEL
E FOR ENERGY RATED
T4 FOR TAPE & REEL (DPAK/D2PAK)
RL FOR TAPE & REEL (DPAK)
HD FOR HIGH CELL DENSITY
V FOR TMOS V (FIVE)
VOLTAGE RATING DIVIDED BY 10
CHANNEL POLARITY, N OR P

Example of exceptions: MTD/MTP3055E


Example of exceptions: MTD/MTP2955E

CURRENT

SO8 (MiniMOS) and SOT223 Power MOSFETs


MMSF4P01HDR1
R1 AND R2 FOR TAPE & REEL
MiniMOS

MOTOROLA
TMOS
M FOR MINIATURE
PACKAGE TYPE
DF DUAL FET
SF SINGLE FET
FT FET TRANSISTOR

OPTIONAL SUFFIX:
E FOR ENERGY RATED
HD FOR HIGH CELL DENSITY
L FOR LOGIC LEVEL
VOLTAGE RATING DIVIDED BY 10
CHANNEL POLARITY, N OR P
C FOR COMPLEMENTARY

CURRENT

Figure 31. TMOS Power MOSFET Numbering System

Motorola TMOS Power MOSFET Transistors Device Data

Introduction and Basic Characteristics


317

Absolute Maximum Ratings


Absolute maximum ratings represent the extreme capabilities of the device. They can best be described as device
characterization boundaries and are given to facilitate worst
case design.

DraintoSource Voltage (VDSS , VDGR ) This represents


the lower limit of the devices blocking voltage capability from
draintosource when either the gate is shorted to the
source (VDSS), or when a 1 M gatetosource resistor is
present (VDGR). It is measured at a specific leakage current
and has a positive temperature coefficient. The voltage
across the Power MOSFET should never exceed this rating
in order to prevent breakdown of the draintosource
junction.
Maximum GatetoSource Voltage (VGS , VGSM ) The
maximum allowable gatetosource voltage as either a continuous condition (VGS), or as a single pulse nonrepetitive
condition (VGSM). Exceeding this limit may result in permanent device degradation.
Continuous Drain Current (ID ) The dc current level that
will raise the devices junction temperature to its rated maximum while its reference temperature is held at 25C. This
can be calculated by the equation:
ID = SQRT (PD/RDS(on) @ MAX TJ)
where,
SQRT = Square root
PD
= Devices maximum power dissipation
RDS(on) = Devices on resistance
MAX TJ = Devices maximum rated junction temperature

Pulsed Drain Current (IDM ) The maximum allowable peak


drain current the device can safely handle under a 10 s
pulsed condition. This rating takes into consideration the devices thermal limitation as well as RDS(on), wire bond and
source metal limitations.
DraintoSource Avalanche Energy (EAS) This specification defines the maximum allowable energy that the device
can safely handle in avalanche due to an inductive current
spike. It is tested at the ID of the device as a single pulse
nonrepetitive condition. This value has a negative temperature coefficient as shown by the Maximum Avalanche Energy versus Starting Junction Temperature figure shown in the
data sheet. For repetitive avalanche conditions, this value
should be derated using the Thermal Response figure
shown in the data sheet for calculating the junction temperature and the Maximum Avalanche Energy versus Starting
Junction Temperature figure also shown in the data sheet.
Maximum Power Dissipation (PD ) Specifies the power
dissipation limit which takes the junction temperature to its
maximum rating while the reference temperature is being
held at 25C. It is calculated by the following equation:
PD
where,
PD
TJ
Tr
Rthjr

= (TJ Tr)/Rthjr
= Maximum power dissipation
= Maximum allowable junction temperature
= Reference (case and or ambient) temperature
= Thermal resistance junctiontoreference
= (case or ambient)

Introduction and Basic Characteristics


318

Junction Temperature (TJ ) This value represents the


maximum allowable junction temperature of the device. It is
derived and based off of long term Reliability data. Exceeding this value will only serve to shorten the devices long term
operating life.
Thermal Resistance (Rthjc , Rthja ) The quantity that resists
or impedes the flow of heat energy in a device is called thermal resistance. Thermal resistance values are needed for
proper thermal design. These values are measured as detailed in Motorola Application Note AN1083.

Electrical Characteristics
The intent of this section in the data sheet is to provide detailed device characterization so that the designer can predict with a high degree of accuracy the behavior of the device
in a specific application.

DraintoSource Breakdown Voltage (V(BR)DSS ) As described earlier, this represents the lower limit of the devices
blocking voltage capability from draintosource with the
gate shorted to the source. It is measured at a specific leakage current and has a positive temperature coefficient.
Zero Gate Voltage Drain Current (IDSS ) The direct current
into the drain terminal of the device when the gatetosource
voltage is zero and the drain terminal is reversed biased with
respect to the source terminal. This parameter generally increases with temperature as shown in the DraintoSource
Leakage Current versus Voltage figure found in the devices
data sheet.
GateBody Leakage Current (IGSS ) The direct current
into the gate terminal of the device when the gate terminal is
biased with either a positive or negative voltage with respect
to the source terminal and the drain terminal is short
circuited to the source terminal.
Gate Threshold Voltage (VGS(th) ) The forward gateto
source voltage at which the magnitude of drain current has
been increased to some low threshold value, usually
specified as 250 A or 1 mA. This parameter has a negative
temperature coefficient.
DraintoSource OnResistance (RDS(on) ) The dc resistance between the draintosource terminals with a specified gatetosource voltage applied to bias the device into
the onstate. This parameter has a positive temperature
coefficient.
DraintoSource OnVoltage (VDS(on) ) The dc voltage
between the draintosource terminals with a specified
gatetosource voltage applied to bias the device into the
onstate. This parameter has a positive temperature coefficient.
Forward Transconductance (gFS ) The ratio of the
change in drain current due to a change in gatetosource
voltage (i.e., ID/ VGS).
Device Capacitance (Ciss , Coss , Crss ) Power MOSFET
devices have internal parasitic capacitance from terminal
toterminal. This capacitance is voltage dependent as
shown by the Capacitance Variation figure on the devices
data sheet. Ciss is the capacitance between the gateto
source terminals with the drain terminal shortcircuited to the
source terminal for alternating current. Coss is the capacitance between the draintosource terminals with the gate
Motorola TMOS Power MOSFET Transistor Device Data

shortcircuited to the source terminal for alternating current.


Crss is the capacitance between the draintogate terminals
with the source terminal connected to the guard terminal of a
threeterminal bridge (Ref. IEEE No. 255). Figures 32, 33
and 34 show test circuits used for Power MOSFET capacitance measurements.

VGS(on)
RL
PULSE
GENERATOR

LOW
IMPEDANCE
DRIVER

VDD

MTP
3055V

RG
+VR

IM
L
B
I
A
S

M
E
A
S.

CAP.
METER
H

L
O
O
P

Cgd
Cds

IM

Figure 35. Switching Test Circuit

0.1
F

ton

C1

Cgs

toff

td(off)

GUARD

tr

tf
90%

90%

OUTPUT, Vout
INVERTED

td(off)

10%
90%

L = 2.5 mH
INPUT, Vin

50%

50%

10%

VDS

PULSE WIDTH

Figure 32. Ciss Test Configuration

Figure 36. Switching Waveforms

IM D
L
B
I
A
S

M
E
A
S.
IM

CAP.
METER
H

L
O
O
P

Cgd
Cds
G

Cgs

GUARD
S

Forward OnVoltage (VSD ) The dc voltage between the


sourcetodrain terminals when the power MOSFETs intrinsic body diode is forward biased.

VDS

Figure 33. Coss Test Configuration


IM

L
B
I
A
S

CAP.
METER

M
E
A
S.

L
O
O
P IM

Cgd
Cds

H
G

Gate Charge (QT, Q1 , Q2 ) Gate charge values are used to


size the gate drive circuit and to estimate switching speeds
and switching losses. QT is defined as the total gate charge
required to charge the devices input capacitance to the applied gate voltage. Q1 is defined as the charge required to
charge the devices input capacitance to the VGS(on) required
to maintain the test current ID. The time required to deliver
this charge is called turnon delay time. Q2 is defined as the
charge time required for the draintosource voltage to drop
to VDS(on).

Cgs

GUARD
S

Reverse Recovery Time (trr , ta , tb , QRR ) The intrinsic


body diode of a power MOSFET is a minority carrier device
and thus has a finite reverse recovery time. Ta is defined as
the time between the dropping IS currents zero crossing
point to the peak IRM. Tb is defined as the time between the
peak IRM to a projected IRM zero current crossing point
through a 25% IRM projection as shown in Figure 37. Total
reverse recovery time, trr, is defined as the sum of ta and tb.
QRR is defined as the integral of the area made up by the IRM
waveform and VR, the reapplied blocking voltage which
forces reverse recovery.

+
VDS

di/dt
IS

Figure 34. Crss Test Configuration

Resistive Switching (td(on) , tr , td(off) , tf ) MOSFET switching speeds are very fast, relative to comparably sized bipolar
transistors. They are tested and measured using a resistive
switching test circuit as shown in Figure 35. A typical
switching waveform showing parameter measurement points
is shown in Figure 36.
Motorola TMOS Power MOSFET Transistors Device Data

trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 37. Diode Reverse Recovery Waveform


Introduction and Basic Characteristics
319

Introduction and Basic Characteristics


320

Motorola TMOS Power MOSFET Transistor Device Data

Section Four
Data Sheets

Motorola TMOS Power MOSFET Transistor Device Data

41

MC33153

Advance Information
Single IGBT Gate Driver
The MC33153 is specifcally designed as an IGBT driver for high power
applications that include ac induction motor control, brushless dc motor control and uninterruptable power supplies. Although designed for driving discrete and module IGBTs, this device offers a cost effective solution for
driving power MOSFETs and Bipolar Transistors. Device protection features
include the choice of desaturation or overcurrent sensing and undervoltage
detection. These devices are available in dualinline and surface mount
packages and include the following features:

SINGLE IGBT
GATE DRIVER
SEMICONDUCTOR
TECHNICAL DATA

High Current Output Stage: 1.0 A Source/2.0 A Sink


Protection Circuits for Both Conventional and Sense IGBTs
Programmable Fault Blanking Time
Protection against Overcurrent and Short Circuit
Undervoltage Lockout Optimzed for IGBTs

Negative Gate Drive Capability

Cost Effectively Drives Power MOSFETs and Bipolar Transistors


P SUFFIX
PLASTIC PACKAGE
CASE 626

Representative Block Diagram


VCC
6
VCC
Fault
Output 7
VEE

Short Circuit
Latch
S
Q
R

VCC

8
1

Short Circuit
Comparator

D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO8)

VCC
Overcurrent
Comparator

Overcurrent
Latch
S
Q
R

Current
Sense
1 Input

130 mV
65 mV
VCC

VEE
VCC

Kelvin
Gnd

PIN CONNECTIONS

270 mA

Fault Blanking/
Desaturation
Comparator

6.5 V

VEE

Fault
8 Blanking/
Desaturation
Input

Current Sense
Input

8 Fault Blanking/
Desaturation Input

Kelvin Gnd

7 Fault Output

VEE

6 VCC

Input

5 Drive Output

VCC
Output
Stage

VCC
Input

VCC

4
VEE

Drive
5 Output

Under
Voltage
Lockout

(Top View)
VEE

ORDERING INFORMATION
12 V/
11 V
3

VEE

This device contains 133 active transistors.

Device

Package

TA = 40 to +105C

DIP8

MC33153D
MC33153P

42

Operating
Temperature Range

SO8

Motorola TMOS Power MOSFET Transistor Device Data

MC33153
MAXIMUM RATINGS
Rating

Symbol

Value

VCC VEE
KGnd VEE

23
23

Logic Input

Vin

VEE 0.3 to VCC

Current Sense Input

VS

0.3 to VCC

VBD

0.3 to VCC

Power Supply Voltage


VCC to VEE
Kelvin Ground to VEE

Unit
V

Blanking/Desaturation Input
Gate Drive Output
Source Current
Sink Current
Diode Clamp Current

IO

A
1.0
2.0
1.0

Fault Output
Source Current
Sink Curent

IFO

mA
25
10

Power Dissipation and Thermal Characteristics


D Suffix SO8 Package, Case 751
Maximum Power Dissipation @ TA = 50C
Thermal Resistance, JunctiontoAir
P Suffix DIP8 Package, Case 626
Maximum Power Dissipation @ TA = 50C
Thermal Resistance, JunctiontoAir

PD
RJA

0.56
180

W
C/W

PD
RJA

1.0
100

W
C/W

Operating Junction Temperature

TJ

+150

Operating Ambient Temperature

TA

40 to +105

Tstg

65 to +150

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25C, for min/max values TA is the operating ambient temperature range that applies (Note 1), unless otherwise noted.)
Symbol

Min

Typ

Max

Input Threshold Voltage


High State (Logic 1)
Low State (Logic 0)

VIH
VIL

1.2

2.70
2.30

3.2

Input Current
High State (VIH = 3.0 V)
Low State (VIL = 1.2 V)

IIH
IIL

130
50

500
100

Output Voltage
Low State (ISink = 1.0 A)
High State (ISource = 500 mA)

VOL
VOH

12

2.0
13.9

2.5

Output PullDown Resistor

RPD

200

VFL
VFH

12

0.2
13.3

1.0

tPLH(in/out)
tPHL (in/out)

80
120

300
300

Drive Output Rise Time (10% to 90%) CL = 1.0 nF

tr

17

55

ns

Drive Output Fall Time (90% to 10%) CL = 1.0 nF

tf

17

55

ns

tP(OC)

0.3

1.0

Characteristic

Unit

LOGIC INPUT
V

DRIVE OUTPUT
V

FAULT OUTPUT
Output voltage
Low State (ISink = 5.0 mA)
High State (ISource = 20 mA)

SWITCHING CHARACTERISTICS
Propagation Delay (50% Input to 50% Output CL = 1.0 nF)
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall

Propagation Delay
Current Sense Input to Drive Output
NOTE:

ns

1. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
Tlow = 40C for MC33153
Thigh = +105C for MC33153

Motorola TMOS Power MOSFET Transistor Device Data

43

MC33153
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25C, for min/max values TA is the operating ambient temperature range that applies (Note 1), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
SWITCHING CHARACTERISTICS (continued)
Fault Blanking/Desaturation Input to Drive Output

Unit

tP(FLT)

0.3

1.0

Startup Voltage

VCC start

12

12.6

Disable Voltage

VCC dis

10.4

11

Overcurrent Threshold Voltage (VPin8 > 7.0 V)

VSOC

50

65

80

mV

Short Circuit Threshold Voltage (VPin8 > 7.0 V)

VSSC

100

130

160

mV

Vth(FLT)

6.0

6.5

7.0

ISI

1.4

10

Ichg

200

270

300

Idschg

1.0

2.5

mA

7.2
7.9

14
20

UVLO

COMPARATORS

Fault Blanking/Desaturation Threshold (VPin1 > 100 mV)


Current Sense Input Current (VSI = 0 V)
FAULT BLANKING/DESATURATION INPUT
Current Source (VPin8 = 0 V, VPin4 = 0 V)
Discharge Current (VPin8 = 15 V, VPin4 = 5.0 V)
TOTAL DEVICE
Power Supply Current
Standby (VPin 4 = VCC, Output Open)
Operating (CL = 1.0 nF, f = 20 kHz)
NOTE:

ICC

mA

1. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
Tlow = 40C for MC33153
Thigh = +105C for MC33153

Figure 2. Output Voltage versus Input Voltage

Figure 1. Input Current versus Input Voltage


1.5

16
VCC = 15 V
TA = 25C

VO , OUTPUT VOLTAGE (V)

I in , INPUT CURRENT (mA)

14
1.0

0.5
VCC = 15 V
TA = 25C
0

2.0

4.0

6.0

8.0

10

Vin, INPUT VOLTAGE (V)

44

12

14

12
10
8.0
6.0
4.0
2.0

16

1.0

2.0

3.0

4.0

5.0

Vin, INPUT VOLTAGE (V)

Motorola TMOS Power MOSFET Transistor Device Data

MC33153
Figure 4. Input Threshold Voltage
versus Supply Voltage

VCC = 15 V
3.0

2.6
2.4
VIL

2.2
2.0
60

40

20

20

40

60

80

100

120

140

TA = 25C

VIH
2.7
2.6
2.5
2.4
VIL

2.3
2.2
12

13

14

15

16

17

18

19

20

VCC, SUPPLY VOLTAGE (V)

Figure 5. Drive Output Low State Voltage


versus Temperature

Figure 6. Drive Output Low State Voltage


versus Sink Current
V OL, OUTPUT LOW STATE VOLTAGE (V)

ISink = 1.0 A

2.0

= 500 mA
1.5
= 250 mA
1.0
0.5
VCC = 15 V
40

20

20

40

60

80

100

120

2.0
1.6
1.2
0.8
0.4
0

140

TA = 25C
VCC = 15 V
0

0.2

0.4

0.6

0.8

1.0

TA, AMBIENT TEMPERATURE (C)

ISink, OUTPUT SINK CURRENT (A)

Figure 7. Drive Output High State Voltage


versus Temperature

Figure 8. Drive Output High State Voltage


versus Source Current

14.0
13.9
13.8
13.7
VCC = 15 V
ISource = 500 mA

13.6
13.5
60

2.8

TA, AMBIENT TEMPERATURE (C)

2.5

0
60

VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)

VIH

2.8

V IH V IL , INPUT THRESHOLD VOLTAGE (V)

3.2

40

20

20

40

60

80

100

120

140

TA, AMBIENT TEMPERATURE (C)

Motorola TMOS Power MOSFET Transistor Device Data

VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)

V OL, OUTPUT LOW STATE VOLTAGE (V)

V IH V IL , INPUT THRESHOLD VOLTAGE (V)

Figure 3. Input Threshold Voltage


versus Temperature

15.0
VCC = 15 V
TA = 25C

14.6
14.2
13.8
13.4
13.0

0.1

0.2

0.3

0.4

0.5

ISource, OUTPUT SOURCE CURRENT (A)

45

MC33153
Figure 10. Fault Output Voltage
versus Current Sense Input Voltage

Figure 9. Drive Output Voltage


versus Current Sense Input Voltage

12
10
8.0
6.0
4.0
2.0
55

60

65

70

75

10
8.0
6.0
4.0
2.0
110

120

130

140

150

VPin 1, CURRENT SENSE INPUT VOLTAGE (mV)

VPin 1, CURRENT SENSE INPUT VOLTAGE (V)

Figure 11. Overcurrent Protection Threshold


Voltage versus Temperature

Figure 12. Overcurrent Protection Threshold


Voltage versus Supply Voltage

70
VCC = 15 V

68
66
64
62
60
60 40

20

20

40

60

80

100

120

140

160

70
TA = 25C

68
66
64
62
60
12

14

16

18

20

TA, AMBIENT TEMPERATURE (C)

VCC, SUPPLY VOLTAGE (V)

Figure 13. Short Circuit Comparator Threshold


Voltage versus Temperature

Figure 14. Short Circuit Comparator Threshold


Voltage versus Supply Voltage

135
VCC = 15 V

130

125
60

40

20

20

40

60

80

TA, AMBIENT TEMPERATURE (C)

46

VCC = 15 V
VPin 4 = 0 V
VPin 8 > 7.0 V
TA = 25C

12

0
100

80

V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)

V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)

0
50

VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)

V Pin 7, FAULT OUTPUT VOLTAGE (V)

14
VCC = 15 V
VPin 4 = 0 V
VPin 8 > 7.0 V
TA = 25C

14

100

120

140

VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)

VO , DRIVE OUTPUT VOLTAGE (V)

16

135
TA = 25C

130

125
12

14

16

18

20

VCC, SUPPLY VOLTAGE (V)

Motorola TMOS Power MOSFET Transistor Device Data

Figure 16. Drive Output Voltage versus Fault


Blanking/Desaturation Input Voltage

Figure 15. Current Sense Input Current


versus Voltage
0

16
VO , DRIVE OUTPUT VOLTAGE (V)

ISI , CURRENT SENSE INPUT CURRENT ( A)

MC33153

VCC = 15 V
TA = 25C
0.5

1.0

1.5

2.0

4.0

6.0

8.0

10

12

14

14

VCC = 15 V
VPin 4 = 0 V
VPin 1 > 100 mV
TA = 25C

12
10
8.0
6.0
4.0
2.0
0
6.0

16

VPin 1, CURRENT SENSE INPUT VOLTAGE (V)

6.6
VCC = 15 V
VPin 4 = 0 V
VPin 1 > 100 mV
6.5

40

20

20

40

60

80

100

120

140

6.6

6.8

7.0

6.6
VPin 4 = 0 V
VPin 1 > 100 mV
TA = 25C
6.5

6.4
12

14

16

18

20

TA, AMBIENT TEMPERATURE (C)

VCC, SUPPLY VOLTAGE (V)

Figure 19. Fault Blanking/Desaturation Current


Source versus Temperature

Figure 20. Fault Blanking/Desaturation Current


Source versus Supply Voltage

200

200
VCC = 15 V
VPin 8 = 0 V

220

Ichg, CURRENT SOURCE ( A)

Ichg, CURRENT SOURCE ( A)

6.4

Figure 18. Fault Blanking/Desaturation Comparator


Threshold Voltage versus Supply Voltage
V BDT , FAULT BLANKING/DESATURATION
THRESHOLD VOLTAGE (V)

V BDT , FAULT BLANKING/DESATURATION


THRESHOLD VOLTAGE (V)

Figure 17. Fault Blanking/Desaturation Comparator


Threshold Voltage versus Temperature

6.4
60

6.2

VPin 8, FAULT BLANKING/DESATURATION INPUT VOLTAGE (V)

240
260
280
300
60

40

20

20

40

60

80

100

120

TA, AMBIENT TEMPERATURE (C)

Motorola TMOS Power MOSFET Transistor Device Data

140

VPin 4 = 0 V
VPin 8 = 0 V
TA = 25C

220
240
260
280
300
5.0

10

15

20

VCC, SUPPLY VOLTAGE (V)

47

MC33153
Figure 22. Fault Blanking/Desaturation Discharge
Current versus Input Voltage

Figure 21. Fault Blanking/Desaturation


Current Source versus Input Voltage

2.5
I dscg, DISCHARGE CURRENT (mA)

I chg, CURRENT SOURCE ( A)

200
VCC = 15 V
VPin 4 = 0 V
TA = 25C

220
240
260
280
300

2.0

4.0

6.0

8.0

10

12

14

0.5
VCC = 15 V
VPin 4 = 5.0 V
TA = 25C

4.0

12

16

Figure 23. Fault Output Low State Voltage


versus Sink Current

Figure 24. Fault Output High State Voltage


versus Source Current
14.0

VCC = 15 V
VPin 4 = 5.0 V
TA = 25C

0.8
0.6
0.4
0.2

2.0

4.0

6.0

8.0

13.6
13.4
13.2
13.0

10

VCC = 15 V
VPin 4 = 0 V
VPin 1 = 1.0 V
Pin 8 = Open
TA = 25C

13.8

2.0

4.0

10

12

14

16

Figure 25. Drive Output Voltage


versus Supply Voltage

Figure 26. UVLO Thresholds


versus Temperature

18

20

120

140

12.5
Vth(UVLO), UNDERVOLTAGE
LOCKOUT THRESHOLD (V)

10
TurnOff
Threshold

6.0
4.0

Startup
Threshold

2.0
0
10

8.0

ISource, OUTPUT SOURCE CURRENT (mA)

12

8.0

6.0

ISink, OUTPUT SINK CURRENT (mA)

Startup Threshold
VCC Increasing

14

11

12

13

VCC, SUPPLY VOLTAGE (V)

48

8.0
VPin 8, INPUT VOLTAGE (V)

VPin 7 , FAULT OUTPUT VOLTAGE (V)

VPin 7 , FAULT OUTPUT VOLTAGE (V)

1.0

VPin 8, INPUT VOLTAGE (V)

16
VO , DRIVE OUTPUT VOLTAGE (V)

1.5

0.5

16

1.0

2.0

VPin 4 = 0 V
TA = 25C
14

15

12.0

11.5
TurnOff Threshold
VCC Decreasing

11.0

10.5
60

40

20

20

40

60

80

100

TA, AMBIENT TEMPERATURE (C)

Motorola TMOS Power MOSFET Transistor Device Data

MC33153
Figure 27. Supply Current versus
Supply Voltage

Figure 28. Supply Current versus Temperature


10

Output High

8.0

ICC, SUPPLY CURRENT (mA)

ICC, SUPPLY CURRENT (mA)

10

Output Low
6.0
4.0
TA = 25C

2.0
0
5.0

10

15

20

8.0
6.0
4.0
VCC = 15 V
VPin 4 = VCC
Drive Output Open

2.0
0
60

40

20

20

40

60

80

100

120

140

TA, AMBIENT TEMPERATURE (C)

VCC, SUPPLY VOLTAGE (V)

Figure 29. Supply Current versus Input Frequency

ICC, SUPPLY CURRENT (mA)

80

CL = 10 nF

VCC = 15 V
TA = 25C

= 5.0 nF

60

40
= 2.0 nF
20
= 1.0 nF
0
1.0

10

100

1000

f, INPUT FREQUENCY (Hz)

OPERATING DESCRIPTION
GATE DRIVE
Controlling Switching Times
The most important design aspect of an IGBT gate drive is
optimization of the switching characteristics. The switching
characteristics are especially important in motor control
applications in which PWM transistors are used in a bridge
configuration. In these applications, the gate drive circuit
components should be selected to optimize turnon, turnoff
and offstate impedance. A single resistor may be used to
control both turnon and turnoff as shown in Figure 30.
However, the resistor value selected must be a compromise
in turnon abruptness and turnoff losses. Using a single
resistor is normally suitable only for very low frequency
PWM. An optimized gate drive output stage is shown in Figure 31. This circuit allows turnon and turnoff to be optimized separately. The turnon resistor, Ron, provides control
over the IGBT turnon speed. In motor control circuits, the
resistor sets the turnon di/dt that controls how fast the free
wheel diode is cleared. The interaction of the IGBT and free
wheeling diode determines the turnon dv/dt. Excessive
turnon dv/dt is a common problem in halfbridge circuits.

Motorola TMOS Power MOSFET Transistor Device Data

The turnoff resistor, Roff, controls the turnoff speed and


ensures that the IGBT remains off under commutation
stresses. Turnoff is critical to obtain low switching losses.
While IGBTs exhibit a fixed minimum loss due to minority carrier recombination, a slow gate drive will dominate the turn
off losses. This is particularly true for fast IGBTs. It is also
possible to turnoff an IGBT too fast. Excessive turnoff
speed will result in large overshoot voltages. Normally, the
turnoff resistor is a small fraction of the turnon resistor.
The MC33153 contains a bipolar totem pole output stage
that is capable of sourcing 1.0 amp and sinking 2.0 amps
peak. This output also contains a pull down resistor to ensure
that the IGBT is off whenever there is insufficient VCC to the
MC33153.
In a PWM inverter, IGBTs are used in a halfbridge configuration. Thus, at least one device is always off. While the
IGBT is in the offstate, it will be subjected to changes in voltage caused by the other devices. This is particularly a problem when the opposite transistor turns on.

49

MC33153
When the lower device is turned on, clearing the upper
diode, the turnon dv/dt of the lower device appears across
the collector emitter of the upper device. To eliminate shoot
through currents, it is necessary to provide a low sink impedance to the device that is in the offstate. In most applications
the turnoff resistor can be made small enough to hold off the
device that is under commutation without causing excessively fast turnoff speeds.

Figure 30. Using a Single Gate Resistor


VCC

Optoisolator Output Fault

IGBT

Output

The MC33153 has an active high fault output. The fault


output may be easily interfaced to an optoisolator. While it is
important that all faults are properly reported, it is equally
important that no false signals are propagated. Again, a high
dv/dt optoisolator should be used.
The LED drive provides a resistor programmable current
of 10 to 20 mA when on, and provides a low impedance path
when off. An active high output, resistor, and small signal
diode provide an excellent LED driver. This circuit is shown in
Figure 32.

Rg

VEE

VEE

3
VEE

Figure 31. Using Separate Resistors


for TurnOn and TurnOff
VCC

Figure 32. Output Fault Optoisolator

IGBT
Ron
Output
5

Doff

Roff

VEE

VEE

The MC33153 may be used with an optically isolated


input. The optoisolator can be used to provide level shifting,
and if desired, isolation from ac line voltages. An optoisolator
with a very high dv/dt capability should be used, such as the
Hewlett Packard HCPL4053. The IGBT gate turnon resistor
should be set large enough to ensure that the optos dv/dt
capability is not exceeded. Like most optoisolators, the
HCPL4053 has an active low opencollector output. Thus,
when the LED is on, the output will be low. The MC33153 has
an inverting input pin to interface directly with an optoisolator
using a pull up resistor. The input may also be interfaced
directly to 5.0 V CMOS logic or a microcontroller.

Short Circuit
Latch Output

VCC

Q
7

VEE

VEE

VEE

UNDERVOLTAGE LOCKOUT
A negative bias voltage can be used to drive the IGBT into
the offstate. This is a practice carried over from bipolar Darlington drives and is generally not required for IGBTs. However, a negative bias will reduce the possibility of
shootthrough. The MC33153 has separate pins for VEE and
Kelvin Ground. This permits operation using a +15/5.0 V
supply.

INTERFACING WITH OPTOISOLATORS


Isolated Input

410

It is desirable to protect an IGBT from insufficient gate voltage. IGBTs require 15 V on the gate to achieve the rated on
voltage. At gate voltages below 13 V, the onvoltage
increases dramatically, especially at higher currents. At very
low gate voltages, below 10 V, the IGBT may operate in the
linear region and quickly overheat. Many PWM motor drives
use a bootstrap supply for the upper gate drive. The UVLO
provides protection for the IGBT in case the bootstrap capacitor discharges.
The MC33153 will typically start up at about 12 V. The
UVLO circuit has about 1.0 V of hysteresis and will disable
the output if the supply voltage falls below about 11V.

Motorola TMOS Power MOSFET Transistor Device Data

MC33153
PROTECTION CIRCUITRY
Desaturation Protection
Bipolar Power circuits have commonly used what is known
as Desaturation Detection. This involves monitoring the collector voltage and turning off the device if this voltage rises
above a certain limit. A bipolar transistor will only conduct a
certain amount of current for a given base drive. When the
base is overdriven, the device is in saturation. When the collector current rises above the knee, the device pulls out of
saturation. The maximum current the device will conduct in
the linear region is a function of the base current and the dc
current gain (hFE) of the transistor.
The output characteristics of an IGBT are similar to a Bipolar device. However, the output current is a function of gate
voltage instead of current. The maximum current depends on
the gate voltage and the device type. IGBTs tend to have a
very high transconductance and a much higher current density under a short circuit than a bipolar device. Motor control
IGBTs are designed for a lower current density under shorted
conditions and a longer short circuit survival time.
The best method for detecting desaturation is the use of a
high voltage clamp diode and a comparator. The MC33153
has a Fault Blanking/Desaturation Comparator which senses
the collector voltage and provides an output indicating when
the device is not fully saturated. Diode D1 is an external high
voltage diode with a rated voltage comparable to the power
device. When the IGBT is on and saturated, D1 will pull
down the voltage on the Fault Blanking/Desaturation Input.
When the IGBT pulls out of saturation or is off, the current
source will pull up the input and trip the comparator. The
comparator threshold is 6.5 V, allowing a maximum onvoltage of about 5.8 V.
A fault exists when the gate input is high and VCE is
greater than the maximum allowable VCE(sat). The output of
the Desaturation Comparator is ANDed with the gate input
signal and fed into the Short Circuit and Overcurrent Latches.
The Overcurrent Latch will turnoff the IGBT for the remainder of the cycle when a fault is detected. When input goes
high, both latches are reset. The reference voltage is tied to
the Kelvin Ground instead of the VEE to make the threshold
independent of negative gate bias. Note that for proper
operation of the Desaturation Comparator and the Fault Output, the Current Sense Input must be biased above the Overcurrent and Short Circuit Comparator thresholds. This can be
accomplished by connecting Pin 1 to VCC.

Figure 33. Desaturation Detection

Desaturation
Comparator

VCC

VCC
270 A

D1
8

Kelvin
Gnd

Vref
6.5 V

VEE

Motorola TMOS Power MOSFET Transistor Device Data

The MC33153 also features a programmable fault blanking time. During turnon, the IGBT must clear the opposing
freewheeling diode. The collector voltage will remain high
until the diode is cleared. Once the diode has been cleared,
the voltage will come down quickly to the VCE(sat) of the
device. Following turnon, there is normally considerable
ringing on the collector due to the COSS capacitance of the
IGBTs and the parasitic wiring inductance. The fault signal
from the Desaturation Comparator must be blanked sufficiently to allow the diode to be cleared and the ringing to
settle out.
The blanking function uses an NPN transistor to clamp the
comparator input when the gate input is low. When the input
is switched high, the clamp transistor will turn off, allowing
the internal current source to charge the blanking capacitor.
The time required for the blanking capacitor to charge up
from the onvoltage of the internal NPN transistor to the trip
voltage of the comparator is the blanking time.
If a short circuit occurs after the IGBT is turned on and saturated, the delay time will be the time required for the current
source to charge up the blanking capacitor from the VCE(sat)
level of the IGBT to the trip voltage of the comparator. Fault
blanking can be disabled by leaving Pin 8 unconnected.
Sense IGBT Protection
Another approach to protecting the IGBTs is to sense the
emitter current using a current shunt or Sense IGBTs. This
method has the advantage of being able to use high gain
IGBTs which do not have any inherent short circuit capability.
Current sense IGBTs work as well as current sense MOSFETs in most circumstances. However, the basic problem of
working with very low sense voltages still exists. Sense
IGBTs sense current through the channel and are therefore
linear with respect to the collector current. Because IGBTs
have a very low incremental onresistance, sense IGBTs
behave much like lowon resistance current sense MOSFETs. The output voltage of a properly terminated sense
IGBT is very low, normally less than 100 mV.
The sense IGBT approach requires fault blanking to prevent false tripping during turnon. The sense IGBT also
requires that the sense signal is ignored while the gate is low.
This is because the mirror output normally produces large
transient voltages during both turnon and turnoff due to the
collector to mirror capacitance. With nonsensing types of
IGBTs, a low resistance current shunt (5.0 to 50 m) can be
used to sense the emitter current. When the output is an
actual short circuit, the inductance will be very low. Since the
blanking circuit provides a fixed minimum ontime, the peak
current under a short circuit can be very high. A short circuit
discern function is implemented by the second comparator
which has a higher trip voltage. The short circuit signal is
latched and appears at the Fault Output. When a short circuit
is detected, the IGBT should be turnedoff for several milliseconds allowing it to cool down before it is turned back on.
The sense circuit is very similar to the desaturation circuit. It
is possible to build a combination circuit that provides protection for both Short Circuit capable IGBTs and Sense IGBTs.

411

MC33153
APPLICATION INFORMATION
Figure 34 shows a basic IGBT driver application. When
driven from an optoisolator, an input pull up resistor is
required. This resistor value should be set to bias the output
transistor at the desired current. A decoupling capacitor
should be placed close to the IC to minimize switching noise.
A bootstrap diode may be used for a floating supply. If the
protection features are not required, then both the Fault
Blanking/Desaturation and Current Sense Inputs should both
be connected to the Kelvin Ground (Pin 2). When used with a
single supply, the Kelvin Ground and VEE pins should be connected together. Separate gate resistors are recommended
to optimize the turnon and turnoff drive.

If desaturation protection is desired, a high voltage diode


is connected to the Fault Blanking/Desaturation pin. The
blanking capacitor should be connected from the Desaturation pin to the VEE pin. If a dual supply is used, the blanking
capacitor should be connected to the Kelvin Ground. The
Current Sense Input should be tied high because the two
comparator outputs are ANDed together. Although the
reverse voltage on collector of the IGBT is clamped to the
emitter by the freewheeling diode, there is normally considerable inductance within the package itself. A small resistor
in series with the diode can be used to protect the IC from
reverse voltage transients.

Figure 34. Basic Application

Figure 36. Desaturation Application


+18 V

+18 V
Bootstrap

B+

6
VCC Desat/ 8
Blank
5
Output

Fault

Fault

6
VCC Desat/ 8
Blank

Output

MC33153
4

Sense

Input
VEE
3

Gnd

1
2

Figure 35. Dual Supply Application


+15 V

Fault

6
VCC Desat/ 8
Blank
5
Output

MC33153
4

Sense

Input
VEE
3

CBlank

MC33153

Gnd

1
2

Sense
Input

VEE
3

Gnd

5
1
2

When using sense IGBTs or a sense resistor, the sense


voltage is applied to the Current Sense Input. The sense trip
voltages are referenced to the Kelvin Ground pin. The sense
voltage is very small, typically about 65 mV, and sensitive to
noise. Therefore, the sense and ground return conductors
should be routed as a differential pair. An RC filter is useful in
filtering any high frequency noise. A blanking capacitor is
connected from the blanking pin to VEE. The stray capacitance on the blanking pin provides a very small level of blanking if left open. The blanking pin should not be grounded
when using current sensing, that would disable the sense.
The blanking pin should never be tied high, that would short
out the clamp transistor.
Figure 37. Sense IGBT Application
+18 V

5.0 V

When used in a dual supply application as in Figure 35, the


Kelvin Ground should be connected to the emitter of the
IGBT. If the protection features are not used, then both the
Fault Blanking/Desaturation and the Current Sense Inputs
should be connected to Ground. The input optoisolator
should always be referenced to VEE.

412

Fault

6
VCC Desat/ 8
Blank
5
Output

MC33153
Sense
4

Input

VEE
3

Gnd

1
2

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MGP20N14CL

SMARTDISCRETES
Internally Clamped, N-Channel
IGBT

20 AMPERES
VOLTAGE CLAMPED
NCHANNEL IGBT
Vce(on) = 1.9 VOLTS
135 VOLTS (CLAMPED)

This Logic Level Insulated Gate Bipolar Transistor (IGBT)


features GateEmitter ESD protection, GateCollector overvoltage
protection from SMARTDISCRETES monolithic circuitry for
usage as an Ignition Coil Driver.
Temperature Compensated GateDrain Clamp Limits Stress
Applied to Load
Integrated ESD Diode Protection
Low Threshold Voltage to Interface Power Loads to Logic or
Microprocessors
Low Saturation Voltage
High Pulsed Current Capability

G
G
C

Rge

CASE 221A06, Style 9


TO220AB

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

CLAMPED

Vdc

CollectorGate Voltage

VCGR

CLAMPED

Vdc

GateEmitter Voltage

VGE

CLAMPED

Vdc

Collector Current Continuous @ TC = 25C


Collector Current Single Pulsed (tp = 10 ms)

IC
ICM

20
60

Adc
Apk

Total Power Dissipation @ TC = 25C (TO220)


Derate Above 25C

PD

150
1.0

Watts
W/C

TJ, Tstg

55 to 175

"

Operating and Storage Temperature Range


Single Pulse CollectorEmitter Avalanche Energy @ Starting TJ = 25C
(VCC = 80 V, VGE = 5 V, Peak IL = 10 A, L = 10 mH)

EAS

mJ
500

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case (TO220)
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

RqJC
RqJA

1.0
62.5

C/W

TL

275

10 lbfin (1.13 Nm)

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

413

MGP20N14CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS
Clamp Voltage
(IClamp = 10 mA, TJ = 40 to 150C)

BVCES

Vdc
135

Zero Gate Voltage Collector Current


(VCE = 100 V, VGE = 0 V)
(VCE = 100 V, VGE = 0 V, TJ = 150C)

ICES

GateEmitter Clamp Voltage (IG = 1 mA)

BVGES

10

IGES

1.0

1.0

1.5
4.4

2.0

GateEmitter Leakage Current (VGE =

"5 V, VCE = 0 V)

10
100

mA
Vdc

mA

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VCE = VGE, IC = 1 mA)
Threshold Temperature Coefficient (Negative)

VCE(th)

CollectorEmitter OnVoltage
(VGE = 5 V, IC = 10 A)
(VGE = 5 V, IC = 10 Adc, TJ = 175C)

VCE(on)

Forward Transconductance (VCE

u 15 V, IC = 10 A)

V
mV/C
V

1.9
1.8

gfs

8.0

15

Mhos

Ciss

430

600

pF

Coss

182

250

Crss

48

100

td(on)

TBD

TBD

tr

TBD

TBD

td(off)

TBD

TBD

tf

TBD

TBD

Qg

14

20

Qgs

3.0

Qgd

6.0

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VCC = 68 V, IC = 20 A,
VGE = 5 V, RG = 9.1 W)

Fall Time
Total Gate Charge
GateEmitter Charge

(VCC = 108 V,
V IC = 20 A,
A
VGE = 5 V)

GateCollector Charge

ns

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

414

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advanced Information

MGP20N35CL

SMARTDISCRETES
Internally Clamped, N-Channel
IGBT

20 AMPERES
VOLTAGE CLAMPED
NCHANNEL IGBT
Vce(on) = 1.8 VOLTS
350 VOLTS (CLAMPED)

This Logic Level Insulated Gate Bipolar Transistor (IGBT)


features GateEmitter ESD protection, GateCollector overvoltage
protection from SMARTDISCRETES monolithic circuitry for
usage as an Ignition Coil Driver.
Temperature Compensated GateDrain Clamp Limits Stress
Applied to Load
Integrated ESD Diode Protection
Low Threshold Voltage to Interface Power Loads to Logic or
Microprocessors
Low Saturation Voltage
High Pulsed Current Capability

G
G
C

Rge

CASE 221A06, Style 9


TO220AB

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

CLAMPED

Vdc

CollectorGate Voltage

VCGR

CLAMPED

Vdc

VGE

CLAMPED

Vdc

IC

20

Adc

ICR

12

Apk

PD

150

Watts

ESD

3.5

kV

TJ, Tstg

55 to 175

RqJC
RqJA

1.0
62.5

C/W

TL

275

GateEmitter Voltage
Collector Current Continuous @ TC = 25C
Reversed Collector Current pulse width

t 100 ms

Total Power Dissipation @ TC = 25C (TO220)


Electrostatic Voltage GateEmitter
Operating and Storage Temperature Range

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case (TO220)
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

10 lbfin (1.13 Nm)

Mounting Torque, 632 or M3 screw

UNCLAMPED INDUCTIVE SWITCHING CHARACTERISTICS


Single Pulse CollectorEmitter Avalanche Energy
@ Starting TJ = 25C
@ Starting TJ = 150C

EAS

mJ
550
150

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

415

MGP20N35CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

320

350

380

1.0
200

Unit

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(IClamp = 10 mA, TJ = 40 to 150C)

BVCES

Zero Gate Voltage Collector Current


(VCE = 250 V, VGE = 0 V, TJ = 125C)
(VCE = 15 V, VGE = 0 V, TJ = 125C)

ICES

Resistance GateEmitter (TJ = 40 to 150C)

RGE

10k

16k

30k

GateEmitter Breakdown Voltage (IG = 2 mA)

BVGES

11

13

15

"V

ICES

100

mA

BVCER

26

40

120

1.0
0.75

1.7

2.4
1.8

1.1
1.4
1.4

1.4
1.9
1.8

gfs

10

16

pF

CollectorEmitter Reverse Leakage (VCE = 15 V, TJ = 40 to 150C)


CollectorEmitter Reversed Breakdown Voltage (IE = 75 mA)

Vdc

mA
mA

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VCE = VGE, IC = 1 mA)
(VCE = VGE, IC = 1 mA, TJ = 150C)

VGE(th)

CollectorEmitter OnVoltage
(VGE = 5 V, IC = 5 A)
(VGE = 5 V, IC = 10 A)
(VGE = 5 V, IC = 10 Adc, TJ = 150C)

VCE(on)

Forward Transconductance (VCE

u 50 V, IC = 10 A)

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Ciss

2800

Coss

200

Crss

25

SWITCHING CHARACTERISTICS (1)


Total Gate Charge
GateEmitter Charge

Qg

45

80

Qgs

8.0

Qgd

20

( CC = 320 V, IC = 20 A,
(V
L = 200 mH, RG = 1 KW)

td(off)

TBD

TBD

tf

TBD

TBD

((VCC = 14 V, IC = 20 A,
L = 200 mH, RG = 1 KW)

td(on)

TBD

TBD

tr

TBD

TBD

(VCC = 280 V,
V IC = 20 A,
A
VGE = 5 V)

GateCollector Charge
TurnOff Delay Time
Fall Time
TurnOn Delay Time
Rise Time

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

416

Motorola TMOS Power MOSFET Transistor Device Data

MGP20N35CL
TYPICAL ELECTRICAL CHARACTERISTICS
40

VGE = 10 V
I C , COLLECTOR CURRENT (AMPS)

TJ = 25C

30
4V
20

10
3V
0

I C , COLLECTOR CURRENT (AMPS)

20

3V

10

10

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

Figure 2. Output Characteristics, TJ = 125C

VCE = 10 V
30

20
TJ = 125C

25C

10

2.2
VGE = 5 V
2.0

IC = 20 A

1.8
15 A
1.6
10 A

1.4
1.2
1.0
50

50

100

150

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

10000

1000
VCE = 0 V

TJ = 25C

Ciss

VCE = 0 V

1000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

4V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

40

TJ = 125C

5V

30

10

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

I C , COLLECTOR CURRENT (AMPS)

40

5V

VGE = 10 V

Coss

100

Crss

10

TJ = 25C

Ciss

100

10

Coss
Crss

1.0

25

50

75

100

125

150

175

200

1.0
10

100

1000

COLLECTORTOEMITTER VOLTAGE (VOLTS)

DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

Figure 6. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

417

Qg

6
Qgs

Qgd

20

10

30

20

20
TF

10

2000

1000

10

3000

4000

Figure 7. GatetoEmitter and


CollectortoEmitter Voltage vs Total Charge

Figure 8. Total Switching Losses


versus Gate Temperature

30
Td(off)
20

3
VDD = 320 V
VGE = 5 V
TJ = 25C
IC = 20 A

TF

10

2000

1000

3000

4000

2
1
0
5000

26
VCC = 320 V
VGE = 5 V
RG = 1000 W
L = 200 mH
IC = 20 A

24
22

Td(off)

20

Eoff

18
16
14

TF

12
25

75

50

100

RG, GATE RESISTANCE (OHMS)

TC, CASE TEMPERATURE (C)

Figure 9. Total Switching Losses


versus Gate Resistance

Figure 10. Total Switching Losses


versus Case Temperature

VCC = 320 V
VGE = 5 V
RG = 1000 W
L = 200 mH
TJ = 125C

Eoff

15

Td(off)

15

10

10

SWITCHING TIME ( m S)

20

4
125

20

25

25

0
5000

SWITCHING TIME ( m S)

40
30

RG, GATE RESISTANCE (OHMS)

Eoff

20

Td(off)

30

SWITCHING TIME ( m S)

TOTAL SWITCHING ENERGY LOSSES (mJ)

40

40

50
Eoff

Qg, TOTAL GATE CHARGE (nC)

40

60
VDD = 320 V
VGE = 5 V
TJ = 125C
IC = 20 A

50

TOTAL SWITCHING ENERGY LOSSES (mJ)

60

LATCH CURRENT (AMPS)

TJ = 25C
IC = 20 A

50

TOTAL SWITCHING ENERGY LOSSES (mJ)

TOTAL SWITCHING ENERGY LOSSES (mJ)

SWITCHING TIME ( mS)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

MGP20N35CL

3 mH

16

12
10 mH

8.0

4.0

TF
5

418

10

15

5
20

25

50

75

100

125

IC, COLLECTORTOEMITTER CURRENT (AMPS)

TEMPERATURE (C)

Figure 11. Total Switching Losses


versus Collector Current

Figure 12. Latch Current versus Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MGP20N35CL
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02

1.0E 01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

419

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advanced Information

MGP20N40CL

SMARTDISCRETES
Internally Clamped, N-Channel
IGBT

20 AMPERES
VOLTAGE CLAMPED
NCHANNEL IGBT
Vce(on) = 1.8 VOLTS
400 VOLTS (CLAMPED)

This Logic Level Insulated Gate Bipolar Transistor (IGBT)


features GateEmitter ESD protection, GateCollector overvoltage
protection from SMARTDISCRETES monolithic circuitry for
usage as an Ignition Coil Driver.
Temperature Compensated GateDrain Clamp Limits Stress
Applied to Load
Integrated ESD Diode Protection
Low Threshold Voltage to Interface Power Loads to Logic or
Microprocessors
Low Saturation Voltage
High Pulsed Current Capability

G
G
C

Rge

CASE 221A06, Style 9


TO220AB

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

CLAMPED

Vdc

CollectorGate Voltage

VCGR

CLAMPED

Vdc

VGE

CLAMPED

Vdc

IC

20

Adc

ICR

12

Apk

PD

150

Watts

ESD

3.5

kV

TJ, Tstg

55 to 175

RqJC
RqJA

1.0
62.5

C/W

TL

275

GateEmitter Voltage
Collector Current Continuous @ TC = 25C
Reversed Collector Current pulse width

t 100 ms

Total Power Dissipation @ TC = 25C (TO220)


Electrostatic Voltage GateEmitter
Operating and Storage Temperature Range

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case (TO220)
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

10 lbfin (1.13 Nm)

Mounting Torque, 632 or M3 screw

UNCLAMPED INDUCTIVE SWITCHING CHARACTERISTICS


Single Pulse CollectorEmitter Avalanche Energy
@ Starting TJ = 25C
@ Starting TJ = 150C

EAS

mJ
550
150

This document contains information on a new product. Specifications and information herein are subject to change without notice.

420

Motorola TMOS Power MOSFET Transistor Device Data

MGP20N40CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

380

405

440

1.0
200

Unit

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(IClamp = 10 mA, TJ = 40 to 150C)

BVCES

Zero Gate Voltage Collector Current


(VCE = 300 V, VGE = 0 V, TJ = 125C)
(VCE = 15 V, VGE = 0 V, TJ = 125C)

ICES

Resistance GateEmitter (TJ = 40 to 150C)

RGE

10k

16k

30k

GateEmitter Breakdown Voltage (IG = 2 mA)

BVGES

11

13

15

"V

ICES

mA

BVCER

26

40

120

1.0
0.75

1.7

2.4
1.8

1.1
1.4
1.4

1.4
1.9
1.8

gfs

10

16

pF

CollectorEmitter Reverse Leakage (VCE = 15 V, TJ = 40 to 150C)


CollectorEmitter Reversed Breakdown Voltage (IE = 75 mA)

Vdc

mA
mA

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VCE = VGE, IC = 1 mA)
(VCE = VGE, IC = 1 mA, TJ = 150C)

VGE(th)

CollectorEmitter OnVoltage
(VGE = 5 V, IC = 5 A)
(VGE = 5 V, IC = 10 A)
(VGE = 5 V, IC = 10 Adc, TJ = 150C)

VCE(on)

Forward Transconductance (VCE

u 50 V, IC = 10 A)

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Ciss

2800

Coss

200

Crss

25

SWITCHING CHARACTERISTICS (1)


Total Gate Charge
GateEmitter Charge

Qg

45

80

Qgs

8.0

Qgd

20

( CC = 320 V, IC = 20 A,
(V
L = 200 mH, RG = 1 KW)

td(off)

TBD

TBD

tf

TBD

TBD

((VCC = 14 V, IC = 20 A,
L = 200 mH, RG = 1 KW)

td(on)

TBD

TBD

tr

TBD

TBD

(VCC = 280 V,
V IC = 20 A,
A
VGE = 5 V)

GateCollector Charge
TurnOff Delay Time
Fall Time
TurnOn Delay Time
Rise Time

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

421

MGP20N40CL
TYPICAL ELECTRICAL CHARACTERISTICS
40

VGE = 10 V
I C , COLLECTOR CURRENT (AMPS)

TJ = 25C

30
4V
20

10
3V
0

I C , COLLECTOR CURRENT (AMPS)

20

3V

10

10

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

Figure 2. Output Characteristics, TJ = 125C

VCE = 10 V
30

20
TJ = 125C

25C

10

2.2
VGE = 5 V
2.0

IC = 20 A

1.8
15 A
1.6
10 A

1.4
1.2
1.0
50

50

100

150

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

10000

1000
VCE = 0 V

TJ = 25C

Ciss

VGS = 0 V

1000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

4V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

40

TJ = 125C

5V

30

10

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

I C , COLLECTOR CURRENT (AMPS)

40

5V

VGE = 10 V

Coss

100

Crss

10

TJ = 25C

Ciss

100

10

Coss
Crss

1.0

422

25

50

75

100

125

150

175

200

1.0
10

100

1000

COLLECTORTOEMITTER VOLTAGE (VOLTS)

DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

Figure 6. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Qg

6
Qgs

Qgd

20

10

30

20

20
TF

10

2000

1000

10

3000

4000

Figure 7. GatetoEmitter and


CollectortoEmitter Voltage vs Total Charge

Figure 8. Total Switching Losses


versus Gate Temperature

30
Td(off)
20

3
VDD = 320 V
VGE = 5 V
TJ = 25C
IC = 20 A

TF

10

2000

1000

3000

4000

2
1
0
5000

26
VCC = 320 V
VGE = 5 V
RG = 1000 W
L = 200 mH
IC = 20 A

24
22

Td(off)

20

Eoff

18
16
14

TF

12
25

75

50

100

RG, GATE RESISTANCE (OHMS)

TC, CASE TEMPERATURE (C)

Figure 9. Total Switching Losses


versus Gate Resistance

Figure 10. Total Switching Losses


versus Case Temperature

VCC = 320 V
VGE = 5 V
RG = 1000 W
L = 200 mH
TJ = 125C

Eoff

15

Td(off)

15

10

10

SWITCHING TIME ( m S)

20

4
125

20

25

25

0
5000

SWITCHING TIME ( m S)

40
30

RG, GATE RESISTANCE (OHMS)

Eoff

20

Td(off)

30

SWITCHING TIME ( m S)

TOTAL SWITCHING ENERGY LOSSES (mJ)

40

40

50
Eoff

Qg, TOTAL GATE CHARGE (nC)

40

60
VDD = 320 V
VGE = 5 V
TJ = 125C
IC = 20 A

50

TOTAL SWITCHING ENERGY LOSSES (mJ)

60

LATCH CURRENT (AMPS)

TJ = 25C
IC = 20 A

50

TOTAL SWITCHING ENERGY LOSSES (mJ)

TOTAL SWITCHING ENERGY LOSSES (mJ)

SWITCHING TIME ( mS)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

MGP20N40CL

3 mH

16

12
10 mH

8.0

4.0

TF
5

10

15

5
20

25

50

75

100

125

IC, COLLECTORTOEMITTER CURRENT (AMPS)

TEMPERATURE (C)

Figure 11. Total Switching Losses


versus Collector Current

Figure 12. Latch Current versus Temperature

Motorola TMOS Power MOSFET Transistor Device Data

423

MGP20N40CL
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02

1.0E 01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

424

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MGW12N120

Insulated Gate Bipolar Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This Insulated Gate Bipolar Transistor (IGBT) uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operation at high frequencies.

IGBT IN TO247
12 A @ 90C
20 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

Industry Standard High Power TO247 Package with


Isolated Mounting Hole
High Speed Eoff: 160 mJ/A typical at 125C
High Short Circuit Capability 10 ms minimum
Robust High Voltage Termination
C

G
G

C
E

E
CASE 340F03, Style 4
TO247AE

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Collector Current Continuous @ TC = 90C
Collector Current Repetitive Pulsed Current (1)

IC25
IC90
ICM

20
12
40

Adc

PD

123
0.98

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJA

1.0
45

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature. Repetitive rating.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

425

MGW12N120
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

870

mV/C

25

Vdc

100
2500

250

2.51
2.36
3.21

3.37

4.42

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

pF

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

EmittertoCollector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc)

BVECS

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc

Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 5.0 Adc)
(VGE = 15 Vdc, IC = 5.0 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 10 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 10 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Cies

930

Coes

126

Cres

16

td(on)

74

tr

83

td(off)

76

tf

231

Eoff

0.55

1.33

mJ

td(on)

66

ns

SWITCHING CHARACTERISTICS (1)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 10 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

TurnOff Switching Loss


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 10 Adc,


Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

TurnOff Switching Loss


Gate Charge
(VCC = 720 Vdc,
Vd IC = 10 Adc,
Ad
VGE = 15 Vdc)

ns

tr

87

td(off)

120

tf

575

Eoff

1.49

mJ

QT

31

nC

Q1

13

Q2

14

13

INTERNAL PACKAGE INDUCTANCE


Internal Emitter Inductance
(Measured from the emitter lead 0.25 from package to emitter bond pad)

LE

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

426

Motorola TMOS Power MOSFET Transistor Device Data

MGW12N120
TYPICAL ELECTRICAL CHARACTERISTICS
40

TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

40

VGE = 20 V

TJ = 25C
30

17.5 V
20

15 V
12.5 V

10

VGE = 20 V

30
17.5 V
20

15 V
12.5 V

10

7.5 V
0

10 V
0

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VCE = 10 V
250 s PULSE WIDTH

16
TJ = 125C

25C

4
0

C, CAPACITANCE (pF)

1600

11

13

15

3.8
3.6

IC = 10 A

3.4
3.2
7.5 A
3.0
2.8
2.6

5A

2.4
VGE = 15 V
250 s PULSE WIDTH

2.2
2
50

50

100

150

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

VCE = 0 V

Cies
800

400

Coes
Cres
0

TJ, JUNCTION TEMPERATURE (C)

1200

VGE, GATETOEMITTER VOLTAGE (VOLTS)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

24

12

Figure 2. Output Characteristics, TJ = 125C


VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

20

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

10

15

20

25

16
QT
12
Q1

Q2

TJ = 25C
IC = 10 A
VGE = 15 V
0

10

15

20

25

35

30

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

Motorola TMOS Power MOSFET Transistor Device Data

427

2.5

IC = 10 A

7.5 A

1.5
5A
1

TOTAL SWITCHING ENERGY LOSSES (mJ)

VCC = 720 V
VGE = 15 V
TJ = 125C

TOTAL SWITCHING ENERGY LOSSES (mJ)

10

20

30

40

50

1.6
1.4
1.2
6

5A

25

75

50

100

125

10

150

25

20
TJ = 125C

15

10
TJ = 25C
5
0

IC, COLLECTORTOEMITTER CURRENT (AMPS)

VFM, FORWARD VOLTAGE DROP (VOLTS)

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

IC, COLLECTORTOEMITTER CURRENT (A)

7.5 A

Figure 8. Total Switching Losses versus


Case Temperature

1.8

IC = 10 A

Figure 7. Total Switching Losses versus


Gate Resistance

VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

VCC = 720 V
VGE = 15 V
RG = 20

TC, CASE TEMPERATURE (C)

2.4
2.2

3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0

RG, GATE RESISTANCE (OHMS)

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

TOTAL SWITCHING ENERGY LOSSES (mJ)

MGW12N120

100

10

1
VGE = 15 V
RGE = 20
TJ 125C
0.1

10

100

1000

10000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 11. Reverse Biased


Safe Operating Area

428

Motorola TMOS Power MOSFET Transistor Device Data

MGW12N120
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

429

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGW12N120D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO247


12 A @ 90C
20 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operation at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.
Industry Standard High Power TO247 Package with
Isolated Mounting Hole
High Speed Eoff: 160 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

C
E

CASE 340F03, Style 4


TO247AE

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

Rating

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

20
12
40

Adc

PD

123
0.98

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

1.0
1.4
45

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Case Diode
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

Apk

10 lbfSin (1.13 NSm)

Mounting Torque, 632 or M3 screw


(1) Pulse width is limited by maximum junction temperature. Repetitive rating.

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

430

Motorola TMOS Power MOSFET Transistor Device Data

MGW12N120D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

870

100
2500

250

2.71
3.78
3.72

3.37

4.42

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

Cies

1003

pF

Coes

126

Cres

106

td(on)

74

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 5.0 Adc)
(VGE = 15 Vdc, IC = 5.0 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 10 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 10 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

(VCC = 720 Vdc


Vdc, IC = 10 Adc
Adc,
VGE = 15 Vdc,, L = 300 mH
RG = 20 , TJ = 25C)
Energy losses include tail
tail

tr

83

td(off)

76

tf

231

TurnOff Switching Loss

Eoff

0.55

1.33

TurnOn Switching Loss

Eon

1.21

1.88

Total Switching Loss

Ets

1.76

3.21

td(on)

66

tr

87

td(off)

120

tf

575

TurnOff Switching Loss

Eoff

1.49

TurnOn Switching Loss

Eon

2.37

Total Switching Loss

Ets

3.86

QT

29

Q1

13

Q2

12

2.26
1.37
2.86

3.32

4.18

TurnOff Delay Time


Fall Time

TurnOn Delay Time


Rise Time
TurnOff Delay Time

(VCC = 720 Vdc


Vdc, IC = 10 Adc
Adc,
VGE = 15 Vdc,, L = 300 mH
RG = 20 , TJ = 125C)
Energy losses include tail
tail

Fall Time

Gate Charge
(VCC = 720 Vdc,
Vd IC = 10 Adc,
Ad
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 5.0 Adc)
(IEC = 5.0 Adc, TJ = 125C)
(IEC = 10 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

VFEC

Vdc

(continued)

431

MGW12N120D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

116

ns

ta

69

tb

47

QRR

0.36

trr

234

ns

ta

149

tb

85

QRR

1.40

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 10 Adc, VR = 720 Vdc,
dIF/dt = 100 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 10 Adc, VR = 720 Vdc,
dIF/dt = 100 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS


40

TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

40

VGE = 20 V

TJ = 25C
30

17.5 V
20

15 V
12.5 V

10

VGE = 20 V

30
17.5 V
20

15 V
12.5 V

10

7.5 V
0

10 V
0

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

24
VCE = 10 V
250 s PULSE WIDTH

16
TJ = 125C

12
8

25C

4
0

11

13

VGE, GATETOEMITTER VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

432

Figure 2. Output Characteristics, TJ = 125C

15

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

20

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

3.8
3.6

IC = 10 A

3.4
3.2
7.5 A
3.0
2.8
2.6

5A

2.4
2.2
2
50

VGE = 15 V
250 s PULSE WIDTH
0

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MGW12N120D
10000

1000

Cies

1000

Coes
100

Cies

VGE = 0 V
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

TJ = 25C

Cres

100

Coes
Cres

TJ = 25C
0

15

10

20

10

25

50

200

COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

Figure 5b. High Voltage Capacitance


Variation

16
QT
12
Q1

Q2

TJ = 25C
IC = 20 A

40

20

60

2.5

7.5 A

1.5
5A

10

20

IC = 10 A

7.5 A
5A

50

75

100

50

2.4

125

150

VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

2.2
2
1.8
1.6
1.4
1.2
1

25

40

Figure 7. Total Switching Losses versus


Gate Resistance

TOTAL SWITCHING ENERGY LOSSES (mJ)

VCC = 720 V
VGE = 15 V
RG = 20

30

RG, GATE RESISTANCE (OHMS)

Figure 6. GatetoEmitter and


CollectortoEmitter Voltage versus Total Charge

3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0

IC = 10 A

80

VCC = 720 V
VGE = 15 V
TJ = 125C

Qg, TOTAL GATE CHARGE (nC)

TOTAL SWITCHING ENERGY LOSSES (mJ)

150

100

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

TOTAL SWITCHING ENERGY LOSSES (mJ)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

10

10

TC, CASE TEMPERATURE (C)

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 8. Total Switching Losses versus


Case Temperature

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

Motorola TMOS Power MOSFET Transistor Device Data

433

25

IC, COLLECTORTOEMITTER CURRENT (A)

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

MGW12N120D

20
TJ = 125C

15

10
TJ = 25C
5
0

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

1000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VFM, FORWARD VOLTAGE DROP (VOLTS)

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

Figure 11. Reverse Biased


Safe Operating Area

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

434

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGW20N60D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO247


20 A @ 90C
32 A @ 25C
600 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operations at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.
Industry Standard High Power TO247 Package with
Isolated Mounting Hole
High Speed Eoff: 60 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

C
E

CASE 340F03, Style 4


TO247AE

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

CollectorEmitter Voltage

VCES

600

Vdc

CollectorGate Voltage (RGE = 1.0 M)

Rating

VCGR

600

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

32
20
64

Adc

PD

142
1.14

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

0.88
2.00
45

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 360 Vdc, VGE = 15 Vdc, TJ = 25C, RG = 20 )
Thermal Resistance

Junction to Case IGBT


Junction to Case Diode
Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

435

MGW20N60D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

870

100
2500

250

2.30
2.20
2.85

2.85

3.65

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

Cies

2280

pF

Coes

165

Cres

12

td(on)

59

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 250 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 600 Vdc, VGE = 0 Vdc)
(VCE = 600 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 10 Adc)
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 20 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 20 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

(VCC = 360 Vdc


Vdc, IC = 20 Adc
Adc,
VGE = 15 Vdc,, L = 300 mH
RG = 20 , TJ = 25C)
Energy losses include tail
tail

tr

61

td(off)

150

tf

212

TurnOff Switching Loss

Eoff

0.60

0.85

TurnOn Switching Loss

Eon

0.75

Total Switching Loss

Ets

1.35

td(on)

51

tr

77

td(off)

184

tf

392

TurnOff Switching Loss

Eoff

1.20

TurnOn Switching Loss

Eon

1.50

Total Switching Loss

Ets

2.70

QT

74

Q1

19

Q2

27

1.50
1.30
1.70

1.90

2.15

TurnOff Delay Time


Fall Time

TurnOn Delay Time


Rise Time
TurnOff Delay Time

(VCC = 360 Vdc


Vdc, IC = 20 Adc
Adc,
VGE = 15 Vdc,, L = 300 mH
RG = 20 , TJ = 125C)
Energy losses include tail
tail

Fall Time

Gate Charge
(VCC = 360 Vdc,
Vd IC = 20 Adc,
Ad
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 10 Adc)
(IEC = 10 Adc, TJ = 125C)
(IEC = 20 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

436

VFEC

Vdc

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MGW20N60D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

117

ns

ta

70

tb

47

QRR

1.2

trr

166

ns

ta

98

tb

68

QRR

1.9

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 20 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 20 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS


60

60
12.5 V
15 V

40
10 V

20

IC, COLLECTOR CURRENT (AMPS)

15 V

40
10 V

20

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

Figure 2. Output Characteristics, TJ = 125C

VCE = 100 V
5 s PULSE WIDTH
30
TJ = 125C
20
25C
10

12.5 V

17.5 V

40

VGE = 20 V

TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

VGE = 20 V
17.5 V

10

11

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

3.2

VGE = 15 V
80 s PULSE WIDTH

IC = 20 A

2.8
15 A

2.4

2
50

10 A

50

100

150

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

437

4000

VCE = 0 V

VGE, GATETOEMITTER VOLTAGE (VOLTS)

MGW20N60D
TJ = 25C

C, CAPACITANCE (pF)

3200
Cies

2400

1600

Coes

800
Cres
5

15

10

20

QT
12
Q1
8

TJ = 25C
IC = 20 A

25

Q2

20

40

60

80

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

VCC = 360 V
VGE = 15 V
TJ = 125C

3.2

TOTAL SWITCHING ENERGY LOSSES (mJ)

4
IC = 20 A

2.4

15 A
10 A

1.6

0.8

TOTAL SWITCHING ENERGY LOSSES (mJ)

10

20

30

40

3
2.5
IC = 20 A
2
15 A
1.5
10 A
1
0

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 7. Total Switching Losses versus


Gate Resistance

Figure 8. Total Switching Losses versus


Junction Temperature

150

1.6
VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

2.5
2
1.5
1
0.5

438

VCC = 360 V
VGE = 15 V
RG = 20

3.5

RG, GATE RESISTANCE (OHMS)

0.5

50

TURNOFF ENERGY LOSSES (mJ)

TOTAL SWITCHING ENERGY LOSSES (mJ)

16

10

15

20

VCC = 360 V
VGE = 15 V
TJ = 125C

IC = 20 A

1.2
15 A
0.8
10 A

0.4

10

20

30

40

IC, COLLECTORTOEMITTER CURRENT (AMPS)

RG, GATE RESISTANCE (OHMS)

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

Figure 10. TurnOff Losses versus


Gate Resistance

50

Motorola TMOS Power MOSFET Transistor Device Data

MGW20N60D
1.2
TURNOFF ENERGY LOSSES (mJ)

1.5

1
IC = 20 A
15 A
10 A

0.5

i F, INSTANTANEOUS FORWARD CURRENT (AMPS)

VCC = 360 V
VGE = 15 V
RG = 20

25

50

75

100

125

10

15

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 11. TurnOff Losses versus


Junction Temperature

Figure 12. TurnOff Losses versus


CollectortoEmitter Current

10
TJ = 125C
TJ = 25C
1

0.4

TJ, JUNCTION TEMPERATURE (C)

100

0.1

VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

0.8

150

IC, COLLECTORTOEMITTER CURRENT (A)

TURNOFF ENERGY LOSSES (mJ)

0.4

0.8

1.2

1.6

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

VFM, FORWARD VOLTAGE DROP (VOLTS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 13. Typical Diode Forward Drop versus


Instantaneous Forward Current

Figure 14. Reverse Biased Safe


Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

20

1000

439

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MGW20N120

Insulated Gate Bipolar Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This Insulated Gate Bipolar Transistor (IGBT) uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time. Fast switching characteristics result in efficient
operation at high frequencies.

IGBT IN TO247
20 A @ 90C
28 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

Industry Standard High Power TO247 Package with


Isolated Mounting Hole
High Speed Eoff: 160 mJ/A typical at 125C
High Short Circuit Capability 10 ms minimum
Robust High Voltage Termination
C

E
CASE 340F03, Style 4
TO247AE

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

28
20
56

Adc

PD

174
1.39

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJA

0.7
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

Apk

10 lbfSin (1.13 NSm)

Mounting Torque, 632 or M3 screw


(1) Pulse width is limited by maximum junction temperature. Repetitive rating.

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

440

Motorola TMOS Power MOSFET Transistor Device Data

MGW20N120
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

870

mV/C

25

Vdc

100
2500

250

3.00
2.36
2.90

3.54

4.99

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

pF

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

EmittertoCollector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc)

BVECS

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc

Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 10 Adc)
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 20 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 20 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Cies

1860

Coes

122

Cres

29

td(on)

88

tr

103

td(off)

190

tf

284

Eoff

1.65

3.75

mJ

td(on)

83

ns

tr

107

td(off)

216

tf

494

Eoff

3.19

mJ

QT

62

nC

Q1

21

Q2

25

13

SWITCHING CHARACTERISTICS (1)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 20 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

TurnOff Switching Loss


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 20 Adc,


Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

TurnOff Switching Loss


Gate Charge
(VCC = 720 Vdc,
Vd IC = 20 Adc,
Ad
VGE = 15 Vdc)

ns

INTERNAL PACKAGE INDUCTANCE


Internal Emitter Inductance
(Measured from the emitter lead 0.25 from package to emitter bond pad)

LE

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

441

MGW20N120
TYPICAL ELECTRICAL CHARACTERISTICS

IC, COLLECTOR CURRENT (AMPS)

60

VGE = 20 V

TJ = 25C
50

17.5 V

40
12.5 V
30
20
10 V

10
0

50
40

12.5 V
30
10 V

20
10
0

TJ = 125C
40

20
25C

10

11

12

13

14

15

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

VCE = 10 V
250 s PULSE WIDTH

VGE = 15 V
250 s PULSE WIDTH
IC = 20 A
3

15 A
10 A

1
50

VGE, GATETOEMITTER VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Cies
1000
Coes

10

Cres

10

15

20

100

150

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

TJ = 25C

100

50

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

VCE = 0 V

VGE, GATETOEMITTER VOLTAGE (VOLTS)

10000

Figure 2. Output Characteristics, TJ = 125C

60

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

15 V

17.5 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VGE = 20 V

TJ = 125C

15 V

IC, COLLECTOR CURRENT (AMPS)

60

25

16
QT
14
12
10
Q1

Q2

6
TJ = 25C
IC = 20 A

4
2
0

10 15 20

25 30 35 40

45 50 55 60 65 70

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

442

Motorola TMOS Power MOSFET Transistor Device Data

IC = 25 A

15 A

3
10 A
2
1
0

10

20

15

25

30

40

35

15 A

2
10 A
1

50

25

75

100

125

Figure 8. Total Switching Losses versus


Case Temperature

VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

10

Figure 7. Total Switching Losses versus


Gate Resistance

IC = 20 A

TC, CASE TEMPERATURE (C)

VCC = 720 V
VGE = 15 V
RG = 20

50

45

RG, GATE RESISTANCE (OHMS)

12

14

16

18

20

150

40

30
TJ = 125C
20
TJ = 25C
10

IC, COLLECTORTOEMITTER CURRENT (AMPS)

VFM, FORWARD VOLTAGE DROP (VOLTS)

Figure 9. TurnOff Losses versus


CollectortoEmitter Current

IC, COLLECTORTOEMITTER CURRENT (A)

TOTAL SWITCHING ENERGY LOSSES (mJ)

VCC = 720 V
VGE = 15 V
TJ = 25C

TOTAL SWITCHING ENERGY LOSSES (mJ)

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

TOTAL SWITCHING ENERGY LOSSES (mJ)

MGW20N120

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

1000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 11. Reverse Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

443

MGW20N120
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

444

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MGW30N60

Insulated Gate Bipolar Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This Insulated Gate Bipolar Transistor (IGBT) uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operation at high frequencies.

IGBT IN TO247
30 A @ 90C
50 A @ 25C
600 VOLTS
SHORT CIRCUIT RATED

Industry Standard High Power TO247 Package with


Isolated Mounting Hole
High Speed Eoff: 60 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Robust High Voltage Termination
Robust RBSOA

E
CASE 340F03, Style 4
TO247AE

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

CollectorEmitter Voltage

Rating

VCES

600

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

600

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

50
30
100

Adc

PD

202
1.61

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJA

0.62
45

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 360 Vdc, VGE = 15 Vdc, TJ = 25C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

445

MGW30N60
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

870

mV/C

25

Vdc

100
2500

250

2.20
2.10
2.60

2.90

3.45

4.0

6.0
10

8.0

mV/C

gfe

15

Mhos

pF

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 250 Adc)
Temperature Coefficient (Positive)

BVCES

EmittertoCollector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc)

BVECS

Zero Gate Voltage Collector Current


(VCE = 600 Vdc, VGE = 0 Vdc)
(VCE = 600 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc

Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 15 Adc)
(VGE = 15 Vdc, IC = 15 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 30 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 30 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Cies

4280

Coes

275

Cres

19

td(on)

76

tr

80

td(off)

348

tf

188

Eoff

0.98

1.28

mJ

td(on)

73

ns

tr

95

td(off)

394

tf

418

Eoff

1.90

mJ

QT

150

nC

Q1

30

Q2

45

13

SWITCHING CHARACTERISTICS (1)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 360 Vdc, IC = 30 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

TurnOff Switching Loss


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 360 Vdc, IC = 30 Adc,


Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

TurnOff Switching Loss


Gate Charge
(VCC = 360 Vdc,
Vd IC = 30 Adc,
Ad
VGE = 15 Vdc)

ns

INTERNAL PACKAGE INDUCTANCE


Internal Emitter Inductance
(Measured from the emitter lead 0.25 from package to emitter bond pad)

LE

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

446

Motorola TMOS Power MOSFET Transistor Device Data

MGW30N60
TYPICAL ELECTRICAL CHARACTERISTICS
60

60
TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

12.5 V

17.5 V

10 V

15 V

40

20

60
IC, COLLECTOR CURRENT (AMPS)

VGE = 20 V

25C

10

11

VGE = 15 V
80 s PULSE WIDTH

IC = 30 A

2.6

22.5 A

15 A
2.2

1.8
50

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ = 25C

6400

VCE = 0 V

5600
C, CAPACITANCE (pF)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

7200

Cies

4800
4000
3200
2400
1600

Coes
Cres
0

Figure 2. Output Characteristics, TJ = 125C

20

Figure 1. Output Characteristics, TJ = 25C

TJ = 125C

800

20

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VCE = 100 V
5 s PULSE WIDTH

10 V

15 V

40

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

40

12.5 V

VGE = 20 V
17.5 V

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

10

15

20

25

16
QT
12

Q1

Q2
TJ = 25C
IC = 30 A

20

40

60

80

100

120

140

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

Motorola TMOS Power MOSFET Transistor Device Data

447

MGW30N60
3
VCC = 360 V
VGE = 15 V
TJ = 125C

2.5

TURNOFF ENERGY LOSSES (mJ)

TURNOFF ENERGY LOSSES (mJ)

IC = 30 A

2
1.5

20 A

1
10 A
0.5
0

10

20

30

40

20 A

0.5

10 A

25

50

75

100

125

Figure 8. TurnOff Losses versus


Junction Temperature
IC, COLLECTORTOEMITTER CURRENT (A)

TURNOFF ENERGY LOSSES (mJ)

Figure 7. TurnOff Losses versus


Gate Resistance

0.8

0.4

448

IC = 30 A

TJ, JUNCTION TEMPERATURE (C)

VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

1.5

RG, GATE RESISTANCE (OHMS)

1.2

50

1.6

VCC = 360 V
VGE = 15 V
RG = 20

2.5

10

15

20

25

30

150

100

10

1
VGE = 15 V
RGE = 20
TJ = 125C
0.1

10

100

IC, COLLECTORTOEMITTER CURRENT (AMPS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 9. TurnOff Losses versus


CollectortoEmitter Current

Figure 10. Reverse Biased Safe


Operating Area

1000

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGY20N120D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO264


20 A @ 90C
28 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operation at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 160 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

G
G
E

CASE 340G02, Style 5


TO264

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

28
20
56

Adc

PD

174
1.39

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

0.7
1.1
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Case Diode
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature. Repetitive rating.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

449

MGY20N120D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

870

100
2500

250

3.00
2.36
2.90

3.54

4.99

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

Cies

1876

pF

Coes

208

Cres

31

td(on)

88

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 10 Adc)
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 20 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 20 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

(VCC = 720 Vdc


Vdc, IC = 20 Adc
Adc,
VGE = 15 Vdc, L = 300 mH
RG = 20 , TJ = 25C)
Energy losses include tail
tail

tr

103

td(off)

190

tf

284

TurnOff Switching Loss

Eoff

1.65

3.75

TurnOn Switching Loss

Eon

2.42

7.68

Total Switching Loss

Ets

4.07

11.43

td(on)

83

tr

107

td(off)

216

tf

494

TurnOff Switching Loss

Eoff

3.19

TurnOn Switching Loss

Eon

4.26

Total Switching Loss

Ets

7.45

QT

63

Q1

20

Q2

27

2.92
1.73
3.67

3.59

4.57

TurnOff Delay Time


Fall Time

TurnOn Delay Time


Rise Time
TurnOff Delay Time

(VCC = 720 Vdc


Vdc, IC = 20 Adc
Adc,
VGE = 15 Vdc, L = 300 mH
RG = 20 , TJ = 125C)
Energy losses include tail
tail

Fall Time

Gate Charge
Vd IC = 20 Adc,
Ad
(VCC = 720 Vdc,
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 10 Adc)
(IEC = 10 Adc, TJ = 125C)
(IEC = 20 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

450

VFEC

Vdc

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MGY20N120D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

114

ns

ta

74

tb

40

QRR

0.68

trr

224

ns

ta

149

tb

75

QRR

2.40

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 20 Adc, VR = 720 Vdc,
dIF/dt = 150 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 20 Adc, VR = 720 Vdc,
dIF/dt = 150 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS

IC, COLLECTOR CURRENT (AMPS)

60

VGE = 20 V

TJ = 25C
50

17.5 V

40
12.5 V
30
20
10 V

10
0

50
40

12.5 V
30
10 V

20
10
0

TJ = 125C
40

20
25C

10

11

12

13

14

VGE, GATETOEMITTER VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

15

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

VCE = 10 V
250 s PULSE WIDTH

Figure 2. Output Characteristics, TJ = 125C

60

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

15 V

17.5 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VGE = 20 V

TJ = 125C

15 V

IC, COLLECTOR CURRENT (AMPS)

60

4
VGE = 15 V
250 s PULSE WIDTH
IC = 20 A
3

15 A
10 A

1
50

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

451

MGY20N120D
10000

10000

VGE = 0 V

TJ = 25C

TJ = 25C
Cies

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

Cies
1000
Coes
100

Cres

1000

Coes

100

Cres

15

10

20

10

25

50

150

100

200

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

Figure 5b. High Voltage Capacitance


Variation

TOTAL SWITCHING ENERGY LOSSES (mJ)

16
QT
14
12
10
Q1

Q2

6
TJ = 25C
IC = 20 A

4
2
0

TOTAL SWITCHING ENERGY LOSSES (mJ)

10 15 20

25 30 35 40

VCC = 720 V
VGE = 15 V
TJ = 25C

IC = 25 A

15 A

3
10 A
2
1
0

45 50 55 60 65 70

10

15

20

25

30

35

45

40

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 6. GatetoEmitter and CollectortoEmitter


Voltage versus Total Charge

Figure 7. Total Switching Losses versus


Gate Resistance

VCC = 720 V
VGE = 15 V
RG = 20

TOTAL SWITCHING ENERGY LOSSES (mJ)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

10

IC = 20 A

15 A

2
10 A
1

25

452

50

75

100

125

150

50

5
VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

10

12

14

16

18

TC, CASE TEMPERATURE (C)

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 8. Total Switching Losses versus


Case Temperature

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

20

Motorola TMOS Power MOSFET Transistor Device Data

40

IC, COLLECTORTOEMITTER CURRENT (A)

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

MGY20N120D

30
TJ = 125C
20
TJ = 25C
10

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

1000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VFM, FORWARD VOLTAGE DROP (VOLTS)

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

Figure 11. Reverse Biased


Safe Operating Area

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

453

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MGY25N120

Insulated Gate Bipolar Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This Insulated Gate Bipolar Transistor (IGBT) uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time. Fast switching characteristics result in efficient
operation at high frequencies.

IGBT IN TO264
25 A @ 90C
38 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 273 mJ/A typical at 125C
High Short Circuit Capability 10 ms minimum
Robust High Voltage Termination

G
G

E
CASE 340G02, Style 5
TO264

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

38
25
76

Adc

PD

212
1.69

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJA

0.6
35

C/W

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

TL

Apk

10 lbfSin (1.13 NSm)

Mounting Torque, 632 or M3 screw


(1) Pulse width is limited by maximum junction temperature. Repetitive rating.

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

454

Motorola TMOS Power MOSFET Transistor Device Data

MGY25N120
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

960

mV/C

25

Vdc

100
2500

250

2.37
2.15
2.98

3.24

4.19

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

pF

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

EmittertoCollector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc)

BVECS

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc

Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 12.5 Adc)
(VGE = 15 Vdc, IC = 12.5 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 25 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 25 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Cies

2795

Coes

181

Cres

45

td(on)

91

tr

124

td(off)

196

tf

310

Eoff

2.44

4.69

mJ

td(on)

88

ns

tr

126

td(off)

236

tf

640

Eoff

5.40

mJ

QT

97

nC

Q1

31

Q2

40

13

SWITCHING CHARACTERISTICS (1)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 25 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

TurnOff Switching Loss


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 720 Vdc, IC = 25 Adc,


Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

TurnOff Switching Loss


Gate Charge
(VCC = 720 Vdc,
Vd IC = 25 Adc,
Ad
VGE = 15 Vdc)

ns

INTERNAL PACKAGE INDUCTANCE


Internal Emitter Inductance
(Measured from the emitter lead 0.25 from package to emitter bond pad)

LE

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

455

MGY25N120
TYPICAL ELECTRICAL CHARACTERISTICS
75

75
VGE = 20 V

15 V
60

45

12.5 V

30
10 V
15

15 V

45

12.5 V

30
10 V
15

TJ = 125C
50
40
30
20
25C
10
8

10

12

14

16

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

VCE = 10 V
250 s PULSE WIDTH

IC = 20 A
3

15 A
10 A

1
50

VGE, GATETOEMITTER VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

1000
Coes
Cres

10

15

20

25

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

456

50

100

150

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

Cies

10

TJ, JUNCTION TEMPERATURE (C)

TJ = 25C

100

VGE = 15 V
250 s PULSE WIDTH

Figure 3. Transfer Characteristics

VCE = 0 V

VGE, GATETOEMITTER VOLTAGE (VOLTS)

10000

Figure 2. Output Characteristics, TJ = 125C

70

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

17.5 V

60

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

60

VGE = 20 V

TJ = 125C

17.5 V
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

16
QT
14
12
10

Q1

Q2

8
6
TJ = 25C
IC = 25 A

4
2
0

10 15 20

25 30 35 40

45 50 55 60 65 70

Qg, TOTAL GATE CHARGE (nC)

Figure 6. GatetoEmitter Voltage versus


Total Charge

Motorola TMOS Power MOSFET Transistor Device Data

TOTAL SWITCHING ENERGY LOSSES (mJ)

6
IC = 25 A
5.5
VCC = 720 V
VGE = 15 V
TJ = 125C
IC = 25 A

5
4.5
4

15 A

3.5
3

10 A

2.5
2

10

20

30

40

TURNOFF ENERGY LOSSES (mJ)

IC = 25 A

4
15 A

3
2

10 A
1
50

25

75

100

125

150

Figure 8. Total Switching Losses versus


Case Temperature

3
2
1
0

Figure 7. Total Switching Losses versus


Gate Resistance

TC, CASE TEMPERATURE (C)

VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

VCC = 720 V
VGE = 15 V
RG = 20

RG, GATE RESISTANCE (OHMS)

7
6

50

10

15

20

25

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

TOTAL SWITCHING ENERGY LOSSES (mJ)

MGY25N120

50

40
TJ = 125C

30

TJ = 25C
20

10
0

Figure 9. TurnOff Losses versus


CollectortoEmitter Current

IC, COLLECTORTOEMITTER CURRENT (A)

VFM, FORWARD VOLTAGE DROP (VOLTS)

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

1000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 11. Reverse Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

457

MGY25N120
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

458

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGY25N120D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO264


25 A @ 90C
38 A @ 25C
1200 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operation at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 226 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

G
G

CASE 340G02, Style 5


TO264

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

1200

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

1200

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

38
25
76

Adc

PD

212
1.69

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

0.6
0.9
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Case Diode
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature. Repetitive rating.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

459

MGY25N120D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

960

100
2500

250

2.37
2.15
2.98

3.24

4.19

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

Cies

1859

pF

Coes

198

Cres

30

td(on)

91

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 25 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 1200 Vdc, VGE = 0 Vdc)
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 12.5 Adc)
(VGE = 15 Vdc, IC = 12.5 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 25 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1.0 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 20 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

(VCC = 720 Vdc


Vdc, IC = 25 Adc
Adc,
VGE = 15 Vdc, L = 300 mH
RG = 20 , TJ = 25C)
Energy losses include tail
tail

tr

124

td(off)

196

tf

310

TurnOff Switching Loss

Eoff

2.44

4.69

TurnOn Switching Loss

Eon

3.14

9.69

Total Switching Loss

Ets

5.58

14.38

td(on)

88

tr

126

td(off)

236

tf

640

TurnOff Switching Loss

Eoff

5.40

TurnOn Switching Loss

Eon

5.03

Total Switching Loss

Ets

10.43

QT

62

Q1

22

Q2

25

2.89
1.75
3.65

3.50

4.45

TurnOff Delay Time


Fall Time

TurnOn Delay Time


Rise Time
TurnOff Delay Time

(VCC = 720 Vdc


Vdc, IC = 25 Adc
Adc,
VGE = 15 Vdc, L = 300 mH
RG = 20 , TJ = 125C)
Energy losses include tail
tail

Fall Time

Gate Charge
Vd IC = 25 Adc,
Ad
(VCC = 720 Vdc,
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 12.5 Adc)
(IEC = 12.5 Adc, TJ = 125C)
(IEC = 25 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

460

VFEC

Vdc

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MGY25N120D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

114

ns

ta

71

tb

43

QRR

0.65

trr

226

ns

ta

165

tb

61

QRR

1.90

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 25 Adc, VR = 720 Vdc,
dIF/dt = 150 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 25 Adc, VR = 720 Vdc,
dIF/dt = 150 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS


75

75
VGE = 20 V

15 V
60

45

12.5 V

30
10 V
15

15 V

45

12.5 V

30
10 V
15

TJ = 125C
50
40
30
20
25C
10
8

10

12

14

VGE, GATETOEMITTER VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

16

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

VCE = 10 V
250 s PULSE WIDTH

Figure 2. Output Characteristics, TJ = 125C

70

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

17.5 V

60

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

60

VGE = 20 V

TJ = 125C

17.5 V
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

4
VGE = 15 V
250 s PULSE WIDTH
IC = 20 A
3

15 A
10 A

1
50

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

461

MGY25N120D
10000

10000

VGE = 0 V

TJ = 25C

TJ = 25C
Cies

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

Cies
1000
Coes
100

Cres

1000

Coes

100

Cres

15

10

20

10

25

50

150

100

200

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 5. Capacitance Variation

Figure 5b. High Voltage Capacitance


Variation

TOTAL SWITCHING ENERGY LOSSES (mJ)

16
QT
14
12
10

Q1

Q2

8
6
TJ = 25C
IC = 25 A

4
2
0

TOTAL SWITCHING ENERGY LOSSES (mJ)

10 15 20

25 30 35 40

6
IC = 25 A
5.5
VCC = 720 V
VGE = 15 V
TJ = 125C
IC = 25 A

5
4.5
4

15 A

3.5
3

10 A

2.5
2

45 50 55 60 65 70

10

20

30

40

50

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 6. GatetoEmitter and CollectortoEmitter


Voltage versus Total Charge

Figure 7. Total Switching Losses versus


Gate Resistance

VCC = 720 V
VGE = 15 V
RG = 20

6
5

TURNOFF ENERGY LOSSES (mJ)

VGE, GATETOEMITTER VOLTAGE (VOLTS)

10

IC = 25 A

4
15 A

3
2

10 A
1
0

5
4
3
2
1
0

25

462

50

75

100

125

150

VCC = 720 V
VGE = 15 V
RG = 20
TJ = 125C

10

15

20

TC, CASE TEMPERATURE (C)

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 8. Total Switching Losses versus


Case Temperature

Figure 9. TurnOff Losses versus


CollectortoEmitter Current

25

Motorola TMOS Power MOSFET Transistor Device Data

50

IC, COLLECTORTOEMITTER CURRENT (A)

I , INSTANTANEOUS FORWARD CURRENT (AMPS)


F

MGY25N120D

40
TJ = 125C

30

TJ = 25C
20

10
0

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

VFM, FORWARD VOLTAGE DROP (VOLTS)

10

100

1000

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 10. Maximum Forward Drop versus


Instantaneous Forward Current

Figure 11. Reverse Biased


Safe Operating Area

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 12. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

463

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGY30N60D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO264


30 A @ 90C
50 A @ 25C
600 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operations at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 60 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

G
G
E

CASE 340G02, Style 5


TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

600

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

600

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

50
30
100

Adc

PD

202
1.61

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

0.62
1.41
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 360 Vdc, VGE = 15 Vdc, TJ = 25C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Junction to Case Diode
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

Apk

10 lbfSin (1.13 NSm)

Mounting Torque, 632 or M3 screw


(1) Pulse width is limited by maximum junction temperature.

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

464

Motorola TMOS Power MOSFET Transistor Device Data

MGY30N60D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

870

100
2500

250

2.20
2.10
2.60

2.90

3.45

4.0

6.0
10

8.0

mV/C

gfe

15

Mhos

Cies

4280

pF

Coes

225

Cres

19

td(on)

76

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 250 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 600 Vdc, VGE = 0 Vdc)
(VCE = 600 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 15 Adc)
(VGE = 15 Vdc, IC = 15 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 30 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 30 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

tr

80

td(off)

348

tf

188

Eoff

0.98

1.28

TurnOn Switching Loss

Eon

2.00

Total Switching Loss

Ets

2.98

TurnOn Delay Time

td(on)

73

TurnOff Delay Time


Fall Time
TurnOff Switching Loss

(VCC = 360 Vdc, IC = 30 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

Rise Time

tr

95

td(off)

394

tf

418

Eoff

1.90

TurnOn Switching Loss

Eon

3.10

Total Switching Loss

Ets

5.00

QT

150

Q1

30

Q2

45

1.30
1.10
1.45

1.80

2.05

TurnOff Delay Time


Fall Time
TurnOff Switching Loss

(VCC = 360 Vdc, IC = 30 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

Gate Charge
(VCC = 360 Vdc,
Vd IC = 30 Adc,
Ad
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 15 Adc)
(IEC = 15 Adc, TJ = 125C)
(IEC = 30 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

VFEC

Vdc

(continued)

465

MGY30N60D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

153

ns

ta

82

tb

71

QRR

2.3

trr

208

ns

ta

117

tb

91

QRR

3.8

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 30 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 30 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS


60

60
TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

12.5 V

17.5 V

10 V

15 V

40

20

60
IC, COLLECTOR CURRENT (AMPS)

VGE = 20 V

20

Figure 1. Output Characteristics, TJ = 25C

Figure 2. Output Characteristics, TJ = 125C

TJ = 125C

25C
20

466

40

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VCE = 100 V
5 s PULSE WIDTH

10 V

15 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

40

12.5 V

VGE = 20 V
17.5 V

10

11

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

VGE = 15 V
80 s PULSE WIDTH

IC = 30 A

2.6

22.5 A

15 A
2.2

1.8
50

50

100

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

150

Motorola TMOS Power MOSFET Transistor Device Data

MGY30N60D

C, CAPACITANCE (pF)

VCE = 0 V

VGE, GATETOEMITTER VOLTAGE (VOLTS)

8000
TJ = 25C

6000
Cies
4000

2000
Coes
Cres
10

15

20

25

QT
15

10

Q1

Q2

TJ = 25C
IC = 30 A

60

30

90

120

150

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

6.4

VCC = 360 V
VGE = 15 V
TJ = 125C

5.6

TOTAL SWITCHING ENERGY LOSSES (mJ)

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC = 30 A

4.8
4

20 A

3.2
2.4

10 A

1.6
0.8
0

TOTAL SWITCHING ENERGY LOSSES (mJ)

10

20

30

40

VCC = 360 V
VGE = 15 V
RG = 20

5.5
4.5

IC = 30 A

3.5
20 A
2.5
10 A

1.5

50

25

75

125

100

150

RG, GATE RESISTANCE (OHMS)

TJ, JUNCTION TEMPERATURE (C)

Figure 7. Total Switching Losses versus


Gate Resistance

Figure 8. Total Switching Losses versus


Junction Temperature

3
VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

6.5

0.5

50

TURNOFF ENERGY LOSSES (mJ)

TOTAL SWITCHING ENERGY LOSSES (mJ)

20

10

15

20

25

30

VCC = 360 V
VGE = 15 V
TJ = 125C

IC = 30 A

2
20 A
1
10 A

10

20

30

40

IC, COLLECTORTOEMITTER CURRENT (AMPS)

RG, GATE RESISTANCE (OHMS)

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

Figure 10. TurnOff Losses versus


Gate Resistance

Motorola TMOS Power MOSFET Transistor Device Data

50

467

MGY30N60D
TURNOFF ENERGY LOSSES (mJ)

VCC = 360 V
VGE = 15 V
RG = 20
2
IC = 30 A
1

20 A
10 A

i F, INSTANTANEOUS FORWARD CURRENT (AMPS)

25

50

75

100

125

10

15

20

25

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 11. TurnOff Losses versus


Junction Temperature

Figure 12. TurnOff Losses versus


CollectortoEmitter Current

TJ = 125C
TJ = 25C
1

468

0.5

TJ, JUNCTION TEMPERATURE (C)

10

150

100

0.1

VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

1.5

IC, COLLECTORTOEMITTER CURRENT (A)

TURNOFF ENERGY LOSSES (mJ)

0.4

0.8

1.2

1.6

30

100

10

1
VGE = 15 V
RGE = 20
TJ = 125C
0.1

10

100

VFM, FORWARD VOLTAGE DROP (VOLTS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 13. Typical Diode Forward Drop versus


Instantaneous Forward Current

Figure 14. Reverse Biased Safe


Operating Area

1000

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MGY40N60

Insulated Gate Bipolar Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This Insulated Gate Bipolar Transistor (IGBT) uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operations at high frequencies.

IGBT IN TO264
40 A @ 90C
66 A @ 25C
600 VOLTS
SHORT CIRCUIT RATED

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 60 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Robust High Voltage Termination
Robust RBSOA
C

G
G

E
CASE 340G02, Style 5
TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

600

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

600

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

66
40
132

Adc

PD

260
2.08

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJA

0.48
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 360 Vdc, VGE = 15 Vdc, TJ = 25C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

469

MGY40N60
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

870

mV/C

25

Vdc

100
2500

250

2.20
2.10
2.60

2.80

3.25

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

pF

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 250 Adc)
Temperature Coefficient (Positive)

BVCES

EmittertoCollector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc)

BVECS

Zero Gate Voltage Collector Current


(VCE = 600 Vdc, VGE = 0 Vdc)
(VCE = 600 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc

Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 20 Adc)
(VGE = 15 Vdc, IC = 20 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 40 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 40 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

Cies

6810

Coes

464

Cres

15

td(on)

126

tr

95

td(off)

530

tf

180

Eoff

1.50

2.10

mJ

td(on)

113

ns

tr

104

td(off)

588

tf

346

Eoff

2.70

mJ

QT

248

nC

Q1

49

Q2

81

13

SWITCHING CHARACTERISTICS (1)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 360 Vdc, IC = 40 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

TurnOff Switching Loss


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

(VCC = 360 Vdc, IC = 40 Adc,


Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

TurnOff Switching Loss


Gate Charge
(VCC = 360 Vdc,
Vd IC = 40 Adc,
Ad
VGE = 15 Vdc)

ns

INTERNAL PACKAGE INDUCTANCE


Internal Emitter Inductance
(Measured from the emitter lead 0.25 from package to emitter bond pad)

LE

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

470

Motorola TMOS Power MOSFET Transistor Device Data

MGY40N60
TYPICAL ELECTRICAL CHARACTERISTICS
80

80
VGE = 20 V

IC, COLLECTOR CURRENT (AMPS)

17.5 V

10 V

15 V

60

TJ = 125C

12.5 V

40

20

IC, COLLECTOR CURRENT (AMPS)

10 V

40

20

Figure 2. Output Characteristics, TJ = 125C

TJ = 125C

40
25C

20

10

VGE = 15 V
80 s PULSE WIDTH

IC = 40 A

2.6
30 A

20 A

2.2

1.8
50

50

100

150

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

TJ = 25C

VCE = 0 V

8000

VGE, GATETOEMITTER VOLTAGE (VOLTS)

12000

C, CAPACITANCE (pF)

15 V

Figure 1. Output Characteristics, TJ = 25C

60

Cies

4000
Coes
Cres
0

17.5 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

VCE = 100 V
5 s PULSE WIDTH

12.5 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

80

VGE = 20 V

60

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

10

15

20

25

20
QT
15

Q1

10

Q2

TJ = 25C
IC = 40 A

50

100

150

250

200

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

Motorola TMOS Power MOSFET Transistor Device Data

471

MGY40N60
4
VCC = 360 V
VGE = 15 V
TJ = 125C

TURNOFF ENERGY LOSSES (mJ)

TURNOFF ENERGY LOSSES (mJ)

IC = 40 A

30 A

20 A
1

10

30

20

40

472

25

50

75

100

125

Figure 8. TurnOff Losses versus


Junction Temperature

IC, COLLECTORTOEMITTER CURRENT (A)

TURNOFF ENERGY LOSSES (mJ)

20 A

Figure 7. TurnOff Losses versus


Gate Resistance

VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

30 A

TJ, JUNCTION TEMPERATURE (C)

IC = 40 A

RG, GATE RESISTANCE (OHMS)

50

VCC = 360 V
VGE = 15 V
RG = 20

10

15

20

25

30

35

40

150

100

10

1
VGE = 15 V
RGE = 20
TJ = 125C
0.1

10

100

IC, COLLECTORTOEMITTER CURRENT (AMPS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 9. TurnOff Losses versus


CollectortoEmitter Current

Figure 10. Reverse Biased Safe


Operating Area

1000

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Insulated Gate Bipolar Transistor
with Anti-Parallel Diode
Designer's

MGY40N60D
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

IGBT & DIODE IN TO264


40 A @ 90C
66 A @ 25C
600 VOLTS
SHORT CIRCUIT RATED

This Insulated Gate Bipolar Transistor (IGBT) is copackaged


with a soft recovery ultrafast rectifier and uses an advanced
termination scheme to provide an enhanced and reliable high
voltageblocking capability. Short circuit rated IGBTs are specifically suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
characteristics result in efficient operations at high frequencies.
Copackaged IGBTs save space, reduce assembly time and cost.

Industry Standard High Power TO264 Package (TO3PBL)


High Speed Eoff: 60 mJ per Amp typical at 125C
High Short Circuit Capability 10 ms minimum
Soft Recovery Free Wheeling Diode is included in the package
Robust High Voltage Termination
Robust RBSOA

G
G

CASE 340G02, Style 5


TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

CollectorEmitter Voltage

VCES

600

Vdc

CollectorGate Voltage (RGE = 1.0 M)

VCGR

600

Vdc

GateEmitter Voltage Continuous

VGE

20

Vdc

Collector Current Continuous @ TC = 25C


Continuous @ TC = 90C
Repetitive Pulsed Current (1)

IC25
IC90
ICM

66
40
132

Adc

PD

260
2.08

Watts
W/C

TJ, Tstg

55 to 150

tsc

10

ms

RJC
RJC
RJA

0.48
1.13
35

C/W

TL

260

Total Power Dissipation @ TC = 25C


Derate above 25C
Operating and Storage Junction Temperature Range
Short Circuit Withstand Time
(VCC = 360 Vdc, VGE = 15 Vdc, TJ = 25C, RG = 20 )
Thermal Resistance Junction to Case IGBT
Thermal Resistance Junction to Case Diode
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
Mounting Torque, 632 or M3 screw

Apk

10 lbfSin (1.13 NSm)

(1) Pulse width is limited by maximum junction temperature.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

473

MGY40N60D
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

870

100
2500

250

2.20
2.10
2.60

2.80

3.25

4.0

6.0
10

8.0

mV/C

gfe

12

Mhos

Cies

6810

pF

Coes

464

Cres

15

td(on)

126

OFF CHARACTERISTICS
CollectortoEmitter Breakdown Voltage
(VGE = 0 Vdc, IC = 250 Adc)
Temperature Coefficient (Positive)

BVCES

Zero Gate Voltage Collector Current


(VCE = 600 Vdc, VGE = 0 Vdc)
(VCE = 600 Vdc, VGE = 0 Vdc, TJ = 125C)

ICES

GateBody Leakage Current (VGE = 20 Vdc, VCE = 0 Vdc)

IGES

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
CollectortoEmitter OnState Voltage
(VGE = 15 Vdc, IC = 20 Adc)
(VGE = 15 Vdc, IC = 20 Adc, TJ = 125C)
(VGE = 15 Vdc, IC = 40 Adc)

VCE(on)

Gate Threshold Voltage


(VCE = VGE, IC = 1 mAdc)
Threshold Temperature Coefficient (Negative)

VGE(th)

Forward Transconductance (VCE = 10 Vdc, IC = 40 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (1)
TurnOn Delay Time
Rise Time

tr

95

td(off)

530

tf

180

Eoff

1.50

2.10

TurnOn Switching Loss

Eon

2.30

Total Switching Loss

Ets

3.80

TurnOn Delay Time

td(on)

113

TurnOff Delay Time


Fall Time
TurnOff Switching Loss

(VCC = 360 Vdc, IC = 40 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 25
25C)
C)
Energy losses include tail

Rise Time

tr

104

td(off)

588

tf

346

Eoff

2.70

TurnOn Switching Loss

Eon

3.80

Total Switching Loss

Ets

6.50

QT

248

Q1

49

Q2

81

1.19
1.04
1.36

1.70

2.00

TurnOff Delay Time


Fall Time
TurnOff Switching Loss

(VCC = 360 Vdc, IC = 40 Adc,


VGE = 15 Vdc,
Vd L = 300 mH
RG = 20 , TJ = 125C)
125 C)
Energy losses include tail

Gate Charge
(VCC = 360 Vdc,
Vd IC = 40 Adc,
Ad
VGE = 15 Vdc)

ns

mJ

ns

mJ

nC

DIODE CHARACTERISTICS
Diode Forward Voltage Drop
(IEC = 20 Adc)
(IEC = 20 Adc, TJ = 125C)
(IEC = 40 Adc)
(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

474

VFEC

Vdc

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MGY40N60D
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

trr

138

ns

ta

78

tb

60

QRR

2.1

trr

213

ns

ta

122

tb

91

QRR

4.9

13

DIODE CHARACTERISTICS continued


Reverse Recovery Time
((IF = 40 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s)
Reverse Recovery Stored Charge
Reverse Recovery Time
((IF = 40 Adc, VR = 360 Vdc,
dIF/dt = 200 A/s, TJ = 125C)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


LE

Internal Emitter Inductance


(Measured from the emitter lead 0.25 from package to emitter bond pad)

nH

TYPICAL ELECTRICAL CHARACTERISTICS


80

80
17.5 V

12.5 V
10 V

15 V

60

TJ = 125C
IC, COLLECTOR CURRENT (AMPS)

VGE = 20 V

40

20

IC, COLLECTOR CURRENT (AMPS)

15 V
10 V

40

20

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics, TJ = 25C

Figure 2. Output Characteristics, TJ = 125C

VCE = 100 V
5 s PULSE WIDTH
60

TJ = 125C

40
25C

20

17.5 V

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

80

12.5 V

VGE = 20 V

60

10

VCE , COLLECTORTOEMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMPS)

TJ = 25C

VGE = 15 V
80 s PULSE WIDTH

IC = 40 A

2.6
30 A

20 A

2.2

1.8
50

50

150

100

VGE, GATETOEMITTER VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation


Voltage versus Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

475

MGY40N60D
TJ = 25C

C, CAPACITANCE (pF)

VCE = 0 V

8000

VGE, GATETOEMITTER VOLTAGE (VOLTS)

12000

Cies

4000
Coes
Cres
5

15

10

20

25

QT
15

Q1

10

Q2

TJ = 25C
IC = 40 A

50

100

250

200

150

GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Capacitance Variation

Figure 6. GatetoEmitter Voltage versus


Total Charge

VCC = 360 V
VGE = 15 V
TJ = 125C

7.5

TOTAL SWITCHING ENERGY LOSSES (mJ)

8.5
IC = 40 A

6.5
5.5

30 A

4.5
20 A

3.5
2.5

TOTAL SWITCHING ENERGY LOSSES (mJ)

10

20

30

40

30 A
3
20 A

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 7. Total Switching Losses versus


Gate Resistance

Figure 8. Total Switching Losses versus


Junction Temperature

150

4
VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

6
5
4
3
2
1

476

IC = 40 A

RG, GATE RESISTANCE (OHMS)

VCC = 360 V
VGE = 15 V
RG = 20

50

TURNOFF ENERGY LOSSES (mJ)

TOTAL SWITCHING ENERGY LOSSES (mJ)

20

10

15

20

25

30

35

40

VCC = 360 V
VGE = 15 V
TJ = 125C

IC = 40 A

30 A
2
20 A
1

10

20

30

40

IC, COLLECTORTOEMITTER CURRENT (AMPS)

RG, GATE RESISTANCE (OHMS)

Figure 9. Total Switching Losses versus


CollectortoEmitter Current

Figure 10. TurnOff Losses versus


Gate Resistance

50

Motorola TMOS Power MOSFET Transistor Device Data

MGY40N60D
3
TURNOFF ENERGY LOSSES (mJ)

IC = 40 A

30 A
1

i F, INSTANTANEOUS FORWARD CURRENT (AMPS)

VCC = 360 V
VGE = 15 V
RG = 20

20 A

50

25

75

100

125

10

15

20

25

30

35

IC, COLLECTORTOEMITTER CURRENT (AMPS)

Figure 11. TurnOff Losses versus


Junction Temperature

Figure 12. TurnOff Losses versus


CollectortoEmitter Current

10
TJ = 125C
TJ = 25C
1

TJ, JUNCTION TEMPERATURE (C)

100

0.1

VCC = 360 V
VGE = 15 V
RG = 20
TJ = 125C

150

IC, COLLECTORTOEMITTER CURRENT (A)

TURNOFF ENERGY LOSSES (mJ)

0.4

0.8

1.2

100

10

0.1

VGE = 15 V
RGE = 20
TJ = 125C
1

10

100

VFM, FORWARD VOLTAGE DROP (VOLTS)

VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 13. Typical Diode Forward Drop versus


Instantaneous Forward Current

Figure 14. Reverse Biased Safe


Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

40

1000

477

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
SMARTDISCRETES
Internally Clamped, Current Limited
NChannel Logic Level Power MOSFET
Designer's

The MLD1N06CL is designed for applications that require a rugged power switching
device with short circuit protection that can be directly interfaced to a microcontrol unit
(MCU). Ideal applications include automotive fuel injector driver, incandescent lamp
driver or other applications where a high inrush current or a shorted load condition could
occur.
This logic level power MOSFET features current limiting for short circuit protection,
integrated GateSource clamping for ESD protection and integral GateDrain clamping
for overvoltage protection and Sensefet technology for low onresistance. No additional
gate series resistance is required when interfacing to the output of a MCU, but a 40 k
gate pulldown resistor is recommended to avoid a floating gate condition.
The internal GateSource and GateDrain clamps allow the device to be applied
without use of external transient suppression components. The GateSource clamp
protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The
GateDrain clamp protects the MOSFET drain from the avalanche stress that occurs
with inductive loads. Their unique design provides voltage clamping that is essentially
independent of operating temperature.
The MLD1N06CL is fabricated using Motorolas SMARTDISCRETES technology which
combines the advantages of a power MOSFET output device with the onchip protective
circuitry that can be obtained from a standard MOSFET process. This approach offers an
economical means of providing protection to power MOSFETs from harsh automotive and
industrial environments. SMARTDISCRETES devices are specified over a wide temperature range from 50C to 150C.

MLD1N06CL
Motorola Preferred Device

VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.75 OHMS

R1
G

R2
S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

Clamped

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

Clamped

Vdc

GatetoSource Voltage Continuous

VGS

10

Vdc

Drain Current Continuous


Single Pulse

ID
IDM

Selflimited
1.8

Adc
Apk

Total Power Dissipation


Operating and Storage Temperature Range
Electrostatic Discharge Voltage (Human Model)

PD

40

Watts

TJ, Tstg

50 to 150

ESD

2.0

kV

RJC
RJA
RJA

3.12
100
71.4

C/W

TL

260

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Junction to Ambient
Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes,
1/8 from case for 5 sec.

CASE 369A13, Style 2


DPAK Surface Mount

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Single Pulse DraintoSource Avalanche Energy
Starting TJ = 25C

EAS

80

mJ

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

478

Motorola TMOS Power MOSFET Transistor Device Data

MLD1N06CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

59
59

62
62

65
65

0.6
6.0

5.0
20

0.5
1.0

5.0
20

1.0
0.6

1.5

2.0
1.6

0.63
0.59
1.1
1.0

0.75
0.75
1.9
1.8

1.1

1.5

2.0
1.1

2.3
1.3

2.75
1.8

gFS

1.0

1.4

mhos

td(on)

1.2

2.0

ns

tr

4.0

6.0

td(off)

4.0

6.0

tf

3.0

5.0

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (Internally Clamped)
(ID = 20 mAdc, VGS = 0 Vdc)
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 45 Vdc, VGS = 0 Vdc)
(VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateSource Leakage Current


(VG = 5.0 Vdc, VDS = 0 Vdc)
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C)

IGSS

Vdc

Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(ID = 250 Adc, VDS = VGS)
(ID = 250 Adc, VDS = VGS, TJ = 150C)

VGS(th)

Static DraintoSource OnResistance


(ID = 1.0 Adc, VGS = 4.0 Vdc)
(ID = 1.0 Adc, VGS = 5.0 Vdc)
(ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150C)
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C)

RDS(on)

Static SourcetoDrain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc)

Vdc

Ohms

VSD

Static Drain Current Limit


(VGS = 5.0 Vdc, VDS = 10 Vdc)
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C)

Vdc

ID(lim)

Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc)

Adc

RESISTIVE SWITCHING CHARACTERISTICS(2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 25 Vdc, ID = 1.0 Adc,


VGS(on) = 5.0 Vdc, RGS = 50 Ohms)

Fall Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

TJ = 25C

10 V
6V

8V
4V

VGS = 3 V

VDS 7.5 V

4
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

50C

3
25C
2
TJ = 150C

0
0

2
4
6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Function

479

MLD1N06CL

480

ID(lim) , DRAIN CURRENT (AMPS)

4
VGS = 5 V
VDS = 7.5 V
3

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 3. ID(lim) Variation


With Temperature

R DS(on), ONRESISTANCE (OHMS)

ID = 1 A

2
25C

150C

TJ = 50C

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

Figure 4. RDS(on) Variation With


GateToSource Voltage

1.25
ID = 1 A
RDS(on), ONRESISTANCE (OHMS)

THE SMARTDISCRETES CONCEPT


From a standard power MOSFET process, several active
and passive elements can be obtained that provide onchip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low onresistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit (MCU).
Ideal applications include automotive fuel injector driver,
incandescent lamp driver or other applications where a high
inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device,
its initial junction temperature, and the supply voltage. Without
some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLD1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature is
under 100C. For longer periods of operation in the current
limited mode, device heatsinking can extend operation from
several seconds to indefinitely depending on the amount of
heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The onchip circuitry of the MLD1N06CL offers an integrated
means of protecting the MOSFET component from high inrush
current or a shorted load. As shown in the schematic diagram,
the current limiting feature is provided by an NPN transistor and
integral resistors R1 and R2. R2 senses the current through the
MOSFET and forward biases the NPN transistors base as the
current increases. As the NPN turns on, it begins to pull gate
drive current through R1, dropping the gate drive voltage across
it, and thus lowering the voltage across the gatetosource of
the power MOSFET and limiting the current. The current limit is
temperature dependent as shown in Figure 3, and decreases
from about 2.3 Amps at 25C to about 1.3 Amps at 150C.
Since the MLD1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to
provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due
to the lower temperature coefficient of R2. The onresistance
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.
Backtoback polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This onchip
protection feature eliminates the need for an external Zener
diode for systems with potentially heavy line transients.

1
VGS = 4 V
0.75
VGS = 5 V
0.5

0.25
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100
80

60

40

20
0

25

50

75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

BV(DSS) , DRAINSOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)

MLD1N06CL
64

63

62

61

60
50

Figure 6. Single Pulse Avalanche Energy


versus Junction Temperature

MAXIMUM DC VOLTAGE CONSIDERATIONS


The maximum draintosource voltage that can be continuously applied across the MLD1N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
(150 TA)
Vsupply =
ID(lim) (RJC + RCA)
where the value of RCA is determined by the heatsink that is
being used in the application.

Motorola TMOS Power MOSFET Transistor Device Data

150

Figure 7. DrainSource Sustaining


Voltage Variation With Temperature

DUTY CYCLE OPERATION


When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =

150 TC
ID(lim) x DC x RJC

10

ID , DRAIN CURRENT (AMPS)

FORWARD BIASED SAFE OPERATING AREA


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal Resistance General
Data and Its Use provides detailed instructions.

0
50
100
TJ, JUNCTION TEMPERATURE (C)

VGS = 10 V
SINGLE PULSE
TC = 25C
10 s
100 s

1.0

1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

dc

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 8. Maximum Rated Forward Bias


Safe Operating Area (MLD1N06CL)

481

MLD1N06CL
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E 01

1.0E+00

1.0E+01

t, TIME (s)

Figure 9. Thermal Response (MLD1N06CL)

ton

VDD
RL

Vin
PULSE GENERATOR
Rgen

Vout

td(on)

toff
tr
90%

td(off)

DUT
OUTPUT, Vout
INVERTED

z = 50

10%

50

90%

50
50%
INPUT, Vin

Figure 10. Switching Test Circuit

ACTIVE CLAMPING
SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, backtoback diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each backtoback
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gatetodrain clamp voltages, several
voltage elements are strung together; the MLD1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gatetosource voltage clamp.
For the MLD1N06CL, the integrated gatetosource voltage

482

tf
90%

50%
PULSE WIDTH

10%

Figure 11. Switching Waveforms

elements provide greater than 2.0 kV electrostatic voltage


protection.
The avalanche voltage of the gatetodrain voltage clamp
is set less than that of the power MOSFET device. As soon
as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate
voltage across the gatetosource impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gatetodrain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the
power device.
The gatetodrain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gatetodrain clamped
conduction mode rather than in the more stressful gateto
source avalanche mode.

Motorola TMOS Power MOSFET Transistor Device Data

MLD1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 k gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.

VBAT
VDD

D
MCU

MLD1N06CL
S

Motorola TMOS Power MOSFET Transistor Device Data

483

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
SMARTDISCRETES
Internally Clamped, Current Limited
NChannel Logic Level Power MOSFET
Designer's

The MLD2N06CL is designed for applications that require a rugged power switching
device with short circuit protection that can be directly interfaced to a microcontrol unit
(MCU). Ideal applications include automotive fuel injector driver, incandescent lamp
driver or other applications where a high inrush current or a shorted load condition could
occur.
This logic level power MOSFET features current limiting for short circuit protection,
integrated GateSource clamping for ESD protection and integral GateDrain clamping
for overvoltage protection and Sensefet technology for low onresistance. No additional
gate series resistance is required when interfacing to the output of a MCU, but a 40 k
gate pulldown resistor is recommended to avoid a floating gate condition.
The internal GateSource and GateDrain clamps allow the device to be applied
without use of external transient suppression components. The GateSource clamp
protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The
GateDrain clamp protects the MOSFET drain from the avalanche stress that occurs
with inductive loads. Their unique design provides voltage clamping that is essentially
independent of operating temperature.
The MLD2N06CL is fabricated using Motorolas SMARTDISCRETES technology which
combines the advantages of a power MOSFET output device with the onchip protective
circuitry that can be obtained from a standard MOSFET process. This approach offers an
economical means of providing protection to power MOSFETs from harsh automotive and
industrial environments. SMARTDISCRETES devices are specified over a wide temperature range from 50C to 150C.

MLD2N06CL
Motorola Preferred Device

VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.4 OHMS

R1
G

R2
S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

Clamped

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

Clamped

Vdc

GatetoSource Voltage Continuous

VGS

10

Vdc

Drain Current Continuous @ TC = 25C

ID

Selflimited

Adc

Total Power Dissipation @ TC = 25C

PD

40

Watts

ESD

2.0

kV

TJ, Tstg

50 to 150

TJ(max)

150

RJC

3.12

C/W

TL

260

80

mJ

Electrostatic Voltage
Operating and Storage Temperature Range

THERMAL CHARACTERISTICS
Maximum Junction Temperature
Thermal Resistance Junction to Case
Maximum Lead Temperature for Soldering Purposes,
1/8 from case for 5 sec.

CASE 369A13, Style 2


DPAK Surface Mount

DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Single Pulse DraintoSource Avalanche Energy
(Starting TJ = 25C, ID = 2.0 A, L = 40 mH)

EAS

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

484

Motorola TMOS Power MOSFET Transistor Device Data

MLD2N06CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

58
58

62
62

66
66

0.6
6.0

5.0
20

0.5
1.0

5.0
20

1.0
0.6

1.5
1

2.0
1.6

3.8
1.6

4.4
2.4

5.2
2.9

0.3
0.53

0.4
0.7

1.0

1.4

1.1

1.5

td(on)

1.0

1.5

tr

3.0

5.0

td(off)

5.0

8.0

tf

3.0

5.0

Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(ID = 20 mAdc, VGS = 0 Vdc)
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 40 Vdc, VGS = 0 Vdc)
(VDS = 40 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateSource Leakage Current


(VG = 5.0 Vdc, VDS = 0 Vdc)
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C)

IGSS

Vdc

Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(ID = 250 Adc, VDS = VGS)
(ID = 250 Adc, VDS = VGS, TJ = 150C)

VGS(th)

Static Drain Current Limit


(VGS = 5.0 Vdc, VDS = 10 Vdc)
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C)

Vdc

ID(lim)

Static DraintoSource OnResistance


(ID = 1.0 Adc, VGS = 5.0 Vdc)
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C)

Adc

RDS(on)

Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc)

gFS

Static SourcetoDrain Diode Voltage


(IS = 1.0 Adc, VGS = 0 Vdc)

VSD

Ohms

mhos
Vdc

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 30 Vdc, ID = 1.0 Adc,


VGS(on) = 5.0 Vdc, RGS = 25 Ohms)

Fall Time

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4.0

TJ = 25C

6.0 V
5.5 V
5.0 V
4.5 V
4.0 V

3.5 V
3.0 V

VDS 7.5 V

55C

25C

3.5
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

2.5 V

TJ = 150C

3.0
2.5
2.0
1.5
1.0
0.5

2.0 V
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Function

485

MLD2N06CL

486

I D(lim) , DRAIN CURRENT (AMPS)

6
VGS = 5 V
VDS = 10 V

5
4
3
2
1
0

50

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 3. ID(lim) Variation


With Temperature

RDS(on) , ONRESISTANCE (OHMS)

1.0
ID = 1 A
0.8

0.6
100C

0.4
25C
0.2

TJ = 50C
0

7
8
4
5
6
2
3
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

Figure 4. RDS(on) Variation With


GateToSource Voltage

0.6
RDS(on) , ONRESISTANCE (OHMS)

THE SMARTDISCRETES CONCEPT


From a standard power MOSFET process, several active
and passive elements can be obtained that provide onchip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low onresistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit (MCU).
Ideal applications include automotive fuel injector driver,
incandescent lamp driver or other applications where a high
inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device,
its initial junction temperature, and the supply voltage. Without
some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLD2N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature is
under 100C. For longer periods of operation in the current
limited mode, device heatsinking can extend operation from
several seconds to indefinitely depending on the amount of
heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The onchip circuitry of the MLD2N06CL offers an integrated
means of protecting the MOSFET component from high inrush
current or a shorted load. As shown in the schematic diagram,
the current limiting feature is provided by an NPN transistor and
integral resistors R1 and R2. R2 senses the current through the
MOSFET and forward biases the NPN transistors base as the
current increases. As the NPN turns on, it begins to pull gate
drive current through R1, dropping the gate drive voltage across
it, and thus lowering the voltage across the gatetosource of
the power MOSFET and limiting the current. The current limit is
temperature dependent as shown in Figure 3, and decreases
from about 2.3 Amps at 25C to about 1.3 Amps at 150C.
Since the MLD2N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to
provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due
to the lower temperature coefficient of R2. The onresistance
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.
Backtoback polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This onchip
protection feature eliminates the need for an external Zener
diode for systems with potentially heavy line transients.

ID = 1 A
0.5
0.4
0.3

VGS = 4 V
VGS = 5 V

0.2
0.1
0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MLD2N06CL
BV(DSS) , DRAINTOSOURCE SUSTAINING
VOLTAGE (VOLTS)

EAS , SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

100
ID = 2 A
80

60

40

20

0
25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

64.0
63.5
63.0
62.5
62.0
61.5
61.0
60.5
60.0
50

Figure 6. Maximum Avalanche Energy


versus Starting Junction Temperature

MAXIMUM DC VOLTAGE CONSIDERATIONS


The maximum draintosource voltage that can be continuously applied across the MLD2N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
Vsupply =

(150 TA)
ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is


being used in the application.

Motorola TMOS Power MOSFET Transistor Device Data

0
50
100
TJ = JUNCTION TEMPERATURE

150

Figure 7. DrainSource Sustaining


Voltage Variation With Temperature

DUTY CYCLE OPERATION


When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =

150 TC
ID(lim) x DC x RJC

10

ID , DRAIN CURRENT (AMPS)

FORWARD BIASED SAFE OPERATING AREA


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal Resistance General
Data and Its Use provides detailed instructions.

ID = 20 mA

VGS = 10 V
SINGLE PULSE
TC = 25C

1.0

dc
10 ms
1 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 8. Maximum Rated Forward Bias


Safe Operating Area (MLD2N06CL)

487

MLD2N06CL
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E 01

1.0E+00

1.0E+01

t, TIME (s)

Figure 9. Thermal Response (MLD2N06CL)

ton

VDD
RL

Vin
PULSE GENERATOR
Rgen

Vout

td(on)

toff
tr
90%

td(off)

DUT
OUTPUT, Vout
INVERTED

z = 50

10%

50

90%

50
50%
INPUT, Vin

Figure 10. Switching Test Circuit

ACTIVE CLAMPING
SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, backtoback diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each backtoback
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gatetodrain clamp voltages, several
voltage elements are strung together; the MLD2N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gatetosource voltage clamp.
For the MLD2N06CL, the integrated gatetosource voltage

488

tf
90%

50%
PULSE WIDTH

10%

Figure 11. Switching Waveforms

elements provide greater than 2.0 kV electrostatic voltage


protection.
The avalanche voltage of the gatetodrain voltage clamp
is set less than that of the power MOSFET device. As soon
as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate
voltage across the gatetosource impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gatetodrain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the
power device.
The gatetodrain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gatetodrain clamped
conduction mode rather than in the more stressful gateto
source avalanche mode.

Motorola TMOS Power MOSFET Transistor Device Data

MLD2N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD2N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 k gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.

VBAT
VDD

D
MCU

MLD2N06CL
S

Motorola TMOS Power MOSFET Transistor Device Data

489

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

SMARTDISCRETES
Internally Clamped, Current Limited
NChannel Logic Level Power MOSFET
These SMARTDISCRETES devices feature current limiting for short circuit
protection, an integral gatetosource clamp for ESD protection and gatetodrain
clamp for overvoltage protection. No additional gate series resistance is required
when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is
recommended to avoid a floating gate condition.
The internal gatetosource and gatetodrain clamps allow the devices to be
applied without use of external transient suppression components. The gateto
source clamp protects the MOSFET input from electrostatic gate voltage stresses
up to 2.0 kV. The gatetodrain clamp protects the MOSFET drain from drain
avalanche stresses that occur with inductive loads. This unique design provides
voltage clamping that is essentially independent of operating temperature.
The MLP1N06CL is fabricated using Motorolas SMARTDISCRETES technology which combines the advantages of a power MOSFET output device with
onchip protective circuitry. This approach offers an economical means for
providing additional functions that protect a power MOSFET in harsh automotive
and industrial environments. SMARTDISCRETES devices are specified over a
wide temperature range from 50C to 150C.

MLP1N06CL
Motorola Preferred Device

VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.75 OHMS

R1
G

Temperature Compensated GatetoDrain Clamp Limits Voltage Stress


Applied to the Device and Protects the Load From Overvoltage
Integrated ESD Diode Protection
Controlled Switching Minimizes RFI

R2

Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors


MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

DraintoSource Voltage

VDSS

Clamped

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

Clamped

Vdc

GatetoSource Voltage Continuous

VGS

10

Vdc

Drain Current Continuous


Drain Current Single Pulse

ID
IDM

Selflimited
1.8

Adc

Rating

Total Power Dissipation

PD

40

Watts

Electrostatic Discharge Voltage (Human Body Model)

ESD

2.0

kV

Operating and Storage Junction Temperature Range

TJ, Tstg

50 to 150

3.12
62.5

C/W

260

G
D
S

THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Maximum Lead Temperature for Soldering Purposes,
1/8 from case

RJC
RJA
TL

CASE 221A06, Style 5


TO220AB

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Single Pulse DraintoSource Avalanche Energy
(Starting TJ = 25C, ID = 2.0 A, L = 40 mH) (Figure 6)

EAS

80

mJ

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

490

Motorola TMOS Power MOSFET Transistor Device Data

MLP1N06CL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

59
59

62
62

65
65

0.6
6.0

5.0
20

0.5
1.0

5.0
20

1.0
0.6

1.5

2.0
1.6

0.63
0.59
1.1
1.0

0.75
0.75
1.9
1.8

gFS

1.0

1.4

mhos

VSD

1.1

1.5

Vdc

2.0
1.1

2.3
1.3

2.75
1.8

td(on)

1.2

2.0

tr

4.0

6.0

td(off)

4.0

6.0

tf

3.0

5.0

OFF CHARACTERISTICS
DraintoSource Sustaining Voltage (Internally Clamped)
(ID = 20 mA, VGS = 0)
(ID = 20 mA, VGS = 0, TJ = 150C)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 45 V, VGS = 0)
(VDS = 45 V, VGS = 0, TJ = 150C)

IDSS

GateBody Leakage Current


(VG = 5.0 V, VDS = 0)
(VG = 5.0 V, VDS = 0, TJ = 150C)

IGSS

Vdc

Adc

Adc

ON CHARACTERISTICS*
Gate Threshold Voltage
(ID = 250 A, VDS = VGS)
(ID = 250 A, VDS = VGS, TJ = 150C)

VGS(th)

Static DraintoSource OnResistance


(ID = 1.0 A, VGS = 4.0 V)
(ID = 1.0 A, VGS = 5.0 V)
(ID = 1.0 A, VGS = 4.0 V, TJ = 150C)
(ID = 1.0 A, VGS = 5.0 V, TJ = 150C)

RDS(on)

Forward Transconductance (ID = 1.0 A, VDS = 10 V)


Static SourcetoDrain Diode Voltage (IS = 1.0 A, VGS = 0)
Static Drain Current Limit
(VGS = 5.0 V, VDS = 10 V)
(VGS = 5.0 V, VDS = 10 V, TJ = 150C)

Vdc

Ohms

ID(lim)

RESISTIVE SWITCHING CHARACTERISTICS*


TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 25 V, ID = 1.0 A,
VGS = 5.0 V, RG = 50 Ohms)

Fall Time

* Indicates Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

TJ = 25C

10 V
6V

8V
4V

VGS = 3 V

VDS 7.5 V

4
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

50C

3
25C
2
TJ = 150C

0
0

2
4
6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Function

491

MLP1N06CL

492

ID(lim) , DRAIN CURRENT (AMPS)

4
VGS = 5 V
VDS = 7.5 V
3

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 3. ID(lim) Variation With Temperature

R DS(on), ONRESISTANCE (OHMS)

ID = 1 A

2
25C

150C

TJ = 50C

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

Figure 4. RDS(on) Variation With


GateToSource Voltage

1.25
ID = 1 A
RDS(on), ONRESISTANCE (OHMS)

THE SMARTDISCRETES CONCEPT


From a standard power MOSFET process, several active
and passive elements can be obtained that provide onchip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low onresistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit
(MCU). Ideal applications include automotive fuel injector
driver, incandescent lamp driver or other applications where
a high inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage.
Without some form of current limiting, a shorted load can
raise a devices junction temperature beyond the maximum
rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLP1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature
is under 100C. For longer periods of operation in the currentlimited mode, device heatsinking can extend operation
from several seconds to indefinitely depending on the
amount of heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The onchip circuitry of the MLP1N06CL offers an integrated means of protecting the MOSFET component from
high inrush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an
NPN transistor and integral resistors R1 and R2. R2 senses
the current through the MOSFET and forward biases the
NPN transistors base as the current increases. As the NPN
turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the
voltage across the gatetosource of the power MOSFET
and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3
Amps at 25C to about 1.3 Amps at 150C.
Since the MLP1N06CL continues to conduct current and
dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C.
The metal current sense resistor R2 adds about 0.4 ohms
to the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard
MOSFET due to the lower temperature coefficient of R2. The
onresistance variation with temperature for gate voltages of
4 and 5 Volts is shown in Figure 5.
Backtoback polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This on
chip protection feature eliminates the need for an external
Zener diode for systems with potentially heavy line transients.

1
VGS = 4 V
0.75
VGS = 5 V
0.5

0.25
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100
80

60

40

20
0

25

50

75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

BV(DSS) , DRAINSOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)

MLP1N06CL
64

63

62

61

60
50

Figure 6. Single Pulse Avalanche Energy


versus Junction Temperature

FORWARD BIASED SAFE OPERATING AREA


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal Resistance General
Data and Its Use provides detailed instructions.

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 7. DrainSource Sustaining


Voltage Variation With Temperature

DUTY CYCLE OPERATION


When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =

150 TC
ID(lim) x DC x RJC

10

MAXIMUM DC VOLTAGE CONSIDERATIONS


The maximum draintosource voltage that can be continuously applied across the MLP1N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
Vsupply =

(150 TA)
ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is


being used in the application.

Motorola TMOS Power MOSFET Transistor Device Data

I D , DRAIN CURRENT (AMPS)

6
ID(lim) MAX

3
2

1 ms
1.5
ms
5 ms

ID(lim) MIN
dc

1
0.6

DEVICE/POWER LIMITED
RDS(on) LIMITED

0.3

VGS = 5 V
SINGLE PULSE
TC = 25C

0.2
0.1

10

20

30

60

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Bias


Safe Operating Area (MLP1N06CL)

493

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

MLP1N06CL
1.0
0.7
0.5

D = 0.5

0.3
0.2

0.2

RJC(t) = r(t) RJC


RJC(t) = 3.12C/W Max
D Curves Apply for Power
Pulse Train Shown
Read Time at t1
TJ(pk) TC = P(pk) RJC(t)

0.1

0.1
0.07
0.05

0.05
0.02

P(pk)

0.03

t1

0.01

t2
DUTY CYCLE, D =t1/t2

0.02
0.01
0.01

SINGLE PULSE
0.02 0.03 0.05

0.1

0.2

0.3

0.5

1.0

2.0

3.0

5.0

10

20

30

50

100

200 300

500

1000

t, TIME (ms)

Figure 9. Thermal Response (MLP1N06CL)

RL

Vin
PULSE GENERATOR
Rgen

Vout

toff

ton

VDD
td(on)

tr
90%

td(off)

DUT
OUTPUT, Vout
INVERTED

z = 50

10%

50

90%

50
50%
INPUT, Vin

Figure 10. Switching Test Circuit

ACTIVE CLAMPING
SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, backtoback diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each backtoback
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gatetodrain clamp voltages, several
voltage elements are strung together; the MLP1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gatetosource voltage clamp.
For the MLP1N06CL, the integrated gatetosource voltage

494

tf
90%

50%
PULSE WIDTH

10%

Figure 11. Switching Waveforms

elements provide greater than 2.0 kV electrostatic voltage


protection.
The avalanche voltage of the gatetodrain voltage clamp
is set less than that of the power MOSFET device. As soon
as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate
voltage across the gatetosource impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gatetodrain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the
power device.
The gatetodrain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gatetodrain clamped
conduction mode rather than in the more stressful gateto
source avalanche mode.

Motorola TMOS Power MOSFET Transistor Device Data

MLP1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLP1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 k gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.

VBAT
VDD

D
MCU

MLP1N06CL
S

Motorola TMOS Power MOSFET Transistor Device Data

495

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
SMARTDISCRETES
Internally Clamped, Current Limited
NChannel Logic Level Power MOSFET
Designer's

The MLP2N06CL is designed for applications that require a rugged power switching
device with short circuit protection that can be directly interfaced to a microcontrol unit
(MCU). Ideal applications include automotive fuel injector driver, incandescent lamp
driver or other applications where a high inrush current or a shorted load condition could
occur.
This logic level power MOSFET features current limiting for short circuit protection,
integrated GateSource clamping for ESD protection and integral GateDrain clamping
for overvoltage protection and Sensefet technology for low onresistance. No additional
gate series resistance is required when interfacing to the output of a MCU, but a 40 k
gate pulldown resistor is recommended to avoid a floating gate condition.
The internal GateSource and GateDrain clamps allow the device to be applied
without use of external transient suppression components. The GateSource clamp
protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The
GateDrain clamp protects the MOSFET drain from the avalanche stress that occurs
with inductive loads. Their unique design provides voltage clamping that is essentially
independent of operating temperature.
The MLP2N06CL is fabricated using Motorolas SMARTDISCRETES technology which
combines the advantages of a power MOSFET output device with the onchip protective
circuitry that can be obtained from a standard MOSFET process. This approach offers an
economical means of providing protection to power MOSFETs from harsh automotive and
industrial environments. SMARTDISCRETES devices are specified over a wide temperature range from 50C to 150C.

MLP2N06CL
Motorola Preferred Device

VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.4 OHMS

R1
G

R2
S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

Clamped

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

Clamped

Vdc

GatetoSource Voltage Continuous

VGS

10

Vdc

Drain Current Continuous @ TC = 25C

ID

Selflimited

Adc

Total Power Dissipation @ TC = 25C

PD

40

Watts

ESD

2.0

kV

TJ, Tstg

50 to 150

TJ(max)

150

RJC

3.12

C/W

TL

260

80

mJ

Electrostatic Voltage
Operating and Storage Temperature Range

G
D
S

THERMAL CHARACTERISTICS
Maximum Junction Temperature
Thermal Resistance Junction to Case
Maximum Lead Temperature for Soldering Purposes,
1/8 from case for 5 sec.

CASE 221A06, Style 5


TO220AB

DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Single Pulse DraintoSource Avalanche Energy
(Starting TJ = 25C, ID = 2.0 A, L = 40 mH)

EAS

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

496

Motorola TMOS Power MOSFET Transistor Device Data

MLP2N06CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

58
58

62
62

66
66

0.6
6.0

5.0
20

0.5
1.0

5.0
20

1.0
0.6

1.5
1

2.0
1.6

3.8
1.6

4.4
2.4

5.2
2.9

0.3
0.53

0.4
0.7

1.0

1.4

1.1

1.5

td(on)

1.0

1.5

tr

3.0

5.0

td(off)

5.0

8.0

tf

3.0

5.0

Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(ID = 20 mAdc, VGS = 0 Vdc)
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 40 Vdc, VGS = 0 Vdc)
(VDS = 40 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateSource Leakage Current


(VG = 5.0 Vdc, VDS = 0 Vdc)
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C)

IGSS

Vdc

Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(ID = 250 Adc, VDS = VGS)
(ID = 250 Adc, VDS = VGS, TJ = 150C)

VGS(th)

Static Drain Current Limit


(VGS = 5.0 Vdc, VDS = 10 Vdc)
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C)

Vdc

ID(lim)

Static DraintoSource OnResistance


(ID = 1.0 Adc, VGS = 5.0 Vdc)
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C)

Adc

RDS(on)

Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc)

gFS

Static SourcetoDrain Diode Voltage


(IS = 1.0 Adc, VGS = 0 Vdc)

VSD

Ohms

mhos
Vdc

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 30 Vdc, ID = 1.0 Adc,


VGS(on) = 5.0 Vdc, RGS = 25 Ohms)

Fall Time

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4.0

TJ = 25C

6.0 V
5.5 V
5.0 V
4.5 V
4.0 V

3.5 V
3.0 V

VDS 7.5 V

55C

25C

3.5
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

2.5 V

TJ = 150C

3.0
2.5
2.0
1.5
1.0
0.5

2.0 V
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Function

497

MLP2N06CL

498

I D(lim) , DRAIN CURRENT (AMPS)

6
VGS = 5 V
VDS = 10 V

5
4
3
2
1
0

50

50

100

150

TJ, JUNCTION TEMPERATURE (C)

Figure 3. ID(lim) Variation With Temperature

RDS(on) , ONRESISTANCE (OHMS)

1.0
ID = 1 A
0.8

0.6
100C

0.4
25C
0.2

TJ = 50C
0

7
8
4
5
6
2
3
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

Figure 4. RDS(on) Variation With


GateToSource Voltage

0.6
RDS(on) , ONRESISTANCE (OHMS)

THE SMARTDISCRETES CONCEPT


From a standard power MOSFET process, several active
and passive elements can be obtained that provide onchip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low onresistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit (MCU).
Ideal applications include automotive fuel injector driver,
incandescent lamp driver or other applications where a high
inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device,
its initial junction temperature, and the supply voltage. Without
some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLP2N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature is
under 100C. For longer periods of operation in the current
limited mode, device heatsinking can extend operation from
several seconds to indefinitely depending on the amount of
heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The onchip circuitry of the MLP2N06CL offers an integrated
means of protecting the MOSFET component from high inrush
current or a shorted load. As shown in the schematic diagram,
the current limiting feature is provided by an NPN transistor and
integral resistors R1 and R2. R2 senses the current through the
MOSFET and forward biases the NPN transistors base as the
current increases. As the NPN turns on, it begins to pull gate
drive current through R1, dropping the gate drive voltage across
it, and thus lowering the voltage across the gatetosource of
the power MOSFET and limiting the current. The current limit is
temperature dependent as shown in Figure 3, and decreases
from about 2.3 Amps at 25C to about 1.3 Amps at 150C.
Since the MLP2N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature
to a maximum of 150C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due
to the lower temperature coefficient of R2. The onresistance
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.
Backtoback polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This onchip
protection feature eliminates the need for an external Zener
diode for systems with potentially heavy line transients.

ID = 1 A
0.5
0.4
0.3

VGS = 4 V
VGS = 5 V

0.2
0.1
0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MLP2N06CL
BV(DSS) , DRAINTOSOURCE SUSTAINING
VOLTAGE (VOLTS)

EAS , SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

100
ID = 2 A
80

60

40

20

0
25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

64.0
63.5
63.0
62.5
62.0
61.5
61.0
60.5
60.0
50

Figure 6. Maximum Avalanche Energy


versus Starting Junction Temperature

MAXIMUM DC VOLTAGE CONSIDERATIONS


The maximum draintosource voltage that can be continuously applied across the MLP2N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
Vsupply =

(150 TA)
ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is


being used in the application.

Motorola TMOS Power MOSFET Transistor Device Data

0
50
100
TJ = JUNCTION TEMPERATURE

150

Figure 7. DrainSource Sustaining


Voltage Variation With Temperature

DUTY CYCLE OPERATION


When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =

150 TC
ID(lim) x DC x RJC

10

ID , DRAIN CURRENT (AMPS)

FORWARD BIASED SAFE OPERATING AREA


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal Resistance General
Data and Its Use provides detailed instructions.

ID = 20 mA

VGS = 10 V
SINGLE PULSE
TC = 25C

1.0

dc
10 ms
1 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 8. Maximum Rated Forward Bias


Safe Operating Area (MLP2N06CL)

499

MLP2N06CL
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.1

0.05

P(pk)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E 01

1.0E+00

1.0E+01

t, TIME (s)

Figure 9. Thermal Response (MLP2N06CL)

ton

VDD
RL

Vin
PULSE GENERATOR
Rgen

Vout

td(on)

toff
tr
90%

td(off)

DUT
OUTPUT, Vout
INVERTED

z = 50

10%

50

90%

50
50%
INPUT, Vin

Figure 10. Switching Test Circuit

ACTIVE CLAMPING
SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, backtoback diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each backtoback
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gatetodrain clamp voltages, several
voltage elements are strung together; the MLP2N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gatetosource voltage clamp.
For the MLP2N06CL, the integrated gatetosource voltage

4100

tf
90%

50%
PULSE WIDTH

10%

Figure 11. Switching Waveforms

elements provide greater than 2.0 kV electrostatic voltage


protection.
The avalanche voltage of the gatetodrain voltage clamp
is set less than that of the power MOSFET device. As soon
as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate
voltage across the gatetosource impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gatetodrain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the
power device.
The gatetodrain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gatetodrain clamped
conduction mode rather than in the more stressful gateto
source avalanche mode.

Motorola TMOS Power MOSFET Transistor Device Data

MLP2N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLP2N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 k gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.

VBAT
VDD

D
MCU

MLP2N06CL
S

Motorola TMOS Power MOSFET Transistor Device Data

4101

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Medium Power Surface Mount Products

MMDF1N05E

TMOS Dual N-Channel


Field Effect Transistors

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.

DUAL TMOS MOSFET


50 VOLTS
1.5 AMPERE
RDS(on) = 0.30 OHM

G
CASE 75105, Style 11
SO8

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed
Avalanche Energy Specified
Mounting Information for SO8 Package Provided
IDSS Specified at Elevated Temperature

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDS

50

Volts

GatetoSource Voltage Continuous

VGS

20

Volts

Drain Current Continuous


Drain Current Pulsed

ID
IDM

2.0
10

Amps

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 V, VGS = 10 V, IL = 2 Apk)

EAS

300

mJ

TJ, Tstg

55 to 150

PD

2.0

Watts

RJA

62.5

C/W

TL

260
10

C
Sec

Rating

Operating and Storage Temperature Range


Total Power Dissipation @ TA = 25C
Thermal Resistance Junction to Ambient (1)
Maximum Temperature for Soldering,
Time in Solder Bath

DEVICE MARKING
F1N05
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF1N05ER2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500

REV 4

4102

Motorola TMOS Power MOSFET Transistor Device Data

MMDF1N05E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

50

Vdc

Zero Gate Voltage Drain Current


(VDS = 50 V, VGS = 0)

IDSS

250

Adc

GateBody Leakage Current


(VGS = 20 Vdc, VDS = 0)

IGSS

100

nAdc

VGS(th)

1.0

3.0

Vdc

RDS(on)
RDS(on)

0.30
0.50

gFS

1.5

mhos

Ciss

330

pF

Coss

160

Crss

50

td(on)

20

tr

30

td(off)

40

tf

25

Qg

12.5

Qgs

1.9

Qgd

3.0

VSD

1.6

trr

45

ns

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 A)

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
DraintoSource OnResistance
(VGS = 10 Vdc, ID = 1.5 Adc)
(VGS = 4.5 Vdc, ID = 0.6 Adc)

Ohms

Forward Transconductance (VDS = 15 V, ID = 1.5 A)


DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 10 V, ID = 1.5 A, RL = 10 ,
VG = 10 V, RG = 50 )

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 10 V,
V ID = 1.5
1 5 A,
A
VGS = 10 V)

GateDrain Charge
SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C)
Forward Voltage(1)
((IS = 1.5 A, VGS = 0 V))
(dIS/dt = 100 A/s)
Reverse Recovery Time

ns

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4103

MMDF1N05E
TYPICAL ELECTRICAL CHARACTERISTICS
10

6V
8V

TJ = 25C

10

8
4.5 V
6
4V
4
VGS = 3.5 V

4
6
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

25C

10

RDS(on) , DRAINTOSOURCE ONRESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE ONRESISTANCE (OHMS)

VGS = 10 V
0.4

0.3

100C
25C

0.1
55C
0

4
6
ID, DRAIN CURRENT (AMPS)

0.5
ID = 1.5 A
VGS = 0

0.3

0.2

0.1

5
6
7
8
TJ, JUNCTION TEMPERATURE

Figure 5. On Resistance versus


GateToSource Voltage

4104

125

150

1.8
1.6
1.4

VGS = 10 V
ID = 1.5 A

1.2
1
0.8
0.6
0.4
0.2
0
50

25

25
75
0
50
100
TJ, JUNCTION TEMPERATURE (C)

Figure 4. OnResistance Variation with Temperature

10

V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. OnResistance versus Drain Current

0.4

55C
3

Figure 2. Transfer Characteristics

0.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

0.2

25C
100C

100C
0

55C

VDS 10 V

5V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

10 V

1.2
VDS = VGS
ID = 1 mA

1.1

0.9

0.8

0.7
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 6. Gate Threshold Voltage Variation


with Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMDF1N05E
VDS

12

Ciss
TJ = 25C

Crss

1000
C, CAPACITANCE (pF)

800
VDS = 0

VGS = 0

600
Ciss

400

Coss

200

Crss
0

VGS , GATETOSOURCE VOLTAGE (VOLTS)

VGS

1200

20
10
0
20
25
15
5
5
10
15
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS = 25 V
ID = 1.2 A

10
8
6
4
2
0

Figure 7. Capacitance Variation

6
10
8
12
Qg, TOTAL GATE CHARGE (nC)

14

16

Figure 8. Gate Charge versus


GateToSource Voltage
100

Forward Biased Safe Operating Area


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal Resistance General
Data and Its Use provides detailed instructions.

I D , DRAIN CURRENT (AMPS)

SAFE OPERATING AREA INFORMATION

10

VGS = 20 V
SINGLE PULSE
TC = 25C

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s

10 s

10 ms
1

dc

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 9. Maximum Rated Forward Biased


Safe Operating Area

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 10. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

4105

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2C01HD

Medium Power Surface Mount Products

Complementary TMOS
Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided

COMPLEMENTARY
DUAL TMOS POWER FET
2.0 AMPERES
12 VOLTS
RDS(on) = 0.045 OHM
(NCHANNEL)
RDS(on) = 0.18 OHM
(PCHANNEL)

D
NChannel

CASE 75105, Style 14


SO8
S
D

PChannel

NSource

NDrain

NGate

NDrain

PSource

PDrain

PGate

PDrain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage

NChannel
PChannel

GatetoSource Voltage
Drain Current Continuous
Pulsed

NChannel
PChannel
NChannel
PChannel

Symbol

Value

Unit

VDSS

20
12

Vdc

VGS

8.0

Vdc

ID

5.2
3.4
48
17

55 to 150

IDM

Operating and Storage Temperature Range

TJ and Tstg

Total Power Dissipation @ TA= 25C (2)


Thermal Resistance Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds.

PD

2.0

Watts

RJA

62.5

C/W

TL

260

DEVICE MARKING
D2C01
(1) Negative signs for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2C01HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4106

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C01HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

Unit

V(BR)DSS

(N)
(P)

20
12

Vdc

(N)
(P)

1.0
1.0

100

(N)
(P)

0.7
0.7

0.8
1.0

1.1
1.1

(N)
(P)

0.035
0.16

0.045
0.18

(N)
(P)

0.043
0.2

0.055
0.22

(N)
(P)

3.0
3.0

6.0
4.75

Ciss

(N)
(P)

425
530

595
740

Coss

(N)
(P)

270
410

378
570

Crss

(N)
(P)

115
177

230
250

td(on)

(N)
(P)

13
21

26
45

tr

(N)
(P)

60
156

120
315

td(off)

(N)
(P)

20
38

40
75

tf

(N)
(P)

29
68

58
135

td(on)

(N)
(P)

10
16

20
35

tr

(N)
(P)

42
44

84
90

td(off)

(N)
(P)

24
68

48
135

tf

(N)
(P)

28
54

56
110

QT

(N)
(P)

9.2
9.3

13
13

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 20 Vdc)
(VGS = 0 Vdc, VDS = 12 Vdc)

Adc

IDSS

GateBody Leakage Current


(VGS = 8.0 Vdc, VDS = 0)

IGSS

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
DraintoSource OnResistance
(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 4.5 Vdc, ID = 2.0 Adc)
DraintoSource OnResistance
(VGS = 2.7 Vdc, ID = 2.0 Adc)
(VGS = 2.7 Vdc, ID = 1.0 Adc)

VGS(th)
RDS(on)

Ohm

RDS(on)

Forward Transconductance
(VDS = 2.5 Adc, ID = 2.0 Adc)
(VDS = 2.5 Adc, ID = 1.0 Adc)

Vdc

Ohm

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc, VGS = 0 Vdc,


f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

((VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 2.7 Vdc,
RG = 2.3 )
(VDD = 6.0 Vdc, ID = 2.0 Adc,
dc,
VGS = 2.7 Vdc,
RG = 6.0 )

TurnOn Delay Time


Rise Time
TurnOff Delay Time
Fall Time

((VDS = 6.0 Vdc, ID = 4.0 Adc,


VGS = 4.5 Vdc,
RG = 2.3 )
(VDS = 6.0 Vdc, ID = 2.0 Adc,
5 Vdc,
dc,
VGS = 4.5
RG = 6.0 )

Total Gate Charge


GateSource Charge

(VDS = 10 Vdc, ID = 4.0 Adc,


VGS = 4.5 Vdc)

Q1

(N)
(P)

1.3
0.8

GateDrain Charge

(VDS = 6.0 Vdc, ID = 2.0 Adc,


VGS = 4.5 Vdc))

Q2

(N)
(P)

3.5
4.0

Q3

(N)
(P)

3.0
3.0

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

ns

nC

(continued)

4107

MMDF2C01HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted)(1)
Characteristic
SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C)
Forward Voltage(2)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time

( F = IS,
(I
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

Symbol

Polarity

Min

Typ

Max

Unit

VSD

(N)
(P)

0.95
1.69

1.1
2.0

Vdc

trr

(N)
(P)

38
48

ns

ta

(N)
(P)

17
23

tb

(N)
(P)

22
25

QRR

(N)
(P)

0.028
0.05

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

TYPICAL ELECTRICAL CHARACTERISTICS


NChannel
4

VGS = 8 V

4.5 V
3.1 V
6 2.7 V

VGS = 8 V
4.5 V
3.1 V

TJ = 25C

2.3 V
2.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

PChannel

2.1 V

1.9 V
1.7 V

2.5 V

TJ = 25C
2.3 V

2.7 V
2.1 V

2
1.9 V
1
1.7 V

1.5 V
1.3 V
0

I D , DRAIN CURRENT (AMPS)

0.2

0.4

0.6

0.8

1.2

1.4

1.5 V
1.6

1.8

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.6

2.8

Figure 1. OnRegion Characteristics

Figure 1. OnRegion Characteristics

100C
25C
TJ = 55C

0.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VDS 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I D , DRAIN CURRENT (AMPS)

VDS 10 V

2
100C

25C

TJ = 55C
0

1.2
1.4
1.6
1.8
2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

4108

2.2

1.2

1.4

1.6

1.8

2.2

2.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
PChannel

0.07
TJ = 25C
ID = 2 A
0.06

0.05

0.04

0.03

6
2
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

NChannel
0.35
TJ = 25C
ID = 1 A

0.30

0.25

0.20

0.15

0.1

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus


GateToSource Voltage

0.050
TJ = 25C
VGS = 2.7 V

0.045

0.040

4.5 V

0.035

0.030

6
4
ID, DRAIN CURRENT (AMPS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. OnResistance versus


GateToSource Voltage

0.30
TJ = 25C
0.25

4.5 V
0.15

0.10

VGS = 4.5 V
ID = 4 A

0.5

0
50

25

25

50

75

100

125

150

0.8

1.6
2.4
ID, DRAIN CURRENT (AMPS)

3.2

Figure 4. OnResistance versus Drain Current


and Gate Voltage

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS = 2.7 V

0.20

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.5

1.5

VGS = 4.5 V
ID = 2 A

0.5

0
50

25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

4109

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel

PChannel

100

1000
VGS = 0 V

VGS = 0 V

10

I DSS , LEAKAGE (nA)

I DSS , LEAKAGE (nA)

TJ = 125C

100C

TJ = 125C
100

10
0

6
2
4
8
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

Figure 6. DrainToSource Leakage


Current versus Voltage

4
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

Figure 6. DrainToSource Leakage


Current versus Voltage

POWER MOSFET SWITCHING


Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

4110

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C01HD
NChannel
2000

VDS = 0 V

VGS = 0 V

2000

TJ = 25C

1600

Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1600

PChannel

1200

Crss

800

Ciss

VGS = 0 V

TJ = 25C

Ciss

1200

800

Crss
Ciss

Coss

400

VDS = 0 V

400

Coss

Crss
4

VGS

12

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Figure 7. Capacitance Variation

8
VGS

VDS
3

6
Q1

Q2
ID = 4 A
TJ = 25C

2
Q3
2

0
10

10
QT

8
VGS

VDS
3

2 Q1

ID = 2 A
TJ = 25C

Q2

2
Q3

0
10

QT, TOTAL CHARGE (nC)

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

1000
VDD = 6 V
ID = 2 A
VGS = 4.5 V
TJ = 25C

tr
tf
td(off)

t, TIME (ns)

VDD = 6 V
ID = 4 A
VGS = 4.5 V
TJ = 25C

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

10

100

t, TIME (ns)

0
VGS

QT

Crss
4

VDS

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

td(on)

100

td(off)
tf
tr
td(on)

1
0.1

10
1

10

100

10

RG, GATE RESISTANCE (OHMS)

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

Motorola TMOS Power MOSFET Transistor Device Data

100

4111

MMDF2C01HD
DRAINTOSOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

NChannel

PChannel
2

VV
GS
GS= =0 0VV
TJTJ= =25C
25C

I S , SOURCE CURRENT (AMPS)

I S , SOURCE CURRENT (AMPS)

0
0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4112

VGS = 0 V
TJ = 25C
1.5

0.5

0
0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C01HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power

averaged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.

NChannel

PChannel
100

10

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

10 ms
1

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided) with one die operating, 10s max.

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

10

VGS = 8 V
SINGLE PULSE
TC = 25C

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4113

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4114

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2C02E

Medium Power Surface Mount Products

Complementary TMOS
Field Effect Transistors

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

COMPLEMENTARY
DUAL TMOS POWER FET
2.5 AMPERES
25 VOLTS
RDS(on) = 0.100 OHM
(NCHANNEL)
RDS(on) = 0.25 OHM
(PCHANNEL)

D
NChannel

G
CASE 75105, Style 14
SO8

S
D
PChannel

NSource

NDrain

NGate

NDrain

PSource

PDrain

PGate

PDrain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
GatetoSource Voltage
Drain Current Continuous
Pulsed

NChannel
PChannel
NChannel
PChannel

Symbol

Value

Unit

VDSS
VGS

25

Vdc

20

Vdc

3.6
2.5
18
13

Adc

ID
IDM

Operating and Storage Temperature Range


Total Power Dissipation @ TA= 25C (2)

TJ and Tstg
PD

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25 )
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)

55 to 150

2.0

Watts

EAS

Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds.

mJ
245
245

NChannel
PChannel
RJA

62.5

C/W

TL

260

DEVICE MARKING
F2C02
(1) Negative signs for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2C02ER2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4115

MMDF2C02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

25

Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)

V(BR)DSS

Vdc

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)

IDSS

(N)
(P)

1.0
1.0

Adc

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

100

nAdc

1.0

2.0

3.0

(N)
(P)

0.100
0.250

(N)
(P)

0.200
0.400

(N)
(P)

2.0
2.0

(N)
(P)

1.0
1.0

2.6
2.8

Ciss

(N)
(P)

380
340

532
475

Coss

(N)
(P)

235
220

329
300

Crss

(N)
(P)

55
75

110
150

td(on)

(N)
(P)

10
20

30
40

tr

(N)
(P)

35
40

70
80

td(off)

(N)
(P)

19
53

38
106

tf

(N)
(P)

25
41

50
82

td(on)

(N)
(P)

7.0
13

21
26

tr

(N)
(P)

17
29

30
58

td(off)

(N)
(P)

27
30

48
60

tf

(N)
(P)

18
28

30
56

QT

(N)
(P)

10.6
10

30
15

Q1

(N)
(P)

1.3
1.0

Q2

(N)
(P)

2.9
3.5

Q3

(N)
(P)

2.7
3.0

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)

VGS(th)

DraintoSource OnResistance
(VGS = 10 Vdc, ID = 2.2 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

DraintoSource OnResistance
(VGS = 4.5 Vdc, ID = 1.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
OnState Drain Current
(VDS = 5.0 Vdc, VGS = 4.5 Vdc)

RDS(on)

ID(on)

Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc
Ohm

Ohm

gFS

Adc
mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc, VGS = 0 Vdc,


f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

((VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 4.5 Vdc,
RG = 9.1 )
(VDD = 10 Vdc, ID = 1.0 Adc,
5.0
VGS = 5
0 Vdc,
dc,
RG = 25 )

TurnOn Delay Time


Rise Time
TurnOff Delay Time
Fall Time

((VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc,
RG = 6.0 )
(VDD = 10 Vdc, ID = 2.0 Adc,
0 Vdc,
dc,
VGS = 10
RG = 6.0 )

Total Gate Charge


GateSource Charge
GateDrain Charge

((VDS = 16 Vdc,, ID = 2.0 Adc,,


VGS = 10 Vdc)

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

4116

ns

nC

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02E
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

Unit

VSD

(N)
(P)

1.0
1.5

1.4
2.0

Vdc

trr

(N)
(P)

34
32

66
64

ns

ta

(N)
(P)

17
19

tb

(N)
(P)

17
12

QRR

(N)
(P)

0.025
0.035

SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C)


Forward Voltage(2)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc)

Reverse Recovery Time


see Figure 7

((IF = IS,
dIS/dt = 100 A/s)

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

TYPICAL ELECTRICAL CHARACTERISTICS


NChannel
4

VGS = 10 V
4.5 V
4.3 V
4.1 V

6
5

3.7 V

VGS = 10 7 V

3.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

PChannel

3.9 V
3.3 V

4
3.1 V
3
2.9 V
2
2.7 V
2.5 V

1
0

TJ = 25C
0

3
4.3 V
2

4.1 V
3.9 V

3.7 V
3.5 V
3.3 V

Figure 1. OnRegion Characteristics

Figure 1. OnRegion Characteristics

1.25

1.5

1.75

VDS 10 V
TJ = 25C

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

4.5 V

0.4
0.8
1.2
1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.75

5
4

100C

3
25C
2
1
0
1.5

TJ = 25C

4.7 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.5

0.25

7
6

5V

VDS 10 V

3
100C
2
25C
TJ = 55C
1

TJ = 55C
2

2.5

3.5

0
2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

3
3.5
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

4.5

4117

MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
PChannel

0.6
ID = 3.5 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
2

4
5
6
7
8
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

NChannel
0.6

ID = 1 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
3

TJ = 25C
VGS = 4.5
0.1
10 V

0.05

0
2

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.15

0.5

0.4
VGS = 4.5

0.3

0.2
10 V
0.1
0

0.5

1.5

1.0

0.5

50

75

100

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation


with Temperature

4118

1.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

125

150

RDS(on) , DRAINTOSOURCE RESISTANCE (NORMALIZED)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

VGS = 10 V
ID = 3.5 A

25

10

ID, DRAIN CURRENT (AMPS)

2.0

TJ = 25C

Figure 4. OnResistance versus Drain Current


and Gate Voltage

25

0.6

ID, DRAIN CURRENT (AMPS)

0
50

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 3. OnResistance versus


GatetoSource Voltage

VGS, GATETOSOURCE VOLTAGE (VOLTS)

2.0
VGS = 10 V
ID = 2 A
1.5

1.0

0.5

0
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel

PChannel

10000

100
VGS = 0 V

TJ = 125C

1000

100C
I DSS , LEAKAGE (nA)

I DSS , LEAKAGE (nA)

VGS = 0 V

100
25C
10

10

15

20

25

TJ = 125C
10

100C

12

20

16

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DraintoSource Leakage Current


versus Voltage

Figure 6. DraintoSource Leakage Current


versus Voltage

POWER MOSFET SWITCHING


Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.

Motorola TMOS Power MOSFET Transistor Device Data

During the turnon and turnoff delay times, gate current is


not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

4119

MMDF2C02E
DRAINTOSOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dt = 300 A/s

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 7. Reverse Recovery Time (trr)

4120

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02E
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

NChannel

PChannel

VGS = 20 V
SINGLE PULSE
TC = 25C

10

100

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

10 s

10 ms
1

dc

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

VGS = 20 V
SINGLE PULSE
TC = 25C

10

100 s

dc

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

100

Figure 8. Maximum Rated Forward Biased


Safe Operating Area

280

280
I pk = 9 A

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Biased


Safe Operating Area

240
200
160
120
80
40
0

10 s

10 ms

0.01
0.1

100

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

25

50

75

100

125

150

I pk = 7 A
240
200
160
120
80
40
0

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 9. Maximum Avalanche Energy versus


Starting Junction Temperature

Figure 9. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4121

MMDF2C02E
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 10. Thermal Response


di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 11. Diode Reverse Recovery Waveform

4122

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2C02HD

Medium Power Surface Mount Products

Complementary TMOS
Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

D
NChannel

G
CASE 75105, Style 14
SO8
S
D
PChannel

Rating
DraintoSource Voltage
GatetoSource Voltage
DraintoGate Voltage (RGS = 1.0 m)

Pulsed

NSource

NDrain

NGate

NDrain

PSource

PDrain

PGate

PDrain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)

Drain Current Continuous

COMPLEMENTARY
DUAL TMOS POWER FET
2.0 AMPERES
20 VOLTS
RDS(on) = 0.090 OHM
(NCHANNEL)
RDS(on) = 0.160 OHM
(PCHANNEL)

Symbol

Value

Unit

VDSS
VGS

20

Vdc

20

Vdc

20

Vdc

3.8
3.3
19
20

VDGR
ID

NChannel
PChannel
NChannel
PChannel

IDM

Operating and Storage Temperature Range


Total Power Dissipation @ TA= 25C (2)

TJ, Tstg
PD

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 )
(VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)

55 to 150

2.0

Watts

EAS

Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds.

mJ
405
324

NChannel
PChannel
RJA

62.5

C/W

TL

260

DEVICE MARKING
D2C02
(1) Negative signs for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2C02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4123

MMDF2C02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

20

Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)

V(BR)DSS

Vdc

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)

IDSS

(N)
(P)

1.0
1.0

Adc

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

100

nAdc

1.0

1.5

2.0

(N)
(P)

0.074
0.152

0.100
0.180

(N)
(P)

0.058
0.118

0.090
0.160

(N)
(P)

2.0
2.0

3.88
3.0

Ciss

(N)
(P)

455
420

630
588

Coss

(N)
(P)

184
290

250
406

Crss

(N)
(P)

45
116

90
232

td(on)

(N)
(P)

11
19

22
38

tr

(N)
(P)

58
66

116
132

td(off)

(N)
(P)

17
25

35
50

tf

(N)
(P)

20
37

40
74

td(on)

(N)
(P)

7.0
11

21
22

tr

(N)
(P)

32
21

64
42

td(off)

(N)
(P)

27
45

54
90

tf

(N)
(P)

21
36

42
72

QT

(N)
(P)

12.5
15

18
20

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)

VGS(th)

DraintoSource OnResistance
(VGS = 4.5 Vdc, ID = 1.5 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

DraintoSource OnResistance
(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)

gFS

Vdc
Ohm

Ohm

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc, VGS = 0 Vdc,


f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

((VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 4.5 Vdc,
RG = 6.0 )
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 )

TurnOn Delay Time


Rise Time
TurnOff Delay Time
Fall Time

((VDD = 10 Vdc,, ID = 3.0 Adc,,


VGS = 10 Vdc,
RG = 6.0 )
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,,
RG = 6.0 )

Total Gate Charge


GateSource Charge

(VDS = 16 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc)

Q1

(N)
(P)

1.3
1.2

GateDrain Charge

(VDS = 16 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc))

Q2

(N)
(P)

2.8
5.0

Q3

(N)
(P)

2.4
4.0

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

4124

ns

nC

(continued)

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted)(1)
Symbol

Polarity

Min

Typ

Max

Unit

VSD

(N)
(P)

0.79
1.5

1.3
2.1

Vdc

trr

(N)
(P)

23
38

ns

(IS = 3.0 Adc, VAS = 0 Vdc,


dIS/dt = 100 A/s)

ta

(N)
(P)

18
17

(IS = 2.0 Adc, VAS = 0 Vdc,


dIS/dt = 100 A/s)
)

tb

(N)
(P)

5.0
21

QRR

(N)
(P)

0.025
0.034

Characteristic
SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C)
Forward Voltage(2)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time

Reverse Recovery Stored Charge

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

TYPICAL ELECTRICAL CHARACTERISTICS


NChannel

PChannel

VGS = 10 V
4.5 V
5
3.9 V

TJ = 25C

3.5 V
3.3 V

3.7 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

4
3.1 V
3
2.9 V
2
2.7 V

VGS = 10 V 4.5 V

3.9 V

3.7 V
3.5 V

3.3 V
2
3.1 V
2.9 V

2.7 V
2.5 V

2.5 V
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.8

0.2

0.6

0.8

1.2

1.4

4
I D , DRAIN CURRENT (AMPS)

VDS 10 V

4
TJ = 100C
25C
2
55C

2.2
2.6
3
1.4
1.8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.8

VDS 10 V

1
25C

100C

1.6

Figure 1. OnRegion Characteristics

6
I D , DRAIN CURRENT (AMPS)

0.4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

TJ = 25C

3.4

Figure 2. Transfer Characteristics

Motorola TMOS Power MOSFET Transistor Device Data

0
1.0

TJ = 55C
1.5
2.0
2.5
3.0
VGS, GATETOSOURCE VOLTAGE (VOLTS)

3.5

Figure 2. Transfer Characteristics

4125

MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS

0.6

PChannel

ID = 1.5 A
TJ = 25C

0.4

0.2

5
6
7
8
3
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)
2

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

NChannel
0.6

ID = 1 A
TJ = 25C

0.4

0.2

0.08
VGS = 4.5 V

0.07

10 V

0.06

0.05

2
3
4
ID, DRAIN CURRENT (AMPS)

TJ = 25C
VGS = 4.5 V

0.16

0.12

10 V

0.08

0.04
0

1.2

0.8

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

4126

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Figure 4. OnResistance versus Drain Current


and Gate Voltage

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS = 10 V
ID = 1.5 A

25

0.5

ID, DRAIN CURRENT (AMPS)

1.6

0.6
50

10

0.20

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.4

Figure 3. OnResistance versus


GateToSource Voltage
RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. OnResistance versus


GateToSource Voltage

TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

1.6
VGS = 10 V
ID = 2 A
1.4

1.2

1.0

0.8

0.6
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel

PChannel
100

1000

VGS = 0 V

TJ = 125C

100

I DSS, LEAKAGE (nA)

I DSS , LEAKAGE (nA)

VGS = 0 V

100C
25C

10

8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

Figure 6. DrainToSource Leakage


Current versus Voltage

TJ = 125C

10
100C

10

15

20

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

POWER MOSFET SWITCHING


Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]

Motorola TMOS Power MOSFET Transistor Device Data

td(off) = RG Ciss In (VGG/VGSP)


The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

4127

MMDF2C02HD
NChannel
1200

TJ = 25C

Ciss

1000
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1200

VGS = 0 V

1000
800
Crss

600

Ciss

400

VGS = 0 V

VDS = 0 V

TJ = 25C

Ciss

800
600
Crss

Ciss

400

Coss

Coss

200

200

Crss
5

10

0
VGS

10

15

Crss

0
10

20

5
VGS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

20
VGS

16
12

ID = 3 A
TJ = 25C
Q2

4
VDS

Q3
0

10

12

0
14

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

v DS , DRAINTOSOURCE VOLTAGE (VOLTS)

24
QT

Q1

12

18
QT

10

15
VGS
VDS

12

4 Q1

Q2

6
ID = 2 A
TJ = 25C

Q3
0

12

0
16

QT, TOTAL GATE CHARGE (nC)

QT, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

1000
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25C

VDD = 10 V
ID = 3 A
VGS = 10 V
tr
TJ = 25C t
d(off)

t, TIME (ns)

t, TIME (ns)

20

15

Figure 7. Capacitance Variation

12

10

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

VDS

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS = 0 V

1400

PChannel

tf
td(on)

10

100
td(off)
tf
tr

1
1

4128

10

100

td(on)

10
1

10

RG, GATE RESISTANCE (OHMS)

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02HD
DRAINTOSOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

NChannel

PChannel
2.0

3.0

I S , SOURCE CURRENT (AMPS)

I S , SOURCE CURRENT (AMPS)

2.5

VGS = 0 V
TJ = 25C

VGS = 0 V
TJ = 25C

2.0
1.5
1.0
0.5
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

1.6

1.2

0.8

0.4

0
0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4129

MMDF2C02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

NChannel

PChannel

10

VGS = 20 V
SINGLE PULSE
TC = 25C

100

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4130

100

10

VGS = 20 V
SINGLE PULSE
TC = 25C

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s
1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C02HD
NChannel

PChannel
350
ID = 9 A

400

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

450

350
300
250
200
150
100
50
0
25

50

75

100

125

ID = 6 A
300
250
200
150
100
50
0

150

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4131

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2C03HD

Medium Power Surface Mount Products

Complementary TMOS
Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain-to-source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc-dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO-8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO-8 Package Provided

COMPLEMENTARY
DUAL TMOS POWER FET
2.0 AMPERES
30 VOLTS
RDS(on) = 0.070 OHM
(N-CHANNEL)
RDS(on) = 0.200 OHM
(P-CHANNEL)

D
NChannel

CASE 75105, Style 14


SO8
S
D

PChannel

NSource

NDrain

NGate

NDrain

PSource

PDrain

PGate

PDrain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
GatetoSource Voltage
Drain Current Continuous NChannel
PChannel
Drain Current Pulsed
NChannel
PChannel

Symbol

Value

Unit

VDSS
VGS

30

Vdc

20

Vdc

4.1
3.0
21
15

ID
IDM

Operating and Storage Temperature Range


Total Power Dissipation @ TA= 25C (2)
Thermal Resistance Junction to Ambient (2)
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 )
(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 )

TJ, Tstg
PD

55 to 150

2.0

Watts

RJA

62.5

C/W

EAS
NChannel
PChannel

Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds.

mJ
324
324

TL

260

DEVICE MARKING
D2C03
(1) Negative signs for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2C03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4132

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

30

Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)

V(BR)DSS

Vdc

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)

IDSS

(N)
(P)

1.0
1.0

Adc

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

100

nAdc

Gate Threshold Voltage


(VDS = VGS, ID = 250 Adc)

VGS(th)

(N)
(P)

1.0
1.0

1.7
1.5

3.0
2.0

Vdc

DraintoSource OnResistance
(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)
(N)
(P)

0.06
0.17

0.070
0.200

DraintoSource OnResistance
(VGS = 4.5 Vdc, ID = 1.5 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)
(N)
(P)

0.065
0.225

0.075
0.300

Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)

gFS
(N)
(P)

2.0
2.0

3.6
3.4

Ciss

(N)
(P)

450
397

630
550

Coss

(N)
(P)

160
189

225
250

Crss

(N)
(P)

35
64

70
126

(VDD = 15 Vdc, ID = 3.0


Adc,
VGS = 4.5 Vdc,
RG = 9.1 )

td(on)

(N)
(P)

12
16

24
32

tr

(N)
(P)

65
18

130
36

(VDD = 15 Vdc, ID = 2.0


Adc,
VGS = 4.5 Vdc,
RG = 6.0 )

td(off)

(N)
(P)

16
63

32
126

tf

(N)
(P)

19
194

38
390

(VDD = 15 Vdc, ID = 3.0


Adc,
VGS = 10 Vdc,
RG = 9.1 )

td(on)

(N)
(P)

8.0
9.0

16
18

tr

(N)
(P)

15
10

30
20

(VDD = 15 Vdc, ID = 2.0


Adc,
VGS = 10 Vdc,
RG = 6.0 )

td(off)

(N)
(P)

30
81

60
162

tf

(N)
(P)

23
192

46
384

QT

(N)
(P)

11.5
14.2

16
19

ON CHARACTERISTICS(2)

Ohm

Ohm

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

Vd VGS = 0
(VDS = 24 Vdc,
Vdc,
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time
Total Gate Charge
GateSource Charge

(VDS = 10 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc)

Q1

(N)
(P)

1.5
1.1

GateDrain Charge

(VDS = 24 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc))

Q2

(N)
(P)

3.5
4.5

Q3

(N)
(P)

2.8
3.5

(1) Negative signs for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

ns

nC

(continued)

4133

MMDF2C03HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Polarity

Min

Typ

Max

Unit

SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C)


Forward Voltage(2)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)

VSD

(N)
(P)

0.82
1.82

1.2
2.0

Vdc

trr

(N)
(P)

24
42

ns

ta

(N)
(P)

17
16

tb

(N)
(P)

7.0
26

QRR

(N)
(P)

0.025
0.043

3.7 V 3.5 V

TJ = 25C

Reverse Recovery Time

((IF = IS,
dIS/dt = 100 A/s)
Reverse Recovery Storage Charge
(1) Negative signs for PChannel device omitted for clarity.
(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

TYPICAL ELECTRICAL CHARACTERISTICS


NChannel
VGS = 10 V
4.5 V
5
4.3 V
4.1 V
4

3.9 V

3.5 V

3.7 V
3.3 V

3.1 V

2
2.9 V
1
0

VGS = 10 V 4.5 V

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

PChannel

3.9 V

3.3 V

3.1 V

2.9 V
1
2.7 V

2.7 V
2.5 V
0

0.2

0.6

0.4

0.8

1.2

2.5 V
1.6

1.4

1.8

0.8

1.2

1.4

1.6

1.8

Figure 1. OnRegion Characteristics

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

0.6

Figure 1. OnRegion Characteristics

VDS 10 V

4
TJ = 100C
3
25C

VDS 10 V

2
TJ = 100C
25C
1

55C

4134

0.4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

55C
2

2.5

3.5

0
1.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.7

1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3


VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

3.5

3.7

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
PChannel

0.6
ID = 1.5 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
2

4
5
6
7
8
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

NChannel
0.6

ID = 1 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0

2
3
4
5
6
7
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

3.5

0.08
TJ = 25C

0.07
VGS = 4.5

0.06
10 V

0.05

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. OnResistance versus


GateToSource Voltage
0.30
TJ = 25C
0.25
VGS = 4.5 V
0.20
10 V
0.15

0.10

ID, DRAIN CURRENT (AMPS)

2.5
3
1.5
2
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

0.5

1.5

2.5

2.0
RDS(on) , DRAINTOSOURCE RESISTANCE
(NORMALIZED)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. OnResistance versus


GateToSource Voltage

VGS = 10 V
ID = 1.5 A
1.5

1.0

0.5

0
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

0.5

1.6
VGS = 10 V
ID = 2 A
1.4

1.2

1.0

0.8

0.6
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

4135

MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel

PChannel
1000

100

VGS = 0 V
TJ = 125C

10

I DSS , LEAKAGE (nA)

I DSS , LEAKAGE (nA)

VGS = 0 V

100C

10

15

20

25

30

TJ = 125C

100

100C

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

5
10
15
20
25
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

Figure 6. DrainToSource Leakage


Current versus Voltage

30

POWER MOSFET SWITCHING


Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]

4136

td(off) = RG Ciss In (VGG/VGSP)


The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C03HD
NChannel
1200

PChannel
1200

VDS = 0 V VGS = 0 V
Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

800
Crss

Ciss

400

800
600 Crss
Ciss
400
Coss

Coss

200

200

Crss

Crss
0
10

5
VGS

10

15

20

10

15

20

30

25

VDS

Figure 7. Capacitance Variation

Figure 7. Capacitance Variation

18

VGS

VDS
6

12

Q1

Q2

6
Q3

ID = 3 A
TJ = 25C
2

10

0
12

12

24
QT
20

10
VGS

16

VDS

8
6
Q1

12

ID = 2 A
TJ = 25C

Q2

2
Q3
0

10

12

14

0
16

Qg, TOTAL GATE CHARGE (nC)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

1000

t, TIME (ns)

VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25C

100

td(off)
tr
tf
td(on)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

24

VGS, GATETOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

1000

t, TIME (ns)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

QT

5
VGS

VDS

12

0
10

30

25

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

TJ = 25C

C
1000 iss

1000

600

VDS = 0 V VGS = 0 V

TJ = 25C

VDD = 15 V
ID = 2 A
VGS = 10 V
TJ = 25C

100

tf
td(off)

tr
td(on)

10

1
1

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

Motorola TMOS Power MOSFET Transistor Device Data

10

100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

4137

MMDF2C03HD
DRAINTOSOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

NChannel

PChannel

3.0

2
TJ = 25C
VGS = 0 V
I S , SOURCE CURRENT (AMPS)

IS, SOURCE CURRENT (AMPS)

2.5
2.0
1.5
1.0
0.5
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

1.6

TJ = 25C
VGS = 0 V

1.2

0.8

0.4

0
0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 10. Diode Forward Voltage versus Current

4138

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2C03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

NChannel

PChannel

10

100
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

1 ms
10 ms

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided) with one die operating, 10s max.

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

10

VGS = 20 V
SINGLE PULSE
TC = 25C

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s
1 ms
10 ms

1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4139

MMDF2C03HD
NChannel

PChannel
350
ID = 9 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

350
300
250
200
150
100
50
0

25

50

75

100

125

250
200
150
100
50
0

150

ID = 6 A

300

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4140

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2N02E

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistors

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.

DUAL TMOS MOSFET


3.6 AMPERES
25 VOLTS
RDS(on) = 0.1 OHM

G
CASE 75105, Style 11
SO8

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
IDSS Specified at Elevated Temperatures
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
GatetoSource Voltage Continuous

Symbol

Value

Unit

VDSS
VGS

25

Vdc

20

Vdc
Adc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)

ID
ID
IDM
PD

3.6
2.5
18
2.0

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 6.0 mH, RG = 25 )
Thermal Resistance, Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds

Apk

mJ
245

RJA

62.5

C/W

TL

260

DEVICE MARKING
F2N02
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2N02ER2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4141

MMDF2N02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

25

1.0
10

100

1.0

2.0

3.0

0.083
0.110

0.100
0.200

gFS

1.0

2.6

Mhos

Ciss

380

532

pF

Coss

235

329

Crss

55

110

td(on)

7.0

21

tr

17

30

td(off)

27

48

tf

18

30

td(on)

10

30

tr

35

70

td(off)

19

38

tf

25

50

QT

10.6

30

Q1

1.3

Q2

2.9

Q3

2.7

VSD

1.0

1.4

Vdc

trr

34

66

ns

ta

17

tb

17

QRR

0.03

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 2.2 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
See Fig
Figure
re 11
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Storage Charge

ns

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4142

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2N02E
TYPICAL ELECTRICAL CHARACTERISTICS
7

VGS = 10 V
4.5 V
4.3 V
4.1 V

6
5

3.7 V
3.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3.9 V
3.3 V

4
3.1 V
3
2.9 V
2
2.7 V
2.5 V

1
0

5
4

100C

3
25C
2
1

TJ = 25C
0

VDS 10 V
TJ = 25C

0.5
0.25
0.75
1.5
1
1.25
1.75
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 55C

0
1.5

0.6
ID = 3.5 A
TJ = 25C

0.4
0.3
0.2
0.1
0
2

4
5
6
7
8
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

3.5

TJ = 25C
VGS = 4.5
0.1
10 V

0.05

0
0

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

10000
VGS = 10 V
ID = 3.5 A

VGS = 0 V

1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

0.15

Figure 3. OnResistance versus


GatetoSource Voltage

1.0

0.5

0
50

2.5

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

25

25

50

75

100

125

150

TJ = 125C

1000

100C

100
25C
10

10

15

25

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4143

MMDF2N02E
POWER MOSFET SWITCHING

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance

1200

VDS = 0 V

C, CAPACITANCE (pF)

1000

VGS = 0 V

TJ = 25C

Ciss

800
Crss

600

Ciss

400

Coss
200

Crss

0
10

10

15

20

td(on) = RG Ciss In [VGG/(VGG VGSP)]


td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
VGS, GATETOSOURCE VOLTAGE (VOLTS)

and Q2 and VGSP are read from the gate charge curve.

During the turnon and turnoff delay times, gate current is


not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

12
QT

8
Q1

4
Q3
0

4
6
8
Qg, TOTAL GATE CHARGE (nC)

10

0
12

7
6

td(off)
tf

IS, SOURCE CURRENT (AMPS)

VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25C

tr
t, TIME (ns)

ID = 2.3 A
TJ = 25C

Figure 8. GatetoSource and


DraintoSource Voltage versus Total Charge

100

10
td(on)

10
RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation


versus Gate Resistance
4144

Q2

Figure 7. Capacitance Variation

12

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS

VDS

25

16

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Switching behavior is most easily modeled and predicted


by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

100

TJ = 25C
VGS = 0 V

5
4
3
2
1
0
0.5

0.6
0.7
0.8
0.9
1
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.1

Figure 10. Diode Forward Voltage


versus Current
Motorola TMOS Power MOSFET Transistor Device Data

MMDF2N02E
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

VGS = 20 V
SINGLE PULSE
TC = 25C

10

280

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10 ms
1

dc

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

I pk = 9 A
240
200
160
120
80
40
0

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

25

50

75

100

150

125

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4145

MMDF2N02E
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4146

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2P01HD

Medium Power Surface Mount Products

TMOS P-Channel
Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.

DUAL TMOS POWER FET


2.0 AMPERES
12 VOLTS
RDS(on) = 0.18 OHM

CASE 75105, Style 11


SO8

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided

S
Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)

Symbol

Value

Unit

VDSS
VDGR

12

Vdc

12

Vdc

VGS
ID
ID
IDM

8.0

Vdc

3.4
2.1
17

Adc

PD

2.0

Watts

Operating and Storage Temperature Range

55 to 150

Thermal Resistance Junction to Ambient (2)


Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk
C

RJA

62.5

C/W

TL

260

DEVICE MARKING
D2P01
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2P01HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4147

MMDF2P01HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

12

17

1.0
10

100

0.7

1.0
3.0

1.1

0.16
0.2

0.180
0.220

gFS

3.0

4.75

mhos

Ciss

530

740

pF

Coss

410

570

Crss

177

250

td(on)

21

45

tr

156

315

td(off)

38

75

tf

68

135

td(on)

16

35

tr

44

90

td(off)

68

135

tf

54

110

QT

9.3

13

Q1

0.8

Q2

4.0

Q3

3.0

1.69
1.2

2.0

trr

48

ta

23

tb

25

QRR

0.05

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 12 Vdc, VGS = 0 Vdc)
(VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 2.0 Adc)
(VGS = 2.7 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 2.5 Vdc, ID = 1.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 6.0 Vdc, ID = 2.0 Adc,


VGS = 2.7
2 7 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 6.0 Vdc, ID = 2.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 10 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

4148

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P01HD
TYPICAL ELECTRICAL CHARACTERISTICS
4
VGS = 8 V
4.5 V
3.1 V

2.5 V

VDS 10 V

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

2.3 V

2.7 V
2.1 V

2
1.9 V
1

2
100C

25C

TJ = 55C

1.7 V
1.5 V
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.4

1.6

1.8

2.2

2.4

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 25C
ID = 1 A

0.20

0.15

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

2.6

2.8

0.30
TJ = 25C
0.25

VGS = 2.7 V

0.20

4.5 V
0.15

0.10

Figure 3. OnResistance versus


GateToSource Voltage

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

1.2

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.25

0.1

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.35

0.30

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.8

1.6
2.4
ID, DRAIN CURRENT (AMPS)

3.2

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

VGS = 0 V

VGS = 4.5 V
ID = 2 A
I DSS , LEAKAGE (nA)

1.5

0.5

0
50

25

25

50

75

100

125

150

TJ = 125C
100

10

TJ, JUNCTION TEMPERATURE (C)

4
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

12

4149

MMDF2P01HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

VDS = 0 V

TJ = 25C

Ciss

1600
C, CAPACITANCE (pF)

VGS = 0 V

1200
Crss

800

Ciss
400
0

Coss
Crss
8

4
VGS

12

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4150

Motorola TMOS Power MOSFET Transistor Device Data

10
QT

8
VGS

VDS
3

2 Q1

ID = 2 A
TJ = 25C

Q2

2
Q3

0
10

1000
VDD = 6 V
ID = 2 A
VGS = 4.5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMDF2P01HD

100

td(off)
tf
tr
td(on)

10
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

2
VGS = 0 V
TJ = 25C
1.5

0.5

0
0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4151

MMDF2P01HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power

I D , DRAIN CURRENT (AMPS)

100

10

VGS = 8 V
SINGLE PULSE
TC = 25C

averaged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4152

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P01HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4153

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA


Designer's

Data Sheet

MMDF2P02E

Medium Power Surface Mount Products

TMOS Dual P-Channel


Field Effect Transistors

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
G
additional safety margin against unexpected voltage transients.
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
IDSS Specified at Elevated Temperatures
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

DUAL TMOS MOSFET


2.5 AMPERES
25 VOLTS
RDS(on) = 0.250 OHM

D
CASE 75105, Style 11
SO8

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
GatetoSource Voltage Continuous

Symbol

Value

Unit

VDSS
VGS

25

Vdc

20

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)
Derate above 25C

ID
ID
IDM
PD

2.5
1.7
13

Adc

2.0
16

W
mW/C

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance, Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds

Apk

C
mJ

245
RJA

62.5

C/W

TL

260

DEVICE MARKING
F2P02
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2P02ER2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 4

4154

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Min

Typ

Max

Unit

25

2.2

1.0
10

100

1.0

2.0
3.8

3.0

0.19
0.3

0.25
0.4

gFS

1.0

2.8

Mhos

Ciss

340

475

pF

Coss

220

300

Crss

75

150

td(on)

20

40

tr

40

80

td(off)

53

106

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc

Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
See Fig
Figure
re 11
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Storage Charge

ns

tf

41

82

td(on)

13

26

tr

29

58

td(off)

30

60

tf

28

56

QT

10

15

Q1

1.0

Q2

3.5

Q3

3.0

VSD

1.5

2.0

Vdc

trr

32

64

ns

ta

19

tb

12

QRR

0.035

nC

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4155

MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4
4.5 V
3
4.3 V
2

4.1 V
3.9 V

3.7 V
3.5 V
3.3 V
0

VDS 10 V

TJ = 25C

4.7 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

5V

VGS = 10 7 V

0.4
0.8
1.2
1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

3
100C
2
25C
TJ = 55C
1

0
2.5

ID = 1 A
TJ = 25C

0.4
0.3
0.2
0.1
0
3

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.6
0.5

4.5

Figure 2. Transfer Characteristics


0.6
TJ = 25C
0.5

0.4
VGS = 4.5

0.3

0.2
10 V
0.1
0

0.5

1.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

100
VGS = 10 V
ID = 2 A

VGS = 0 V

1.5
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

3
3.5
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.0

0.5

0
50

4156

25

25

50

75

100

125

150

TJ = 125C
10

100C

12

16

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02E
POWER MOSFET SWITCHING

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
1000

VDS = 0 V

TJ = 25C

Ciss

800
C, CAPACITANCE (pF)

VGS = 0 V

600

Crss

400

Ciss
Coss

200

Crss
0
10

td(on) = RG Ciss In [VGG/(VGG VGSP)]


td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12
QT
9

4
6
8
Qg, TOTAL GATE CHARGE (nC)

0
12

10

2
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25C

TJ = 25C
VGS = 0 V
IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

ID = 2 A
TJ = 25C

Figure 8. GatetoSource and


DraintoSource Voltage versus Total Charge

100

td(off)
tr
tf
td(on)
1

Q3

Q2

Q1

Figure 7. Capacitance Variation

10

12

VGS

VDS

30
5
0
5
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

16

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

During the turnon and turnoff delay times, gate current is


not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Switching behavior is most easily modeled and predicted


by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time Variation


versus Gate Resistance
Motorola TMOS Power MOSFET Transistor Device Data

1.6

1.2

0.8

0.4

0
0.6

0.8
1
1.2
1.4
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.6

Figure 10. Diode Forward Voltage


versus Current
4157

MMDF2P02E
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

10

VGS = 20 V
SINGLE PULSE
TC = 25C

280

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

100 s

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10 ms
1

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4158

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

I pk = 7 A
240
200
160
120
80
40
0

100

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4159

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF2P02HD

Medium Power Surface Mount Products

TMOS P-Channel
Field Effect Transistors

Motorola Preferred Device

DUAL TMOS POWER FET


2.0 AMPERES
20 VOLTS
RDS(on) = 0.160 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

D
CASE 75105, Style 11
SO8
G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 18 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM

20

Vdc

3.3
2.1
20

Adc
Apk

PD
TJ, Tstg
EAS

2.0

Watts

55 to 150

324

mJ

RJA

62.5

C/W

TL

260

DEVICE MARKING
D2P02
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2P02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4160

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

20

25

1.0
10

100

1.0

1.5
4.0

2.0

0.118
0.152

0.160
0.180

gFS

2.0

3.0

mhos

Ciss

420

588

pF

Coss

290

406

Crss

116

232

td(on)

19

38

tr

66

132

td(off)

25

50

tf

37

74

td(on)

11

22

tr

21

42

td(off)

45

90

tf

36

72

QT

15

20

Q1

1.2

Q2

5.0

Q3

4.0

1.5
1.24

2.1

trr

38

ta

17

tb

21

QRR

0.034

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 10 Vdc, ID = 2.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
(VDD = 15 V, IS = 2.0 A,
dIS/dt = 100 A/s)

VSD

ns

nC

Vdc

ns

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4161

MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V 4.5 V

3.9 V

TJ = 25C

3.7 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3.5 V

3.3 V
2
3.1 V
2.9 V

VDS 10 V

0
0

0.2

0.4
0.6 0.8
1
1.2 1.4 1.6 1.8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 55C

0
1.0

1.5

0
4

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.2

3.5

0.20
TJ = 25C
VGS = 4.5 V

0.16

0.12

10 V

0.08

0.04
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

1.6

VGS = 0 V

VGS = 10 V
ID = 2 A

TJ = 125C

1.4
I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)


RDS(on) , DRAINTOSOURCE RESISTANCE
(NORMALIZED)

0.4

3.0

Figure 2. Transfer Characteristics

ID = 1 A
TJ = 25C

2.5

2.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

0.6

25C

100C

2.7 V
2.5 V

1.2

1.0

10
100C

0.8

0.6
50

4162

25

25

50

75

100

125

150

10

15

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage Current


versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

C, CAPACITANCE (pF)

1000

VGS = 0 V

VDS = 0 V

TJ = 25C

Ciss

800
600
Crss

Ciss

400
Coss

200
0
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4163

18
QT

10

15
VGS

12

4 Q1

Q2

6
ID = 2 A
TJ = 25C

2
Q3
0

VDS
4

3
0
16

12

1000
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

MMDF2P02HD

100
td(off)
tf
tr
td(on)

10
1

10

QT, TOTAL GATE CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

2.0

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
1.6

1.2

0.8

0.4

0
0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4164

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

10

VGS = 20 V
SINGLE PULSE
TC = 25C

350

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

ID = 6 A
300
250
200
150
100
50
0

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4165

MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.5776 0.7086

0.0154 F

0.0854 F

0.3074 F

1.7891 F

0.01
0.01
107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4166

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA


Designer's

Data Sheet

MMDF2P03HD

Medium Power Surface Mount Products

TMOS Dual P-Channel


Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

DUAL TMOS
POWER MOSFET
2.0 AMPERES
30 VOLTS
RDS(on) = 0.200 OHM

D
CASE 75105, Style 11
SO8
G

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

S
Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous

Symbol

Value

Unit

VDSS
VDGR
VGS

30

Vdc

30

Vdc

20

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TC = 25C (2)

ID
ID
IDM
PD

3.0
1.9
15

Adc

2.0

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

EAS

324

mJ

RJA

62.5

C/W

TL

260

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

DEVICE MARKING
D2P03
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF2P03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 5

Motorola TMOS Power MOSFET Transistor Device Data

4167

MMDF2P03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

30

27

1.0
10

100

1.0

1.5
4.0

2.0

0.170
0.225

0.200
0.300

gFS

2.0

3.4

mhos

Ciss

397

550

pF

Coss

189

250

Crss

64

126

td(on)

16.25

33

tr

17.5

35

td(off)

62.5

125

tf

194

390

td(on)

9.0

18

tr

10

20

td(off)

81

162

tf

192

384

QT

14.2

19

Q1

1.1

Q2

4.5

Q3

3.5

VSD

1.82
1.36

2.0

Vdc

trr

42.3

ns

ta

15.6

tb

26.7

QRR

0.044

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 2.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 24 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

ns

nC

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

4168

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
4
3.7 V

TJ = 25C

3.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V 4.5 V

3.3 V

3.9 V
2

3.1 V
2.9 V

1
2.7 V

VDS 10 V

2
TJ = 100C
25C
1
55C

2.5 V
0

0.6

0.2

0.4

0.6

0.8

1.2

1.4

1.6

2.5

2.7

2.9

3.1

3.3

0.1

3
4
5
6
7
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

3.5

3.7

0.30
TJ = 25C
0.25
VGS = 4.5 V
0.20
10 V
0.15

0.10

Figure 3. OnResistance versus


GatetoSource Voltage

0.5

2.5
3
1.5
2
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

1000

VGS = 10 V
ID = 2 A

VGS = 0 V

1.4
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.3

Figure 2. Transfer Characteristics

0.2

2.1

Figure 1. OnRegion Characteristics

0.3

1.9

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.4

1.7

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 1 A
TJ = 25C

0.5

0
1.5

1.8

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

1.0

TJ = 125C

100

100C

0.8

0.6
50

25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

10

10
20
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

30

Figure 6. DrainToSource Leakage


Current versus Voltage

4169

MMDF2P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

C, CAPACITANCE (pF)

1000

VDS = 0 V VGS = 0 V

TJ = 25C

Ciss

800
600 Crss
Ciss
400
Coss
200
0
10

Crss
5
VGS

10

15

20

25

30

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4170

Motorola TMOS Power MOSFET Transistor Device Data

24
QT
20

10
VGS
8

16

VDS

6
Q1

12

ID = 2 A
TJ = 25C

Q2

2
Q3
0

10

12

0
16

14

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMDF2P03HD
VDD = 15 V
ID = 2 A
VGS = 10 V
TJ = 25C

100

tf
td(off)

tr
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

1.6

TJ = 25C
VGS = 0 V

1.2

0.8

0.4

0
0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4171

MMDF2P03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

10

VGS = 20 V
SINGLE PULSE
TC = 25C

350

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms

1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

100

ID = 6 A

300
250
200
150
100
50
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

4172

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMDF2P03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4173

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF3N02HD

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistors

Motorola Preferred Device

DUAL TMOS
POWER MOSFET
3.0 AMPERES
20 VOLTS
RDS(on) = 0.090 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

D
CASE 75105, Style 11
SO8
G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

3.8
2.6
19

Adc

2.0

Watts

TJ, Tstg
EAS

55 to 150

405

mJ

RJA

62.5

C/W

TL

260

Apk

DEVICE MARKING
D3N02
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMDF3N02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 4

4174

Motorola TMOS Power MOSFET Transistor Device Data

MMDF3N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

29

1.0
10

100

1.0

1.5
4.0

2.0

0.058
0.074

0.090
0.100

gFS

2.0

3.88

Mhos

Ciss

455

630

pF

Coss

184

250

Crss

45

90

td(on)

11

22

tr

58

116

td(off)

17

35

tf

20

40

td(on)

7.0

21

tr

32

64

td(off)

27

54

tf

21

42

QT

12.5

18

Q1

1.3

Q2

2.8

Q3

2.4

VSD

0.79
0.72

1.3

Vdc

trr

23

ns

ta

18

tb

5.0

QRR

0.025

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc)

Vdc
mV/C
Ohms

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 16 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

ns

nC

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4175

MMDF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
4.5 V
5
3.9 V

TJ = 25C

3.5 V

VDS 10 V

3.3 V

3.7 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

4
3.1 V
3
2.9 V
2
2.7 V

4
TJ = 100C
25C
2
55C

1
2.5 V
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.8

0.4

0.2

5
6
7
8
3
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)
2

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

ID = 1.5 A
TJ = 25C

TJ = 25C

3.4

VGS = 4.5 V

0.07

10 V

0.06

0.05

2
3
4
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

1000
VGS = 0 V

VGS = 10 V
ID = 1.5 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.6

0.08

Figure 3. OnResistance versus


GateToSource Voltage

1.4

2.2

Figure 2. Transfer Characteristics

0.6

1.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

1.4

1.2

TJ = 125C

100

100C
25C

10

0.8

0.6
50

4176

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

4
8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MMDF3N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1400

C, CAPACITANCE (pF)

1200

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

1000
800
600

Crss
Ciss

400
Coss
200
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4177

24
QT

10

20
VGS

16

12

ID = 3 A
TJ = 25C
Q1

Q2

8
4

2
VDS

Q3
0

10

12

0
14

100

t, TIME (ns)

12

v DS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMDF3N02HD
VDD = 10 V
ID = 3 A
VGS = 10 V
tr
TJ = 25C t
d(off)
tf
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

2.5

VGS = 0 V
TJ = 25C

2
1.5
1
0.5
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4178

Motorola TMOS Power MOSFET Transistor Device Data

MMDF3N02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

10

VGS = 20 V
SINGLE PULSE
TC = 25C

450

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms

0.1

0.01
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100

400

ID = 9 A

350
300
250
200
150
100
50
0

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4179

MMDF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4180

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF3N03HD

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

DUAL TMOS
POWER MOSFET
4.1 AMPERES
30 VOLTS
RDS(on) = 0.070 OHM

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

CASE 75105, Style 11


SO8
S

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

30

Vdc

30

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

4.1
3.0
40

Adc

2.0

Watts

TJ, Tstg
EAS

55 to 150

324

mJ

RJA

62.5

C/W

TL

260

Apk

DEVICE MARKING
D3N03

ORDERING INFORMATION
Device

Reel Size

Tape Width

Quantity

MMDF3N03HDR2
13
12 mm embossed tape
2500 units
(1) When mounted on 2 square FR4 board (1 square 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 5

Motorola TMOS Power MOSFET Transistor Device Data

4181

MMDF3N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

30

34.5

1.0
10

100

1.0

1.7

3.0

Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

RDS(on)

Vdc
mV/C

Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)

Ohms

0.06
0.065

0.07
0.075

2.0

3.6

Ciss

450

630

Coss

160

225

Crss

35

70

td(on)

12

24

tr

65

130

td(off)

16

32

tf

19

38

td(on)

16

tr

15

30

td(off)

30

60

tf

23

46

QT

11.5

16

Q1

1.5

Q2

3.5

Q3

2.8

0.82
0.7

1.2

trr

24

ta

17

tb

QRR

0.025

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 3.0 Adc,


VGS = 4
4.5
5 Vdc,
Vdc
RG = 9.1 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 10 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
See Figure
Fig re 12

(IS = 3
3.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s)

Reverse Recovery Storage Charge

VSD

ns

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4182

Motorola TMOS Power MOSFET Transistor Device Data

MMDF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
4.5 V
5
4.3 V
4.1 V
4

3.9 V

VDS 10 V

TJ = 25C
I D , DRAIN CURRENT (AMPS)

3.7 V
3.3 V

3.1 V

2
2.9 V
1
0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

3.5 V

0.2

0.6

0.4

0.8

1.2

1.6

1.4

4
100C
3
25C

1.8

TJ = 55C

3.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

ID = 1.5 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
3

4
5
6
7
8
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.08
TJ = 25C

0.07
VGS = 4.5

0.06
10 V

0.05
0

0.5

1.5

2.5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

2.0
VGS = 10 V
ID = 1.5 A

VGS = 0 V

1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.6

2.7 V
2.5 V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

1.0

TJ = 125C

10

100C

0.5

0
50

25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4183

MMDF3N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.

During the turnon and turnoff delay times, gate current is


not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 7. Reverse Recovery Time (trr)


4184

Motorola TMOS Power MOSFET Transistor Device Data

MMDF3N03HD
SAFE OPERATING AREA

VDS = 0 V VGS = 0 V
Ciss

TJ = 25C

C, CAPACITANCE (pF)

1000
800
600

Crss

Ciss

400
Coss

200

Crss

12

5
5
30
0
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

6
Q3

3.0
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25C

2.5
IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

td(off)
tr
tf
td(on)

10
RG, GATE RESISTANCE (OHMS)

Q2

ID = 3 A
TJ = 25C
2

4
6
8
Qg, TOTAL GATE CHARGE (nC)

10

0
12

Figure 9. GatetoSource and


DraintoSource Voltage versus Total Charge

1000

10

12

Q1

Figure 8. Capacitance Variation

100

18

VGS

VDS

0
10

24
QT

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1200

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

VGS, GATETOSOURCE VOLTAGE (VOLTS)

The Forward Biased Safe Operating Area curves define


the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

100

Figure 10. Resistive Switching Time Variation


versus Gate Resistance

Motorola TMOS Power MOSFET Transistor Device Data

TJ = 25C
VGS = 0 V

2.0
1.5
1.0
0.5
0
0.5

0.6
0.65
0.7
0.75
0.8
0.55
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.85

Figure 11. Diode Forward Voltage


versus Current

4185

MMDF3N03HD
350
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s
1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

0.01
0.1

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided) with one die operating, 10s max.

ID = 9 A

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10

300
250
200
150
100
50
0

100

25

50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4186

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMDF4N01HD

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.

DUAL TMOS
POWER MOSFET
4.0 AMPERES
20 VOLTS
RDS(on) = 0.045 OHM

D
CASE 75105, Style 11
SO8
G

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

20

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

20

Vdc

GatetoSource Voltage Continuous

VGS

8.0

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

5.2
4.1
48

Adc

Total Power Dissipation @ TA = 25C (1)

PD

2.0

Watts

TJ, Tstg

55 to 150

RJA

62.5

C/W

TL

260

Operating and Storage Temperature Range


Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

DEVICE MARKING
D4N01
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device
MMSF4N01HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4187

MMDF4N01HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

2.0

1.0
10

100

0.6

0.8
2.8

1.1

0.035
0.043

0.045
0.055

gFS

3.0

6.0

mhos

Ciss

425

595

pF

Coss

270

378

Crss

115

230

td(on)

13

26

tr

60

120

td(off)

20

40

tf

29

58

td(on)

10

20

tr

42

84

td(off)

24

48

tf

28

56

QT

9.2

13

Q1

1.3

Q2

3.5

Q3

3.0

0.95
0.78

1.1

trr

38

ta

17

tb

22

QRR

0.028

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 12 Vdc, VGS = 0 Vdc)
(VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)

RDS(on)

Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 2.7
2 7 Vdc,
Vdc
RG = 2.3 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 2.3 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 10 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4188

Motorola TMOS Power MOSFET Transistor Device Data

MMDF4N01HD
TYPICAL ELECTRICAL CHARACTERISTICS
8

VDS 10 V

TJ = 25C

2.3 V
2.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 8 V

4.5 V
3.1 V
6 2.7 V

2.1 V

1.9 V
1.7 V

100C

25C
TJ = 55C

1.5 V
1.3 V
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6

1.4

1.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 25C
ID = 2 A
0.06

0.05

0.04

6
2
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

2.2

0.050
TJ = 25C
VGS = 2.7 V

0.045

0.040

4.5 V

0.035

0.030

Figure 3. OnResistance versus


GateToSource Voltage

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

1.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.07

0.03

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

4
6
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

VGS = 0 V

VGS = 4.5 V
ID = 4 A

TJ = 125C
I DSS , LEAKAGE (nA)

1.5

0.5

0
50

25

25

50

75

100

125

150

10

100C

TJ, JUNCTION TEMPERATURE (C)

2
4
8
10
6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

12

4189

MMDF4N01HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

VDS = 0 V

C, CAPACITANCE (pF)

1600

VGS = 0 V

TJ = 25C

Ciss

1200

Crss

800

Ciss
Coss

400

Crss
0

4
VGS

12

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4190

Motorola TMOS Power MOSFET Transistor Device Data

10

QT
4

8
VGS

VDS
3

6
Q1

Q2
ID = 4 A
TJ = 25C

2
Q3

0
10

100
VDD = 6 V
ID = 4 A
VGS = 4.5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMDF4N01HD
tr
tf
td(off)
td(on)

10

1
0.1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

4
VV
GS
GS= =0 0VV
TJTJ= =25C
25C
3

0
0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4191

MMDF4N01HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.

The Forward Biased Safe Operating Area curves define


the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power

I D , DRAIN CURRENT (AMPS)

100

10

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms
10 ms

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided) with one die operating, 10s max.

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4192

Motorola TMOS Power MOSFET Transistor Device Data

MMDF4N01HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0175

0.0710

0.2706

0.0154 F

0.0854 F

0.3074 F

0.5776

0.7086

0.01
0.01
1.7891 F

107.55 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4193

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MMDF4N01Z

Medium Power Surface Mount Products

TMOS Dual N-Channel with


Monolithic Zener ESD
Protected Gate

Motorola Preferred Device

EZFETs are an advanced series of power MOSFETs which


utilize Motorolas High Cell Density TMOS process and contain
monolithic backtoback zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low RDS(on) and
true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important.
Typical applications are dcdc converters, and power manageG
ment in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as
disk drives and tape drives.
Zener Protected Gates Provide Electrostatic Discharge Protection
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided

DUAL TMOS
POWER MOSFET
4.0 AMPERES
20 VOLTS
RDS(on) = 0.045 OHM

CASE 75105, Style 11


SO8
S

Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

4.5
4.0
23

Adc

2.0
16

Watts
mW/C

PD

1.39
11.11

Watts
mW/C

TJ, Tstg

55 to 150

Typ.

Max.

Unit

62.5
90

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating

Symbol

Junction to Ambient, PCB Mount (1)


RJA
RJA
Junction to Ambient, PCB Mount (2)
(1) When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.
Thermal Resistance

DEVICE MARKING
D4N01Z

ORDERING INFORMATION
Device
MMDF4N01ZR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4194

Motorola TMOS Power MOSFET Transistor Device Data

MMDF4N01Z
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

20

15

2.0
10

5.0

0.7

0.83
3.0

1.1

35
45

45
55

5.0

8.5

Ciss

450

630

Coss

160

225

Crss

330

460

td(on)

28

40

tr

128

180

td(off)

194

270

tf

195

270

td(on)

50

70

tr

340

475

td(off)

106

150

tf

197

275

QT

10.5

15

Q1

0.8

Q2

4.4

Q3

3.0

0.84
0.65

1.2

trr

250

ta

88

tb

162

QRR

1.0

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)

(Cpk 2.0) (3)

Forward Transconductance
(VDS = 2.5 Vdc, ID = 2.0 Adc)

VGS(th)

Vdc

RDS(on)

mV/C
m

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 6.0 Vdc, ID = 4.0 Adc,


VGS = 4
4.5
5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 2
2.7
7 Vdc,
Vdc
RG = 6.0 )

Fall Time
Gate Charge
(see fig
figure
re 8)
((VDS = 10 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
(IS = 4
4.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s)
Reverse Recovery Storage Charge

VSD

ns

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4195

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Medium Power Field Effect Transistor


NChannel Enhancement Mode
Silicon Gate TMOS EFETt

MMFT1N10E
Motorola Preferred Device

SOT223 for Surface Mount

This advanced EFET is a TMOS Medium Power MOSFET


designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a
draintosource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
dcdc converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients. The device is
housed in the SOT223 package which is designed for medium
power surface mount applications.

MEDIUM POWER
TMOS FET
1 AMP
100 VOLTS
RDS(on) = 0.25 OHM

2,4
D

4
1

Silicon Gate for Fast Switching Speeds


Low RDS(on) 0.25 max
The SOT223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die
Available in 12 mm Tape and Reel
Use MMFT1N10ET1 to order the 7 inch/1000 unit reel.
Use MMFT1N10ET3 to order the 13 inch/4000 unit reel.

2
3

1
G
S

CASE 318E04, STYLE 3


TO261AA

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Symbol

Rating

Value

Unit

DraintoSource Voltage

VDS

100

GatetoSource Voltage Continuous

VGS

20

Drain Current Continuous


Drain Current Pulsed

ID
IDM

1
4

Adc

PD(1)

0.8
6.4

Watts
mW/C

TJ, Tstg

65 to 150

EAS

168

mJ

RJA

156

C/W

TL

260
10

C
Sec

Total Power Dissipation @ TA = 25C


Derate above 25C
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 60 V, VGS = 10 V, Peak IL= 1 A, L = 0.2 mH, RG = 25 )

Vdc

DEVICE MARKING
1N10

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted)
Maximum Temperature for Soldering Purposes,
Time in Solder Bath

(1) Power rating when mounted on FR4 glass epoxy printed circuit board using recommended footprint.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4196

Motorola TMOS Power MOSFET Transistor Device Data

MMFT1N10E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

100

Vdc

Zero Gate Voltage Drain Current, (VDS = 100 V, VGS = 0)

IDSS

10

Adc

GateBody Leakage Current, (VGS = 20 V, VDS = 0)

IGSS

100

nAdc

Gate Threshold Voltage, (VDS = VGS, ID = 1 mA)

VGS(th)

4.5

Vdc

Static DraintoSource OnResistance, (VGS = 10 V, ID = 0.5 A)

RDS(on)

0.25

Ohms

DraintoSource OnVoltage, (VGS = 10 V, ID = 1 A)

VDS(on)

0.33

Vdc

Forward Transconductance, (VDS = 10 V, ID = 0.5 A)

gFS

2.2

mhos

Ciss

410

Coss

145

Crss

55

td(on)

15

tr

15

td(off)

30

tf

32

Qg

Qgs

1.3

Qgd

3.2

0.8

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage, (VGS = 0, ID = 250 A)

ON CHARACTERISTICS

DYNAMIC CHARACTERISTICS
Input Capacitance

(VDS = 20 V,
VGS = 0,
f = 1 MHz)
MH )

Output Capacitance
Reverse Transfer Capacitance

pF

SWITCHING CHARACTERISTICS
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 25 V, ID = 0.5 A
VGS = 10 V
V, RG = 50 ohms
ohms,
RGS = 25 ohms)

Fall Time
Total Gate Charge
GateSource Charge
GateDrain Charge

(VDS = 80 V, ID = 1 A,
VGS = 10 Vdc)
S Fi
See
Figures 15 and
d 16

ns

nC

SOURCE DRAIN DIODE CHARACTERISTICS(1)


Forward OnVoltage

IS = 1 A, VGS = 0

VSD

Forward TurnOn Time

IS = 1 A, VGS = 0,
dlS/dt = 400 A/s
A/s,
VR = 50 V

ton

Reverse Recovery Time

trr

Vdc

Limited by stray inductance

90

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%

Motorola TMOS Power MOSFET Transistor Device Data

4197

MMFT1N10E
10 V
9V

1.2

7V

8V

TJ = 25C

6V
6

5V

2
VGS = 4 V

VGS(TH), GATE THRESHOLD VOLTAGE


(NORMALIZED)

I D, DRAIN CURRENT (AMPS)

10

0
0

4
6
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VDS = VGS
ID = 1.0 mA

1.1

1.0

0.9

0.8

0.7
50

10

VDS = 10 V
100C

3
25C

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

10

0.4
TJ = 100C

0.3

25C

0.2

55C
0.1

Figure 4. OnResistance versus Drain Current

0.3

0.2

0.1

0
6
8
10
12
14
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance versus


GatetoSource Voltage

4198

VGS = 10 V

Figure 3. Transfer Characteristics

TJ = 25C
ID = 1 A

0.5

ID, DRAIN CURRENT (AMPS)

0.5

0.4

150

VGS, GATETOSOURCE VOLTAGE (VOLTS)

16

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D, DRAIN CURRENT (AMPS)

TJ = 55C

50
100
TJ, JUNCTION TEMP (C)

Figure 2. GateThreshold Voltage Variation


With Temperature
RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. On Region Characteristics

0.5
VGS = 10 V
ID = 1 A

0.4

0.3

0.2

0.1

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 6. OnResistance versus Junction


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMFT1N10E
FORWARD BIASED SAFE OPERATING AREA
10

I D, DRAIN CURRENT (AMPS)

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on an ambient temperature of 25C and a
maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. Motorola
Application Note, AN569, Transient Thermal Resistance
General Data and Its Use provides detailed instructions.

VGS = 20 V
SINGLE PULSE
TA = 25C

20 ms
100 ms
0.1

1s
DC
500 ms

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

SWITCHING SAFE OPERATING AREA


The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turnon and turnoff of the devices for
switching times less than one microsecond.

r(t), EFFECTIVE THERMAL RESISTANCE


(NORMALIZED)

1.0

0.001
0.1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

D = 0.5
0.2

0.1

0.1
0.05

P(pk)

0.02
0.01
0.01

t1
SINGLE PULSE

0.001
1.0E05

1.0E04

1.0E03

t2
DUTY CYCLE, D = t1/t2

1.0E02
t, TIME (s)

1.0E01

RJA(t) = r(t) RJA


RJA = 156C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TA = P(pk) RJA(t)

1.0E+00

1.0E+01

Figure 8. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA)


The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated sourcedrain
current versus reapplied drain voltage when the sourcedrain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
9 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package,
and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward
sourcedrain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in Motorolas test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was attained with dI S /dt of 400 A/s.

Motorola TMOS Power MOSFET Transistor Device Data

4199

MMFT1N10E
15 V
VGS
0
IFM
90%

dlS/dt

IS

trr

10%
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 9. Commutating Waveforms

5
IS , SOURCE CURRENT (AMPS)

RGS

dIS/dt 400 A/s

4.5

DUT

4
3.5

VR

2.5

VDS

20 V

1
VGS

0.5
0

20

40

60

80

100

120

VR = 80% OF RATED VDSS


VdsL = Vf + Li dlS/dt

140

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10. Commutating Safe Operating Area


(CSOA)

Li

IS
+

1.5

IFM

Figure 11. Commutating Safe Operating Area


Test Circuit

BVDSS

L
VDS
IL

IL(t)
VDD

RG

VDD
tP

Figure 12. Unclamped Inductive Switching


Test Circuit

4200

t, (TIME)

Figure 13. Unclamped Inductive Switching


Waveforms

Motorola TMOS Power MOSFET Transistor Device Data

MMFT1N10E
VGS
1400

VDS

Ciss
TJ = 25C
f = 1 MHz

1200
Coss

C, CAPACITANCE (pF)

Crss
1000
800
600

Ciss
400
Coss

200
0

Crss
20

15

10

10

15

20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 14. Capacitance Variation With Voltage

10
VDS = 50 V

VDS = 80 V

4
TJ = 25C
ID = 1 A
VGS = 10 V

Qg, TOTAL GATE CHARGE (nC)

Figure 15. Gate Charge versus GateToSource Voltage

+18 V

47 k
Vin

15 V

VDD
1 mA

10 V

100 k
0.1 F

2N3904
2N3904

100 k
47 k

SAME
DEVICE TYPE
AS DUT

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 16. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

4201

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Medium Power Field Effect Transistor


NChannel Enhancement Mode
Silicon Gate TMOS EFETt

MMFT2N02EL
Motorola Preferred Device

SOT223 for Surface Mount

This advanced EFET is a TMOS Medium Power MOSFET


designed to withstand high energy in the avalanche and commutation modes. This device is also designed with a low threshold
voltage so it is fully enhanced with 5 Volts. This new energy efficient
device also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, dcdc converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
The device is housed in the SOT223 package which is designed
for medium power surface mount applications.

MEDIUM POWER
LOGIC LEVEL TMOS FET
1.6 AMP
20 VOLTS
RDS(on) = 0.15 OHM

2,4
D

4
1

2
3

Silicon Gate for Fast Switching Speeds


Low Drive Requirement to Interface Power Loads to Logic
Level ICs, VGS(th) = 2 Volts Max
Low RDS(on) 0.15 max
The SOT223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die
Available in 12 mm Tape and Reel
Use MMFT2N02ELT1 to order the 7 inch/1000 unit reel.
Use MMFT2N02ELT3 to order the 13 inch/4000 unit reel.

G
S

CASE 318E04, STYLE 3


TO261AA

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating

Symbol

Value

DraintoSource Voltage

VDS

20

GatetoSource Voltage Continuous

VGS

15

Drain Current Continuous


Drain Current Pulsed

ID
IDM

1.6
6.4

Adc

PD(1)

0.8
6.4

Watts
mW/C

TJ, Tstg

65 to 150

EAS

66

mJ

RJA

156

C/W

TL

260
10

C
Sec

Total Power Dissipation @ TA = 25C


Derate above 25C
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 10 V, VGS = 5 V, Peak IL= 2 A, L = 0.2 mH, RG = 25 )

Unit
Vdc

DEVICE MARKING
2N02L

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted)
Maximum Temperature for Soldering Purposes,
Time in Solder Bath

(1) Power rating when mounted on FR4 glass epoxy printed circuit board using recommended footprint.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4202

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2N02EL
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

20

Vdc

Zero Gate Voltage Drain Current, (VDS = 20 V, VGS = 0)

IDSS

10

Adc

GateBody Leakage Current, (VGS = 15 V, VDS = 0)

IGSS

100

nAdc

Gate Threshold Voltage, (VDS = VGS, ID = 1 mA)

VGS(th)

Vdc

Static DraintoSource OnResistance, (VGS = 5 V, ID = 0.8 A)

RDS(on)

0.15

Ohms

DraintoSource OnVoltage, (VGS = 5 V, ID = 1.6 A)

VDS(on)

0.32

Vdc

Forward Transconductance, (VDS = 10 V, ID = 0.8 A)

gFS

2.6

mhos

Ciss

580

Coss

430

Crss

250

td(on)

16

tr

73

td(off)

77

tf

107

Qg

20

Qgs

1.7

Qgd

0.9

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage, (VGS = 0, ID = 250 A)

ON CHARACTERISTICS

DYNAMIC CHARACTERISTICS
Input Capacitance

(VDS = 15 V,
VGS = 0,
f = 1 MHz)
MH )

Output Capacitance
Reverse Transfer Capacitance

pF

SWITCHING CHARACTERISTICS
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 V, ID = 1.6 A
VGS = 5 V
V, RG = 50 ohms
ohms,
RGS = 25 ohms)

Fall Time
Total Gate Charge
GateSource Charge
GateDrain Charge

(VDS = 16 V, ID = 1.6 A,
VGS = 5 Vdc)
S Fi
See
Figures 15 and
d 16

ns

nC

SOURCE DRAIN DIODE CHARACTERISTICS(1)


Forward OnVoltage

IS = 1.6 A, VGS = 0

VSD

Forward TurnOn Time

IS = 1.6 A, VGS = 0,
dlS/dt = 400 A/s
A/s,
VR = 16 V

ton

Reverse Recovery Time

trr

Vdc

Limited by stray inductance

55

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%

Motorola TMOS Power MOSFET Transistor Device Data

4203

MMFT2N02EL

I D, DRAIN CURRENT (AMPS)

10

1.2
5

TJ = 25C

4.5

VGS(TH), GATE THRESHOLD VOLTAGE


(NORMALIZED)

10

3.5

2
VGS = 2.5 V
0

2
3
4
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VDS = VGS
ID = 1 mA
1.1

0.9

0.8

0.7
50

I D, DRAIN CURRENT (AMPS)

TJ = 55C

VDS = 8 V
25C

6
100C
4

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 5 V
0.25
0.2
TJ = 100C

0.15

25C
0.1
55C
0.05
0

0.3

0.2

0.1

3
4
5
6
7
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance versus


GatetoSource Voltage

4204

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 25C
ID = 1.6 A

2
3
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

0.5

150

0.3

Figure 3. Transfer Characteristics

0.4

50
100
TJ, JUNCTION TEMP (C)

Figure 2. GateThreshold Voltage Variation


With Temperature
RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. On Region Characteristics

0.5

0.4

VGS = 5 V
ID = 1.6 A

0.3

0.2

0.1

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 6. OnResistance versus Junction


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2N02EL
FORWARD BIASED SAFE OPERATING AREA
10

I D, DRAIN CURRENT (AMPS)

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on an ambient temperature of 25C and a
maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. Motorola
Application Note, AN569, Transient Thermal Resistance
General Data and Its Use provides detailed instructions.

VGS = 15 V
SINGLE PULSE
TA = 25C

20 ms
100
1s
DC

0.1

r(t), EFFECTIVE THERMAL RESISTANCE


(NORMALIZED)

1.0

500 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

SWITCHING SAFE OPERATING AREA


The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA is
applicable for both turnon and turnoff of the devices for
switching times less than one microsecond.

ms

0.01
0.1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

D = 0.5
0.2

0.1

0.1
0.05

P(pk)

0.02
0.01

0.01

t1
SINGLE PULSE

0.001
1.0E05

1.0E04

1.0E03

RJA(t) = r(t) RJA


RJA = 156C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TA = P(pk) RJA(t)

t2
DUTY CYCLE, D = t1/t2

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 8. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA)


The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated sourcedrain
current versus reapplied drain voltage when the sourcedrain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
9 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package,
and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward
sourcedrain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in Motorolas test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dI S /dt of 400 A/s.

Motorola TMOS Power MOSFET Transistor Device Data

4205

MMFT2N02EL
15 V
VGS
0
IFM

dlS/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

Vf

VdsL
MAX. CSOA
STRESS AREA

Figure 9. Commutating Waveforms

10

RGS

IS , SOURCE CURRENT (AMPS)

DUT

8
dIS/dt 400 A/s

VR
+

IFM

IS

20 V

VGS

Li
VDS

1
0

VR = 80% OF RATED VDSS


VdsL = Vf + Li dlS/dt

10 12 14 16 18 20 22 24 26 28 30

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10. Commutating Safe Operating Area (CSOA)

Figure 11. Commutating Safe Operating Area


Test Circuit

BVDSS

L
VDS
IL

IL(t)
VDD

RG

VDD
tP

Figure 12. Unclamped Inductive Switching


Test Circuit

4206

t, (TIME)

Figure 13. Unclamped Inductive Switching


Waveforms

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2N02EL
VGS
1800

Ciss

1600

Crss

VDS
Coss

TJ = 25C
f = 1 MHz

C, CAPACITANCE (pF)

1400
1200
1000
800
Ciss

600
400

Coss

200

Crss

15
5
0
5
10
15
20
20
10
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 14. Capacitance Variation With Voltage

10
TJ = 25C
VDS = 16 V
ID = 1.6 A

9
8
7
6
5
4
3
2
1
0

10
15
5
Qg, TOTAL GATE CHARGE (nC)

20

Figure 15. Gate Charge versus GateToSource Voltage

VDD

+18 V

47 k
Vin

15 V

1 mA

5V

0.1 F

2N3904
2N3904

100 k
47 k

SAME
DEVICE TYPE
AS DUT

100 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 16. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

4207

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Medium Power Field Effect Transistor


PChannel Enhancement Mode
Silicon Gate TMOS EFETt

MMFT2955E
Motorola Preferred Device

SOT223 for Surface Mount

TMOS MEDIUM POWER FET


1.2 AMP
60 VOLTS
RDS(on) = 0.3 OHM

This advanced EFET is a TMOS medium power MOSFET


designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a
draintosource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients. The device is housed in the
SOT223 package which is designed for medium power surface
mount applications.

4
1

Silicon Gate for Fast Switching Speeds


Low RDS(on) 0.3 max
The SOT223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die
Available in 12 mm Tape and Reel
Use MMFT2955ET1 to order the 7 inch/1000 unit reel.
Use MMFT2955ET3 to order the 13 inch/4000 unit reel.

2
3

G
S

CASE 318E04, STYLE 3


TO261AA

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDS

60

GatetoSource Voltage Continuous

VGS

15

Drain Current Continuous


Drain Current Pulsed

ID
IDM

1.2
4.8

Adc

PD(1)

0.8
6.4

Watts
mW/C

TJ, Tstg

65 to 150

EAS

108

mJ

RJA

156

C/W

TL

260
10

C
Sec

Total Power Dissipation @ TA = 25C


Derate above 25C
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 V, VGS = 10 V, Peak IL= 1.2 A, L = 0.2 mH, RG = 25 )

Vdc

DEVICE MARKING
2955

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted)
Maximum Temperature for Soldering Purposes,
Time in Solder Bath

(1) Power rating when mounted on FR4 glass epoxy printed circuit board using recommended footprint.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4208

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2955E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

60

Vdc

Zero Gate Voltage Drain Current, (VDS = 60 V, VGS = 0)

IDSS

10

Adc

GateBody Leakage Current, (VGS = 15 V, VDS = 0)

IGSS

100

nAdc

Gate Threshold Voltage, (VDS = VGS, ID = 1 mA)

VGS(th)

4.5

Vdc

Static DraintoSource OnResistance, (VGS = 10 V, ID = 0.6 A)

RDS(on)

0.3

Ohms

DraintoSource OnVoltage, (VGS = 10 V, ID = 1.2 A)

VDS(on)

0.48

Vdc

gFS

7.5

mhos

Ciss

460

Coss

210

Crss

84

td(on)

18

tr

29

td(off)

44

tf

32

Qg

18

Qgs

2.8

Qgd

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage, (VGS = 0, ID = 250 A)

ON CHARACTERISTICS

Forward Transconductance, (VDS = 15 V, ID = 0.6 A)


DYNAMIC CHARACTERISTICS
Input Capacitance

(VDS = 20 V,
VGS = 0,
f = 1 MHz)
MH )

Output Capacitance
Reverse Transfer Capacitance

pF

SWITCHING CHARACTERISTICS
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 25 V, ID = 1.6 A
VGS = 10 V
V, RG = 50 ohms
ohms,
RGS = 25 ohms)

Fall Time
Total Gate Charge
GateSource Charge
GateDrain Charge

(VDS = 48 V, ID = 1.2 A,
VGS = 10 Vdc)
S Figures
See
Fi
15 and
d 16

ns

nC

SOURCE DRAIN DIODE CHARACTERISTICS(1)


Forward OnVoltage

IS = 1.2 A, VGS = 0

VSD

Forward TurnOn Time

IS = 1.2 A, VGS = 0,
dlS/dt = 400 A/s
A/s,
VR = 30 V

ton

Reverse Recovery Time

trr

Vdc

Limited by stray inductance

90

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%

Motorola TMOS Power MOSFET Transistor Device Data

4209

10
20 V

8V

10 V

I D, DRAIN CURRENT (AMPS)

15 V

TJ = 25C

7V

6
6V
4
5V
2
VGS = 4 V
0

4
6
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

VGS(th), GATE THRESHOLD VOLTS (NORMALIZED

MMFT2955E
1.2
VDS = VGS
ID = 1 mA

1.1

0.9

0.8

0.7
50

8
25C

55C
I D, DRAIN CURRENT (AMPS)

VDS = 10 V

100C

4
25C

55C

2
100C
55C
0

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.6
VGS = 10 V
0.5
100C
0.4
25C
0.3
55C
0.2
0.1
0

0.5
TJ = 25C
ID = 1.2 A

0.3

0.2

0.1

7
10
13
16
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance versus


GatetoSource Voltage

4210

4
6
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

19

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 3. Transfer Characteristics

0.4

150

Figure 2. GateThreshold Voltage Variation


With Temperature
RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. On Region Characteristics

0
50
100
TJ, JUNCTION TEMPERATURE (C)

0.5

0.4

VGS = 10 V
ID = 1.2 A

0.3

0.2

0.1

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 6. OnResistance versus


Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2955E
FORWARD BIASED SAFE OPERATING AREA
10

ID , DRAIN CURRENT (AMPS)

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a ambient temperature of 25C and a
maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. Motorola
Application Note, AN569, Transient Thermal Resistance
General Data and Its Use provides detailed instructions.

20 ms
100 ms

500 ms
1s
DC

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

SWITCHING SAFE OPERATING AREA


The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turnon and turnoff of the devices for
switching times less than one microsecond.

r(t), EFFECTIVE THERMAL RESISTANCE


(NORMALIZED)

1.0

VGS = 20 V
SINGLE PULSE
TA = 25C

0.01
0.1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

D = 0.5
0.2

0.1

0.1
0.05

P(pk)

0.02
0.01

0.001
1.0E05

0.01

t1
t2

SINGLE PULSE

RJA(t) = r(t) RJA


RJA = 156C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TA = P(pk) RJA(t)

DUTY CYCLE, D = t1/t2


1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 8. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA)


The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated sourcedrain
current versus reapplied drain voltage when the sourcedrain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
9 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package,
and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward
sourcedrain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in Motorolas test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was attained with dI S /dt of 400 A/s.

Motorola TMOS Power MOSFET Transistor Device Data

4211

MMFT2955E
15 V
VGS
0
IFM

dlS/dt

90%
IS

trr

10%
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 9. Commutating Waveforms

RGS

IS , SOURCE CURRENT (AMPS)

dIS/dt 400 A/s

DUT

VR
3

IS

20 V

VGS
0

10

20

30

40

50

60

70

VR = 80% OF RATED VDSS


VdsL = Vf + Li dlS/dt

80

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10. Commutating Safe Operating


Area (CSOA)

Li
VDS

IFM

Figure 11. Commutating Safe Operating Area


Test Circuit

BVDSS

L
VDS
IL

IL(t)
VDD

RG

VDD
tP

Figure 12. Unclamped Inductive Switching


Test Circuit

4212

t, (TIME)

Figure 13. Unclamped Inductive Switching


Waveforms

Motorola TMOS Power MOSFET Transistor Device Data

MMFT2955E
VGS

VDS

1800
Ciss

1600

TJ = 25C
f = 1 MHz

Crss

C, CAPACITANCE (pF)

1400
Coss

1200
1000
800
600

Ciss

400

Coss
Crss

200
0
15

10
5
0
5
10
15
20
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 14. Capacitance Variation with Voltage

10
9
8
7
TJ = 25C
VDS = 48 V
ID = 1.2 A

6
5
4
3
2
1
0

7.5
13
Qg, TOTAL GATE CHARGE (nC)

20

Figure 15. Gate Charge versus GateToSource Voltage

+18 V

47 k
Vin

15 V

VDD
1 mA

0.1 F

2N3904
2N3904

100 k
47 k

SAME
DEVICE TYPE
AS DUT

10 V 100 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 16. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

4213

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MMFT3055V

TMOS V
SOT-223 for Surface Mount
NChannel EnhancementMode Silicon Gate
TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TMOS POWER FET


1.7 AMPERES
60 VOLTS
RDS(on) = 0.130 OHM

TM

D
4
G

1
2
3

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

S
CASE 318E04, Style 3
TO261AA

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Available in 12 mm Tape & Reel
Use MMFT3055VT1 to order the 7 inch/1000 unit reel
Use MMFT3055VT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

20
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.7
1.4
6.0

Adc

Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR4 bd material


Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR4 bd material
Total PD @ TA = 25C mounted on min. Drain pad on FR4 bd material
Derate above 25C

PD

2.0
1.7
0.9
6.3

Watts

mW/C

TJ, Tstg
EAS

55 to 175

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GatetoSource Voltage Nonrepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 )

Apk

mJ
58
C/W

Thermal Resistance
Junction to Ambient on 1 sq. Drain pad on FR4 bd material
Junction to Ambient on 0.70 sq. Drain pad on FR4 bd material
Junction to Ambient on min. Drain pad on FR4 bd material
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

RJA
RJA
RJA
TL

70
88
159
260

This document contains information on a new product. Specifications and information herein are subject to change without notice.
EFET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

4214

Motorola TMOS Power MOSFET Transistor Device Data

MMFT3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

63

Vdc
mV/C

10
100

100

nAdc

2.0

2.8
5.6

4.0

Vdc
mV/C

0.115

0.13

Ohm

0.27
0.25

gFS

1.0

2.7

mhos

Ciss

360

500

pF

Coss

110

150

Crss

25

50

td(on)

8.0

20

tr

9.0

20

td(off)

32

60

tf

18

40

QT

13

20

Q1

2.0

Q2

5.0

Q3

4.0

0.85
0.7

1.6

trr

40

ta

34

tb

6.0

QRR

0.089

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 0.85 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 1.7 Adc)
(VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 1.7 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 1.7 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 48 Vdc, ID = 1.7 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.7 Adc, VGS = 0 Vdc)


(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 1.7 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4215

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MMFT3055VL

TMOS V
SOT-223 for Surface Mount
NChannel EnhancementMode Silicon Gate
TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TMOS POWER FET


1.5 AMPERES
60 VOLTS
RDS(on) = 0.140 OHM

TM

D
4
G

1
2

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 318E04, Style 3


TO261AA

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Available in 12 mm Tape & Reel
Use MMFT3055VLT1 to order the 7 inch/1000 unit reel
Use MMFT3055VLT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.5
1.2
5.0

Adc

Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR4 bd material


Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR4 bd material
Total PD @ TA = 25C mounted on min. Drain pad on FR4 bd material
Derate above 25C

PD

2.0
1.7
0.9
6.3

Watts

mW/C

TJ, Tstg
EAS

55 to 175

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GatetoSource Voltage Nonrepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 )

Apk

mJ
45
C/W

Thermal Resistance
Junction to Ambient on 1 sq. Drain pad on FR4 bd material
Junction to Ambient on 0.70 sq. Drain pad on FR4 bd material
Junction to Ambient on min. Drain pad on FR4 bd material
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

RJA
RJA
RJA
TL

70
88
159
260

This document contains information on a new product. Specifications and information herein are subject to change without notice.
EFET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

4216

Motorola TMOS Power MOSFET Transistor Device Data

MMFT3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

65

Vdc
mV/C

10
100

100

nAdc

1.0

1.5
3.7

2.0

Vdc
mV/C

0.125

0.14

Ohm

0.25
0.24

gFS

1.0

3.5

mhos

Ciss

350

490

pF

Coss

110

150

Crss

29

60

td(on)

9.5

20

tr

18

40

td(off)

35

70

tf

22

40

QT

9.0

10

Q1

1.0

Q2

4.0

Q3

4.0

0.82
0.68

1.2

trr

41

ta

29

tb

12

QRR

0.066

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 0.75 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5.0 Vdc, ID = 1.5 Adc)
(VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 1.5 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 48 Vdc, ID = 1.5 Adc,


VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.5 Adc, VGS = 0 Vdc)


(IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 1.5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4217

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF2P02E

Medium Power Surface Mount Products

TMOS Single P-Channel


Field Effect Transistors

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
2.5 AMPERES
20 VOLTS
RDS(on) = 0.250 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.

CASE 75105, Style 13


SO8

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed
Avalanche Energy Specified
Mounting Information for SO8 Package Provided
IDSS Specified at Elevated Temperature

S
NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (2)
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C(2)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 12 mH, RG = 25 )
Thermal Resistance Junction to Ambient(2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VGS

20

Vdc

20

Vdc

ID
ID
IDM
PD

2.5
1.7
13

Adc

2.5

Watts

TJ, Tstg
EAS

55 to 150

216

mJ

RJA

50

C/W

TL

260

Apk

DEVICE MARKING
S2P02
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF2P02ER2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4218

Motorola TMOS Power MOSFET Transistor Device Data

MMSF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Min

Typ

Max

Unit

20

24.7

1.0
10

100

1.0

2.0
4.7

3.0

0.19
0.3

0.25
0.4

gFS

1.0

2.8

Mhos

Ciss

340

475

pF

Coss

220

300

Crss

75

150

td(on)

20

40

tr

40

80

td(off)

53

106

tf

41

82

td(on)

13

26

tr

29

58

td(off)

30

60

tf

28

56

QT

10

15

Q1

1.1

Q2

3.3

Q3

2.5

VSD

1.5

2.0

Vdc

trr

34

64

ns

ta

18

tb

16

QRR

0.035

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

ns

ns

nC

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4219

MMSF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4

4.1 V
3.9 V

3.7 V
3.5 V
3.3 V
0

0.4

0.8

1.2

1.6

100C
2
25C
TJ = 55C
1

3.5

4.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.6
ID = 1 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
3

0
2.5

10

0.6
TJ = 25C
0.5

0.4
VGS = 4.5

0.3

0.2
10 V
0.1
0

0.5

1.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

100
VGS = 10 V
ID = 2 A

VGS = 0 V

1.5
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

4.3 V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

4.5 V

VDS 10 V

TJ = 25C

4.7 V

RDS(on) , DRAINTOSOURCE RESISTANCE (NORMALIZED)

5V

VGS = 10 7 V

1.0

0.5

0
50

4220

25

25

50

75

100

125

150

TJ = 125C
10

100C

12

16

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MMSF2P02E
POWER MOSFET SWITCHING

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
1000

VDS = 0 V

TJ = 25C

Ciss

800
C, CAPACITANCE (pF)

VGS = 0 V

600

Crss

400

Ciss
Coss

200

Crss
0
10

td(on) = RG Ciss In [VGG/(VGG VGSP)]


td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12

Q3

Q2

Q1

ID = 2 A
TJ = 25C
2

4
6
8
Qg, TOTAL GATE CHARGE (nC)

0
12

10

Figure 8. GatetoSource and


DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


100

2
TJ = 25C
VGS = 0 V
IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25C

td(off)
tr
tf
td(on)
10

12

VGS

VDS

30
5
0
5
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

16
QT

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

During the turnon and turnoff delay times, gate current is


not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Switching behavior is most easily modeled and predicted


by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time Variation


versus Gate Resistance
Motorola TMOS Power MOSFET Transistor Device Data

1.6

1.2

0.8

0.4

0
0.6

0.8
1
1.2
1.4
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.6

Figure 10. Diode Forward Voltage


versus Current
4221

MMSF2P02E
di/dt = 300 A/s

100
I D , DRAIN CURRENT (AMPS)

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

10

VGS = 20 V
SINGLE PULSE
TC = 25C

1 ms
10 ms

dc

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

t, TIME

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 11. Reverse Recovery Time (trr)


250
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06


thick single sided), 10s max.

ID = 6 A

200

150

100

50

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents
below rated continuous ID can safely be assumed to equal
the values indicated.

Although many EFETs can withstand the stress of drain


tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0022

0.0210

0.2587

0.0020 F

0.0207 F

0.3517 F

0.7023

0.6863

0.01
0.01
3.1413 F

108.44 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

4222

Motorola TMOS Power MOSFET Transistor Device Data

MMSF2P02E
di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4223

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF3P02HD

Medium Power Surface Mount Products

TMOS Single P-Channel


Field Effect Transistors

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
3.0 AMPERES
20 VOLTS
RDS(on) = 0.075 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

CASE 75105, Style 13


SO8

G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 14 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

5.6
3.6
30

Adc

2.5

Watts

TJ, Tstg
EAS

55 to 150

567

mJ

RJA

50

C/W

TL

260

Apk

DEVICE MARKING
S3P02
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF3P02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4224

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)(1)
Characteristic

Symbol

Min

Typ

Max

Unit

20

24

1.0
10

100

1.0

1.5
4.0

2.0

0.06
0.08

0.075
0.095

gFS

3.0

7.2

mhos

Ciss

1010

1400

pF

Coss

740

920

Crss

260

490

td(on)

25

50

tr

135

270

td(off)

54

108

tf

84

168

td(on)

16

32

tr

40

80

td(off)

110

220

tf

97

194

QT

33

46

Q1

3.0

Q2

11

Q3

10

1.35
0.96

1.75

trr

76

ta

32

tb

44

QRR

0.133

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 16 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4225

MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
6
5

3.3 V

VDS 10 V

TJ = 25C

3.7 V

4.5 V

3.9 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3.5 V

VGS = 10 V

3.1 V

4
3

2.9 V

2
2.7 V

5
4
3
TJ = 100C

25C

1
2.5 V
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.6

2.4

2.8

3.2

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

ID = 1.5 A
TJ = 25C
0.4

0.2

0
1

10

3.4

0.09
TJ = 25C
0.08
VGS = 4.5 V
0.07

10 V

0.06

0.05
0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

1.20

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

1.8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.6

0
1.6

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

55C

VGS = 0 V

VGS = 10 V
ID = 3.0 A
I DSS , LEAKAGE (nA)

1.10

1.00

0.90

0.80
50

4226

25

50

75

100

125

150

TJ = 125C
100

10

12

16

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500

C, CAPACITANCE (pF)

3000
2500

VDS = 0 V

TJ = 25C

VGS = 0 V

Ciss

2000
1500

Crss

Ciss

1000

Coss

500
0
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4227

12
10

VDD = 10 V
ID = 3 A
VGS = 10 V
TJ = 25C
td(off)

16

6
Q1

12

ID = 3 A
TJ = 25C

Q2

4
2

4
VDS

Q3

0
0

12

16

20

24

28

32

t, TIME (ns)

20
VGS

1000

24
QT

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF3P02HD

100
tf
tr
td(on)
10
1

36

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
3

I S , SOURCE CURRENT (AMPS)

2.5

VGS = 0 V
TJ = 25C

2
1.5
1
0.5
0
0.3 0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4228

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
600

10

VGS = 20 V
SINGLE PULSE
TC = 25C

100 s
1 ms
10 ms

0.1

0.01
0.1

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

450

300

150

0
100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

ID = 9 A

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4229

MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4230

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MMSF3P02Z

Medium Power Surface Mount Products

TMOS Single P-Channel with


Monolithic Zener ESD
Protected Gate
EZFETs are an advanced series of power MOSFETs which utilize
Motorolas High Cell Density TMOS process and contain monolithic
backtoback zener diodes. These zener diodes provide protection
against ESD and unexpected transients. These miniature surface
mount MOSFETs feature ultra low RDS(on) amd true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a very low reverse recovery time. EZFET devices are designed
for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dcdc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives.

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
3.0 AMPERES
20 VOLTS
RDS(on) = 0.060 OHM

CASE 75105, Style 12


SO8

Zener Protected Gates Provide Electrostatic Discharge Protection


Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Designed to withstand 200V Machine Model and 2000V Human Body Model
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) *

S
Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

15

Vdc

6.5
3.0
52

Adc

2.5
20

Watts
mW/C

PD

1.6
12

Watts
mW/C

TJ, Tstg
EAS

55 to 150

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9 Apk, L = 14 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Junction to Ambient (2)

Apk

C
mJ

567
RJA

50
80

C/W

* Negative sign for PChannel omitted for clarity.


(1) When mounted on 1 inch square FR4 or G10 board (VGS = 10 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
S3P02Z

ORDERING INFORMATION
Device
MMSF3P02ZR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4231

MMSF3P02Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

23

0.05
0.2

2.0
10

0.85

5.0

1.0

1.8
3.7

3.0

45
65

60
80

gFS

4.0

5.6

Mhos

Ciss

1100

2200

pF

Coss

720

1440

Crss

320

640

td(on)

90

180

tr

350

700

td(off)

810

1620

tf

1030

2060

td(on)

230

460

tr

1300

2600

td(off)

510

1020

tf

1040

2080

QT

39

55

Q1

2.7

Q2

14.3

Q3

10.2

1.2
0.76

1.6

trr

677

ta

256

tb

420

QRR

5.0

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc)

(1) (3)

(1) (3)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc, RG = 6.0 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 10 Vdc, ID = 3.0 Adc,


VGS = 4.5 Vdc, RG = 6.0 ) (1)

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc) (1)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 3.0 Adc, VGS = 0 Vdc) (1)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
(IS = 3
3.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

ns

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4232

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P02Z
TYPICAL ELECTRICAL CHARACTERISTICS
6

VGS = 10 V
4.5 V

3.8 V
3.1 V

VDS 10 V

TJ = 25C

3.3 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3
2.9 V
2
2.7 V

5
4
3
TJ = 55C

25C
1

100C

2.4 V
0

0.5

1.5

0
1.5

2.5

3.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.4
ID = 1.5 A
TJ = 25C
0.3

0.2

0.1

0
0

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.08
TJ = 25C
VGS = 4.5
0.06
10 V
0.04

0.02

0
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000
VGS = 0 V

VGS = 10 V
ID = 1.5 A
1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.0

TJ = 125C

100

100C
10

0.5

0
50

1
25

25

50

75

100

125

150

10

20

15

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4233

MMSF3P02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2500

TJ = 25C
VGS = 0 V

C, CAPACITANCE (pF)

2000

1500
Ciss
1000

Coss

500

Crss

10

15

20

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4234

Motorola TMOS Power MOSFET Transistor Device Data

16
QT
12

9
VDS

VGS

8
Q1

Q2

4
Q3

ID = 3 A
TJ = 25C
10

VDD = 10 V
ID = 3 A
VGS = 10 V
TJ = 25C
tf
td(off)

1000

tr
td(on)

100

0
40

30

20

10000

t, TIME (ns)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF3P02Z

10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
3

VGS = 0 V
TJ = 25C

2.5
I S , SOURCE CURRENT (AMPS)

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

2
1.5
1
0.5
0

0.4

0.6

0.8

1.0

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4235

MMSF3P02Z
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

600

VGS = 15 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
1 ms
10 ms
1

0.1
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

dc
10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4236

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

ID = 9 A

400

200

0
100

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P02Z
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4237

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF3P03HD

Medium Power Surface Mount Products

TMOS P-Channel
Field Effect Transistors

Motorola Preferred Device

SINGLE TMOS POWER FET


3.0 AMPERES
30 VOLTS
RDS(on) = 0.1 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

D
CASE 75105, Style 13
SO8
G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)
Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)

NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Symbol

Value

Unit

VDSS
VDGR

30

Vdc

30

Vdc

VGS
ID
ID
IDM

20

Vdc

4.6
3.0
50

Adc

PD

2.5

Watts

Operating and Storage Temperature Range

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 9.0 Apk, L = 14 mH, RG = 25 )
Thermal Resistance Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk
C

EAS

567

mJ

RJA

50

C/W

TL

260

DEVICE MARKING
S3P03
(1) Negative signs for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF3P03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4238

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

30

30

1.0
10

5.0

100

1.0

1.5
3.9

2.0

0.80
0.90

0.100
0.110

gFS

3.0

5.0

mhos

Ciss

1015

1420

pF

Coss

470

660

Crss

135

190

td(on)

26

52

tr

102

204

td(off)

67

134

tf

69

138

td(on)

14

28

tr

32

64

td(off)

104

208

tf

66

132

QT

32.4

45

Q1

2.7

Q2

9.0

Q3

6.9

1.3
0.85

2.0

trr

31

ta

22

tb

9.0

QRR

0.034

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

RDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 15 Vdc, ID = 3.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 15 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
((IS = 3.0 Adc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4239

MMSF3P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6

6
TJ = 25C

4.5 V

VDS 10 V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V
3.1 V
3.8 V
4

2.9 V
3
2

2.7 V

5
4
3
TJ = 100C

25C
1

1
2.4 V
0

55C

1.2
0.4
0.8
1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 1.5 A
0.5
0.4
0.3
0.2
0.1
0
2

10

0.095
TJ = 25C
0.09
VGS = 4.5 V

0.085

0.08

10 V

0.075

0.07
0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

3.0
2.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.6

3.2

Figure 2. Transfer Characteristics

1000
VGS = 0 V

VGS = 4.5 V
ID = 1.5 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

3
2.2
2.4
2.6
2.8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

2.0
1.5
1.0

100

100C

10

0.5
0
50

4240

25

25

50

75

100

125

150

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500
VDS = 0 V

TJ = 25C

VGS = 0 V

3000
C, CAPACITANCE (pF)

Ciss
2500
2000
1500

Crss

Ciss

1000
Coss
500
0
10

Crss
5
5
0
VGS
VDS

10

15

20

25

30

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4241

24
QT

10

20
VGS

VDS

16

12

4 Q1
2
0

ID = 3 A
TJ = 25C

Q2

8
4

Q3

10

15

20

25

30

0
35

1000
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF3P03HD

td(off)

100

tf
tr
td(on)
10
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
3

I S , SOURCE CURRENT (AMPS)

2.5

VGS = 0 V
TJ = 25C

2
1.5
1
0.5
0
0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4242

Motorola TMOS Power MOSFET Transistor Device Data

MMSF3P03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
600

10

VGS = 20 V
SINGLE PULSE
TC = 25C

1 ms

0.01
0.1

10 s
100 s

10 ms

0.1

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

500
400
300
200
100
0

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

ID = 9 A

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4243

MMSF3P03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4244

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF4P01HD

Medium Power Surface Mount Products

TMOS P-Channel
Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.

SINGLE TMOS POWER FET


4.0 AMPERES
12 VOLTS
RDS(on) = 0.08 OHM

CASE 75105, Style 13


SO8

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided

S
NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)(1)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

12

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

12

Vdc

GatetoSource Voltage Continuous

VGS

8.0

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (2)

ID
ID
IDM

5.1
3.3
26

Adc

PD

2.5

Watts

Operating and Storage Temperature Range

55 to 150

Thermal Resistance Junction to Ambient (2)


Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk
C

RJA

50

C/W

TL

260

DEVICE MARKING
S4P01
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF4P01HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4245

MMSF4P01HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

12

22

1.0
10

100

0.7

0.95
2.7

1.1

0.073
0.08

0.08
0.09

gFS

3.0

7.0

mhos

Ciss

1270

1700

pF

Coss

935

1300

Crss

420

600

td(on)

25

35

tr

250

350

td(off)

58

80

tf

106

150

td(on)

17

25

tr

71

100

td(off)

95

140

tf

106

150

QT

24

34

Q1

2.4

Q2

11.4

Q3

8.4

1.3
1.1

1.8

trr

134

ta

66

tb

68

QRR

0.33

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 12 Vdc, VGS = 0 Vdc)
(VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)

RDS(on)

Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 6.0 Vdc, ID = 4.0 Adc,


VGS = 2.7
2 7 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
Gate Charge
((VDS = 10 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(2)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Negative sign for PChannel device omitted for clarity.


(2) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
(3) Switching characteristics are independent of operating junction temperature.

4246

Motorola TMOS Power MOSFET Transistor Device Data

MMSF4P01HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 8 V
4.5 V
3.1 V

2.5 V

2.3 V

2.7 V

VDS 10 V

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

2.1 V

4
1.9 V
2
1.7 V

4
TJ = 100C

25C

2
55C

1.5 V
0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.2

1.4

1.6

1.8

2.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.16
TJ = 25C
ID = 2 A
0.12

0.08

0.04

0
2

2.4

0.1
TJ = 25C
0.09
VGS = 2.7 V
0.08

4.5 V

0.07

0.06
0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

1.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS = 0 V
VGS = 4.5 V
ID = 4 A

TJ = 125C
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100

100C

0.5

0
50

25

25

50

75

100

125

150

10

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

12

4247

MMSF4P01HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

4800
4000
C, CAPACITANCE (pF)

VGS = 0 V

VDS = 0 V

TJ = 25C

Ciss

3200
2400
Crss
1600

Ciss

800

Coss

Crss
8

0
VGS

12

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4248

Motorola TMOS Power MOSFET Transistor Device Data

8
VGS

VDS
3

6
Q1

Q2

4
ID = 4 A
TJ = 25C

Q3

10

15

0
25

20

VDD = 6 V
ID = 4 A
VGS = 4.5 V
TJ = 25C
t, TIME (ns)

1000

10
QT

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF4P01HD

tf
100

td(off)

tr

td(on)
10

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

4
VGS = 0 V
TJ = 25C
3

0
0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4249

MMSF4P01HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.

The Forward Biased Safe Operating Area curves define


the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power

I D , DRAIN CURRENT (AMPS)

100

10

VGS = 10 V
SINGLE PULSE
TC = 25C

1 ms
10 ms

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4250

Motorola TMOS Power MOSFET Transistor Device Data

MMSF4P01HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4251

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MMSF4P01Z

Medium Power Surface Mount Products

TMOS Single P-Channel with


Monolithic Zener ESD
Protected Gate
EZFETs are an advanced series of power MOSFETs which utilize
Motorolas High Cell Density TMOS process and contain monolithic
backtoback zener diodes. These zener diodes provide protection
against ESD and unexpected transients. These miniature surface
mount MOSFETs feature ultra low RDS(on) amd true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a very low reverse recovery time. EZFET devices are designed
for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dcdc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives.

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
4.0 AMPERES
20 VOLTS
RDS(on) = 0.070 OHM

CASE 75105, Style 12


SO8
G

Zener Protected Gates Provide Electrostatic Discharge Protection


Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Designed to withstand 200V Machine Model and 2000V Human Body Model
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) *

S
Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

5.7
4.0
46

Adc

2.5
20

Watts
mW/C

PD

1.6
12

Watts
mW/C

TJ, Tstg
RJA

55 to 150

50
80

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range
Thermal Resistance Junction to Ambient (1)
Junction to Ambient (2)

Apk

* Negative sign for PChannel omitted for clarity.


(1) When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
S4P01Z

ORDERING INFORMATION
Device
MMSF4P01ZR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4252

Motorola TMOS Power MOSFET Transistor Device Data

MMSF4P01Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

16.6

0.05
0.55

2.0
10

0.15

5.0

0.7

0.85
2.5

1.1

50
70

70
90

gFS

4.0

7.5

Mhos

Ciss

270

540

pF

Coss

825

1650

Crss

100

200

td(on)

150

300

tr

800

1600

td(off)

1420

2840

tf

1830

3660

td(on)

260

520

tr

1950

3900

td(off)

600

1200

tf

1390

2780

QT

24

34

Q1

3.0

Q2

11

Q3

8.0

1.1
0.75

1.8

trr

373

ta

750

tb

1120

QRR

9.0

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 12 Vdc, VGS = 0 Vdc)
(VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 3.0 Vdc, ID = 2.0 Adc)

(1) (3)

(1) (3)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 4.5 Vdc, RG = 6.0 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 6.0 Vdc, ID = 4.0 Adc,


VGS = 2.7 Vdc, RG = 6.0 ) (1)

Fall Time
Gate Charge
((VDS = 10 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc) (1)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 4.0 Adc, VGS = 0 Vdc) (1)
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
(IS = 4
4.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

ns

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4253

MMSF4P01Z
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 8 V
4.5 V
3.1 V

2.7 V
2.4 V

VDS 10 V

TJ = 25C
2V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

1.8 V

1.6 V

TJ = 55C

25C
100C

0.4

1.2

0.6

1.6

0.4

1.2

1.6

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.4
ID = 2 A
TJ = 25C
0.3

0.2

0.1

0
0

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.09
TJ = 25C
VGS = 2.7 V
0.06

4.5 V

0.03

0
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000
VGS = 0 V

VGS = 4.5 V
ID = 2 A
1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

0.8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.0

TJ = 125C

100
100C

10

0.5

0
50

4254

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

12

Motorola TMOS Power MOSFET Transistor Device Data

MMSF4P01Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500

TJ = 25C
VGS = 0 V

C, CAPACITANCE (pF)

2800

2100
Ciss

1400

Coss

700

Crss

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4255

10

QT

VDS
Q2

Q1

VGS

1
Q3
0

ID = 4 A
TJ = 25C
5

10
15
Qg, TOTAL GATE CHARGE (nC)

20

25

10000

VDD = 6 V
ID = 4 A
VGS = 4.5 V
tf
TJ = 25C
td(off)

1000

tr

t, TIME (ns)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF4P01Z

td(on)
100

10

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

4
VGS = 0 V
TJ = 25C
3

0
0.1

0.3

0.5

0.7

0.9

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4256

Motorola TMOS Power MOSFET Transistor Device Data

MMSF4P01Z
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature. Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

I D , DRAIN CURRENT (AMPS)

100
VGS = 8 V
SINGLE PULSE
TC = 25C
100 s

10

1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

dc
10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

4257

MMSF4P01Z
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4258

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF5N02HD

Medium Power Surface Mount Products

TMOS Single N-Channel


Field Effect Transistors

Motorola Preferred Device

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

SINGLE TMOS
POWER MOSFET
5.0 AMPERES
20 VOLTS
RDS(on) = 0.025 OHM

D
CASE 75105, Style 13
SO8
G

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

S
NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C
Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 6.0 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

8.2
5.6
41

Adc

2.5

Watts

TJ, Tstg
EAS

55 to 150

675

mJ

RJA

50

C/W

TL

260

Apk

DEVICE MARKING
S5N02
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF5N02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 4

Motorola TMOS Power MOSFET Transistor Device Data

4259

MMSF5N02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

41

0.02

1.0
10

100

1.0

1.5
4.0

2.0

0.0185
0.0219

0.025
0.040

gFS

3.0

12

Mhos

Ciss

1130

1582

pF

Coss

464

650

Crss

117

235

td(on)

15

30

tr

93

185

td(off)

35

70

tf

40

80

td(on)

9.0

tr

53

td(off)

56

tf

39

QT

30.3

43

Q1

3.0

Q2

7.5

Q3

6.0

0.82
0.69

1.0

trr

32

ta

24

tb

8.0

QRR

0.045

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 5.0 Adc)
(VGS = 4.5 Vdc, ID = 2.5 Adc)

RDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc)

Vdc
mV/C
Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 5.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.0 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 16 Vdc, ID = 5.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 5.0 Adc, VGS = 0 Vdc)
(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 5.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4260

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V

10

TJ = 25C
3.1 V

4.5 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

10

3.8 V
6

VDS 10 V

4
TJ = 100C
25C

2
55C

2.4 V
0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.9

2.1

2.3

2.5

2.7

2.9

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.16

0.12

0.08

0.04

0
1

10

3.1

3.3

0.023
TJ = 25C

VGS = 4.5 V

0.021

0.019
10 V

0.017
0

10

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

1000
VGS = 0 V

VGS = 10 V
ID = 2.5 A

TJ = 125C
I DSS , LEAKAGE (nA)

1.4

1.7

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 2.5 A

0
1.5

1.8

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.2

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

100
100C
25C

10

0.8

0.6
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

8
12
4
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

20

4261

MMSF5N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500

VDS = 0 V

VGS = 0 V

TJ = 25C

3000
C, CAPACITANCE (pF)

Ciss
2500
2000
1500

Crss

Ciss

1000
Coss
500
0
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4262

Motorola TMOS Power MOSFET Transistor Device Data

12

24
QT

10

1000
VDD = 10 V
ID = 5 A
VGS = 10 V
TJ = 25C

16

6
Q1

12

ID = 5 A
TJ = 25C

Q2

4
VDS

Q3

0
0

12

16

20

24

t, TIME (ns)

20
VGS

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF5N02HD

100

tf
tr

td(on)
10

1
1

32

28

td(off)

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4263

MMSF5N02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
675

10

VGS = 10 V
SINGLE PULSE
TC = 25C

100 s
1 ms
10 ms

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4264

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

475
375
275
175
75
25

100

ID = 15 A

575

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4265

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF5N03HD

Medium Power Surface Mount Products

TMOS Single N-Channel


Field Effect Transistors

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
5.0 AMPERES
30 VOLTS
RDS(on) = 0.040 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

D
CASE 75105, Style 13
SO8
G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous

Symbol

Value

Unit

VDSS
VDGR
VGS

30

Vdc

30

Vdc

20

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)

ID
ID
IDM
PD

6.5
4.4
33

Adc

2.5

Watts

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 150

450

mJ

RJA

50

C/W

TL

260

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

DEVICE MARKING
S5N03
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF5N03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4

4266

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

30

34

1.0
10

100

1.0

2.0
5.0

3.0

0.033
0.04

0.040
0.050

gFS

3.0

8.0

Mhos

Ciss

1207

1680

pF

Coss

354

490

Crss

62

120

td(on)

20

40

tr

108

216

td(off)

36

72

tf

37

74

td(on)

11

22

tr

36

72

td(off)

68

136

tf

38

76

QT

15.2

21

Q1

3.4

Q2

6.6

Q3

5.6

0.88
0.77

1.3

trr

33

ta

21

tb

12

QRR

0.037

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 5.0 Adc)
(VGS = 4.5 Vdc, ID = 2.5 Adc)

RDS(on)

Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc)

Vdc
mV/C
Ohms

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 5.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 9.1 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 24 Vdc, ID = 5.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 5 Adc, VGS = 0 Vdc)
(IS = 5 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 5.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4267

MMSF5N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10

10
VDS 10 V

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V
8
4.5 V
6
3.8 V
4

3.1 V

4
TJ = 100C
25C

2
55C

2.4 V
0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

3.2

3.4

3.6

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.16

0.12

0.08

0.04

0
1

10

3.8

0.0425
TJ = 25C
0.04
VGS = 4.5 V
0.0375

0.035
10 V
0.0325

0.03
0

10

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

1.6

VGS = 0 V

VGS = 10 V
ID = 5 A

TJ = 125C
I DSS , LEAKAGE (nA)

1.4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 2.5 A

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.2

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

100

100C

10

0.8
25C
0.6
50

4268

25

25

50

75

100

125

150

10

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500
VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

3000
2500

Ciss

2000
1500

Ciss

Crss

1000
Coss

500
Crss
0
10

0
VGS

5
10
VDS

15

20

25

30

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4269

12

1000

25
QT

10

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDD = 15 V
ID = 5 A
VGS = 4.5 V
TJ = 25C

20
VGS

Q1

Q2

t, TIME (ns)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

MMSF5N03HD

15
6

ID = 5 A
TJ = 25C

10

4
5

2
Q3
0

VDS
4

10

12

0
14

100

tr
td(off)
tf
td(on)

10
1

16

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4270

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

10

450
VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
100 s
1 ms
10 ms
1

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

ID = 15 A

300

150

0
100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4271

MMSF5N03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4272

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MMSF5N03Z

Medium Power Surface Mount Products

TMOS Single N-Channel with


Monolithic Zener ESD
Protected Gate
EZFETs are an advanced series of power MOSFETs which utilize
Motorolas High Cell Density TMOS process and contain monolithic
backtoback zener diodes. These zener diodes provide protection
against ESD and unexpected transients. These miniature surface
mount MOSFETs feature ultra low RDS(on) amd true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a very low reverse recovery time. EZFET devices are designed
for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dcdc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives.

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
5.0 AMPERES
30 VOLTS
RDS(on) = 0.030 OHM

CASE 75105, Style 12


SO8

Zener Protected Gates Provide Electrostatic Discharge Protection


Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Designed to withstand 200V Machine Model and 2000V Human Body Model
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

S
Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

30

Vdc

30

Vdc

VGS
ID
ID
IDM
PD

15

Vdc

7.5
5.6
60

Adc

2.5
20

Watts
mW/C

PD

1.6
12

Watts
mW/C

TJ, Tstg
EAS

55 to 150

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Junction to Ambient (2)

Apk

C
mJ

450
RJA

50
80

C/W

(1) When mounted on 1 inch square FR4 or G10 board (VGS = 10 V, @ Steady State)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
S5N03Z

ORDERING INFORMATION
Device
MMSF5N03ZR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4273

MMSF5N03Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

30

35

0.03
0.15

2.0
10

1.3

5.0

1.0

2.0
5.5

3.0

22
30

30
40

gFS

4.0

9.5

Mhos

Ciss

750

1500

pF

Coss

340

680

Crss

45

90

td(on)

40

80

tr

90

180

td(off)

470

940

tf

170

340

td(on)

120

240

tr

350

700

td(off)

430

860

tf

140

280

QT

34

48

Q1

3.5

Q2

9.5

Q3

6.5

0.83
0.67

1.6

trr

110

ta

22

tb

90

QRR

0.17

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 5.0 Adc)
(VGS = 4.5 Vdc, ID = 2.5 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 3.0 Vdc, ID = 2.5 Adc)

(1) (3)

(1) (3)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 15 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc, RG = 6 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 15 Vdc, ID = 5.0 Adc,


VGS = 4.5 Vdc, RG = 6 ) (1)

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 5.0 Adc,
VGS = 10 Vdc) (1)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 5.0 Adc, VGS = 0 Vdc) (1)
(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
(IS = 5
5.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

ns

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4274

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N03Z
TYPICAL ELECTRICAL CHARACTERISTICS
10

TJ = 25C

VDS 10 V

3.5 V
VGS = 10 V
4.5 V
3.8 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

10

3.3 V

4
3.1 V
2

4
100C
25C

2.7 V
0

0.4

0.8

TJ = 55C
1.6

1.2

1.8

2.6

3.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

ID = 2.5 A
TJ = 25C

0.08

0.06

0.04

0.02

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

3.8

0.05
TJ = 25C
0.04
VGS = 4.5

0.03

10 V
0.02

0.01

0
0

10

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000
VGS = 0 V

VGS = 10 V
ID = 2.5 A
1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

2.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.0

TJ = 125C

100

100C
10

0.5

0
50

25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4275

MMSF5N03Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2500

TJ = 25C
VGS = 0 V

C, CAPACITANCE (pF)

2000

Ciss

1500

1000
Coss

500

Crss
0

12

18

24

30

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4276

Motorola TMOS Power MOSFET Transistor Device Data

24
QT
20

10
8

16
VDS

VGS
12

6
Q1

Q2

8
ID = 5 A
TJ = 25C

Q3
0

10

15

20

25

1000

t, TIME (ns)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF5N03Z
td(off)

tf
100

tr
td(on)

0
35

30

VDD = 15 V
ID = 5 A
VGS = 10 V
TJ = 25C

10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
5

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4277

MMSF5N03Z
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

500

VGS = 15 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms

0.1

0.01

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

ID = 15 A
400

300

200

100

0
10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4278

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MMSF5N03Z
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4279

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MMSF7N03HD

Medium Power Surface Mount Products

TMOS Single N-Channel


Field Effect Transistors

Motorola Preferred Device

SINGLE TMOS
POWER MOSFET
8.0 AMPERES
30 VOLTS
RDS(on) = 0.028 OHM

MiniMOS devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

D
CASE 75105, Style 13
SO8
G
S

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO8 Package Provided

NC

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous

Symbol

Value

Unit

VDSS
VDGR
VGS

30

Vdc

30

Vdc

20

Vdc

Drain Current Continuous @ TA = 25C


Drain Current Continuous @ TA = 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ TA = 25C (1)

ID
ID
IDM
PD

8.2
5.6
50

Adc

2.5

Watts

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 150

450

mJ

RJA

50

C/W

TL

260

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 )
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

DEVICE MARKING
S7N03
(1) Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

ORDERING INFORMATION
Device
MMSF7N03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

2500 units

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2

4280

Motorola TMOS Power MOSFET Transistor Device Data

MMSF7N03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

30

41

0.02

1.0
10

100

1.0

1.5
4.0

2.0

0.023
0.029

0.028
0.040

gFS

3.0

12

Mhos

Ciss

931

1190

pF

Coss

371

490

Crss

89

120

td(on)

15

30

tr

93

185

td(off)

35

70

tf

40

80

td(on)

9.0

tr

53

td(off)

56

tf

39

QT

30

43

Q1

3.0

Q2

7.5

Q3

6.0

0.82
0.69

1.0

trr

32

ta

24

tb

8.0

QRR

0.045

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 7.0 Adc)
(VGS = 4.5 Vdc, ID = 3.5 Adc)

RDS(on)

Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc)

Vdc
mV/C
Ohms

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 5.0 Adc,


VGS = 4.5
4 5 Vdc,
Vdc
RG = 9.1 )

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 10 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
S Fi
See
Figure 8
((VDS = 16 Vdc, ID = 5.0 Adc,
VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage(1)
(IS = 7.0 Adc, VGS = 0 Vdc)
(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C)
Reverse Recovery Time
S Figure
See
Fi
15
((IS = 7.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

ns

nC

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4281

MMSF7N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
7

VGS = 10 V
4.5 V
3.9 V
3.7 V

6
5

2.9 V

3.5 V
3.3 V
3.1 V

4
3

VDS 10 V
TJ = 25C

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

2.7 V

2
2.5 V

6
5
4

TJ = 100C

3
2

25C
1
55C

0.25

0.5

0.75

1.25

1.5

1.75

Figure 2. Transfer Characteristics

0.5
0.4
0.3
0.2
0.1
0
2

10

3.5

Figure 1. OnRegion Characteristics

ID = 3.5 A
TJ = 25C

0.05
TJ = 25C
0.04

VGS = 4.5 V

0.03

10 V
0.02

0.01
0

10

15

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

VGS = 0 V

VGS = 10 V
ID = 3.5 A

TJ = 125C

1000

1.5

0.5

4282

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.6

0
50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0
1.5

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100
100C
10
25C
1

25

25

50

75

100

125

150

0.1

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MMSF7N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

4000

C, CAPACITANCE (pF)

3500
3000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

2500
2000 Crss
1500
Ciss

1000
Coss
500
0
10

Crss
5

0
VGS

5
10
VDS

15

20

25

30

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4283

12

24
QT

10

1000
VDD = 10 V
ID = 5 A
VGS = 10 V
TJ = 25C

16

6
Q1

12

ID = 5 A
TJ = 25C

Q2

4
VDS

Q3

0
0

12

16

20

24

28

t, TIME (ns)

20
VGS

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MMSF7N03HD

100

td(off)
tf
tr

td(on)
10

1
1

32

10

QT, TOTAL CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

6
5
4
3
2
1
0
0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4284

Motorola TMOS Power MOSFET Transistor Device Data

MMSF7N03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
480

10

VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10s
100 s
1 ms
10 ms
1

0.1

0.01
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06
thick single sided), 10s max.

10

280
240
200
160
120
80
40
0

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

ID = 9 A
I pk = 9 A
L = 4 mH

440
400
360
320

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4285

MMSF7N03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

10

0.1

D = 0.5
0.2
0.1
0.05
0.02

Normalized to ja at 10s.
Chip

0.0163

0.0652

0.1988

0.0307 F

0.1668 F

0.5541 F

0.6411

0.9502

0.01
0.01
1.9437 F

72.416 F

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Ambient
1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4286

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Power Products Division

Advance Information

MPIC2111

HALF-BRIDGE DRIVER
The MPIC2111 is a high voltage, high speed, power MOSFET and IGBT driver
with dependent high and low side referenced output channels designed for half
bridge applications. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic input is compatible with standard
CMOS outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. Internal deadtime is provided to
avoid shootthrough in the output halfbridge. The floating channel can be used to
drive an Nchannel power MOSFET or IGBT in the high side configuration which
operates from 10 to 600 volts.

HALFBRIDGE DRIVER

Floating Channel Designed for Bootstrap Operation


8

Fully Operational to +600 V

Tolerant to Negative Transient Voltage


dV/dt Immune

P SUFFIX
PLASTIC PACKAGE
CASE 62605

Gate Drive Supply Range from 10 to 20 V


Undervoltage Lockout for Both Channels
CMOS Schmitttriggered Inputs with Pulldown
Matched Propagation Delay for Both Channels
Internally Set Deadtime

High Side Output in Phase with Input

PRODUCT SUMMARY
VOFFSET

600 V MAX

IO+/

200 mA/420 mA

VOUT

10 20 V

ton/off (typical)

130 & 90 ns

Deadtime (typical)

700 ns

D SUFFIX
PLASTIC PACKAGE
CASE 75105
(SO8)

ORDERING INFORMATION
Device

Package

MPIC2111D

SOIC

MPIC2111P

PDIP

PIN CONNECTIONS
(TOP VIEW)
VCC 1

8 VB

VCC 1

8 VB

IN 2

7 HO

IN 2

7 HO

COM 3

6 VS

COM 3

6 VS

LO 4

5
8 LEADS DIP
MPIC2111P

LO 4

5
8 LEAD SOIC
MPIC2111D

This document contains information on a new product. Specifications and information herein are subject
to change without notice.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4287

MPIC2111
SIMPLIFIED BLOCK DIAGRAM

VB
UV
DETECT

HV
LEVEL
SHIFT

DEAD
TIME

PULSE
FILTER

R
R
S

Q
HO

VS

PULSE
GEN
IN

UV
DETECT

VCC

LO
DEAD
TIME
COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply
Su ly Voltage
Low Side Output Voltage
L i IInput V
Logic
Voltage
l
Allowable Offset Supply Voltage Transient

Symbol

Min

Max

Unit

VB
VS
VHO
VCC
VLO
VIN

0.3
VB25
VS0.3
03
0.3
0.3
0.3
0.3
03

625
VB+0.3
VB+0
+0.3
3
25
VCC+0.3
VCC+0.3
03

VDC

dVS/dt

50

V/ns

*Package Power Dissipation @ TC +25C

(8 Lead DIP)
(8 Lead SOIC)

PD

1.0
0.625

Watt

Thermal Resistance, Junction to Ambient

(8 Lead DIP)
(8 Lead SOIC)

RJA

125
200

C/W

Tj, Tstg

55

150

TL

260

Operating and Storage Temperature


Lead Temperature for Soldering Purposes, 10 seconds

RECOMMENDED OPERATING CONDITIONS


The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage

VB

VS+10

VS+20

High Side Floating Supply Offset Voltage

VS

Note 1

600

High Side Floating Output Voltage

VHO

VS

VB

Low Side Fixed Supply Voltage

VCC

10

20

Low Side Output Voltage

VLO

VCC

Logic Input Voltage

VIN

VCC

40

125

Ambient Temperature

TA
Note 1: Logic operational for VS of 5 to +600 V. Logic state held for VS of 5 V to VBS.

4288

mA

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2111
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS) = 15 V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters
are referenced to COM and are applicable to the respective output leads: HO or LO.
Logic 1 Input Voltage for HO & Logic 0 Input Voltage for LO @ VCC = 10 V

VIH

6.4

Logic 1 Input Voltage for HO & Logic 0 Input Voltage for LO @ VCC = 15 V

VIH

9.5

Logic 1 Input Voltage for HO & Logic 0 Input Voltage for LO @ VCC = 20 V

VIH

12.6

Logic 0 Input Voltage for HO & Logic 1 Input Voltage for LO @ VCC = 10 V

VIL

3.8

Logic 0 Input Voltage for HO & Logic 1 Input Voltage for LO @ VCC = 15 V

VIL

6.0

Logic 0 Input Voltage for HO & Logic 1 Input Voltage for LO @ VCC = 20 V

VIL

8.3

High Level Output Voltage, VBIASVO @ IO = 0 A

VOH

100

Low Level Output Voltage, VO @ IO = 0 A

VOL

100

Offset Supply Leakage Current @ VB = VS = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or VCC

IQBS

50

Quiescent VCC Supply Current @ VIN = 0 V or VCC

IQCC

70

Logic 1 Input Bias Current @ VIN = 15 V

IIN+

20

40

Logic 0 Input Bias Current @ VIN = 0 V

IIN

1.0

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

8.5

VBS Supply Undervoltage Negative Going Threshold

VBSUV

8.2

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

8.6

VCC Supply Undervoltage Negative Going Threshold

VCCUV

8.2

Output High Short Circuit Pulsed Current @ VOUT = 0 V, PW 10 s

IO+

200

250

Output Low Short Circuit Pulsed Current @ VOUT = 15 V, PW 10 s

IO

420

500

TurnOn Propagation Delay @ VS = 0 V

ton

850

TurnOff Propagation Delay @ VS = 600 V

toff

150

TurnOn Rise Time @ CL = 1000 pF

tr

80

TurnOff Fall Time @ CL = 1000 pF

tf

40

Deadtime, LS TurnOff to HS TurnOn & HS TurnOff to LS TurnOn

DT

700

Delay Matching, HS & LS TurnOn/Off

MT

30

VDC

mV
A

mA

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS) = 15 V unless otherwise specified
ns

TYPICAL CONNECTION
10 TO 600 V

VCC

IN

VCC

VB

IN

HO

COM

VS

TO
LOAD

LO

Motorola TMOS Power MOSFET Transistor Device Data

4289

MPIC2111
LEAD DEFINITIONS
Symbol

Lead Description

IN

Logic Input for High Side and Low Side Gate Driver Outputs (HO & LO), In Phase with HO

VB

High Side Floating Supply

HO

High Side Gate Drive Output

VS

High Side Floating Supply Return

VCC

Low Side Supply

LO

Low Side Gate Drive Output

COM

Logic and Low Side Return

IN (LO)

IN

50%

50%

IN (HO)
tf

tr

HO

ton

toff
90%

LO
HO

LO

Figure 1. Input / Output Timing Diagram

10%

90%
10%

Figure 2. Switching Time Waveform


Definitions

50%

50%

IN

90%
HO

10%
DT

LO

90%
10%

Figure 3. Deadtime Waveform Definitions

4290

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MPIC2112

Power Products Division

HIGH AND LOW SIDE DRIVER


The MPIC2112 is a high voltage, high speed, power MOSFET and IGBT driver
with independent high and low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
crossconduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an Nchannel power
MOSFET or IGBT in the high side configuration which operates from 10 to 600
volts.

HIGH AND LOW


SIDE DRIVER

14
1

Floating Channel Designed for Bootstrap Operation

P SUFFIX
PLASTIC PACKAGE
CASE 64606

Fully Operational to +600 V


Tolerant to Negative Transient Voltage
dV/dt Immune

16

Gate Drive Supply Range from 10 to 20 V


Undervoltage Lockout for Both Channels

Separate Logic Supply

DW SUFFIX
PLASTIC PACKAGE
CASE 751G02
SOIC WIDE

Operating Supply Range from 5 to 20 V


Logic and Power Ground Operating Offset Range from 5 to +5 V
CMOS Schmitttriggered Inputs with Pulldown

ORDERING INFORMATION

Cycle by Cycle Edgetriggered Shutdown Logic

Device

Matched Propagation Delay for Both Channels


Outputs in Phase with Inputs

Package

MPIC2112DW

SOIC WIDE

MPIC2112P

PDIP

PRODUCT SUMMARY
VOFFSET

600 V MAX

IO+/

200 mA/400 mA

VOUT

10 20 V

ton/off (typical)

125 & 105 ns

Delay Matching

30 ns

PIN CONNECTIONS
(TOP VIEW)
8
9
10
11

HO
VDD
HIN
LIN

13

VSS

6
5
4

SD

12
14

VB
VS

VCC
COM
LO

3
2
1

HO

10

VB
VS

11
12

VDD
HIN

13

SD

14

LIN

15

VSS

16

6
5
4

VCC
COM

LO

14 LEADS PDIP MPIC2112P


16 LEADS SOIC (WIDE BODY)
MPIC2112DW

Motorola TMOS Power MOSFET Transistor Device Data

4291

MPIC2112
SIMPLIFIED BLOCK DIAGRAM

VB
VDD

UV
DETECT

HV
LEVEL
SHIFT

R Q
S

VDD/VCC
LEVEL
SHIFT

HIN

R
R
S

PULSE
FILTER

Q
HO

VS

PULSE
GEN

SD

VCC
UV
DETECT

VDD/VCC
LEVEL
SHIFT

LIN
S

LO

R Q

DELAY

VSS

COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating

Symbol

Min

Max

Unit

High Side Floating Absolute Voltage


High
g Side Floating
g Supplyy Offset Voltage
g
High
g Side Floating
g Output Voltage
g
Low Side Fixed Supplyy Voltage
g
Low Side Output Voltage
Logic Supply Voltage
L i S
l Off
l
Logic
Supply
Offset V
Voltage
L i IInputt V
Logic
Voltage
lt
(HIN
(HIN, LIN & SD)

VB
VS
VHO
VCC
VLO
VDD
VSS
VIN

0.3
0.3
VB25
VS0.3
0.3
0.3
0.3
VCC25
VSS0.3
03

625
VB+0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
03

VDC

Allowable Offset Supply Voltage Transient

dVS/dt

50

V/ns

*Package Power Dissipation @ TA +25C

(14 Lead DIP)


(16 SOICWIDE)

PD

1.6
1.25

Watt

Thermal Resistance, Junction to Ambient

(14 Lead DIP)


(16 SOICWIDE)

RJA

75
100

C/W

Tj, Tstg

55

150

TL

260

Operating and Storage Temperature


Lead Temperature for Soldering Purposes, 10 seconds

RECOMMENDED OPERATING CONDITIONS


The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage

VB

VS+10

VS+20

High Side Floating Supply Offset Voltage

VS

Note 1

600

High Side Floating Output Voltage

VHO

VS

VB

Low Side Fixed Supply Voltage

VCC

10

20

Low Side Output Voltage

VLO

VCC

Logic Supply Voltage

VDD

VSS+5

VSS+20

Logic Supply Offset Voltage

VSS

Logic Input Voltage (HIN, LIN & SD)

VIN

VSS

VDD

TA
Note 1: Logic operational for VS of 5 to +600 V. Logic state held for VS of 5 V to VBS.

40

125

Ambient Temperature

4292

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2112
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS SUPPLY CHARACTERISTICS


VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VSS and are applicable to
the respective output leads: HO or LO.
Logic 1 Input Voltage

VIH

9.5

Logic 0 Input Voltage

VIL

6.0

High Level Output Voltage, VBIASVO @ VIN = VIH, IO = 0 A

VOH

100

Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A

VOL

100

Offset Supply Leakage Current @ VB = VS = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or VDD

IQBS

25

60

Quiescent VCC Supply Current @ VIN = 0 V or VDD

IQCC

80

180

Quiescent VDD Supply Current @ VIN = 0 V or VDD

IQDD

2.0

5.0

Logic 1 Input Bias Current @ VIN = 15 V

IIN+

20

40

Logic 0 Input Bias Current @ VIN = 0 V

IIN

1.0

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

7.4

9.6

VBS Supply Undervoltage Negative Going Threshold

VBSUV

7.0

9.2

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

7.6

9.6

VCC Supply Undervoltage Negative Going Threshold

VCCUV

7.2

9.2

Output High Short Circuit Pulsed Current


@ VOUT = 0 V, VIN = 15 V, PW 10 s

IO+

200

250

Output Low Short Circuit Pulsed Current


@ VOUT = 15 V, VIN = 0 V, PW 10 s

IO

420

500

mV

mA

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. TA = 25C.
TurnOn Propagation Delay @ VS = 0 V

ton

125

180

TurnOff Propagation Delay @ VS = 600 V

toff

105

160

Shutdown Propagation Delay @ VS = 600 V

tsd

105

160

tr

80

130

tf

40

65

MT

30

TurnOn Rise Time @ CL = 1000 pF


TurnOff Fall Time @ CL = 1000 pF
Delay Matching, HS & LS TurnOn/Off

ns

TYPICAL CONNECTION
10 TO 600 V

VDD
HIN

VDD
HIN

SD

SD

LIN

LIN

VSS
VCC

VSS

HO
VB
VS

TO
LOAD

VCC
COM
LO

Motorola TMOS Power MOSFET Transistor Device Data

4293

MPIC2112
LEAD DEFINITIONS
Symbol

Lead Description

VDD

Logic Supply

HIN

Logic Input for High Side Gate Driver Output (HO), In Phase

SD

Logic Input for Shutdown

LIN

Logic Input for Low Side Gate Driver Output (LO), In Phase

VSS

Logic Ground

VB

High Side Floating Supply

HO

High Side Gate Drive Output

VS

High Side Floating Supply Return

VCC

Low Side Supply

LO

Low Side Gate Drive Output

COM

Low Side Return

HIN
LIN

50%

HIN
LIN

50%

tr

ton
SD

90%
HO
LO

50%

SD

50%

LO
tsd

HO
LO

10%

Figure 2. Switching Time Waveform


Definitions

HIN
LIN

50%

90%

10%

HO
LO

Figure 1. Input / Output Timing Diagram

tf

toff

HO
10%

90%

MT

MT
90%
LO

Figure 3. Deadtime Waveform Definitions

4294

HO

Figure 4. Delay Matching Waveform


Definitions

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MPIC2113

Power Products Division

Advance Information
HIGH AND LOW SIDE DRIVER

HIGH AND LOW


SIDE DRIVER

The MPIC2113 is a high voltage, high speed, power MOSFET and IGBT driver
with independent high and low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
crossconduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an Nchannel power
MOSFET or IGBT in the high side configuration which operates from 10 to 600
volts.

14
1

P SUFFIX
PLASTIC PACKAGE
CASE 64606

Floating Channel Designed for Bootstrap Operation


Fully Operational to +600 V
Tolerant to Negative Transient Voltage

16

dV/dt Immune

Gate Drive Supply Range from 10 to 20 V


DW SUFFIX
PLASTIC PACKAGE
CASE 751G02
SOIC WIDE

Undervoltage Lockout for Both Channels


Separate Logic Supply
Operating Supply Range from 5 to 20 V
Logic and Power Ground Operating Offset Range from 5 to +5 V

ORDERING INFORMATION

CMOS Schmitttriggered Inputs with Pulldown

Device

Cycle by Cycle Edgetriggered Shutdown Logic


Matched Propagation Delay for Both Channels

Package

MPIC2113DW

SOIC WIDE

MPIC2113P

PDIP

Outputs In Phase with Inputs


PRODUCT SUMMARY

VOFFSET

600 V MAX

IO+/

2 A/2 A

VOUT

10 20 V

ton/off (typical)

120 & 94 ns

Delay Matching

10 ns

PIN CONNECTIONS
(TOP VIEW)
8
9
10

VDD
HIN

11

SD

12

LIN

13

VSS

14

HO

VB
VS

6
5
4

VCC
COM

LO

14 LEADS PDIP MPIC2113P

HO

10

VB
VS

11
12

VDD
HIN

13

SD

14

LIN

15

VSS

16

6
5
4

VCC
COM

LO

16 LEADS SOIC (WIDE BODY)


MPIC2113DW

This document contains information on a new product. Specifications and information herein are subject
to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4295

MPIC2113
SIMPLIFIED BLOCK DIAGRAM

VB
VDD

UV
DETECT

HV
LEVEL
SHIFT

R Q
S

VDD/VCC
LEVEL
SHIFT

HIN

R
R
S

PULSE
FILTER

Q
HO

VS

PULSE
GEN

SD

VCC
UV
DETECT

VDD/VCC
LEVEL
SHIFT

LIN
S

LO

R Q

DELAY

VSS

COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Symbol

Min

Max

Unit

High Side Floating Absolute Voltage


High
g Side Floating
g Supplyy Offset Voltage
g
g Side Floating
g Output Voltage
g
High
Low Side Fixed Supplyy Voltage
g
Low Side Output Voltage
Logic Supply Voltage
L i S
Logic
Supply
l Off
Offset V
Voltage
l
L i IInputt V
lt
(HIN
Logic
Voltage
(HIN, LIN & SD)

VB
VS
VHO
VCC
VLO
VDD
VSS
VIN

0.3
0.3
VB25
VS0.3
0.3
0.3
0.3
VCC25
03
VSS0.3

625
VB+0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
03
VDD+0.3

VDC

Allowable Offset Supply Voltage Transient

dVS/dt

50

V/ns

Rating

*Package Power Dissipation @ TA +25C

(14 Lead DIP)


(16 SOICWIDE)

PD

1.6
1.25

Watt

Thermal Resistance, Junction to Ambient

(14 Lead DIP)


(16 SOICWIDE)

RJA

75
100

C/W

Tj, Tstg

55

150

TL

260

Operating and Storage Temperature


Lead Temperature for Soldering Purposes, 10 seconds

RECOMMENDED OPERATING CONDITIONS


The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage

VB

VS+10

VS+20

VS

Note 1

600

High Side Floating Output Voltage

VHO

VS

VB

Low Side Fixed Supply Voltage

VCC

10

20

Low Side Output Voltage

VLO

VCC

Logic Supply Voltage

VDD

VSS+5

VSS+20

Logic Supply Offset Voltage

VSS

Logic Input Voltage (HIN, LIN & SD)

VIN

VSS

VDD

TA
Note 1: Logic operational for VS of 5 to +600 V. Logic state held for VS of 5 V to VBS.

40

125

Ambient Temperature

4296

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2113
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS SUPPLY CHARACTERISTICS


VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VSS and are applicable to
the respective output leads: HO or LO.
Logic 1 Input Voltage

VIH

9.5

Logic 0 Input Voltage

VIL

6.0

High Level Output Voltage, VBIASVO @ VIN = VIH, IO = 0 A

VOH

1.2

Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A

VOL

0.1

Offset Supply Leakage Current @ VB = VS = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or VDD

IQBS

125

230

Quiescent VCC Supply Current @ VIN = 0 V or VDD

IQCC

180

340

Quiescent VDD Supply Current @ VIN = 0 V or VDD

IQDD

15

30

Logic 1 Input Bias Current @ VIN = 15 V

IIN+

20

40

Logic 0 Input Bias Current @ VIN = 0 V

IIN

1.0

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

7.5

9.7

VBS Supply Undervoltage Negative Going Threshold

VBSUV

7.0

9.4

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

7.4

9.6

VCC Supply Undervoltage Negative Going Threshold

VCCUV

7.0

9.4

Output High Short Circuit Pulsed Current


@ VOUT = 0 V, VIN = 15 V, PW 10 s

IO+

2.0

2.5

Output Low Short Circuit Pulsed Current


@ VOUT = 15 V, VIN = 0 V, PW 10 s

IO

2.0

2.5

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. TA = 25C.
TurnOn Propagation Delay @ VS = 0 V

ton

120

150

TurnOff Propagation Delay @ VS = 600 V

toff

94

125

Shutdown Propagation Delay @ VS = 600 V

tsd

110

140

tr

25

35

tf

17

25

MT

10

TurnOn Rise Time @ CL = 1000 pF


TurnOff Fall Time @ CL = 1000 pF
Delay Matching, HS & LS TurnOn/Off

ns

TYPICAL CONNECTION
10 TO 600 V

VDD
HIN

VDD
HIN

SD

SD

LIN

LIN

VSS
VCC

VSS

HO
VB
VS

TO
LOAD

VCC
COM
LO

Motorola TMOS Power MOSFET Transistor Device Data

4297

MPIC2113
LEAD DEFINITIONS
Symbol

Lead Description

VDD

Logic Supply

HIN

Logic Input for High Side Gate Driver Output (HO), In Phase

SD

Logic Input for Shutdown

LIN

Logic Input for Low Side Gate Driver Output (LO), In Phase

VSS

Logic Ground

VB

High Side Floating Supply

HO

High Side Gate Drive Output

VS

High Side Floating Supply Return

VCC

Low Side Supply

LO

Low Side Gate Drive Output

COM

Low Side Return

HIN
LIN

50%

HIN
LIN

50%

tr

ton
SD

90%
HO
LO

50%

SD

50%

LO
tsd

HO
LO

10%

Figure 2. Switching Time Waveform


Definitions

HIN
LIN

50%

90%

10%

HO
LO

Figure 1. Input / Output Timing Diagram

tf

toff

HO
10%

90%

MT

MT
90%
LO

Figure 3. Shutdown Waveform Definitions

4298

HO

Figure 4. Delay Matching Waveform


Definitions

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Power Products Division

MPIC2117

Advance Information
SINGLE CHANNEL DRIVER
The MPIC2117 is a high voltage, high speed, power MOSFET and IGBT driver.
Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS outputs. The
output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an Nchannel power MOSFET or IGBT in the high side or low side configuration which operates from
10 to 600 volts.

SINGLE CHANNEL DRIVER

Floating Channel Designed for Bootstrap Operation


Fully Operational to +600 V
Tolerant to Negative Transient Voltage

dV/dt Immune

Gate Drive Supply Range from 10 to 20 V


P SUFFIX
PLASTIC PACKAGE
CASE 62605

Undervoltage Lockout
CMOS Schmitttriggered Input with Pulldown
Output In Phase with Input

PRODUCT SUMMARY
VOFFSET

600 V MAX

IO+/

200 mA/420 mA

VOUT

10 20 V

ton/off (typical)

125 & 105 ns

D SUFFIX
PLASTIC PACKAGE
CASE 75105
(SO8)

ORDERING INFORMATION
Device

Package

MPIC2117D

SOIC

MPIC2117P

PDIP

PIN CONNECTIONS
(TOP VIEW)
VCC 1

8 VB

VCC 1

8 VB

IN 2

7 HO

IN 2

7 HO

COM 3

6 VS

COM 3

6 VS

5
8 LEADS DIP
MPIC2117P

5
8 LEAD SOIC
MPIC2117D

This document contains information on a new product. Specifications and information herein are subject
to change without notice.
REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4299

MPIC2117
SIMPLIFIED BLOCK DIAGRAM

VCC

VB
UV
DETECT

HV
LEVEL
SHIFT
IN

PULSE
FILTER

R
R
S

Q
HO

VS

PULSE
GEN

UV
DETECT
COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating
High
g Side Floating
g Supply
y Absolute Voltage
g
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Logic
Supply
Voltage
L i S
l V
lt
Logic Input Voltage
Allowable Offset Supply Voltage Transient

Symbol

Min

Max

Unit

VB
VS
VHO
VCC
VIN

0.3
VB25
VS0.3
0.3
03
03
0.3

625
VB+0.3
VB+0.3
25
3
VCC+0
+0.3

VDC

dVS/dt

50

V/ns

*Package Power Dissipation @ TA +25C

(8 Lead DIP)
(8 Lead SOIC)

PD

1.0
0.625

Watt

Thermal Resistance, Junction to Ambient

(8 Lead DIP)
(8 Lead SOIC)

RJA

125
200

C/W

Tj, Tstg

55

150

TL

260

Operating and Storage Temperature


Lead Temperature for Soldering Purposes, 10 seconds

RECOMMENDED OPERATING CONDITIONS


The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage

VB

VS+10

VS+20

High Side Floating Supply Offset Voltage

VS

Note 1

600

High Side Floating Output Voltage

VHO

VS

VB

Logic Supply Voltage

VCC

10

20

Logic Input Voltage

VIN

VCC

Ambient Temperature

TA

40

125

Note 1: Logic operational for VS of 5 to +600 V. Logic state held for VS of 5 V to VBS.

4300

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2117
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS) = 15 V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters
are referenced to COM and are applicable to the respective output leads: HO or LO.
Logic 1 Input Voltage @ VCC = 10 V

VIH

6.4

Logic 1 Input Voltage @ VCC = 15 V

VIH

9.5

Logic 1 Input Voltage @ VCC = 20 V

VIH

12.6

Logic 0 Input Voltage @ VCC = 10 V

VIL

3.8

Logic 0 Input Voltage @ VCC = 15 V

VIL

6.0

Logic 0 Input Voltage @ VCC = 20 V

VIL

8.3

High Level Output Voltage, VBSVO @ VIN = VIH, IO = 0 A

VOH

100

Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A

VOL

100

Offset Supply Leakage Current @ VB = VS = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or VCC

IQBS

50

Quiescent VCC Supply Current @ VIN = 0 V or VCC

IQCC

70

Logic 1 Input Bias Current @ VIN = 15 V

IIN+

20

40

Logic 0 Input Bias Current @ VIN = 0 V

IIN

1.0

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

8.5

VBS Supply Undervoltage Negative Going Threshold

VBSUV

8.2

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

8.6

VCC Supply Undervoltage Negative Going Threshold

VCCUV

8.2

Output High Short Circuit Pulsed Current


@ VOUT = 0 V, VIN = 15 V, PW 10 s

IO+

200

250

Output Low Short Circuit Pulsed Current


@ VOUT = 15 V, VIN = 0 V, PW 10 s

IO

420

500

TurnOn Propagation Delay @ VS = 0 V

ton

125

TurnOff Propagation Delay @ VS = 600 V

toff

105

TurnOn Rise Time @ CL = 1000 pF

tr

80

TurnOff Fall Time @ CL = 1000 pF

tf

40

VDC

mV
A

mA

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS) = 15 V unless otherwise specified
ns

TYPICAL CONNECTION

VCC

IN

VCC

VB

IN

HO

COM

VS

Motorola TMOS Power MOSFET Transistor Device Data

4301

MPIC2117
LEAD DEFINITIONS
Symbol
VCC
IN

Lead Description
Logic Supply
Logic Input for High Side Gate Driver Outputs (HO), In Phase with HO

COM

Logic Ground

VB

High Side Floating Supply

HO

High Side Gate Drive Output

VS

High Side Floating Supply Return

50%

IN

50%

IN
ton

tr
90%

HO

HO

Figure 1. Input / Output Timing Diagram

4302

10%

tf

toff
90%

10%

Figure 2. Switching Time Waveform


Definitions

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Power Products Division

Advance Information

3-PHASE BRIDGE DRIVER


The MPIC2130 is a high voltage, high speed, power MOSFET and IGBT driver
with three independent high side and low side referenced output channels for
3Phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with 5 V CMOS or LSTTL outputs. A
ground referenced operational amplifier provides an analog feedback of bridge
current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal
is provided to indicate that an overcurrent or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for
minimum driver crossconduction. Propagation delays are matched to simplify use
in high frequency applications.
The floating channels can be used to drive Nchannel power MOSFET or
IGBTs in the high side configuration which operate from 10 to 600 volts.

MPIC2130

3PHASE
BRIDGE DRIVER

28
1

Floating Channel Designed for Bootstrap Operation

P SUFFIX
PLASTIC PACKAGE
CASE 71002

Fully Operational to +600 V


Tolerant to Negative Transient Voltage
dV/dt Immune
Gate Drive Supply Range from 10 to 20 V
Undervoltage Lockout for All Channels
Overcurrent Shut Down Turns Off All Six Drivers
Independent Halfbridge Drivers

PIN CONNECTIONS
1

VCC

VB1 28

HIN1

HO1 27

HIN2

VS1 26

HIN3

25

LIN1

VB2 24

LIN2

HO2 23

LIN3

VS2 22

FAULT

ITRIP

VB3 20

10

CAO

HO3 19

11

CA

VS3 18

12

VSS

17

13

VSO

LO1 16

14

LO3

LO2 15

Matched Propagation Delay for All Channels


Outputs Out of Phase with Inputs
PRODUCT SUMMARY

VOFFSET

600 V MAX

IO+/

200 mA/420 mA

VOUT

10 20 V

ton/off (typical)

675 & 425 ns

Deadtime (typical)

2.5 ms

21

(TOP VIEW)

ORDERING INFORMATION
This document contains information on a new product. Specifications and information herein are subject
to change without notice.

Device

Package

MPIC2130P

PDIP

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4303

MPIC2130
SIMPLIFIED BLOCK DIAGRAM

H1
INPUT
SIGNAL
L1
GENERATOR

HIN1
HIN2

PULSE
GENERATOR
LEVEL
SHIFTER

SET

PULSE
GENERATOR
LEVEL
SHIFTER

SET

PULSE
GENERATOR
LEVEL
SHIFTER

SET

VB1

LATCH
DRIVER

UV
RESET DETECTOR

VS1

HIN3
LIN1

H2
INPUT
SIGNAL
L2
GENERATOR

LIN2
LIN3
FAULT
CLEAR
LOGIC

H3
INPUT
SIGNAL
L3
GENERATOR

FAULT
LOGIC
C

HO1

VB2

LATCH
DRIVER

UV
RESET DETECTOR

HO2
VS2
VB3

LATCH
DRIVER

UV
RESET DETECTOR

HO3
VS3

VCC

0.5 V

CURRENT
COMPARATOR

CAO
CURRENT
AMP

DRIVER

LO1

DRIVER

LO2

DRIVER

LO3

UNDER
VOLTAGE
DETECTOR

ITRIP

CA

VSS

VSO

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to VSS. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions.
Rating

Symbol

Min

Max

Unit

High Side Floating Absolute Voltage


High Side Floating Supply
Su ly Offset Voltage
High Side Floating Output Voltage
Fi d Supply
Fixed
S
l V
Voltage
lt
Low Side Driver Return
Low Side Output Voltage
Logic Input
In ut Voltage (HIN
(HIN,, LIN,
LIN , & ITRIP)
Fault Output Voltage
Amplifier
Am
lifier Output
Out ut Voltage
Amplifier Inverting Input Voltage

VB1,2,3
VS1,2,3
S1 2 3
VHO1,2,3
VCC
VSO
VLO1,2,3
VIN
FAULT
CAO
CA

0.3
VB1,2,3
B1 2 325
VS1,2,30.3
0.3
03
VCC0.3
VSO0.3
0.3
0.3
0.3
0 3
0.3
0.3

625
VB1,2,3
+0 3
B1 2 3+0.3
VB1,2,3+0.3
25
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
+0 3
VCC+0.3

VDC

Allowable Offset Supply Voltage Transient

dVS/dt

50

V/ns

PD

1.5

Watt

Tj, Tstg

55

150

RJA

83

C/W

TL

260

*Package Power Dissipation @ TA +25C


Operating and Storage Temperature
Thermal Resistance, Junction to Ambient
Lead Temperature for Soldering Purposes, 10 seconds

4304

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2130
RECOMMENDED OPERATING CONDITIONS
The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage

VB1,2,3

VS1,2,3+10

VS1,2,3+20

VS1,2,3

Note 1

VSO+600

VHO1,2,3

VS1,2,3

VB1,2,3

Fixed Supply Voltage

VCC

10

20

Low Side Driver Return

VSO

VLO1,2,3

VSO

VCC

VIN

VSS

High Side Floating Output Voltage

Low Side Output Voltage


Logic Input Voltage (HIN, LIN, & ITRIP)
Fault Output Voltage

FAULT

VSS

VCC

Amplifier Output Voltage

CAO

VSS

Amplifier Inverting Input Voltage

CA

VSS

40

125

Ambient Temperature

TA
Note 1: Logic operational for VS of 5 V to +600 V. Logic state held for VS of VSO5 V to VSOVBS.

ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)


Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS1,2,3) = 15 V and VSO = VSS unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Logic 0 Input Voltage (OUT = LO)

VIH

2.2

Logic 1 Input Voltage (OUT = HI)

VIL

0.8

VIT,TH+

400

580

mV

High Level Output Voltage, VBIASVO @ VIN = 0 V, IO = 0 A

VOH

100

mV

Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A

VOL

100

mV

Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or 5 V

IQBS

15

30

Quiescent VCC Supply Current @ VIN = 0 V or 5 V

ITRIP Input Positive Going Threshold

IQCC

3.0

4.0

mA

Logic 1 Input Bias Current (OUT = HI) @ VIN = 0 V

IIN+

400

500

Logic 0 Input Bias Current (OUT = LO) @ VIN = 5 V

IIN

200

320

High ITRIP Bias Current @ ITRIP = 5 V

ITRIP+

75

150

Low ITRIP Bias Current @ ITRIP = 0 V

ITRIP

100

nA

VBSUV+

8.0

9.2

VBS Supply Undervoltage Negative Going Threshold

VBSUV

7.6

8.8

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

8.3

9.7

VCC Supply Undervoltage Negative Going Threshold

VCCUV

8.0

9.4

FAULT Low On Resistance

Ron,FLT

55

75

Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW 10 s

IO+

200

250

mA

Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW 10 s

IO

420

500

mA

Amplifier Input Offset Voltage @ VSO = CA = 0.2

VOS

30

mV

CA Input Bias Current @ CA = 2.5 V

ICA

4.0

nA

CMRR

60

80

dB

VBS Supply Undervoltage Positive Going Threshold

Amplifier Common Mode Rejection Ratio @ VSO = CA = 0.1 V & 5 V

Motorola TMOS Power MOSFET Transistor Device Data

4305

MPIC2130
ELECTRICAL CHARACTERISTICS (continued) (TA = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS1,2,3) = 15 V and VSO = VSS unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Amplifier Power Supply Rejection Ratio
@ VSO = CA=0.2 V, VCC = 10 & 20 V

PSRR

55

75

dB

Amplifier High Level Output Voltage @ CA = 0 V, VSO = 1 V

VOH,Amp

5.0

5.4

Amplifier Low Level Output Voltage @ CA = 1 V, VSO = 0 V

VOL,Amp

20

mV

Amplifier Output Source Current @ CA = 0 V, VSO = 1 V, CAO = 4 V

ISRC,Amp

2.3

4.0

mA

Amplifier Output Sink Current @ CA = 1 V, VSO = 0 V, CAO = 2 V

ISNK,Amp

1.0

2.1

mA

Amplifier Output High Short Circuit Current


@ CA = 1 V, VSO = 5 V, CAO = 0 V

IO+,Amp

4.5

6.5

mA

Amplifier Output Low Short Circuit Current


@ CA = 5 V, VSO = 0 V, CAO = 5 V

IO,Amp

3.2

5.2

mA

Symbol

Min

Typ

Max

Unit

ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)


Characteristic

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and CL = 1000 pF unless otherwise specified. TA = 25C.
TurnOn Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

ton

500

850

ns

TurnOff Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

toff

300

550

ns

TurnOn Rise Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

tr

80

125

ns

TurnOff Fall Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

tf

35

55

ns

titrip

400

920

ns

ITRIP Blanking Time @ ITRIP = 1 V

tbl

400

ns

ITRIP to FAULT Propagation Delay @ VIN, VITRIP = 0 & 5 V

tflt

335

845

ns

Input Filter Time (all six inputs) @ VIN = 0 & 5 V

tflt,in

310

ns

LIN1,2,3 to FAULT Clear Time @ VIN, VITRIP = 0 & 5 V

tfltclr

6.0

12

DT

1.3

3.7

Amplifier Slew Rate (Positive)

SR+

4.4

6.2

V/s

Amplifier Slew Rate (Negative)

SR

2.4

3.2

V/s

ITRIP to Output Shutdown Propagation Delay @ VIN, VITRIP = 0 & 5 V

Deadtime, LS TurnOff to HS TurnOn & HS TurnOff to LS TurnOn


@ VIN = 0 & 5 V

TYPICAL CONNECTION
10 TO 600 V

VCC
HIN1,2,3

VCC
HIN1,2,3

VB1,2,3
HO1,2,3

LIN1,2,3

LIN1,2,3

VS1,2,3

FAULT

FAULT

TO
LOAD

ITRIP
CAO

CAO
CA
VSS
VSO

LO1,2,3

COM

4306

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2130
LEAD DEFINITIONS
Symbol

Lead Description

HIN1,2,3

Logic Inputs for High Side Gate Driver Outputs (HO1,2,3), Out of Phase

LIN1,2,3

Logic Inputs for Low Side Gate Driver Outputs (LO1,2,3), Out of Phase

FAULT

Indicates Overcurrent, or Undervoltage Lockout (Low Side) has Occurent, Negative Logic

VCC

Logic and Low Side Fixed Supply

ITRIP

Input for Overcurrent Shut Down

CAO

Output of Current Amplifier

CA

Negative Input of Current Amplifier

VSS

Logic Ground

VB1,2,3

High Side Floating Supplies

HO1,2,3

High Side Gate Drive Outputs

VS1,2,3

High Side Floating Supply Returns

LO1,2,3

Low Side Gate Drive Outputs

VSO

Low Side Return, Positive Input of Current Amplifier

HIN
HIN
LIN

LIN

50%

ITRIP
ton

FAULT

50%

tr
90%

toff
90%

tf

HO

HO13

LO

10%

10%

LO13

Figure 1. Input / Output Timing Diagram

HIN

Figure 2. Switching Time Waveform


Definitions

50%

LIN2
50%

50%

LIN
ITRIP

50%

FAULT

50%

50%

LO
50%

50%

LO2

HO
DT

DT

Figure 3. Deadtime Waveform Definitions

Motorola TMOS Power MOSFET Transistor Device Data

50%
tfltclr

tflt
titrip

Figure 4. Overcurrent Shutdown Waveform


Definitions

4307

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Power Products Division

MPIC2131

Advance Information

3-HIGH SIDE &


3-LOW SIDE DRIVER
The MPIC2131 is a high voltage, high speed, power MOSFET and IGBT driver
with three independent high side and low side referenced output channels for
3Phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with 5 V CMOS or LSTTL outputs. A
ground referenced operational amplifier provides an analog feedback of bridge
current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from an external current sense resistor. An extra shutdown input is provided for customizing the shutdown function. An open
drain FAULT signal is provided to indicate that any of shutdown conditions has occurred. The output drivers feature a high pulse current buffer stage designed for
minimum driver crossconduction. Propagation delays are matched to simplify use
in high frequency applications.
The floating channels can be used to drive Nchannel power MOSFET or
IGBTs in the high side configuration which operate from 10 to 600 volts.

3 HIGH SIDE &


3 LOW SIDE
DRIVER

28
1

P SUFFIX
PLASTIC PACKAGE
CASE 71002

Floating Channel Designed for Bootstrap Operation


Fully Operational to +600 V
Tolerant to Negative Transient Voltage
dV/dt Immune

PIN CONNECTIONS

Gate Drive Supply Range from 10 to 20 V


Undervoltage Lockout for All Channels

VCC

VB1 28

Independent 3 High Side & 3 Low Side Drivers

HIN1

HO1 27

Matched Propagation Delay for All Channels

HIN2

VS1 26

Outputs Out of Phase with Inputs

HIN3

25

LIN1

VB2 24

LIN2

HO2 23

LIN3

VS2 22

FAULT

Overcurrent Shut Down Turns Off All Six Drivers

PRODUCT SUMMARY
VOFFSET

600 V MAX

IO+/

200 mA/420 mA

VOUT

10 20 V

ton/off (typical)

1.4 & 0.7 ms

ITRIP

VB3 20

Delay Matching

700 ns

10

FLT+CLR

HO3 19

11

SD

VS3 18

12

VSS

17

13

COM

LO1 16

14

LO3

LO2 15

21

(TOP VIEW)

ORDERING INFORMATION
This document contains information on a new product. Specifications and information herein are subject
to change without notice.

Device

Package

MPIC2131P

PDIP

REV 1

4308

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2131
SIMPLIFIED BLOCK DIAGRAM

H1
INPUT
SIGNAL
L1
GENERATOR

HIN1
HIN2

PULSE
GENERATOR
LEVEL
SHIFTER

SET

PULSE
GENERATOR
LEVEL
SHIFTER

SET

PULSE
GENERATOR
LEVEL
SHIFTER

SET

VB1

LATCH
DRIVER

UV
RESET DETECTOR

VS1

HIN3
LIN1

H2
INPUT
SIGNAL
L2
GENERATOR

LIN2
LIN3
FLTCLR

H3
INPUT
SIGNAL
L3
GENERATOR

SD
FAULT

HO1

VB2

LATCH
DRIVER

UV
RESET DETECTOR

HO2
VS2
VB3

LATCH
DRIVER

UV
RESET DETECTOR

HO3
VS3

FAULT
LOGIC

VCC
DRIVER

LO1

DRIVER

LO2

DRIVER

LO3

UNDER
VOLTAGE
DETECTOR

VSS

ITRIP
CURRENT
COMPARATOR
0.5 V
VSS

COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating

Symbol

Min

Max

Unit

VB1,2,3
VS1,2,3
VHO1,2,3
HO1 2 3
VLO1,2,3
, ,
VCC
VSS
VIN
FAULT

0.3
VB1,2,325
25
VS1,2,3
0.3
S1 2 30.3
0.3
0.3
VCC25
VSS0.3
VSS0.3

625
VB1,2,3+0.3
03
VB1,2,3
B1 2 3+0.3
VCC+0.3
25
VCC+0.3
+0 3
VCC+0.3
VCC+0.3

VDC

dVS/dt

50

V/ns

PD

1.5

Watt

Tj, Tstg

55

150

Thermal Resistance, Junction to Ambient (8 Lead DIP)

RJA

83

C/W

Lead Temperature for Soldering Purposes, 10 seconds

TL

260

High Side Floating Absolute Voltage


Hi h Side
High
Sid Floating
Fl ti Supply
S
l Off
Offsett V
Voltage
lt
High Side Floating Out
Output
ut Voltage
Low Side Output Voltage
Fixed Supply Voltage
Fixed Su
Supply
ly Offset Voltage
Logic
g Input Voltage
g (HIN, LIN, FLT, CLR, SD & ITRIP)
Fault Output Voltage
Allowable Offset Supply Voltage Transient
*Package Power Dissipation @ TC +25C (28 Lead DIP)
Operating and Storage Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4309

MPIC2131
RECOMMENDED OPERATING CONDITIONS
The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage

VB1,2,3

High Side Floating Supply Offset Voltage

VS1,2,3+10

VS1,2,3+20

VS1,2,3

Note 1

VSO+600

VHO1,2,3

VS1,2,3

VB1,2,3

VCC

10

20

VLO1,2,3

VCC

Low Side Driver Return

VSS

Logic Input Voltage (HIN, LIN, FLTCLR, SD & ITRIP)

VIN

VSS

FAULT

VSS

VCC

40

125

High Side Floating Output Voltage


Fixed Supply Voltage
Low Side Output Voltage

Fault Output Voltage


Ambient Temperature

TA
Note 1: Logic operational for VS of 5 V to +600 V. Logic state held for VS of 5 V to VBS.

ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)


Symbol

Characteristic

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS1,2,3) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to COM and VSO1,2,3 and are applicable to
the respective output leads: HO1,2,3 or LO1,2,3.
Logic 0 Input Voltage (OUT = LO)

VIH

2.2

Logic 1 Input Voltage (OUT = HI)

VIL

0.8

Logic 0 Fault Clear Input Voltage

VFCLR,IH

2.2

Logic 1 Fault Clear Input Voltage

VFCLR,IL

0.8

SD Input Positive Going Threshold

VSD,TH+

1.8

SD Input Negative Going Threshold

VSD,TH

1.5

ITRIP Input Positive Going Threshold

VIT,TH+

485

mV

ITRIP Input Negative Going Threshold

VIT,TH

400

mV

High Level Output Voltage, VBIASVO @ VIN = 0 V, IO = 0 A

VOH

100

mV

Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A

VOL

100

mV

Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V

ILK

50

Quiescent VBS Supply Current @ VIN = 0 V or 5 V

IQBS

30

Quiescent VCC Supply Current @ VIN = 0 V or 5 V

IQCC

3.0

mA

Logic 1 Input Bias Current (OUT = HI) @ VIN = 0 V

IIN+

190

Logic 0 Input Bias Current (OUT = LO) @ VIN = 5 V

IIN

100

High ITRIP Bias Current @ ITRIP = 5 V

ITRIP+

60

Low ITRIP Bias Current @ ITRIP = 0 V

ITRIP

50

nA

Logic 1 Fault Clear Bias Current @ FLTCLR = 0 V

IFCLR+

190

Logic 0 Fault Clear Bias Current @ FLTCLR = 5 V

IFCLR

100

Logic 1 Shut Down Bias Current @ SD = 5 V

ISD+

60

Logic 0 Shut Down Bias Current @ SD = 5 V

ISD

150

nA

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

8.6

VBS Supply Undervoltage Negative Going Threshold

VBSUV

8.2

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

9.0

VCC Supply Undervoltage Negative Going Threshold

VCCUV

8.7

FAULT Low On Resistance

Ron,FLT

55

Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW 10 s

IO+

200

250

mA

Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW 10 s

IO

420

500

mA

4310

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2131
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

DYNAMIC ELECTRICAL CHARACTERISTICS


VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and CL = 1000 pF unless otherwise specified. TA = 25C.
TurnOn Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

ton

1.4

TurnOff Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

toff

0.7

TurnOn Rise Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

tr

80

ns

TurnOn Fall Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V

tf

40

ns

titrip

550

ns

ITRIP Blanking Time @ ITRIP = 1 V

tbl

400

ns

ITRIP to FAULT Propagation Delay @ VIN, VITRIP = 0 & 5 V

tflt

450

ns

Input Filter Time (all six inputs) @ VIN = 0 & 5 V

tflt,in

310

ns

FLTCLR to FAULT Clear Time @ VIN, VIT, VFC = 0 & 5 V

tfltclr

450

ns

SD to OUTPUT Shutdown Propagation Delay @ VIN, VSD = 0 & 5 V

tsd

550

ns

Deadtime, LS TurnOff to HS TurnOn & HS TurnOff to LS TurnOn


@ VIN = 0 & 5 V

DT

700

ns

ITRIP to Output Shutdown Propagation Delay @ VIN, VITRIP = 0 & 5 V

TYPICAL CONNECTION
10 TO 600 V

VCC
HIN1,2,3

VB1,2,3
HO1,2,3

LIN1,2,3

VS1,2,3

FAULT

TO
LOAD

ITRIP
FLTCLR
SD
VSS
COM

LO1,2,3

LEAD DEFINITIONS
Symbol

Lead Description

HIN1,2,3

Logic Inputs for High Side Gate Driver Outputs (HO1,2,3), Out of Phase

LIN1,2,3

Logic Inputs for Low Side Gate Driver Outputs (LO1,2,3), Out of Phase

FLTCLR

Logic Inputs for Fault Clear

SD

Logic Input for Shut Down

FAULT

Indicates Overcurrent, Shut Down or Low Side Undervoltage Condition, Negative Logic

ITRIP

Input for Overcurrent Shut Down

VSS

Logic Ground

VB1,2,3

High Side Floating Supplies

HO1,2,3

High Side Gate Drive Outputs

VS1,2,3

High Side Floating Supply Returns

VCC

Logic and Low Side Fixed Supply

LO1,2,3
COM

Low Side Gate Drive Outputs


Low Side Return

Motorola TMOS Power MOSFET Transistor Device Data

4311

MPIC2131
HIN
HIN
LIN

LIN
ITRIP

50%

SD

tr

ton

FLTCLR

50%

90%

FAULT

toff
90%

tf

HO

HO

LO

10%

10%

LO

Figure 1. Input / Output Timing Diagram

Figure 2. Switching Time Waveform


Definitions

LIN2

HIN
50%

50%

ITRIP

LIN

50%
50%

SD
FLTCLR

50%

LO
50%

FAULT

50%

50%

50%

HO
LO2
DT

DT

Figure 3. Deadtime Waveform Definitions

4312

tflt
titrip

50%

50%
tfltclr

tsd

Figure 4. Shutdown Waveform Definitions

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Power Products Division

Advance Information

SELF-OSCILLATING
HALF-BRIDGE DRIVER
The MPIC2151 is a high voltage, high speed, selfoscillating power MOSFET
and IGBT driver with both high side and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The frontend features a programmable oscillator which is similar
to the 555 timer. The output drivers feature a high pulse current buffer stage and an
internal deadtime designed for minimum driver crossconduction. Propagation delays for the two channels are matched to simplify use in 50% duty cycle applications. The floating channel can be used to drive an Nchannel power MOSFET or
IGBT in the high side configuration that operates off a high voltage rail from 10 to
600 volts.

SELFOSCILLATING
HALFBRIDGE
DRIVER

8
1

Floating Channel Designed for Bootstrap Operation


Fully Operational to +600 V
Tolerant to Negative Transient Voltage

P SUFFIX
PLASTIC PACKAGE
CASE 62605

dV/dt Immune
Undervoltage Lockout
Programmable Oscillator Frequency:

MPIC2151

+ 1.4 (RT )1 75W) CT

Matched Propagation Delay for Both Channels

Low Side Output In Phase with RT

PRODUCT SUMMARY
VOFFSET

600 V MAX

Duty Cycle

50%

VOUT

10 20 V

tr/f (typical)

120 & 60 ns

Deadtime (typical)

1.2 s

D SUFFIX
PLASTIC PACKAGE
CASE 75105
(SO8)

PIN CONNECTIONS
VCC 1

8 VB

RT 2

7 HO

CT 3

6 VS

COM 4

5 LO

(TOP VIEW)

ORDERING INFORMATION

This document contains information on a new product. Specifications and information herein are subject
to change without notice.

Device

Package

MPIC2151D

SOIC

MPIC2151P

PDIP

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4313

MPIC2151
SIMPLIFIED BLOCK DIAGRAM

VB
R

HV
LEVEL
SHIFT

RT

+
R

DEAD
TIME

Q
PULSE
FILTER

HO

PULSE
GEN

VS
VCC

CT

R
S

15.6 V
DEAD
TIME

UV
DETECT

LO

DELAY

COM

ABSOLUTE MAXIMUM RATINGS


Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are
measured under board mounted and still air conditions.
Rating
High Side Floating Su
Supply
ly Absolute Voltage
High
g Side Floating
g Supplyy Offset Voltage
g
High
g Side Floating
g Output Voltage
g
Low Side Output Voltage
g
RT Voltage
CT Voltage
Supply
y Current ((Note 1))
High Side Output Current
Low Side Output Current
RT O
Output
Currentt
t tC
Allowable Offset Supply Voltage Transient
*Package Power Dissipation @ TC +25C

(8 Lead DIP)
(8 Lead SOIC)

Operating and Storage Temperature


Thermal Resistance, Junction to Ambient

(8 Lead DIP)
(8 Lead SOIC)

Lead Temperature for Soldering Purposes, 10 seconds

Symbol

Min

Max

Unit

VB
VS
VHO
VLO
VRT
VCT
ICC
IHO
ILO
IRT

0.3
0.3
VB25
VS0.3
0.3
0.3
0.3

625
VB+0.3
VB+0.3
VCC+0.3
VCC+0.3
VCC+0.3

VDC

500
500
5.0
50

25
500
500
5.0
50

mADC

dVS/dt

50

V/ns

PD

1.0
0.625

Watt

Tj, Tstg

55

150

RJA

125
200

C/W

TL

260

RECOMMENDED OPERATING CONDITIONS


The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions.
High Side Floating Supply Absolute Voltage

VB

VS+10

VS+Vclamp

High Side Floating Supply Offset Voltage

VS

600

High Side Floating Output Voltage

VHO

VS

VB

Low Side Output Voltage

VLO

VCC

Supply Current (Note 1)

ICC

5.0

mA

TA
40
125
C
Note 1: Because the MPIC2151 is designed specifically for offline supply systems, this IC contains a zener clamp structure between the chip
VCC and COM which has a nominal breakdown voltage of 15.6 V. Therefore, the IC supply voltage is normally derived by forcing current into
the supply lead (typically by means of a high value resistor connected between the chip VCC and the rectified line voltage and a local decoupling capacitor from VCC to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. Therefore, this circuit
should not be driven by a DC, low impedance power source of greater than VCLAMP.
Ambient Temperature

4314

Motorola TMOS Power MOSFET Transistor Device Data

MPIC2151
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise specified)
Characteristic

Symbol

Min

Typ

Max

Unit

VDC

STATIC ELECTRICAL CHARACTERISTICS


Supply Characteristics
VBIAS (VCC, VBS) = 12 V, VSS = COM and CL = 1000 pF unless otherwise specified.
VCC Supply Undervoltage Positive Going Threshold

VCCUV+

8.4

VCC Supply Undervoltage Negative Going Threshold

VCCUV

8.0

IQCC

400

VCLAMP

15.6

VDC

ILK

50

ADC

IQBS

10

Oscillator Frequency @ RT = 35.7 K, CT = 1 nF

fOSC

20

Oscillator Frequency @ RT = 7.04 K, CT = 1 nF

fOSC

100

ICT

0.001

1.0

A
mV

Quiescent VCC Supply Current


VCC Zener Shunt Clamp Voltage @ IOC = 5 mA
Floating Supply Characteristics
Offset Supply Leakage Current @ VB = VS = 600 V
Quiescent VBS Supply Current
Oscillator I/O Characteristics

CT Input Current
CT Undervoltage Lockout @ 2.5 V < VCC < VCCUV+

kHz

VCTUV

RT High Level Output Voltage, VCC RT @ IRT = 100 A


@ IRT = 1 mA

VRT+
VRT+

20
200

RT Low Level Output Voltage, VCC + RT @ IRT = 100 A


@ IRT = 1 mA

VRT
VRT

20
200

VRTUV

2/3 VCC Threshold

VCT+

8.0

1/3 VCC Threshold

VCT

4.0

High Level Output Voltage, VBIASVO @ IO = 0 A

VOH

100

Low Level Output Voltage, VO @ IO = 0 A

VOL

100

TurnOn Rise Time

tr

120

TurnOff Fall Time

tf

60

Deadtime, LS TurnOff to HS TurnOn & HS TurnOff to LS TurnOn

DT

1.2

RT Duty Cycle, fOSC = 20 kHz

DC

50

RT Undervoltage Lockout, VCC RT

@ 2.5 V < VCC < VCCUV+

VDC

Output Characteristics
mV

Dynamic Electrical Characteristics


VBIAS (VCC, VBS) = 12 V and CL = 1000 pF unless otherwise specified. TA = 25C.

Motorola TMOS Power MOSFET Transistor Device Data

ns

4315

MPIC2151
TYPICAL CONNECTION
10 TO 600 V

VCC

VB

RT

HO

CT

VS

COM

LO

TO
LOAD

LEAD DEFINITIONS
Symbol

Lead Description

RT

Oscillator timing resistor input; a resistor is connected from RT to CT. RT is in phase with LO for normal IC operation.

CT

Oscillator timing capacitor input; a capacitor is connected from CT to COM in order to program the oscillator frequency
according to the following equation:
1

+ 1.4 (RT ) 75W) CT

where 75 is the effective impedance of the RT output stage.


VB

High Side Floating Supply

HO

High Side Gate Drive Output

VS

High Side Floating Supply Return

VCC

Logic and Low Side Fixed Supply

LO

Low Side Gate Drive Output

COM

Logic and Low Side Return

VCCUV+
VCLAMP

VCC

RT(HO)
50%

RT

50%

RT(LO)

CT

tr

tf
90%

HO
LO
HO
LO

Figure 1. Input / Output Timing Diagram

RT

10%

90%
10%

Figure 2. Switching Time Waveform Definitions

50%

50%

90%
HO

10%
DT

LO

90%
10%

Figure 3. Deadtime Waveform Definitions

4316

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB1N100E
Motorola Preferred Device

TMOS POWER FET


1.0 AMPERES
1000 VOLTS
RDS(on) = 9.0 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

1000

Vdc

1000

Vdc

20
40

Vdc
Vpk

ID
ID
IDM
PD

1.0
0.8
3.0

Adc

75
0.6
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

45

mJ

RJC
RJA
RJA
TL

1.67
62.5
50

C/W

260

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4317

MTB1N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1.251

Vdc
mV/C

10
100

100

nAdc

2.0

6.0

4.0

Vdc
mV/C

6.7

9.0

Ohm

4.86

9.0
10.5

gFS

0.9

1.32

mhos

Ciss

587

810

pF

Coss

59.6

120

Crss

12.2

25

td(on)

9.0

20

tr

12

25

td(off)

28

50

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 500 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time

ns

tf

34

70

QT

14.6

20

Q1

2.8

Q2

6.8

Q3

5.2

0.764
0.62

1.0

trr

655

ta

42

tb

613

QRR

0.957

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4318

Motorola TMOS Power MOSFET Transistor Device Data

MTB1N100E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

2.0
TJ = 25C

1.4

5V

1.2
1.0
0.8
0.6
0.4

10

12

14

18

16

1.0

25C

0.8
0.6
0.4

TJ = 55C
3.6

4.0

4.4

4.8

25C

6
4
55C

2
0.2

0.4

0.6
1.4
0.8 1.0 1.2
ID, DRAIN CURRENT (AMPS)

1.6

1.8

2.0

5.2

5.6

8.0
TJ = 25C

7.8
7.6
7.4
7.2
7.0

VGS = 10 V

6.8
6.6

15 V

6.4
6.2
6.0

Figure 3. OnResistance versus Drain Current


and Temperature

0.2

0.4

0.6 0.8 1.0


1.2
1.4
ID, DRAIN CURRENT (AMPS)

1.6

1.8

2.0

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.8

TJ = 125C

VGS = 10 V
ID = 0.5 A

1000
100C

2.0

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.2

Figure 2. Transfer Characteristics

10

1.6
1.2
0.8

100
10
1.0

25C

0.1

0.4
0
50

2.8

Figure 1. OnRegion Characteristics

TJ = 100C

2.4

2.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

1.4

0
2.0

20

16
14

100C

1.6

0.2

4V

0.2
0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

6V

1.6

VDS 10 V

1.8

VGS = 10 V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

1.8

VGS = 0 V
0.01
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100

200 300 400 500 600 700 800 900 1000


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

4319

MTB1N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

1000
VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C
VGS = 0 V

800

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000

Ciss
600

Crss

400
Coss

200
Crss

0
10

5
VGS

TJ = 25C

100
Coss
10

Crss

1
5

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4320

Ciss

25

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

480
QT
400

10
8

320

VGS
Q1

Q2

240
ID = 1 A
TJ = 25C

160

80
Q3

VDS

0
0

4 5 6 7 8 9 10 11 12 13 14
QG, TOTAL GATE CHARGE (nC)

0
15

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB1N100E
VDD = 500 V
ID = 1 A
VGS = 10 V
TJ = 25C

100

tf
td(off)

tr
td(on)

10

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C

0.8

0.6

0.4

0.2

0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4321

MTB1N100E
SAFE OPERATING AREA
50
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

1.0
10 s
100 s
1 ms
10 ms

0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 1 A
40

30

20

10

0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1

0.05
0.02
t1

0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4322

PD, POWER DISSIPATION (WATTS)

3
2.5

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB2N40E
Motorola Preferred Device

TMOS POWER FET


2.0 AMPERES
400 VOLTS
RDS(on) = 3.8 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

400

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

400

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.5
6.0

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

40
0.32
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

45

mJ

RJC
RJA
RJA

3.13
62.5
50

C/W

TL

260

Rating
DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance

Junction to Case
Junction to Ambient
Junction to Ambient (1)

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4323

MTB2N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

451

10
100

100

nAdc

2.0

3.2
7.0

4.0

Vdc
mV/C

3.1

3.5

Ohm

7.3

8.4
7.4

gFS

0.5

1.0

mhos

Ciss

229

320

pF

Coss

34

40

Crss

7.3

10

td(on)

8.0

16

tr

8.4

14

td(off)

12

26

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 200 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 320 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

tf

11

20

QT

8.6

12

Q1

2.6

Q2

3.2

Q3

5.0

0.88
0.76

1.2

trr

156

ta

99

tb

57

QRR

0.89

4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc )


(IS = 2.0 Adc, VGS = 0 Vdc , TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 2.0 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4324

Motorola TMOS Power MOSFET Transistor Device Data

MTB2N40E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V
8V

3.2

ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

7V
2.4
6V

1.6

0.8

VDS 10 V

1
TJ = 100C

5V

12

16

20

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 25C

55C

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

5.0
TJ = 25C
4.5

4.0
VGS = 10 V
3.5

15 V

3.0

2.5
0.5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

1000
VGS = 10 V
ID = 1 A

VGS = 0 V

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 2. Transfer Characteristics

VGS = 10 V

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


8

25C
55C

1.5

TJ = 125C
100

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

10
0

100
200
300
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400

Figure 6. DrainToSource Leakage


Current versus Voltage

4325

MTB2N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

500

VGS = 0 V

Ciss

300
Ciss

Crss
200

4326

Ciss

Coss
10
Crss

Crss
5

TJ = 25C
VGS = 0

100

Coss

100
0
10

1000

TJ = 25C

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

400

VDS = 0 V

10

15

20

25

1
10

100

1000

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

400
QT

10

300

VGS

8
6

200

Q2

Q1
4

TJ = 25C
ID = 2 A

2
0

VDS

Q3
0

100

100

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTB2N40E

td(off)
tf

10

tr

TJ = 25C
ID = 2 A
VDD = 200 V
VGS = 10 V

td(on)

10
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
1.5

0.5

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4327

MTB2N40E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms

10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

45

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

100

ID = 2 A

40
35
30
25
20
15
10
5
0

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1

0.05
P(pk)
0.02
0.01
SINGLE PULSE
t1

t2
DUTY CYCLE, D = t1/t2
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4328

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB2N60E
Motorola Preferred Device

TMOS POWER FET


2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

600

Vdc

600

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.3
7.0

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

50
0.4
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

190

mJ

RJC
RJA
RJA

2.5
62.5
50

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25 )
Thermal Resistance

Junction to Case
Junction to Ambient
Junction to Ambient (1)

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4329

MTB2N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

480

0.25
1.0

100

nAdc

2.0

3.1
8.5

4.0

Vdc
mV/C

3.0

3.8

Ohm

8.2
8.4

gFS

1.0

mhos

Ciss

435

pF

Coss

100

Crss

20

td(on)

12

tr

21

td(off)

30

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 300 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 18 )

Fall Time

tf

24

QT

13

Q1

2.0

Q2

6.0

Q3

5.0

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

VSD

1.0
0.9

1.6

(IS = 2.0 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

trr

340

3.5

7.5

Gate Charge
(S Fi
(See
Figure 8)
((VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Reverse Recovery Time

Vdc
ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4330

Motorola TMOS Power MOSFET Transistor Device Data

MTB2N60E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V

VDS 10 V

7V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

3
6V
2
5.5 V
1

4
TJ = 100C

55C
25C

5V
0

12

16

20

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

12
100C

VGS = 10 V

8
TJ = 25C

4
55C

1.5

4.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

4.5
TJ = 25C

4.3
4.1
3.9
3.7

VGS = 10 V

3.5
3.3

15 V

3.1
2.9
2.7
2.5
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

0.5

1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage
1000

2.5
VGS = 10 V
ID = 1 A

VGS = 0 V
TJ = 125C

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

10

1.5

100
100C

10

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

1
0

100
300
500
200
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

4331

MTB2N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800
700

VDS = 0 V

VGS = 0 V

Ciss

Ciss

500

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

600

400

Ciss
Crss

300
200

4332

100
Coss
10
Crss
1

Coss
Crss

100
0
10

1000

TJ = 25C

10

15

20

25

0.1

TJ = 25C
VGS = 0
10

100

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance


Variation

1000

Motorola TMOS Power MOSFET Transistor Device Data

12

TJ = 25C
ID = 2 A

VDS

400
QT

9
6

VDS = 100 V
VDS = 250 V
VDS = 400 V

Q1

300
200

Q2
3

00

100

VGS
Q3
4

12

16

20

1000

TJ = 25C
ID = 2 A
VDS = 300 V
VGS = 10 V

100

td(off)

t, TIME (ns)

500

15

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTB2N60E
tf
tr

td(on)
10

1
1

10
100
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

1000

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4333

MTB2N60E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms

10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

200

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

Peak IL = 2 A
VDD = 50 V

150

100

50

0
25

10

100

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

1000

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4334

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB2P50E
Motorola Preferred Device

TMOS POWER FET


2.0 AMPERES
500 VOLTS
RDS(on) = 6.0 OHM

PChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDSS
VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

ID
ID
IDM
PD

2.0
1.6
6.0

Adc

75
0.6
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

80

mJ

RJC
RJA
RJA
TL

1.67
62.5
50

C/W

260

Rating
DrainSource Voltage

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4335

MTB2P50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

564

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
4.0

4.0

Vdc
mV/C

4.5

6.0

Ohm

9.5

14.4
12.6

gFS

1.5

2.9

mhos

Ciss

845

1183

pF

Coss

100

140

Crss

26

52

td(on)

12

24

tr

14

28

td(off)

21

42

tf

19

38

QT

19

27

Q1

3.7

Q2

7.9

Q3

9.9

2.3
1.85

3.5

trr

223

ta

161

tb

62

QRR

1.92

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 2.0 Adc,


VGS = 10 dc,
dc
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4336

Motorola TMOS Power MOSFET Transistor Device Data

MTB2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4

4
7V
8V

6V
2.5
2
1.5
5V

VDS 10 V

3.5
I D , DRAIN CURRENT (AMPS)

3.5
I D , DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25C

0.5

25C

3
TJ = 55C

2.5

100C

2
1.5
1
0.5

4V
0

12

16

20

24

4.5

5.5

Figure 2. Transfer Characteristics

TJ = 100C

6
25C
4
55C
2

0.5

3
1.5
2.5
2
ID, DRAIN CURRENT (AMPS)

3.5

6.5

6
TJ = 25C

5.75
5.5
5.25

VGS = 10 V

15 V

4.75
4.5
4.25
4

Figure 3. OnResistance versus Drain Current


and Temperature

0.5

2
3
1.5
2.5
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000
VGS = 0 V

VGS = 10 V
ID = 1 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.5

Figure 1. OnRegion Characteristics

1.5

0.5
50

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

28

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100
100C

10
25C

50

100 150 200 250 300 350 400 450


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

4337

MTB2P50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1800
1600

1000
VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1400
1200
1000

Ciss

800
600

Crss

400
200
0
10

Ciss

VGS = 0 V
TJ = 25C

Ciss
100

Coss
Crss
10

Coss

Crss

1
5

0
VGS

10

15

20

25

VDS

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4338

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

300
QT

10

250
VGS

8
Q1

200

Q2

150

ID = 2 A
TJ = 25C

100

50
VDS

Q3
0

10

12

14

16

18

0
20

1000
VDD = 250 V
ID = 2 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB2P50E

100
tf

td(off)

tr
td(on)
10

10

QG, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

2
VGS = 0 V
TJ = 25C

1.6

1.2

0.8

0.4

0
0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4339

MTB2P50E
SAFE OPERATING AREA
80
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s

1 ms
10 ms

ID = 2 A

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

dc

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

60

40

20

0.01
0.1

10

100

0
25

1000

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
P(pk)

0.05

0.1
0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E01

1.0E+01

1.0E+00

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

PD, POWER DISSIPATION (WATTS)

3
2.5

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.0
1.5
1
0.5
0
25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

4340

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB3N100E
Motorola Preferred Device

TMOS POWER FET


3.0 AMPERES
1000 VOLTS
RDS(on) = 4.0 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

1000

Vdc

1000

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

3.0
2.4
9.0

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

245

mJ

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 7.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4341

MTB3N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1.23

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
6.0

4.0

Vdc
mV/C

2.96

4.0

Ohm

4.97

14.4
12.6

gFS

2.0

3.56

mhos

Ciss

1316

1800

pF

Coss

117

260

Crss

26

75

td(on)

13

25

tr

19

40

td(off)

42

90

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time

ns

tf

33

55

QT

32.5

45

Q1

6.0

Q2

14.6

Q3

13.5

0.794
0.63

1.1

trr

615

ta

104

tb

511

QRR

2.92

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 3.0 Adc, VGS = 0 Vdc)


(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4342

Motorola TMOS Power MOSFET Transistor Device Data

MTB3N100E
TYPICAL ELECTRICAL CHARACTERISTICS
6

6
VGS = 10 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

6V

5V
3
2

VDS 10 V

100C

5
4
25C

3
2

TJ = 55C

1
4V
0

6
8
10
12
14
16 18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

20

2.4

2.8
3.2 3.6
4.0 4.4 4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

TJ = 100C

4
25C
3

2
55C
1
1.0

1.5

2.5

2.0

3.0

3.5

4.0

4.5

5.0

6.0

5.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

6
VGS = 10 V

6.0

5.5

6.0

Figure 2. Transfer Characteristics

3.8
TJ = 25C
3.6

VGS = 10 V

3.4

3.2

15 V

3.0

2.8
1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage
100000

2.4

2.0

VGS = 10 V
ID = 1.5 A

VGS = 0 V

1.6

1.2

100C
1000

100
25C
10

0.8

0.4
50

TJ = 125C

10000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

5.6

1
25

25

50

75

100

125

150

100

200

300

400

500

600

700

800

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

900 1000

4343

MTB3N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800

10000

Ciss

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000
2000
Ciss

1600
Crss

1200
800

100
Coss
Crss

10

Coss

400

Crss

10

5
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4344

TJ = 25C

VGS = 0 V

2400

25

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

400

14

350
QT

12

300
250

10
8

200

VGS
Q1

Q2

150
ID = 3 A
TJ = 25C

4
2

50

Q3

VDS

0
0

100

12
16
20
24
QG, TOTAL GATE CHARGE (nC)

28

0
30

1000
VDD = 500 V
ID = 3 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB3N100E

100

td(off)
tf
tr
td(on)

10
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


3.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

2.5
2.0
1.5
1.0
0.5
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78 0.80

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4345

MTB3N100E
SAFE OPERATING AREA
250
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms

0.1

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

ID = 3 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

dc

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

150

100

50

0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05

t1

0.02

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4346

PD, POWER DISSIPATION (WATTS)

3.0
2.5

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.0
1.5
1.0
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB3N120E
Motorola Preferred Device

TMOS POWER FET


3.0 AMPERES
1200 VOLTS
RDS(on) = 5.0 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

CASE 418B02, Style 2


D2PAK

Avalanche Energy Capability Specified at Elevated Temperature


S
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery time Comparable to Discrete Fast Recovery Diode
* See App. Note AN1327 Very Wide Input Voltage Range; Offline Flyback Switching Power Supply
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

DrainSource Voltage

VDSS

1200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1200

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

3.0
2.2
11

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg

55 to 150

Rating

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
101

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4347

MTB3N120E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

1.28

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

4.0

5.0

Ohm

18.0
15.8

gFS

2.5

3.1

mhos

Ciss

2130

2980

pF

Coss

1710

2390

Crss

932

1860

td(on)

13.6

30

tr

12.6

30

td(off)

35.8

70

tf

20.7

40

QT

31

40

Q1

8.0

Q2

11

Q3

14

0.80
0.65

1.0

trr

394

ta

118

tb

276

QRR

2.11

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1200 Vdc, VGS = 0 Vdc)
(VDS = 1200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 600 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 600 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 3.0 Adc, VGS = 0 Vdc)


(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4348

Motorola TMOS Power MOSFET Transistor Device Data

MTB3N120E
TYPICAL ELECTRICAL CHARACTERISTICS
6

6
TJ = 25C

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VDS 10 V

VGS = 10 V

6V

3
5V

5
100C

4
3
2
25C
1

TJ = 55C

4V
0

12

24

18

30

3.4

3.8

4.2

4.6

5.0

5.4

5.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

TJ = 100C

4
25C

2
55C

6.2

5.4
TJ = 25C
5.0
VGS = 10 V

4.6

15 V
4.2

3.8

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

2.0

10,000
VGS = 0 V

VGS = 10 V
ID = 1.5 A

TJ = 125C
1,000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

1.0

0.5

0
50

25

25

50

75

100

125

150

100C
100
25C
10

200

400

600

800

1000

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

1200

4349

MTB3N120E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

10,000

2800
Ciss VDS = 0 V

VGS = 0 V
TJ = 25C

TJ = 25C

Ciss

2000
1600

Crss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

2400

VGS = 0 V

Ciss

1200
800

Coss

1,000

Coss

100

400

Crss

Crss
0

10

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4350

25

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

MTB3N120E
350

12

300
QT

10

250

8
Q2

Q1

150
ID = 3 A
TJ = 25C

4
2
0

200

VGS

50

VDS

Q3
8

12

16

100

20

24

28

0
32

1000

t, TIME (ns)

14

VGS, GATETOSOURCE VOLTAGE (VOLTS)

400

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

16

VDD = 600 V
ID = 3 A
VGS = 10 V
TJ = 25C

100

td(off)
tf
td(on)
tr

10

Qg, TOTAL GATE CHARGE (nC)

10
RG, GATE RESISTANCE (OHMS)

10

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


3.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

2.4

1.8

1.2

0.6

0
0.55

0.59

0.63

0.67

0.71

0.75

0.79

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4351

MTB3N120E
SAFE OPERATING AREA

10

120
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1.0
1 ms
10 ms
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

dc

1,000

100

ID = 3 A
100
80
60
40
20
0

10,000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r (t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

0.01
1.0E05

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4352

Motorola TMOS Power MOSFET Transistor Device Data

MTB3N120E

L1

H1
90VAC
600VAC

C1
0.1
1 kV

D1 D4
1N4007s
C4
0.1
1 kV

L1

+Vin

H2
C3
0.0047
3 kV

C2
0.0047
3 kV

EARTH
GND

C6
100 mF
450 V

C5
100 mF
450 V

R4

470 k
1/2 W

R3

470 k
1/2 W

R2

470 k
1/2 W

R1

470 k
1/2 W
INPUT GND

Figure 15. The AC Input/Filter Circuit Section

T1

C11
D8
100 mF
MBR370 10 V

+Vin
R9
R8

100 mF
20 V

D9
MUR430

Vaux

82 k, 1/2 W
R7

R6

R5

R16
100 k
1/2 W

10 mF
25 V
+

D10

+
C13

C9

LL

MUR1100

4
C7
220 pF

1
U2
1/2
MOC8102

R12 10 W
R15
680 W

U2
MOC8102

D6

D7

R13
1k

R20
120 W
C15
1.5 nF

R19
32.4 k

1.3 mF 7.5 k

C17
2.2 nF

Q1

C8
1000 pF

+5 V

C14

MTP3N120E

UC3845BN

D5
3.3 V

C12

Vaux

7
R10
27 k

MUR130

C10

R11
1.8 k

1 nF
3 kV

+12 V

U3
TL431

C16 R17
R21
2.49 k
GND

R14
1.2 W
1/2 W

INPUT GND

Figure 16. The DC/DC Converter Circuit Section

Motorola TMOS Power MOSFET Transistor Device Data

4353

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB4N80E
Motorola Preferred Device

TMOS POWER FET


4.0 AMPERES
800 VOLTS
RDS(on) = 3.0 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

800

Vdc

800

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

4.0
2.9
12

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

320

mJ

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2

4354

Motorola TMOS Power MOSFET Transistor Device Data

MTB4N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

1.02

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

1.95

3.0

Ohm

8.24

12
10

gFS

2.0

4.3

mhos

Ciss

1320

2030

pF

Coss

187

400

Crss

72

160

td(on)

13

30

tr

36

90

td(off)

40

80

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 4.0 Adc)
(ID = 2.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time

ns

tf

30

75

QT

36

80

Q1

7.0

Q2

16.5

Q3

12

0.812
0.7

1.5

trr

557

ta

100

tb

457

QRR

2.33

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 4.0 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 4.0 Adc, VGS = 0 Vdc)


(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4355

MTB4N80E
TYPICAL ELECTRICAL CHARACTERISTICS
8

8
TJ = 25C

6V

5
5V

4
3
2
1
0

6
5

100C

4
25C
3
2
TJ = 55C

4V
0

VDS 10 V

VGS = 10 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

6
8
10
12
14
16
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

20

4.6
VGS = 10 V
3.8

TJ = 100C

3.0
25C

2.2

1.4
55C
0.6
1

3
4
5
6
ID, DRAIN CURRENT (AMPS)

TJ = 25C

2.5
2.4
2.3
2.2

VGS = 10 V

2.1
2.0

15 V

1.9
1.8
1

3
4
5
6
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.2
VGS = 10 V
ID = 2 A

VGS = 0 V
TJ = 125C
1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

5.6

2.6

Figure 3. OnResistance versus Drain Current


and Temperature

1.8

2.8
3.2
3.6
4.0
4.4
4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.4

1.4

1.0

100C

100

25C

10

0.6

0.2
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4356

150

100

700
200
300
400
500
600
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB4N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800

10000
VDS = 0 V

Ciss

2400

VGS = 0 V

TJ = 25C

VGS = 0 V

TJ = 25C
Ciss

1600

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000
2000
Ciss
Crss

1200
800

100
Coss
Crss

10

Coss

400
Crss
0
10

0
VGS

1
10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

25

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

4357

500
QT

400
VGS
Q1

Q2

300

200
ID = 4 A
TJ = 25C

100
VDS

Q3
0
0

12
18
24
QG, TOTAL GATE CHARGE (nC)

30

0
36

1000
VDD = 400 V
ID = 4 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB4N80E

100
tf
td(off)

tr

td(on)

10
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


4.0

I S , SOURCE CURRENT (AMPS)

3.6

VGS = 0 V
TJ = 25C

3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4358

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB4N80E
SAFE OPERATING AREA
350
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1.0

1 ms
10 ms
dc

0.1

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 4 A

300
250
200
150
100
50
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05

t1

0.02

t2
DUTY CYCLE, D = t1/t2

0.01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

4359

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB6N60E
Motorola Preferred Device

TMOS POWER FET


6.0 AMPERES
600 VOLTS
RDS(on) = 1.2 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

600

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR
VGS
VGSM

600

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

6.0
4.6
18

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Rating

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

C
mJ

405
RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4360

Motorola TMOS Power MOSFET Transistor Device Data

MTB6N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

0.94

1.2

Ohms

6.0

8.6
7.6

gFS

2.0

5.5

mhos

Ciss

1498

2100

pF

Coss

158

217

Crss

29

56

td(on)

14

30

tr

19

40

td(off)

40

80

tf

26

50

QT

35.5

50

Q1

8.1

Q2

14.1

Q3

15.8

0.83
0.72

1.5

trr

266

ta

166

tb

100

QRR

2.5

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDS = 300 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 300 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4361

MTB6N60E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12
VGS = 10 V

VDS 10 V

6V

10

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

7V
8V

8
6
5V
4

10
8
6
4
100C

2
4V
0

TJ = 55C
0

18

4
8
12
16
6
10
14
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

2.0

2.5
VGS = 10 V
2.0
TJ = 100C
1.5
25C
1.0
55C
0.5

6
4
8
ID, DRAIN CURRENT (AMPS)

10

12

6.0

TJ = 25C
1.3
1.2
1.1

VGS = 10 V

1.0
15 V
0.9
0.8
0

4
6
8
ID, DRAIN CURRENT (AMPS)

10

12

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 3 A

VGS = 0 V

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.5

1.5

0.5

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4362

3.0
4.0
5.0
3.5
4.5
5.5
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.4

Figure 3. OnResistance versus Drain Current


and Temperature

0
50

2.5

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

25C

150

100C
100

25C

10

1
0

100
200
300
400
500
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB6N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3200

VDS = 0 V

VGS = 0 V

TJ = 25C

10000

TJ = 25C
VGS = 0 V

Ciss

1600

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

2400

Ciss

Crss

800

Ciss

1000

Coss

100

Crss
10

Coss
0
10

Crss
5

0
VGS

10

15

20

25

10

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4363

300
QT

10
8

VGS
Q1

Q2

ID = 6 A
TJ = 25C

2
Q3
0

200

VDS
12

24

18

30

100

0
36

100

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB6N60E
VDD = 300 V
ID = 6 A
VGS = 10 V
TJ = 25C

td(off)
tf
tr
td(on)

10

10

QT, TOTAL CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
5

VGS = 0 V
TJ = 25C

4
3
2
1
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4364

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB6N60E

I D , DRAIN CURRENT (AMPS)

100

EAS, SINGLE PULSE DRAINNTOSOURCE


AVALANCHE ENERGY (mJ)

SAFE OPERATING AREA


VGS = 20 V
SINGLE PULSE
TC = 25C
10 s
10
100 s
1 ms
1.0

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10

dc

100

450
ID = 6 A

400
350
300
250
200
150
100
50
0

1000

25

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

4365

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTB8N50E

TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

500

Vdc

500

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

8.0
5.0
32

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

510

mJ

RJC
RJA
RJA

1.0
40
50

C/W

TL

260

DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 15.9 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

4366

Motorola TMOS Power MOSFET Transistor Device Data

MTB8N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

500

Vdc
mV/C

250
1000

100

nAdc

2.0

5.0

4.0

Vdc
mV/C

0.6

0.8

Ohms

7.2
6.4

gFS

4.0

mhos

Ciss

1200

1800

pF

Coss

176

264

Crss

72

108

td(on)

25

50

tr

36

72

td(off)

75

150

tf

30

60

QT

92

125

Q1

12

Q2

45

Q3

35

1.1
1.0

2.0

trr

420

ta

280

tb

140

QRR

4.4

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 4.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 50 Vdc, ID = 4.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 8.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 400 Vdc, ID = 8.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 8.0 Adc, VGS = 0 Vdc)


(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 8.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4367

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB9N25E
Motorola Preferred Device

TMOS POWER FET


9.0 AMPERES
250 VOLTS
RDS(on) = 0.45 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
S

CASE 418B02, Style 2


D2PAK

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

250

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

250

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

9.0
5.7
32

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

80
0.64
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Rating
DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance

Junction to Case
Junction to Ambient
Junction to Ambient (1)

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

mJ
122

RJC
RJA
RJA

1.56
62.5
50

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

4368

Motorola TMOS Power MOSFET Transistor Device Data

MTB9N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

328

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.37

0.45

Ohm

3.5

5.4
4.7

gFS

3.0

5.2

mhos

Ciss

783

1100

pF

Coss

144

200

Crss

32

65

td(on)

10

20

tr

36

70

td(off)

27

55

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 4.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 125 Vdc, ID = 9.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 200 Vdc, ID = 9.0 Adc,


VGS = 10 Vdc)

tf

26

50

QT

26

40

Q1

4.8

Q2

12.7

Q3

9.2

0.9
0.81

1.5

trr

191

ta

126

tb

65

QRR

1.387

4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 9.0 Adc, VGS = 0 Vdc )


(IS = 9.0 Adc, VGS = 0 Vdc , TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 9.0 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4369

MTB9N25E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

TJ = 25C

18

VGS = 10 V
9V

15

VDS 10 V

8V
7V

I D , DRAIN CURRENT (AMPS)

18

12
9
6V
6
3

25C

12

100C
9
6
3

5V

0
0

2
4
6
8
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

1.2
VGS = 10 V
1.0
0.8
TJ = 100C
0.6
25C
0.4
0.2

55C

0
0

6
9
12
ID, DRAIN CURRENT (AMPS)

3
4
5
6
7
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

15

18

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics


0.6

TJ = 25C

0.5

VGS = 10 V
0.4
15 V

0.3
0

Figure 3. OnResistance versus Drain Current


and Temperature

6
9
12
ID, DRAIN CURRENT (AMPS)

15

18

Figure 4. OnResistance versus Drain Current


and Gate Voltage
1000

2.5

VGS = 0 V

VGS = 10 V
ID = 4.5 A
2.0

TJ = 125C

100
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C

15

1.5

1.0

100C
10
25C
1

0.5

0
50

0.1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4370

150

50
100
150
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB9N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

VDS = 0 V

1600
C, CAPACITANCE (pF)

VGS = 0 V

TJ = 25C

Ciss

1200

Ciss
Crss

800

Coss

400
0

Crss
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4371

240

12

180

QT
VGS

8
Q1

120

Q2

ID = 9 A
TJ = 25C

60

Q3
0

VDS
0

24

12
18
QT, TOTAL CHARGE (nC)

0
30

1000

t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB9N25E
VDD = 250 V
ID = 9 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
10

tf

td(on)

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

9.0
7.5

VGS = 0 V
TJ = 25C

6.0
4.5
3.0
1.5
0
0.5

0.55

0.65
0.75
0.85
0.6
0.7
0.8
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.9

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4372

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB9N25E
SAFE OPERATING AREA
125

VGS = 20 V
SINGLE PULSE
TC = 25C
10 s

10

100 s
1

1 ms
10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

ID = 9 A
100

75

50

25
0

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE
0.01
0.00001

t2
DUTY CYCLE, D = t1/t2

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0

10

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

4373

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB10N40E
Motorola Preferred Device

TMOS POWER FET


10 AMPERES
400 VOLTS
RDS(on) = 0.55 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

G
CASE 418B02, Style 2
D2PAK

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

VDSS
VDGR
VGS

400

Vdc

400

Vdc

20

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

10
6.0
40

Amps

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.00
2.5

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vpk, IL = 10 Apk, L = 10 mH, RG = 25 )

EAS

520

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.00
62.5
50

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

4374

Motorola TMOS Power MOSFET Transistor Device Data

MTB10N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

398

Vdc
mV/C

0.1
1.0

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

Adc

IDSS

GateBody Leakage CurrentForward


(Vgsf = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage CurrentReverse


(Vgsr = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0

2.8
6.3

4.0

Vdc
mV/C

0.4

0.55

Ohm

5.61

6.6
5.5

gFS

4.0

mhos

Ciss

1570

2200

pF

Coss

230

325

Crss

55

110

td(on)

25

50

tr

37

75

td(off)

75

150

tf

31

65

QT

46

63

Q1

10

Q2

23

Q3

0.9

2.0

trr

250

ns

QRR

3000

nC

3.5
4.5

7.5

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 10 Adc)
(ID = 5.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 200 Vdc, ID = 10 Adc,


VGS = 10 Vdc
Vdc,
RG = 10 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 320 Vdc, ID = 10 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

Reverse Recovery Time


(See Figure 14)
Reverse Recovery Stored Charge

(IS = 10 Adc, VGS = 0 Vdc)


(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)
(IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4375

MTB10N40E
TYPICAL ELECTRICAL CHARACTERISTICS
20

25
TJ = 25C

7V

16

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VDS 10 V

10 V

12

VGS = 6 V

20

15

10
TJ = 25C
5

55C

100C

5V
0

12

16

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

100C

1
TJ = 25C
0.5
55C

10

15

20

25

30

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.5

20

0.55
TJ = 25C
0.5
0.45
0.4

VGS = 10 V
15 V

0.35
0.3
0.25

10

15

20

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

VGS = 0 V

VGS = 10 V
ID = 5 A

40

TJ = 125C

20
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

10
100C
4
2
1
25C
0.4
0.2

0
50

4376

25

25

50

75

100

125

150

0.1
100

150

200

250

300

350

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

400

Motorola TMOS Power MOSFET Transistor Device Data

MTB10N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500
TJ = 25C

VGS = 0 V

C, CAPACITANCE (pF)

3000
2500
2000

Crss

Ciss

1500
1000
500

VDS = 0 V

0
10

Coss
0

VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4377

16

10000
TJ = 25C
ID = 10 A

VDS = 100 V
2000

250 V

12

VDD = 200 V
ID 10 A
VGS = 10 V
TJ = 25C

4000

t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB10N40E

320 V
8

1000

td(off)
tf
tr
td(on)

400
200
100

40
20

20

40

10

80

Qg, TOTAL CHARGE (nC)

10
100
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

60

1000

DRAINTOSOURCE DIODE CHARACTERISTICS


10
I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

8
7
6
5
4
3
2
1
0

0.2

0.4

0.6

0.8

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4378

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB10N40E
SAFE OPERATING AREA
100

I D , DRAIN CURRENT (AMPS)

40
20

10 s
100 s

10
4

1 ms

10 ms

1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.4
0.2
0.1

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

600
VGS = 20 V
SINGLE PULSE
TC = 25C

dc

10

100

ID = 10 A
450

300

150

0
25

1000

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t) , NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
0.7
0.5

D = 0.5

0.3
0.2

0.2
0.1

0.1
0.07
0.05

P(pk)

0.05

t1

t2
DUTY CYCLE, D = t1/t2

0.02

0.03
0.02

0.01

0.01
0.01

RJC(t) = r(t) RJC


RJC = 1C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE

0.02

0.05

0.1

0.2

0.5

10

20

50

100

200

500

1000

t,TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

PD, POWER DISSIPATION (WATTS)

3
RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4379

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTB15N06V

Designer's

TMOS
Power Field Effect Transistor
D2PAK for Surface Mount

TMOS POWER FET


15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

TM

G
S

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETs


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
8.7
45

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

55
0.37
3.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

113

mJ

RJC
RJA
RJA

2.73
62.5
50

C/W

TL

260

DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 2

4380

Motorola TMOS Power MOSFET Transistor Device Data

MTB15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

67

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
5.0

4.0

Vdc
mV/C

0.08

0.12

Ohm

2.0

2.2
1.9

gFS

4.0

6.2

mhos

Ciss

469

660

pF

Coss

148

200

Crss

35

60

td(on)

7.6

20

tr

51

100

td(off)

18

40

tf

33

70

QT

14.4

20

Q1

2.8

Q2

6.4

Q3

6.1

1.05
0.9

1.6

trr

59.3

ta

46

tb

13.3

QRR

0.165

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 15 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4381

MTB15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30

VGS = 10 V
9V

TJ = 25C
25

7V
20
15

6V

10
5V

25
100C
20

25C

15

TJ = 55C

10
5

0
1

0.2

10

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

0.14

TJ = 100C

25C
0.08

(o )

55C

0.02
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

10

15

20

25

30

0.13
TJ = 25C
0.11

VGS = 10 V

0.09

15 V
0.07

0.05

10

15

20

25

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

30

100

VGS = 0 V

VGS = 10 V
ID = 7.5 A
1.6
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS 10 V

8V
I D , DRAIN CURRENT (AMPS)

30

1.2

0.8

0.4
50

25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

4382

150

175

TJ = 125C

10

10

20

30

40

50

60

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements


complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500

C, CAPACITANCE (pF)

1200

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

900
Crss
600

Ciss

300

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4383

60
QT

10

50
VGS

40
Q1

Q2
30

6
ID = 15 A
TJ = 25C

20
10

2
VDS

Q3

0
0

6
9
QT, TOTAL CHARGE (nC)

12

0
15

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB15N06V
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25C

100

tr
tf
td(off)
10

td(on)

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

15
VGS = 0 V
TJ = 25C

12

0
0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4384

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB15N06V
SAFE OPERATING AREA
120

VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10
100 s
1 ms
10 ms

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

ID = 15 A

100
80
60
40
20
0

10

1.0

100

25

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01
SINGLE PULSE

0.01
1.0E05

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

t1

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

25

50

75

100

125

150

175

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4385

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB16N25E
Motorola Preferred Device

TMOS POWER FET


16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

250

Vdc

250

Vdc

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ TC = 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

16
10
56

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

384

mJ

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Rating
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4386

Motorola TMOS Power MOSFET Transistor Device Data

MTB16N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

333

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.17

0.25

Ohm

3.6

4.8
4.2

gFS

3.0

7.0

mhos

Ciss

1558

2180

pF

Coss

281

390

Crss

130

260

td(on)

15

30

tr

64

130

td(off)

56

110

tf

44

90

QT

53.4

70

Q1

9.3

Q2

27.5

Q3

17.1

0.915
1.39

1.5

trr

234

ta

170

tb

64

QRR

2.165

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 16 Adc)
(ID = 8.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 125 Vdc, ID = 16 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 16 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 16 Adc, VGS = 0 Vdc)


(IS = 16 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4387

MTB16N25E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

32

VGS = 10 V

TJ = 25C

VDS 10 V

8V
I D , DRAIN CURRENT (AMPS)

32

7V
24

6V

16

24

25C

16

100C

5V
TJ = 55C
0

0
1

0.5
TJ = 100C

0.4
0.3
0.2

25C

0.1

55C

0
5

10
15
20
25
ID, DRAIN CURRENT (AMPS)

35

30

Figure 2. Transfer Characteristics


0.26
TJ = 25C
0.22
VGS = 10 V
0.18

15 V

0.14

0.1
0

Figure 3. OnResistance versus Drain Current


and Temperature

16
24
ID, DRAIN CURRENT (AMPS)

32

40

Figure 4. OnResistance versus Drain Current


and Gate Voltage
1000

3.0

VGS = 0 V

VGS = 10 V
ID = 8 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

VGS = 10 V

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

2.0
1.5
1.0

100
100C

10
25C

0.5
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4388

150

50
150
250
100
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

300

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB16N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements


complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

4000
Ciss
3000

2000

Ciss

Crss

1000
0

10

5
VGS

Crss
5
0
VDS

Coss
10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4389

200

QT
VGS

150
Q1

Q2
100

6
ID = 16 A
TJ = 25C

3
Q3
0

10

VDS
50

40
20
30
QT, TOTAL CHARGE (nC)

50

0
60

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB16N25E
VDD = 250 V
ID = 16 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
td(on)

10

tf

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

16
VGS = 0 V
TJ = 25C
12

0
0.5

0.55

0.65 0.7
0.75 0.8
0.85 0.9
0.6
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.95

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4390

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB16N25E
SAFE OPERATING AREA
400

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

10

100 s

1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

ID = 16 A
300

200

100

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

0.05

P(pk)

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

1.0

10

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 9 450 mils x 350 mils

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4391

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB20N20E
Motorola Preferred Device

TMOS POWER FET


20 AMPERES
200 VOLTS
RDS(on) = 0.16 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDSS
VDGR

200

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
12
60

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

600

mJ

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

DrainSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4392

Motorola TMOS Power MOSFET Transistor Device Data

MTB20N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Min

Typ

Max

Unit

200

263

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.12

0.16

Ohm

3.84
3.36

gFS

8.0

11

mhos

Ciss

1880

2700

pF

Coss

378

535

Crss

68

100

td(on)

17

40

tr

86

180

td(off)

50

100

tf

60

120

QT

54

75

Q1

12

Q2

24

Q3

22

1.0
0.82

1.35

trr

239

ta

136

tb

103

QRR

2.09

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Characteristic

Symbol

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 100 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 160 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4393

MTB20N20E
TYPICAL ELECTRICAL CHARACTERISTICS
40

40
TJ = 25C

8V
9V

7V

30

20
6V
10
5V

25
100C
20
15
10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.35
VGS = 10 V
0.30
TJ = 100C

0.25
0.20
0.15

25C

0.10
55C
0.05
0

25C
30

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

10

12
20 24
28
16
ID, DRAIN CURRENT (AMPS)

32

36

40

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 25C
0.16
0.15
0.14

VGS = 10 V

0.13
0.12
15 V
0.11
0.10

16
24
28
12
20
ID, DRAIN CURRENT (AMPS)

32

36

40

10000

VGS = 10 V
ID = 10 A

VGS = 0 V

2.0

TJ = 125C

1000

1.6

1.2

0.8

100C
100

25C

10

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4394

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.4

8.5

0.17

Figure 3. OnResistance versus Drain Current


and Temperature

0.4
50

TJ = 55C

0
0

VDS 10 V

35
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V

150

50
100
150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB20N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000
Ciss

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

4000

3000

Crss
Ciss

2000

1000

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4395

180
QT

10
Q1

150

VGS

Q2

120

90

60

ID = 20 A
TJ = 25C

30
Q3

VDS

0
0

10

50

20
30
40
QG, TOTAL GATE CHARGE (nC)

0
60

1000
VDD = 30 V
ID = 20 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB20N20E

100
tr
tf
td(off)
td(on)

10
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

20
VGS = 0 V
TJ = 25C

16

12

0
0.5

0.55

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95


VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4396

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB20N20E
SAFE OPERATING AREA
600
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s
100 s
1 ms
1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

0.01

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 20 A
500
400
300
200
100
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.01
1.0E05

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

PD, POWER DISSIPATION (WATTS)

3.0

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1.0
0.5
0
25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4397

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTB23P06V

Designer's

TMOS
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


23 AMPERES
60 VOLTS
RDS(on) = 0.120 OHM

PChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

23
15
81

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

90
0.60
3.0

Watts
W/C

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 175

794

mJ

RJC
RJA
RJA

1.67
62.5
50

C/W

TL

260

DraintoSource Voltage

Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4398

Motorola TMOS Power MOSFET Transistor Device Data

MTB23P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

60.5

Vdc
mV/C

10
100

100

nAdc

2.0

2.8
5.3

4.0

Vdc
mV/C

0.093

0.12

Ohm

2.1

3.3
3.2

5.0

11.5

Ciss

1160

1620

Coss

380

530

Crss

105

210

td(on)

13.8

30

tr

98.3

200

td(off)

41

80

tf

62

120

QT

38

50

Q1

7.0

Q2

18

Q3

14

2.2
1.8

3.5

trr

142

ta

100

tb

41

QRR

0.804

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 11.5 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 23 Adc)
(VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 10.9 Vdc, ID = 11.5 Adc)

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 23 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 23 Adc, VGS = 0 Vdc)


(IS = 23 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 23 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4399

MTB23P06V
TYPICAL ELECTRICAL CHARACTERISTICS
40
VGS = 10V

I D , DRAIN CURRENT (AMPS)

TJ = 25C
40

8V
9V
7V

30
6V

20

10

VDS 10 V

35
I D , DRAIN CURRENT (AMPS)

50

5V

TJ = 55C
25C

30
100C

25
20
15
10
5

4V
0

Figure 2. Transfer Characteristics

TJ = 100C

0.12
25C

0.1
0.08

55C
0.06
0.04
0.02
5

10

15
20
25
30
ID, DRAIN CURRENT (AMPS)

35

40

45

0.12
TJ = 25C
0.115
0.11
0.105

VGS = 10 V

0.1
0.095
15 V

0.09
0.085
0.08

Figure 3. OnResistance versus Drain Current


and Temperature

10

15
20
30
35
25
ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

100
VGS = 0 V

VGS = 10 V
ID = 11.5 A
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

0.14

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2
1
0.8
0.6

TJ = 125C

10

0.4
0.2
0
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4400

175

50
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB23P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
4000

C, CAPACITANCE (pF)

Ciss
3000

VGS = 0 V

VDS = 0 V

TJ = 25C

Crss

2000
Ciss
1000
Coss
Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4401

30
QT

9
8

27
24

Q2

Q1

VGS

21

18

15

12
9

3
2
Q3

1
0

TJ = 25C
ID = 23 A

VDS
10

15

20

25

30

35

6
3
0
40

1000

t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB23P06V
TJ = 25C
ID = 23 A
VDD = 30 V
VGS = 10 V

100

tr
tf
td(off)
td(on)

10

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

25
TJ = 25C
VGS = 0 V

20

15

10

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4402

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB23P06V
SAFE OPERATING AREA
800

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

10

1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

600
500
400
300
200
100
0

0.1
0.1

ID = 23 A

700

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

25

100

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.10
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

25

50

75

100

125

175

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4403

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTB30N06VL

Designer's

TMOS
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


30 AMPERES
60 VOLTS
RDS(on) = 0.050 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

G
S

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETs


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

30
20
105

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

90
0.6
3.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

154

mJ

RJC
RJA
RJA

1.67
62.5
50

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 30 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 3

4404

Motorola TMOS Power MOSFET Transistor Device Data

MTB30N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

63

Vdc
mV/C

10
100

100

nAdc

1.0

1.5
4.0

2.0

Vdc
mV/C

0.033

0.05

Ohms

1.1

1.8
1.73

gFS

13

21

Mhos

Ciss

1130

1580

pF

Coss

360

500

Crss

95

190

td(on)

14

30

tr

260

520

td(off)

54

110

tf

108

220

QT

27

40

Q1

Q2

17

Q3

15

0.98
0.89

1.6

trr

86

ta

49

tb

37

QRR

0.228

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 15 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5 Vdc, ID = 30 Adc)
(VGS = 5 Vdc, ID = 15 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS = 5 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc,
VGS = 5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4405

MTB30N06VL
TYPICAL ELECTRICAL CHARACTERISTICS

50

I D , DRAIN CURRENT (AMPS)

60

VGS = 10 V
8V

TJ = 25C

6V
5V

40

4V

30
20

3V

25C
100C

40
30
20

0
0

0.08

10

Figure 2. Transfer Characteristics

0.06

TJ = 100C

0.05
0.04

25C

0.03
0.02

55C

0.01
0
0

10

20
30
40
ID, DRAIN CURRENT (AMPS)

60

50

0.06
TJ = 25C
0.05
VGS = 5 V

0.04

10 V

0.03
0.02
0.01
0

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000
VGS = 5 V
ID = 15 A

VGS = 0 V
TJ = 125C

1.4

I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

0.07

1.6

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

50

10

10
0

TJ = 55C

VDS 10 V
I D , DRAIN CURRENT (AMPS)

60

1.2
1
0.8
0.6

100
100C
10

0.4
0.2
0
50

25

25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4406

175

1
0

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB30N06VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements


complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
5000

C, CAPACITANCE (pF)

4500 C
iss
4000

VDS = 0 V

VGS = 0 V

TJ = 25C

3500
3000

Crss

2500
2000
1500

Ciss

1000
500

Coss

Crss

0
10

5
VGS

0
VDS

10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4407

30

4.5

27

24

QT

3.5

VGS

Q2

Q1

21
18

2.5

15

12

1.5

Q3

1
0.5
0

10

15

6
3

VDS
0

TJ = 25C
ID = 30 A

0
25

20

1000
TJ = 25C
ID = 30 A
VDD = 30 V
VGS = 5 V
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB30N06VL

tr
tf

100

td(off)
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

DRAINTOSOURCE DIODE CHARACTERISTICS


30

I S , SOURCE CURRENT (AMPS)

25

TJ = 25C
VGS = 0 V

20
15
10
5
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4408

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB30N06VL
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

160

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10 s

100 s

10

1 ms
10 ms
dc

1
0.1

10

ID = 30 A

140
120
100
80
60
40
20
0

100

25

50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

75

100

125

175

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.05

0.10
0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

25

50

75

100

125

150

175

TA, AMBIENT TEMPERATURE (C)

Figure 15. D2PAK Power Derating Curve

4409

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTB30P06V

Designer's

TMOS
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


30 AMPERES
60 VOLTS
RDS(on) = 0.080 OHM

PChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

30
19
105

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

125
0.83
3.0

Watts
W/C

Operating and Storage Temperature Range

TJ, Tstg
EAS

55 to 175

450

mJ

RJC
RJA
RJA

1.2
62.5
50

C/W

TL

260

DraintoSource Voltage

Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 30 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4410

Motorola TMOS Power MOSFET Transistor Device Data

MTB30P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

62

Vdc
mV/C

10
100

100

nAdc

2.0

2.6
5.3

4.0

Vdc
mV/C

0.067

0.08

Ohm

2.0

2.9
2.8

5.0

7.9

Ciss

1562

2190

Coss

524

730

Crss

154

310

td(on)

14.7

30

tr

25.9

50

td(off)

98

200

tf

52.4

100

QT

54

80

Q1

9.0

Q2

26

Q3

20

2.3
1.9

3.0

trr

175

ta

107

tb

68

QRR

0.965

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 30 Adc)
(VGS = 10 Vdc, ID = 15 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 8.3 Vdc, ID = 15 Adc)

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4411

MTB30P06V
TYPICAL ELECTRICAL CHARACTERISTICS
60

60
TJ = 25C

40
30

6V

20
5V

10
0

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

7V

4V
0

50

25C

40
30

TJ = 55C

20

12

10

Figure 2. Transfer Characteristics

0.1
0.08

25C

0.06
55C
0.04
0.02

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

0.08
TJ = 25C
VGS = 10 V

0.07

15 V
0.06

0.05

0.04

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

100
VGS = 0 V

VGS = 10 V
ID = 15 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

TJ = 100C

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.12

100C

10

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

9V

VGS = 10V

50

VDS 10 V

8V

1.2
1
0.8
0.6

10
100C

0.4
0.2
0
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4412

175

50
60
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

70

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB30P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
Ciss

C, CAPACITANCE (pF)

5000
4000

VGS = 0 V

VDS = 0 V

TJ = 25C

Crss

3000
Ciss

2000

Coss
1000
Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4413

30
VGS
27

QT

24

8
Q2

Q1

21

18

15

12

VDS

1
0

TJ = 25C
ID = 30 A

Q3

10

20

30

40

50

6
3
0
60

1000

t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB30P06V
TJ = 25C
ID = 30 A
VDD = 30 V
VGS = 10 V

100

td(off)
tf
tr
td(on)

10

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


30
TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

25
20
15
10
5
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4414

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB30P06V
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

450

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
10 s
100 s

10

1 ms

10 ms
dc

ID = 30 A

400
350
300
250
200
150
100
50
0

1
0.1

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

25

100

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.10

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 9 450 mils x 350 mils

25

50

75

100

125

175

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 15. D2PAK Power Derating Curve

4415

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB33N10E
Motorola Preferred Device

TMOS POWER FET


33 AMPERES
100 VOLTS
RDS(on) = 0.06 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

33
20
99

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 33 Apk, L = 1.000 mH, RG = 25 )

EAS

545

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4416

Motorola TMOS Power MOSFET Transistor Device Data

MTB33N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

118

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.04

0.06

Ohm

1.6

2.4
2.1

gFS

8.0

mhos

Ciss

1830

2500

pF

Coss

678

1200

Crss

559

1100

td(on)

18

40

tr

164

330

td(off)

48

100

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 25C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 33 Adc)
(ID = 16.5 Adc, TJ = 25C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 16.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 50 Vdc, ID = 33 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 80 Vdc, ID = 33 Adc,
VGS = 10 Vdc)

tf

83

170

QT

52

110

Q1

12

Q2

32

Q3

24

1.0
0.98

2.0

trr

144

ta

108

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 33 Adc, VGS = 0 Vdc)


(IS = 33 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 33 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

36

QRR

0.93

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4417

MTB33N10E
TYPICAL ELECTRICAL CHARACTERISTICS
90

90
TJ = 25C

VGS = 10 V
9V

70
60

8V
50
40

7V

30
20

6V

10

5V
2

50
100C
40
30
20

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.07
0.06
25C

0.05
0.04

55C

0.03
0.02
6

25C

60

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.09
0.08

70

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10

10

12

18
24 30 36 42 48
ID, DRAIN CURRENT (AMPS)

54

60

66

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.053
TJ = 25C

0.051
0.049
0.047
0.045

VGS = 10 V

0.043
0.041
15 V

0.039
0.037

11

17

23
29
35 41
47
ID, DRAIN CURRENT (AMPS)

53

59

65

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.0

VGS = 0 V

VGS = 10 V
ID = 16.5 A

1.6

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.8

TJ = 55C

10

0
0

VDS 10 V

80
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

80

1.4
1.2
1.0

TJ = 125C

1000

100C
100
25C

0.8
0.6
50

4418

25

25

50

75

100

125

150

10
20

30

40

50

60

70

80

90

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

100

Motorola TMOS Power MOSFET Transistor Device Data

MTB33N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000
4500

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

4000
3500
3000

Crss

2500
Ciss

2000
1500

Coss

1000
500
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4419

140
VGS

12

120

QT
100

10
Q2
8

80

Q1

60

6
ID = 33 A
TJ = 25C

40

Q3

20
VDS

0
0

10

20
30
40
QG, TOTAL GATE CHARGE (nC)

50

0
60

1000
VDD = 50 V
ID = 33 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

14

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB33N10E

tr
100
tf
td(off)

td(on)

10
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


33

I S , SOURCE CURRENT (AMPS)

30
27

VGS = 0 V
TJ = 25C

24
21
18
15
12
9
6
3
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4420

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB33N10E
SAFE OPERATING AREA
550
VGS = 20 V
SINGLE PULSE
TC = 25C

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100 s

10

1 ms
1.0

10 ms

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

0.01
0.1

ID = 33 A

450
400
350
300
250
200
150
100
50
0

100

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PD, POWER DISSIPATION (WATTS)

3.0

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1.0
0.5
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

150

Figure 15. D2PAK Power Derating Curve

4421

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTB35N06ZL

HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount

TMOS POWER FET


35 AMPERES
60 VOLTS
RDS(on) = 26 m

NChannel EnhancementMode Silicon Gate


This advanced high voltage TMOS EFET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode
ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

35
22.8
105

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

94
0.63
3.0

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 5.0 Vdc, Peak IL = 35 Apk, L = 0.3 mH, RG = 25 )

EAS

184

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

1.6
62.5
50

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

4422

Motorola TMOS Power MOSFET Transistor Device Data

MTB35N06ZL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

52

Vdc
mV/C

10
100

5.0

Adc

1.0

1.5
4.0

2.0

Vdc
mV/C

22

26

0.78
0.7

1.1
1.0

gFS

10

12

mhos

Ciss

1600

pF

Coss

560

Crss

140

td(on)

40

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Cpk 3.0)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk 3.0)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(Cpk 2.0)
(VGS = 5.0 Vdc, ID = 11.5 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 5.0 Vdc)


(ID = 23 Adc)
(ID = 11.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 4.0 Vdc, ID = 11.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 23 Adc,


5 0 Vdc,
Vdc
VGS(on) = 5.0
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc,
VGS = 5.0 Vdc)

ns

tr

250

td(off)

130

tf

170

QT

45

Q1

8.0

Q2

22

Q3

19

0.92
0.81

1.1

trr

43

ta

24

tb

20

QRR

0.055

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 23 Adc, VGS = 0 Vdc)


(IS = 23 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 23 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4423

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTB36N06V

Designer's

TMOS
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


32 AMPERES
60 VOLTS
RDS(on) = 0.04 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

G
S

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETs


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

32
22.6
112

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

90
0.6
3.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

205

mJ

RJC
RJA
RJA

1.67
62.5
50

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 50 s)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 32 Apk, L = 0.1 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 2

4424

Motorola TMOS Power MOSFET Transistor Device Data

MTB36N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

61

Vdc
mV/C

10
100

100

nAdc

2.0

2.6
6.0

4.0

Vdc
mV/C

0.034

0.04

Ohm

1.25

1.54
1.47

gFS

5.0

7.83

mhos

Ciss

1220

1700

pF

Coss

337

470

Crss

74.8

150

td(on)

14

30

tr

138

270

td(off)

54

100

tf

91

180

QT

39

50

Q1

Q2

17

Q3

13

1.03
0.94

2.0

trr

92

ta

64

tb

28

QRR

0.332

3.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 32 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 32 Adc, VGS = 0 Vdc)


(IS = 32 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4425

MTB36N06V
TYPICAL ELECTRICAL CHARACTERISTICS
72

TJ = 100C

VDS 10 V
7V

9V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

72

VGS = 10 V

TJ = 25C
54
8V

6V
36

5V

18

25C

54

36

18
55C

4V
0

0.1

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.052

0.08
TJ = 100C

25C

0.04

TJ = 25C

0.044

0.06

VGS = 10 V

0.036

55C
0.02
0
0

18

54
36
ID, DRAIN CURRENT (AMPS)

72

0.028

15 V

18

Figure 3. OnResistance versus Drain Current


and Temperature

36
54
ID, DRAIN CURRENT (AMPS)

72

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

1000
VGS = 0 V

VGS = 10 V
ID = 16 A

TJ = 125C
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.4
1.2
1

100
100C

10

25C

0.8
0.6
50

1
25

25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4426

175

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB36N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements


complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
4000

C, CAPACITANCE (pF)

VDS = 0 V
3000

VGS = 0 V

TJ = 25C

Ciss

2000
Ciss

Crss
1000

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4427

QT
25

10
VGS

20

Q2

Q1

15

6
4
Q3

2
0

10

TJ = 25C
ID = 32 A

VDS
0

10

15

20

25

30

35

40

1000
TJ = 25C
ID = 32 A
VDD = 30 V
VGS = 10 V
t, TIME (ns)

30

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB36N06V

tr
tf

100

td(off)
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


32

I S , SOURCE CURRENT (AMPS)

TJ = 25C
VGS = 0 V
24

16

0
0.5 0.55

0.6 0.65

0.7 0.75

0.8 0.85 0.9

0.95

1.05

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4428

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTB36N06V
SAFE OPERATING AREA
225

VGS = 20 V
SINGLE PULSE
TC = 25C

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
10 s

100 s

10

1 ms
10 ms
dc

1
1

0.1

10

ID = 32 A

200
175
150
125
100
75
50
25
0

100

25

50

75

100

125

175

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.10 0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PD, POWER DISSIPATION (WATTS)

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0

25

50

75

100

125

175

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. D2PAK Power Derating Curve

4429

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB50P03HDL
Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
50 AMPERES
30 VOLTS
RDS(on) = 0.025 OHM

PChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
highcell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

30

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

30

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

50
31
150

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size

PD

125
1.0
2.5

Watts
W/C
Watts

Rating

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 )

EAS

1250

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4430

Motorola TMOS Power MOSFET Transistor Device Data

MTB50P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

30

26

10
100

100

1.0

1.5
4.0

2.0

20.9

25

0.83

1.5
1.3

15

20

Ciss

3500

4900

Coss

1550

2170

Crss

550

770

td(on)

22

30

tr

340

466

td(off)

90

117

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 3.0) (3)

Static DrainSource OnResistance


(VGS = 5.0 Vdc, ID = 25 Adc)

(Cpk 3.0) (3)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 50 Adc)
(ID = 25 Adc, TJ =125C)

VGS(th)

Vdc

RDS(on)

mOhm

VDS(on)

Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)

mV/C

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

Vd VGS = 0 Vdc,
Vd
(VDS = 25 Vdc,
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD= 15 Vdc, ID = 50 Adc,


5 0 Vdc,
Vdc
VGS = 5.0
RG = 2.3 )

Fall Time

ns

tf

218

300

QT

74

100

Q1

13.6

Q2

44.8

Q3

35

2.39
1.84

3.0

trr

106

ta

58

tb

48

QRR

0.246

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

3.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(S Fi
(See
Figure 8)
((VDS = 24 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 50 Adc, VGS = 0 Vdc)


(IS = 50 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
(See
Fi
15)
((IS = 50 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4431

MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100

TJ = 25C

VGS = 10 V
8V

80

6V
4V

4.5 V

60

VDS 5 V

5V

3.5 V
40
3V
20

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

TJ = 55C
25C

100C

80

60

40

20

2.5 V
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.9

2.3

2.7

3.9

3.5

3.1

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5 V
0.027
0.025

TJ = 100C

0.023
25C
0.021
0.019
55C

0.017
0.015

0
1.5

2.0

1.8

20

40

60

80

100

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.029

4.3

0.022
VGS = 5 V

TJ = 25C
0.021
0.020
0.019
0.018
0.017

10 V
0.016
0.015

20

40

60

80

100

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.35

1.25

1000
VGS = 0 V

VGS = 5 V
ID = 25 A
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.15

1.05

TJ = 125C
100

0.95
100C
0.85
50

4432

10
25

25

50

75

100

125

150

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DraintoSource Leakage


Current versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MTB50P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

14000

VGS = 0 V

C, CAPACITANCE (pF)

VDS = 0 V
C
12000 iss

TJ = 25C

10000
8000
Crss
6000
Ciss

4000

Coss
2000

Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4433

30
QT

25

VGS
Q1

Q2

20
15

3
ID = 50 A
TJ = 25C

10
5

1
Q3
0

10

VDS

20

30

40

50

60

70

1000

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB50P03HDL
VDD = 30 V
VGS = 10 V

ID = 50 A
TJ = 25C

tr
tf
td(off)

100

td(on)

0
80

10

10

QT, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

50
VGS = 0 V
TJ = 25C
40

30

20

10
0
0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4434

Motorola TMOS Power MOSFET Transistor Device Data

MTB50P03HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
VGS = 20 V
SINGLE PULSE
TC = 25C
100

100 s
1 ms

10

1
0.1

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

1400
ID = 50 A

1200
1000
800
600
400
200
0

10

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4435

MTB50P03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

4436

Figure 16. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTB52N06V

TMOS V
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

TM

G
S

CASE 418B02, Style 2


D2PAK

Features Common to TMOS V and TMOS EFETs


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

20
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

52
41
182

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

165
1.1
3.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

406

mJ

RJC
RJA
RJA

0.91
62.5
50

C/W

TL

260

DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4437

MTB52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
TBD

4.0

Vdc
mV/C

0.019

0.022

Ohm

1.4
1.2

gFS

17

25

mhos

Ciss

1700

2380

pF

Coss

500

700

Crss

150

300

td(on)

15

30

tr

130

260

td(off)

68

140

tf

70

140

QT

70

80

Q1

10

Q2

30

Q3

20

1.0
0.9

1.5

trr

90

ta

80

tb

10

QRR

0.3

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 26 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 52 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 52 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 52 Adc, VGS = 0 Vdc)


(IS = 52 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4438

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTB52N06VL

TMOS V
Power Field Effect Transistor
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


52 AMPERES
60 VOLTS
RDS(on) = 0.025 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS EFET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

TM

Features Common to TMOS V and TMOS EFETs


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

CASE 418B02, Style 2


D2PAK

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
25

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

52
41
182

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

165
1.1
3.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

406

mJ

RJC
RJA
RJA

0.91
62.5
50

C/W

TL

260

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
NonRepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 52 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance Junction to Case
Junction to Ambient
Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4439

MTB52N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

1.0

1.5
TBD

2.0

Vdc
mV/C

0.022

0.025

Ohm

1.5
1.3

gFS

17

30

Mhos

Ciss

1600

2240

pF

Coss

550

770

Crss

170

340

td(on)

18

40

tr

370

740

td(off)

90

180

tf

170

340

QT

45

60

Q1

12

Q2

22

Q3

18

1.0
0.9

1.5

trr

93

ta

65

tb

28

QRR

0.3

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = .25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 26 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5 Vdc, ID = 52 Adc)
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 52 Adc,


VGS = 5 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 48 Vdc, ID = 52 Adc,


VGS = 5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 52 Adc, VGS = 0 Vdc)


(IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C)

Reverse Recovery Time


((IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4440

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTB55N06Z

TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount

TMOS POWER FET


55 AMPERES
60 VOLTS
RDS(on) = 16 m

NChannel EnhancementMode Silicon Gate


This advanced high voltage TMOS EFET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode
ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

55
35.5
165

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

136
0.91
3.0

Watts
W/C
Watts

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 )

EAS

454

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

1.1
62.5
50

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4441

MTB55N06Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

53

Vdc
mV/C

10
100

5.0

Adc

2.0

3.0
6.0

4.0

Vdc
mV/C

14

16

0.825
0.74

1.2
1.0

gFS

12

15

mhos

Ciss

1390

1950

pF

Coss

520

730

Crss

119

238

td(on)

27

54

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Cpk 2.0)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk 2.0)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(Cpk 2.0)
(VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 30 Adc)
(ID = 15 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 4.0 Vdc, ID = 15 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS(on) = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

tr

157

314

td(off)

116

232

tf

126

252

QT

40

56

Q1

7.0

Q2

18

Q3

15

0.93
0.82

1.1

trr

57

ta

32

tb

25

QRR

0.11

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4442

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB60N06HD
Motorola Preferred Device

TMOS POWER FET


60 AMPERES
60 VOLTS
RDS(on) = 0.014 OHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
highcell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

60
42.3
180

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 )

EAS

540

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When mounted with the minimum recommended pad size.


Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4443

MTB60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

60

71

10
100

100

2.0

3.0
7.0

4.0

0.011

0.014

1.0
0.9

15

20

Ciss

1950

2800

Coss

660

920

Crss

147

300

td(on)

14

26

tr

197

394

td(off)

50

102

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 3.0) (3)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 30 Adc)

(Cpk 3.0) (3)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 60 Adc)
(ID = 30 Adc, TJ =125C)

VGS(th)

Vdc

RDS(on)

Ohm

VDS(on)

Forward Transconductance
(VDS = 4.0 Vdc, ID = 30 Adc)

mV/C

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

Vd VGS = 0 Vdc,
Vd
(VDS = 25 Vdc,
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD= 30 Vdc, ID = 60 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time

ns

tf

124

246

QT

51

71

Q1

12

Q2

24

Q3

21

0.99
0.89

1.0

trr

60

ta

36

tb

24

QRR

0.143

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(S Fi
(See
Figure 8)
((VDS = 48 Vdc, ID = 60 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 60 Adc, VGS = 0 Vdc)


(IS = 60 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
(See
Fi
15)
((IS = 60 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4444

Motorola TMOS Power MOSFET Transistor Device Data

MTB60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120

120

8V

VGS = 10 V

7V

VDS 10 V

9V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100
TJ = 25C

80
6V

60
40

5V

20

100
80
60
40
100C

25C

20

TJ = 55C
0.5

1.5

1.0

2.5

2.0

3.0

3.5

4.0

4.5

5.0

3.6

4.4

6.0

5.2

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

0.016
0.014

25C

0.012
0.010

55C

0.008
10

20

30

40

50

60

70

80

90 100 110 120

7.6

6.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.018

2.8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

0.006

0
2.0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.020

0.0132
TJ = 25C

0.0128
0.0124
0.0120

VGS = 10 V

0.0116
0.0112
0.0108
15 V

0.0104
0.0100

10

20

30

40

50

60

70

80

90

100 110 120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8
1.6

1000
VGS = 0 V

VGS = 10 V
ID = 30 A

TJ = 125C
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.4
1.2
1.0

100
100C
25C
10

0.8
0.6
50

1
25

25

50

75

100

125

150

10

20

30

40

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DraintoSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

60

4445

MTB60N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000

VDS = 0 V

VGS = 0 V

Ciss

TJ = 25C

C, CAPACITANCE (pF)

4000

3000
Crss

Ciss

2000
Coss
1000
Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4446

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

10

50
VGS

40
Q1

Q2

30

20

ID = 60 A
TJ = 25C

10

2
Q3
0

VDS
16

24

32

40

48

0
56

1000
VDD = 30 V
ID = 60 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB60N06HD

tr
tf

100

td(off)

td(on)
10

10

QT, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

60
50

VGS = 0 V
TJ = 25C

40
30
20
10
0
0.5

0.6

0.7

0.8

0.9

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4447

MTB60N06HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
VGS = 20 V
SINGLE PULSE
TC = 25C
10 s

100

100 s
10

1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

4448

1.0

10 ms
dc
10

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

600
ID = 60 A
500
400
300
200
100
0

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTB60N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E01

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

PD, POWER DISSIPATION (WATTS)

3
2.5

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.0
1.5
1
0.5
0
25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

Figure 16. D2PAK Power Derating Curve

4449

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advanced Information

MTB75N03HDL

HDTMOS E-FET.
High Density Power FET
D2PAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
75 AMPERES
25 VOLTS
RDS(on) = 9 mOHM

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
highcell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

G
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Ultra Low RDS(on), HighCell Density, HDTMOS
Short Heatsink Tab Manufactured Not sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 418B02, Style 2


D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

25

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

25

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

75
59
225

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (1)

PD

125
1.0
2.5

Watts
W/C
Watts

Operating and Storage Temperature Range

55 to 150

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 )

EAS

280

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

1.0
62.5
50

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) When mounted with the minimum recommended pad size.

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4450

Motorola TMOS Power MOSFET Transistor Device Data

MTB75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

25

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DrainSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Vdc
mV/C

Zero Gate Voltage Drain Current


(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V)

IGSS

Adc

100
500

100

1.0

1.5

2.0

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

(Cpk 3.0) (3)

Static DrainSource OnResistance


(VGS = 5.0 Vdc, ID = 37.5 Adc)

(Cpk 2.0) (3)

VGS(th)

Vdc
mV/C

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125C)

RDS(on)

6.0

9.0

0.68
0.6

gFS

15

55

mhos

pF

VDS(on)

Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance

Ciss

4025

5635

Coss

1353

1894

Crss

307

430

td(on)

24

48

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS= 15 Vdc, ID = 75 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 4.7 )

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc)

tr

493

986

td(off)

60

120

tf

149

300

QT

61

122

Q1

14

28

Q2

33

66

Q3

27

54

0.97
0.87

1.1

trr

58

ta

27

tb

30

QRR

0.088

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 75 Adc, VGS = 0 Vdc)


(IS = 75 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 75 Adc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4451

MTB75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V

5V

I D , DRAIN CURRENT (AMPS)

8V
120

150

4.5 V TJ = 25C
I D , DRAIN CURRENT (AMPS)

150

4V

6V

90
3.5 V
60
3V

30

VDS 10 V

120

90

60
100C

TJ = 55C

2.5 V
0

0.2

0.4 0.6 0.8


1
1.2
1.4 1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.8

0
1.5

TJ = 100C

25C

55C
0.004

0.002

30

60

90

120

150

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS = 5 V

0.006

2
2.5
3
3.5
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.009
TJ = 25C
0.008

0.007

VGS = 5 V

0.006
10 V
0.005

0.004

ID, DRAIN CURRENT (AMPS)

75
50
100
ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

I DSS , LEAKAGE (nA)

1.2

0.8

25

125

150

TJ = 125C

VGS = 10 V
ID = 37.5 A

1.6

4.5

Figure 2. Transfer Characteristics

0.01

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.008

25C

30

100C

1000

100

10

0.4

25C
VGS = 0 V

50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4452

150

5
10
15
20
25
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

30

Figure 6. DraintoSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTB75N03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

15000

C, CAPACITANCE (pF)

12000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

9000
Crss
Ciss

6000

Coss

3000
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4453

28

24
QT
20

5
Q2

Q1

VGS
16
12

3
TJ = 25C
ID = 75 A

4
VDS

Q3

0
0

10

20
30
40
50
QT, TOTAL GATE CHARGE (nC)

60

0
70

10000

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB75N03HDL

tr

1000

TJ = 25C
ID = 75 A
VDD = 15 V
VGS = 5 V

tf
td(off)
td(on)

100

10
1

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

75

60

TJ = 25C
VGS = 0 V

45

30

15

0
0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4454

Motorola TMOS Power MOSFET Transistor Device Data

MTB75N03HDL
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

280

1000

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100
100 s
1 ms
10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

dc

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

ID = 75 A

240
200
160
120
80
40
0
25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

4455

MTB75N03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E01

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp

PD, POWER DISSIPATION (WATTS)

3
2.5
2.0
1.5
1
0.5
0
IS

RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

4456

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
Designer's

MTB75N05HD
Motorola Preferred Device

TMOS POWER FET


75 AMPERES
50 VOLTS
RDS(on) = 9.5 m

NChannel EnhancementMode Silicon Gate


The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
highcell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

G
CASE 418B02, Style 2
D2PAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

50

Volts

DraintoGate Voltage (RGS = 1.0 M)

VDGR

50

GatetoSource Voltage Continuous

VGS

20

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

75
65
225

Amps

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C (minimum footprint, FR4 board)

PD

125
1.0
2.5

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 )

EAS

500

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (minimum footprint, FR4 board)

RJC
RJA
RJA

1.0
62.5
50

C/W

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

TL

260

Operating and Storage Temperature Range

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4457

MTB75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

50

54.9

Vdc
mV/C

10
100

100

2.0

6.3

4.0

7.0

9.5

0.63

0.34

gFS

15

mhos

Ciss

2600

2900

pF

Coss

1000

1100

Crss

230

275

td(on)

15

30

tr

170

340

td(off)

70

140

tf

100

200

QT

71

100

Q1

13

Q2

33

Q3

26

0.97
0.80
0.68

1.00

Vdc

trr

57

ns

ta

40

tb

17

QRR

0.17

3.5
4.5

7.5

OFF CHARACTERISTICS
(Cpk 2)(2)

DraintoSource Breakdown Voltage


(VGS = 0, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 50 V, VGS = 0)
(VDS = 50 V, VGS = 0, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 20 Vdc, VDS = 0)

IGSS

Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 1.5)(2)

Static DraintoSource OnResistance(3)


(VGS = 10 Vdc, ID = 20 Adc)

(Cpk 3.0)(2)

DraintoSource OnVoltage (VGS = 10 Vdc)(3)


(ID = 75 A)
(ID = 20 Adc, TJ = 125C)

VGS(th)

RDS(on)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc)

Vdc
mV/C

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance

(VDS = 25 V,
V VGS = 0
0, (Cpk 2
2.0)
0)(2)
f = 1.0 MHz)
(Cpk 2.0)(2)
(Cpk 2.0)
2 0)(2)

SWITCHING CHARACTERISTICS (4)


TurnOn Delay Time
(VDD = 25 V, ID = 75 A,
VGS = 10 V,
V
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 40 V, ID = 75 A,
VGS = 10 V)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 75 A, VGS = 0)
(Cpk 10)(2)
(IS = 20 A, VGS = 0)
(IS = 20 A, VGS = 0, TJ = 125C)

VSD

Reverse Recovery Time


((IS = 37.5 A, VGS = 0,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

(1)
(2)
(3)
(4)

nH

Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


Reflects Typical Values. Cpk = ABSOLUTE VALUE OF (SPEC AVG) / 3 * SIGMA).
For accurate measurements, good Kelvin contact required.
Switching characteristics are independent of operating junction temperature.

4458

Motorola TMOS Power MOSFET Transistor Device Data

MTB75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS(1)
160

160
TJ = 25C
I D , DRAIN CURRENT (AMPS)

120
100
80

6V

60
40
5V

20
0

0.5

1.5

2.5

3.5

80
60
TJ = 55C

100C

40

4.5

25C
0

140

160

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.012
TJ = 100C
0.01
25C

0.008
0.006

55C

0.004

20

40

60

80

100

120

140

0.009
TJ = 25C
0.008

VGS = 10 V

0.007
15 V
0.006

0.005
0

20

40

60

80

100

120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2
VGS = 10 V
ID = 37.5 A

VGS = 0 V

1.5

I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

120

20

0.014

0.002

VDS 10 V

140

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

140

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

7V

VGS = 10 V

1000

TJ = 125C

100

100C

10

0.5

25C
0
50

0
25

25

50

75

100

125

150

10

15

20

25

30

35

40

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

45

50

(1)Pulse Tests: Pulse Width 250 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

4459

MTB75N05HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with boardmounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in a RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000

VDS = 0

VGS = 0

TJ = 25C

C, CAPACITANCE (pF)

7000
6000

Ciss

5000
4000
3000

Ciss

Crss

Coss

2000

Crss

1000
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4460

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

10

50
VGS

40
Q1

Q2

30
TJ = 25C
ID = 75 A

20
10

2
VDS

Q3

0
75

25
50
QG, TOTAL GATE CHARGE (nC)

1000
TJ = 25C
ID = 75 A
VDD = 35 V
VGS = 10 V

tf
tr

100
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTB75N05HD

td(off)

td(on)

10

1
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
40

80

di/dt = 300 A/s


30
I S , SOURCE CURRENT (AMPS)

I S , SOURCE CURRENT (AMPS)

TJ = 25C
70 VGS = 0 V
60
50
40
30
20
10

STANDARD CELL DENSITY


trr
HIGH CELL DENSITY
trr
tb
ta

20
10
0
10
20
30

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

40
120 100 80 60

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

40 20
0
t, TIME (ns)

Figure 10. Diode Forward Voltage versus Current

Figure 11. Reverse Recovery Time (trr)

Motorola TMOS Power MOSFET Transistor Device Data

20

40

60

80

4461

MTB75N05HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

500
VGS = 20 V
SINGLE PULSE
TC = 25C

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
10 s

100 s

10

1 ms
10 ms
1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

dc

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400
350
300
250
200
150
100
50
0
25

100

Figure 12. Maximum Rated Forward Biased


Safe Operating Area
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

ID = 75 A

450

150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5

0.2
P(pk)

0.1
0.1

0.05
0.02

t1

t2
DUTY CYCLE, D = t1/t2

0.01

RJC(t) = r(t) RJC


RJC = 1.0C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE
0.01
1.0E 05

1.0E 04

1.0E 03

1.0E 02
t, TIME (s)

1.0E 01

1.0E+00

1.0E+01

Figure 14. Thermal Response

4462

Motorola TMOS Power MOSFET Transistor Device Data

MTB75N05HD
PD, POWER DISSIPATION (WATTS)

3
RJA = 50C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils

2.5
2.0
1.5
1
0.5
0
25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

4463

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD1N50E
Motorola Preferred Device

TMOS POWER FET


1.0 AMPERE
500 VOLTS
RDS(on) = 5.0 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

500

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GatetoSource Voltage Continuous


Nonrepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4464

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

480

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
6.0

4.0

Vdc
mV/C

4.3

5.0

Ohm

4.5

6.0
5.3

gFS

0.5

0.9

mhos

Ciss

215

315

pF

Coss

30.2

42

Crss

6.7

12

td(on)

8.0

20

tr

9.0

10

td(off)

14

30

tf

17

30

QT

7.4

9.0

Q1

1.6

Q2

3.8

Q3

5.0

0.81
0.68

1.2

trr

141

ta

82

tb

58.5

QRR

0.65

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 10 Vd
Vdc,
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4465

MTD1N50E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

2.0
7V
8V

1.50

VDS 10 V

1.75
I D , DRAIN CURRENT (AMPS)

1.75
I D , DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25C

6V

1.25
1.0
0.75
0.50

5V

1.50
1.25
1.0
0.75
0.50

TJ = 100C
25C

0.25

0.25
55C
2

10

12

14

16

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

1.75

2.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

10
VGS = 10 V
TJ = 100C

6
25C
4
55C
2

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.4

0.8

1.2

1.6

2.0

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0
2.0

6.0
TJ = 25C
5.5
5.0
VGS = 10 V
4.5
15 V

4.0
3.5
3.0
0

0.25

0.50

0.75

1.0

1.25

1.50

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.5

2.0

VGS = 0 V

VGS = 10 V
ID = 0.5 A

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

1.0

100C
100

25C

10

0.5

0
50

4466

25

25

50

75

100

125

150

100

200

300

400

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

500

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
500

1000
VDS = 0 V

450

VGS = 0 V

TJ = 25C

VGS = 0 V
TJ = 25C

350

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

400

300
Ciss

250
200
150
100

Crss

50
0
10

0
VGS

100

Coss
10
Crss

Coss

Crss
5

Ciss

10

15

20

25

VDS

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Figure 7b. High Voltage Capacitance


Variation

4467

360
QT

10

300
VGS

Q1

240

Q2

180

6
4

120

ID = 1 A
TJ = 25C

VDS

Q3

0
0

60

4
QT, TOTAL CHARGE (nC)

0
8

100
VDD = 250 V
ID = 1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD1N50E

tf
td(off)
td(on)

10

tr

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C

0.8

0.6

0.4

0.2

0.5

0.54

0.58
0.62
0.66
0.70
0.74
0.78
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.82

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4468

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N50E
SAFE OPERATING AREA
50

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

10 s

1.0
100 s
1 ms
10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

40

30

20

10

1000

ID = 1 A

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1 0.05

P(pk)
0.02
0.01

t1

SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4469

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD1N60E
Motorola Preferred Device

TMOS POWER FET


1.0 AMPERE
600 VOLTS
RDS(on) = 8.0 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

600

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4470

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

720

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
6.0

4.0

Vdc
mV/C

5.9

8.0

Ohm

9.6
8.4

gFS

0.5

0.8

mhos

Ciss

224

310

pF

Coss

27

40

Crss

6.0

10

td(on)

8.8

20

tr

6.8

14

td(off)

15

30

tf

20

40

QT

7.1

11

Q1

1.7

Q2

3.2

Q3

3.9

0.82
0.7

1.4

trr

464

ta

36

tb

428

QRR

0.629

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 300 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4471

MTD1N60E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

I D , DRAIN CURRENT (AMPS)

1.8

VGS = 10 V
7V

6V

I D , DRAIN CURRENT (AMPS)

1.6
1.4
1.2
1
0.8
0.6

5V

0.4

VDS 10 V

1.6

1.2

0.8
100C

0.4

0.2

TJ = 55C
2

10

12

14

18

16

4.4

4.8

5.2

5.6

10
8
25C
6
4

55C

2
0.2

1.2 1.4
0.8
0.6
1
ID, DRAIN CURRENT (AMPS)

0.4

1.6

1.8

6.4

6.8

9
TJ = 25C

8.5
8
7.5
7

VGS = 10 V

6.5

15 V
6
5.5
5

Figure 3. OnResistance versus Drain Current


and Temperature

0.2

0.4

1.2 1.4
0.6 0.8
1
ID, DRAIN CURRENT (AMPS)

1.6

1.8

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.4

1000
VGS = 0 V

VGS = 10 V
ID = 0.5 A

TJ = 125C
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.2 3.6

Figure 2. Transfer Characteristics

TJ = 100C

2.8

Figure 1. OnRegion Characteristics

VGS = 10 V

2.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

16
14

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C

1.6
1.2
0.8

100

100C

10
25C

0.4
0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4472

150

500
100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

500

VDS = 0 V

450

1000

TJ = 25C

VGS = 0 V
TJ = 25C

Ciss

400
350

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

VGS = 0 V

300
Ciss

250
Crss

200
150

Ciss

100

Coss
10
Crss

100
Coss

50

Crss

0
10

0
VGS

1
5

10

15

20

25

VDS

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Figure 7b. High Voltage Capacitance


Variation

4473

600

QT

500

10
VGS

400
Q1

Q2

300

ID = 1 A
TJ = 25C

200
100

2
Q3
0

VDS
3

0
8

100
VDD = 300 V
ID = 1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD1N60E

tf
td(off)
td(on)

10

tr

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1
VGS = 0 V
TJ = 25C

0.8

0.6

0.4

0.2

0
0.5

0.54

0.58

0.62

0.66

0.7

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4474

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N60E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINNTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10
10 s

100 s
0.1
dc

1 ms
10 ms

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

50
ID = 1 A
40

30

20

10

0.001
0.1

10

100

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t,TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4475

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD1N80E
Motorola Preferred Device

TMOS POWER FET


1.0 AMPERES
800 VOLTS
RDS(on) = 12 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

G
CASE 369A13, Style 2
DPAK

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

800

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

800

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

48
0.38
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 )

EAS

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

2.6
100
71.4

C/W

TL

260

20

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4476

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

981

10
100

100

2.0

3.3
6.3

4.0

mV/C

10.3

12

Ohm

11

14.4
12.6

gFS

0.4

0.985

mhos

Ciss

297

420

pF

Coss

29

40

Crss

6.0

10

td(on)

9.0

20

tr

10

20

td(off)

20

40

tf

27

55

QT

9.6

20

Q1

2.1

Q2

4.2

Q3

4.7

0.82
0.7

1.2

trr

317

ta

56

tb

261

QRR

0.93

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 1.0 Adc)
(VGS = 10 Vdc, ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4477

MTD1N80E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

TJ = 25C

1.6

ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

2.0

VGS = 10 V
6V
8V

1.2

0.8
5V
0.4

VDS 10 V

1.6

1.2

0.8
TJ = 100C
0.4

25C

4V
0

10

15

0
2.0

20

55C
2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

18

VGS = 10 V

15

100C

12
TJ = 25C

9
6

55C

3
0

0.25

0.50

0.75

1.0

1.25

1.50

1.75

2.0

16
TJ = 25C
15
14
13
12

VGS = 10 V

11

15 V

10
9
0

0.4

ID, DRAIN CURRENT (AMPS)

2.5

1.6

2.0

1000
VGS = 10 V
ID = 0.5 A

VGS = 0 V
TJ = 125C

2
100
1.5

0.5

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4478

0.8
1.2
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

0
50

6.0

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

3.0
3.5
4.0
4.5
5.0
5.5
VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

100C

10
25C
1

0.1
0

100

200
300
400
500
600
700
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

700
600
500
400

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000

TJ = 25C
VGS = 0 V

Ciss

300
200

TJ = 25C
VGS = 0

Ciss

100
Coss
10
Crss

Coss
100
0

Crss
0

10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

4479

400
QT

10

300

VGS
8
6

200
Q1

Q2

4
ID = 1 A
100
TJ = 25C

2
0

VDS

Q3
0

4
6
QT, TOTAL CHARGE (nC)

0
10

100
VDD = 400 V
ID = 1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD1N80E

tf
td(off)

10
tr

td(on)

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C
0.8

0.6

0.4

0.2

0
0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4480

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD1N80E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

1
100 s
1 ms
10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

100

20

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

ID = 1 A
15

10

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)
0.02

0.01
SINGLE PULSE

0.01
0.00001

t1

t2
DUTY CYCLE, D = t1/t2
0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4481

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTD1P50E

TMOS E-FET.
High Energy Power FET

Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


1.0 AMPERES
500 VOLTS
15

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Capability Specified at Elevated


Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

CASE 369A13, Style 2


DPAK Surface Mount
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Symbol

Value

Unit

DraintoSource Voltage

VDSS

500

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Single Pulse (tp 50 s)

VGS
VGSM

20
40

Vdc

Drain Current Continuous @ TC = 25C


Drain Current Continuous @ TC = 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
4.0

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TC = 25C, when mounted to minimum recommended pad size

PD

50
0.4
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

EAS

45

mJ

RJC
RJA
RJA

2.5
100
71.4

C/W

TL

260

Rating

Operating and Storage Temperature Range

Apk

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 )

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

4482

Motorola TMOS Power MOSFET Transistor Device Data

MTD1P50E
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

TBD

Vdc
V/C

10
100

100

nAdc

2.0

3.1
TBD

4.0

Vdc
mV/C

12

15

Ohms

18
15.8

gFS

0.4

0.6

mhos

Ciss

TBD

TBD

pF

Coss

TBD

TBD

Crss

TBD

TBD

td(on)

TBD

TBD

tr

TBD

TBD

td(off)

TBD

TBD

tf

TBD

TBD

QT

TBD

TBD

Q1

TBD

Q2

TBD

Q3

TBD

2.0
TBD

3.5

trr

TBD

ta

TBD

tb

TBD

QRR

TBD

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 250 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 1.0 Adc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

* Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

4483

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
DPAK for Surface Mount
Designer's

MTD2N40E
Motorola Preferred Device

TMOS POWER FET


2.0 AMPERES
400 VOLTS
RDS(on) = 3.5 OHM

NChannel EnhancementMode Silicon Gate


This advanced high voltage TMOS EFET is designed to
withstand high energy in the avalanche and switch efficiently. This
new high energy device also offers a draintosoure diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD1N40E

CASE 369A13, Style 2


DPAK

G
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.5
6.0

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TC = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4484

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

451

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
7.0

4.0

Vdc
mV/C

3.1

3.5

Ohm

7.3

8.4
7.4

gFS

0.5

1.0

mhos

Ciss

229

320

pF

Coss

34

40

Crss

7.3

10

td(on)

8.0

16

tr

8.4

14

td(off)

12

26

tf

11

20

QT

8.6

12

Q1

2.6

Q2

3.2

Q3

5.0

0.88
0.76

1.2

trr

156

ta

99

tb

57

QRR

0.89

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mA)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 200 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 320 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4485

MTD2N40E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V
8V

3.2

ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

7V
2.4
6V

1.6

0.8

VDS 10 V

1
TJ = 100C

5V

12

16

20

55C
2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 25C

55C

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

5.0
TJ = 25C
4.5

4.0
VGS = 10 V
3.5

15 V

3.0

2.5
0

0.5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

1000
VGS = 10 V
ID = 1 A

VGS = 0 V

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 2. Transfer Characteristics

VGS = 10 V

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


8

25C

1.5

TJ = 125C
100

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4486

150

10
0

100
200
300
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
500

VGS = 0 V

Ciss

300
Ciss

Crss
200

Ciss

Coss
10
Crss

Crss
5

TJ = 25C
VGS = 0 V

100

Coss

100
0
10

1000

TJ = 25C

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

400

VDS = 0 V

10

15

20

25

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

1
10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

4487

400
QT

10

300

VGS

8
6

200

Q2

Q1
4

TJ = 25C
ID = 2 A

2
0

VDS

Q3
0

100

100

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTD2N40E

td(off)
tf

10

tr

TJ = 25C
ID = 2 A
VDD = 200 V
VGS = 10 V

td(on)

10

100

RG, GATE RESISTANCE (OHMS)

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
1.5

0.5

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4488

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N40E
SAFE OPERATING AREA

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10
10 s
100 s
1 ms

10 ms
dc

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

100

45

ID = 2 A

40
35
30
25
20
15
10
5
0

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4489

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD2N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


TMOS POWER FET
2.0 AMPERES
500 VOLTS
RDS(on) = 3.6 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD2N50

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.5
6.0

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 75 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 50 mH, RG = 25 )

EAS

100

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4490

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

562

Vdc
mV/C

0.1
1.0

100

nAdc

2.0

6.0

4.0

Vdc
mV/C

2.7

3.6

Ohm

6.0

8.64
6.48

gFS

1.2

1.6

mhos

Ciss

323

450

pF

Coss

45

63

Crss

9.0

20

td(on)

8.0

20

tr

6.0

20

td(off)

16

30

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Figure 8)

(VDS = 400 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

tf

10

20

QT

11

15

Q1

2.0

Q2

5.4

Q3

5.1

0.8
0.69

1.6

trr

334

ta

62

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

272

QRR

0.99

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4491

MTD2N50E
TYPICAL ELECTRICAL CHARACTERISTICS
4.0

4
VGS = 10 V

VDS 10 V

3.5

6V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C
3

2
5V
1

25C

TJ = 55C
3.0
100C

2.5
2.0
1.5
1.0
0.5

10

12

14

16

18

3.5

4.0

TJ = 100C

5
4
25C
3
55C

2
1
0
0.4

0.8

1.2
1.6 2.0 2.4
2.8
ID, DRAIN CURRENT (AMPS)

3.2

3.6

4.0

5.5

6.0

6.5

7.0

3.6

4.0

4.2
TJ = 25C
3.8

3.4
VGS = 10 V
3.0
15 V
2.6
0

0.4

0.8

1.2 1.6 2.0 2.4


2.8
ID, DRAIN CURRENT (AMPS)

3.2

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000
VGS = 0 V

VGS = 10 V
ID = 1 A

TJ = 125C
I DSS , LEAKAGE (nA)

1.6

1.2

0.8

4492

5.0

Figure 2. Transfer Characteristics

0.4
50

4.5

Figure 1. OnRegion Characteristics

Figure 3. OnResistance versus Drain Current


and Temperature

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

8
7

0
2.0

20

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25

25

50

75

100

125

150

100

100C

25C
10

50

100

150

200

250

300

350

400

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

450

500

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

700

1000
Ciss

VGS = 0 V

VGS = 0 V

TJ = 25C

500
400

Ciss

Crss

300

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

600

VDS = 0 V

200

Ciss

100
Coss
10
Crss

Coss

100
Crss

1
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4493

18

450
ID = 2 A
TJ = 25C

16

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDD = 250 V
ID = 2 A
VGS = 10 V
TJ = 25C

400
350

14
12

300

QT

250

10
8

VGS

Q1

200

Q2

150

100
50

2
VDS

Q3
0

100

0
10

t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD2N50E

td(off)
tf
td(on)
tr

10

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

2.0
VGS = 0 V
TJ = 25C

1.6

1.2

0.8

0.4

0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4494

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD2N50E
SAFE OPERATING AREA
100
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

10 s

1.0

100 s
1 ms
10 ms

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01

dc

100
1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 2 A
80

60

40

20
0

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4495

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD3N25E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


TMOS POWER FET
3 AMPERES
250 VOLTS
RDS(on) = 1.4 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

250

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

250

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

3.0
2.0
9.0

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4496

Motorola TMOS Power MOSFET Transistor Device Data

MTD3N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

367

Vdc
mV/C

10
100

100

nAdc

2.0

6.0

4.0

Vdc
mV/C

1.1

1.4

Ohm

5.04
4.41

gFS

1.0

1.8

mhos

Ciss

307

430

pF

Coss

57

75

Crss

14

25

td(on)

7.0

15

tr

5.0

15

td(off)

15

30

tf

6.0

15

QT

9.8

15

Q1

2.1

Q2

4.2

Q3

3.8

0.9
0.728

1.6

trr

153

ta

64

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 125 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 ))

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 200 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 3.0 Adc, VGS = 0 Vdc)


(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Fi
(See
Figure 14)

((IS = 3.0 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

89

QRR

0.51

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4497

MTD3N25E
TYPICAL ELECTRICAL CHARACTERISTICS
6

6
VGS = 10 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

7V

6V
3
2
5V

VDS 10 V

TJ = 55C

5
25C
4
100C
3
2
1

1
4V
0

4.5

5.0

5.5

6.0

6.5

TJ = 100C

2.0
1.6

25C
1.2
0.8

55C
0.5 1.0

1.5

2.0 2.5 3.0 3.5 4.0 4.5


ID, DRAIN CURRENT (AMPS)

5.0

5.5

6.0

7.0

7.5

1.7
TJ = 25C

1.6
1.5
1.4
1.3

VGS = 10 V

1.2
1.1

15 V
1.0

Figure 3. OnResistance versus Drain Current


and Temperature

0.5

1.0 1.5

2.0 2.5 3.0 3.5 4.0 4.5


ID, DRAIN CURRENT (AMPS)

5.0

5.5 6.0

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

100
VGS = 10 V
ID = 1.5 A

1.6

VGS = 0 V

TJ = 125C
100C

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

4.0

Figure 2. Transfer Characteristics

2.4

1.2

0.8

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4498

3.5

Figure 1. OnRegion Characteristics

2.8

0.4
50

3.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

3.2

0.4

0
2.0

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

150

10
25C

1.0

50
100
150
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD3N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800

C, CAPACITANCE (pF)

700

VDS = 0

Ciss

VGS = 0

TJ = 25C

600
500

Crss

400

Ciss

300
200

Coss

100

Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4499

240
QT
200

10
VGS

8
Q1

160

Q2

120

TJ = 25C
ID = 3 A

80

40
Q3

VDS

0
0

3
5
6
4
7
QG, TOTAL GATE CHARGE (nC)

0
10

100
VDD = 125 V
ID = 3 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD3N25E

td(off)
10
tf
tr

td(on)

1
1

Figure 8. GateToSource and DrainToSource


Voltage versus Ttotal Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


3.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

2.5
2.0
1.5
1.0
0.5
0
0.5

0.55
0.6
0.65
0.85
0.7
0.75
0.8
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.9

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4500

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD3N25E
SAFE OPERATING AREA

VGS = 20 V
SINGLE PULSE
TC = 25C

45

10 s

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

100 s

1.0
1 ms
10 ms
ds

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

40

ID = 3 A

35
30
25
20
15
10
5
0

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E02
t, TIME (s)

1.0E03

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4501

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD4N20E
Motorola Preferred Device

TMOS POWER FET


4.0 AMPERES
200 VOLTS
RDS(on) = 1.2 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

D
CASE 369A13, Style 2
DPAK

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

G
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GateSource Voltage Continuous


Nonrepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

4.0
2.6
12

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 )

EAS

80

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4502

Motorola TMOS Power MOSFET Transistor Device Data

MTD4N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

263

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.98

1.2

Ohm

3.5

5.8
5.0

gFS

1.5

2.1

mhos

Ciss

311

430

pF

Coss

66

80

Crss

11

20

td(on)

10

17

tr

4.0

26

td(off)

15

29

tf

6.0

18

QT

9.2

14

Q1

2.4

Q2

4.1

Q3

5.6

0.92
0.82

trr

123

ta

82

tb

41

QRR

0.58

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 4.0 Adc)
(ID = 2.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 100 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 160 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 4.0 Adc, VGS = 0 Vdc)


(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4503

MTD4N20E
TYPICAL ELECTRICAL CHARACTERISTICS
8

TJ = 25C

VGS = 10 V

7V

5
4
3

6V

2
5V

1
0

10

12

100C

4
3
2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

3.5
3.0
2.5
TJ = 100C

2.0
1.5
1.0

25C

0.5

55C

0
0

25C

14

4.5
4.0

TJ = 55C

2.8

TJ = 25C

2.4
2.0
1.6
VGS = 10 V

1.2

15 V

0.8
0.4
0
0

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

2.5

VGS = 0 V

VGS = 10 V
ID = 4 A

TJ = 125C

2.0

100C
I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

I D , DRAIN CURRENT (AMPS)

9V

VDS 10 V

8V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

1.5

1.0

10
25C

0.5

0
50

4504

25

25

50

75

100

125

150

50

100

150

200

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

250

Motorola TMOS Power MOSFET Transistor Device Data

MTD4N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800

VDS = 0 V

C, CAPACITANCE (pF)

600

400

VGS = 0 V

TJ = 25C

Ciss

Crss

Ciss

200
Coss
Crss
0

10

10

15

20

25

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4505

180

16

160
QT

14

140

12

120
VGS

10

Q1

100

Q2
80

8
6

60
ID = 4 A
TJ = 25C

4
2
0

20

VDS

Q3
4

40

100

t, TIME (ns)

18

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTD4N20E

td(off)
td(on)

10

tf

tr

0
10

VDD = 100 V
ID = 4 A
VGS = 10 V
TJ = 25C

10

100

RG, GATE RESISTANCE (OHMS)

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


4.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

3.2

2.4

1.6

0.8

0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

4506

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD4N20E
SAFE OPERATING AREA

VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms
dc

0.1

80

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

ID = 4 A

60

40

20

0.01
0.1

1.0

10

100

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2

0.1

0.1
0.05

P(pk)
0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E03

1.0E04

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4507

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD5N25E
Motorola Preferred Device

TMOS POWER FET


5.0 AMPERES
250 VOLTS
RDS(on) = 1.0 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

D
CASE 369A13, Style 2
DPAK

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

G
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

Rating

VDSS

250

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

250

Vdc

GateSource Voltage Continuous


Nonrepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

5.0
3.2
15

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

50
0.4
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, IL = 7.5 Apk, L = 3.0 mH, RG = 25 )

EAS

84

mJ

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

2.50
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4508

Motorola TMOS Power MOSFET Transistor Device Data

MTD5N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

326

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
6.0

4.0

Vdc
mV/C

0.81

1.0

Ohm

3.4

6.0
5.3

gFS

1.5

2.6

mhos

Ciss

369

520

pF

Coss

66

90

Crss

14

30

td(on)

10

tr

18

40

td(off)

21

40

tf

18

40

QT

13.2

15

Q1

2.9

Q2

6.2

Q3

5.9

0.93
0.82

1.6

trr

147

ta

100

tb

47

QRR

0.847

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 5.0 Adc)
(ID = 2.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 125 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 200 Vdc, ID = 5.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 5.0 Adc, VGS = 0 Vdc)


(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 5.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4509

MTD5N25E
TYPICAL ELECTRICAL CHARACTERISTICS
10

VGS = 10 V
9V

TJ = 25C

7V

6
6V

5V

25C

6
100C
4

10

12

14

16

18

Figure 2. Transfer Characteristics

3.0
2.5
2.0
TJ = 100C
1.5
25C
1.0
55C
0.5
0
1

6
4
5
7
ID, DRAIN CURRENT (AMPS)

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

VGS = 10 V

VGS, GATETOSOURCE VOLTAGE (VOLTS)

3.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.7
TJ = 25C
1.5

1.3
VGS = 10 V
1.1
15 V
0.9

0.7
0

Figure 3. OnResistance versus Drain Current


and Temperature

3
6
4
5
7
ID, DRAIN CURRENT (AMPS)

10

Figure 4. OnResistance versus Drain Current


and Gate Voltage
100

2.5

VGS = 0 V

VGS = 10 V
ID = 2.5 A

TJ = 125C

2.0
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C

0
0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

8V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

10

1.5

1.0

100C
10

25C

0.5

0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4510

150

50
150
100
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD5N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by
recognizing that the power MOSFET is charge controlled. The
lengths of various switching intervals (t) are determined by
how fast the FET input capacitance can be charged by current
from the generator.

The capacitance (Ciss) is read from the capacitance curve at a


voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate
when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly
with applied voltage. Accordingly, gate charge data is used. In
most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that

At high switching speeds, parasitic circuit elements


complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function
of drain current, the mathematical solution is complex. The
MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance
which effectively adds to the resistance of the driving source,
but the internal resistance is difficult to measure and,
consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and is
believed readily achievable with board mounted components.
Most power electronic loads are inductive; the data in the
figure is taken with a resistive load, which approximates an
optimally snubbed inductive load. Power MOSFETs may be
safely operated into an inductive load; however, snubbing
reduces switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1000

VDS = 0 V

TJ = 25C

Ciss

800
C, CAPACITANCE (pF)

VGS = 0 V

600

400

Ciss

Crss

200
0

Coss
Crss
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4511

300
QT

10

250
VGS
200

8
Q1

Q2

150

ID = 5 A
100
TJ = 25C

50
Q3

VDS
0

8
10
6
QT, TOTAL CHARGE (nC)

12

0
14

100

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD5N25E
VDD = 125 V
ID = 5 A
VGS = 10 V
TJ = 25C

tf

td(off)
tr
10

td(on)

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

5
VGS = 0 V
TJ = 25C
4

0
0.5

0.55

0.65 0.7
0.75 0.8
0.85
0.6
0.9
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.95

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used in
switching circuits with unclamped inductive loads. For reliable

4512

operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated continuous
current (ID), in accordance with industry custom. The energy
rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD5N25E
SAFE OPERATING AREA
120

VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1 ms
10 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

dc

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 5 A
80

60

40

20
0

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

0.05

P(pk)

0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0

10

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4513

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V.

Designer's

TMOS

MTD5P06V
Motorola Preferred Device

Power Field Effect Transistor


DPAK for Surface Mount

TMOS POWER FET


5 AMPERES
60 VOLTS
RDS(on) = 0.450 OHM

PChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 369A13, Style 2


DPAK Surface Mount

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm, 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GatetoSource Voltage Nonrepetitive (tp 10 ms)
Drain Current Continuous @ 25C
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
25

Vdc
Vpk

5
4
18

Adc

40
0 27
0.27
2.1

Watts
W/C
Watts

ID
ID
IDM
PD

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 5 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

TJ, Tstg
EAS

55 to 175

125

mJ

RJC
RJA
RJA

3.75
100
71.4

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4514

Motorola TMOS Power MOSFET Transistor Device Data

MTD5P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

61.2

10
100

100

2.0

2.8
4.7

4.0

mV/C

0.34

0.45

Ohm

2.7
2.6

1.5

3.6

Ciss

367

510

Coss

140

200

Crss

29

60

td(on)

11

20

tr

26

50

td(off)

17

30

tf

19

40

QT

12

20

Q1

3.0

Q2

5.0

Q3

5.0

1.72
1.34

3.5

trr

97

ta

73

tb

24

QRR

0.42

4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 5 Adc)
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 15 Vdc, ID = 2.5 Adc)

Vdc

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 5 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 5 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 5 Adc, VGS = 0 Vdc)


(IS = 5 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4515

MTD5P06V
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

VGS = 10V
8

10

8V

9V

7V

TJ = 25C
6V

4
5V
2

6
5
4
3
2

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.45
0.4

25C

0.35
0.3

0.4
TJ = 25C
VGS = 10 V

0.35

0.5

15 V

0.3

0.25

55C

0.25
0.2
1

4
5
6
7
ID, DRAIN CURRENT (AMPS)

10

0.2

Figure 3. OnResistance versus Drain Current


and Temperature

4
5
7
6
ID, DRAIN CURRENT (AMPS)

10

100

1.8
1.6

Figure 4. OnResistance versus Drain Current


and Gate Voltage

VGS = 0 V

VGS = 10 V
ID = 2.5 A

1.4
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.6
0.55

100C

25C

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 55C

4V
0

VDS 10 V

9
I D , DRAIN CURRENT (AMPS)

10

1.2
1
0.8
0.6

TJ = 125C

10

0.4
0.2
50

25

0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4516

175

50
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD5P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1000

VDS = 0 V

Ciss

900

TJ = 25C

C, CAPACITANCE (pF)

800
700
600

Crss

500
Ciss

400
300

Coss

200
100
0

Crss

VGS = 0 V
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4517

60
VGS
54

QT

48

8
7

Q2

Q1

42

36

30

24
18

3
2

Q3
VDS

1
0

TJ = 25C
ID = 5 A

12

10

12
6
0
14

100
TJ = 25C
ID = 5 A
VDD = 30 V
VGS = 10 V
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD5P06V

tr
td(off)
tf

10

td(on)

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


5
TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4518

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD5P06V
SAFE OPERATING AREA
140

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s
1 ms

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

dc

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 5 A
120
100
80
60
40
20
0

100

25

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4519

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD6N10E
Motorola Preferred Device

TMOS POWER FET


6.0 AMPERES
100 VOLTS
RDS(on) = 0.400 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD5N10

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

6.0
4.5
18

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG =25 )

EAS

50

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4520

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

124

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
4.0

4.0

Vdc
mV/C

0.29

0.4

Ohm

1.75

2.9
2.5

gFS

1.5

2.4

mhos

Ciss

310

420

pF

Coss

120

210

Crss

25

50

td(on)

8.0

15

tr

31

49

td(off)

13

31

tf

12

27

QT

10

14

Q1

3.3

Q2

4.3

Q3

5.5

0.98
0.9

2.0

trr

86.7

ta

64

tb

22.7

QRR

0.327

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 13 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 50 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 80 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4521

MTD6N10E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12

VGS = 10 V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

10

I D , DRAIN CURRENT (AMPS)

VDS 10 V

9V

8V

8
6

7V
4
6V

TJ = 55C

10

25C

100C

6
4
2

2
5V
0

2
4
6
3
5
7
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.65

VGS = 10 V

0.55

TJ = 100C

0.45

0.35

25C

0.25

0.15

55C

4
8
6
10
ID, DRAIN CURRENT (AMPS)

12

14

0.45

TJ = 25C

0.40
VGS = 10 V

0.35

0.30
15 V
0.25

0.20

8
12
6
10
ID, DRAIN CURRENT (AMPS)

16

14

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

100
VGS = 0 V

VGS = 10 V
ID = 3 A

TJ = 125C
100C

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.6

10

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

4
6
8
5
7
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.4
1.2
1.0

10

25C

0.8
0.6
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4522

150

40
80
20
60
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

120

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800

C, CAPACITANCE (pF)

VDS = 0 V
600

VGS = 0 V

TJ = 25C

Ciss

400

Ciss
Crss

200

Coss
Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4523

120

QT

10

100
VGS
Q1

Q2

80

60

40

ID = 6 A
TJ = 25C

20
Q3

VDS
4

10

1000
VDD = 50 V
ID = 6 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD6N10E

100
tr
td(off)
tf
td(on)

10

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


6

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

4
3
2
1
0
0.50 0.55 0.60 0.65

0.70 0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4524

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N10E
SAFE OPERATING AREA
50

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s
1 ms

1.0

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

dc

40
35
30
25
20
15
10
5

0.1
0.1

10

1.0

ID = 6 A

45

0
25

100

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4525

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTD6N15

Power Field Effect Transistor


DPAK for Surface Mount

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


6.0 AMPERES
150 VOLTS
RDS(on) = 0.3 OHM

This TMOS Power FET is designed for high speed, low loss
power switching applications such as switching regulators, converters, solenoid and relay drivers.

Silicon Gate for Fast Switching Speeds


Low RDS(on) 0.3 Max
Rugged SOA is Power Dissipation Limited
SourcetoDrain Diode Characterized for Use With
Inductive Loads
Low Drive Requirement VGS(th) = 4.0 V Max
Surface Mount Package on 16 mm Tape

CASE 369A13, Style 2


DPAK (TO252)

G
S

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

150

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

150

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 50 s)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

6.0
20

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

20
0.16

Watts
W/C

Total Power Dissipation @ TA = 25C


Derate above 25C

PD

1.25
0.01

Watts
W/C

Total Power Dissipation @ TA = 25C (1)


Derate above 25C

PD

1.75
0.014

Watts
W/C

TJ, Tstg

65 to +150

RJC
RJA
RJA

6.25
100
71.4

C/W

Operating and Storage Junction Temperature Range

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic

Symbol

Min

Max

Unit

V(BR)DSS

150

Vdc

10
100

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0 Vdc)
TJ = 125C

Adc

IDSS

(1) These ratings are applicable when surface mounted on the minimum pad size recommended.

(continued)

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

4526

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N15
ELECTRICAL CHARACTERISTICS continued (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Max

Unit

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc)


TJ = 100C

VGS(th)

2.0
1.5

4.5
4.0

Vdc

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

0.3

Ohm

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 100C)

VDS(on)

1.8
1.5

gFS

2.5

mhos

Ciss

1200

pF

Coss

500

Crss

120

td(on)

50

tr

180

td(off)

200

tf

100

OFF CHARACTERISTICS continued

ON CHARACTERISTICS*

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,


f = 1.0 MHz)
S Fi
See
Figure 11

Output Capacitance
Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS* (TJ = 100C)


TurnOn Delay Time
(VDD = 25 Vdc, ID = 3.0 Adc,
RG = 50 )
See Figures 13 and 14

Rise Time
TurnOff Delay Time
Fall Time
Total Gate Charge

(VDS = 0.8 Rated VDSS,


ID = Rated ID, VGS = 10 Vdc)
S Figure
See
Fi
12

GateSource Charge
GateDrain Charge

Qg

15 (Typ)

30

Qgs

8.0 (Typ)

Qgd

7.0 (Typ)

VSD

1.3 (Typ)

2.0

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage
(IS = 6.0
6 0 Adc,
Ad di/dt = 25 A/s
A/
VGS = 0 Vdc,)

Forward TurnOn Time

ton

Reverse Recovery Time

Vdc

Limited by stray inductance

trr

325 (Typ)

ns

* Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

PD, POWER DISSIPATION (WATTS)

TA TC
2.5 25

20

1.5

15

10

0.5

TC

25

50

75

100

125

150

T, TEMPERATURE (C)

Figure 1. Power Derating

Motorola TMOS Power MOSFET Transistor Device Data

4527

MTD6N15
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

10 V

VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS)

24
9V

20

TJ = 25C
16
8V
12
8

7V

6V
5V

10
20
30
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

3.6

2.8

2.4

50

TJ = 25C

I D , DRAIN CURRENT (AMPS)

VDS = 10 V
12
10
8
6
4

100C
55C

2
0
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

1.6

0.25
0.20

TJ = 100C

25C

0.15
55C

0.10
0.05
0

8
12
16
ID, DRAIN CURRENT (AMPS)

20

Figure 6. OnResistance versus Drain Current

4528

VGS = 0 V
ID = 0.25 mA

1.2

0.8

0.4

0
50

50
100
150
TJ, JUNCTION TEMPERATURE (C)

200

Figure 5. Breakdown Voltage Variation


With Temperature

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS = 10 V

150

Figure 4. Transfer Characteristics

0.30

0
50
100
TJ, JUNCTION TEMPERATURE (C)

Figure 3. GateThreshold Voltage Variation


With Temperature
V(BR)DSS , DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 2. OnRegion Characteristics

14

VDS = VGS
ID = 1 mA

3.2

1.6

VGS = 10 V
ID = 3 A

1.2

0.8

0.4

0
50

50
100
150
TJ, JUNCTION TEMPERATURE (C)

200

Figure 7. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N15
SAFE OPERATING AREA
20
100 s

10 s

10

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

20

1 ms

5
2

10 ms

1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.5
0.2
0.1

dc

15

TJ 150C

10

TC = 25C
VGS = 20 V SINGLE PULSE

0.05
0.03
0.3 0.5 0.7 1
2 3 5 7 10
20 30 50 70 100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200 300

20

Figure 8. Maximum Rated Forward Biased


Safe Operating Area

40
60
80
100
120
140
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

160

Figure 9. Maximum Rated Switching


Safe Operating Area

SWITCHING SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

The switching safe operating area (SOA) of Figure 9 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.
The power averaged over a complete switching cycle must
be less than:

r(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE (NORMALIZED)

FORWARD BIASED SAFE OPERATING AREA

0.7
0.5

D = 0.5

0.3

0.2

TJ(max) TC
RJC

0.2
0.1
P(pk)

0.1 0.05
0.07
0.02
0.05
0.03
0.02
0.01
0.01

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE

0.02 0.03

0.05

0.1

0.2 0.3

0.5

1
2 3
5
10
t, TIME OR PULSE WIDTH (ms)

20

RJC(t) = r(t) RJC


RJC(t) = 6.25C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1000

Figure 10. Thermal Response

Motorola TMOS Power MOSFET Transistor Device Data

4529

MTD6N15
2000
TJ = 25C
VGS = 0

C, CAPACITANCE (pF)

1600

1200

800

400

0
15

Ciss

VDS = 0

Coss
Crss
25
30

10

5
5
10
20
35
0
15
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATE SOURCE VOLTAGE (VOLTS)

16
TJ = 25C
ID = 6 A
12
75 V

120 V

VDS = 50 V

8
12
Qg, TOTAL GATE CHARGE (nC)

Figure 11. Capacitance Variation

16

20

Figure 12. Gate Charge versus


GateToSource Voltage

RESISTIVE SWITCHING
VDD
ton
td(on)

RL
Vout
Vin
PULSE GENERATOR
Rgen

50

tr
90%

td(off)

tf
90%

OUTPUT, Vout
INVERTED

DUT

z = 50

toff

10%
90%

50
INPUT, Vin

50%

50%
10%
PULSE WIDTH

Figure 13. Switching Test Circuit

4530

Figure 14. Switching Waveforms

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD6N20E
Motorola Preferred Device

TMOS POWER FET


6.0 AMPERES
200 VOLTS
RDS(on) = 0.7 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
G
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

200

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GatetoSource Voltage Continuous


Nonrepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

6.0
3.8
18

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

50
0.4
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25 )

EAS

54

mJ

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

2.50
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4531

MTD6N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

0.46

0.700

Ohm

2.9

5.0
4.4

gFS

1.5

mhos

Ciss

342

480

pF

Coss

92

130

Crss

27

55

td(on)

8.8

17.6

tr

29

58

td(off)

22

44

tf

20

40.8

QT

13.7

21

Q1

2.7

Q2

7.1

Q3

5.9

0.99
0.9

1.2

trr

138

ta

93

tb

45

QRR

0.74

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 100 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 160 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4532

Motorola TMOS Power MOSFET Transistor Device Data

MTD6N20E
TYPICAL ELECTRICAL CHARACTERISTICS

7V

6
4

6V

5V
2

100C

6
4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

1.2
VGS = 10 V
1.0
TJ = 100C

0.8
0.6

25C

0.4
55C
0.2
0

25C

10

12

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 55C

10

0.70
TJ = 25C
0.65
0.60
0.55
VGS = 10 V
0.50
0.45

15 V

0.40
0

10

12

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

2.5

2.0

VGS = 10 V
ID = 3 A

VGS = 0 V

I DSS , LEAKAGE (nA)

I D , DRAIN CURRENT (AMPS)

8V

VDS 10 V

9V

10

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

12

VGS = 10 V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

12

1.5

1.0

TJ = 125C

100C
10

25C

0.5

0
50

25

25

50

75

100

125

150

50

100

150

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

200

4533

MTD6N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
900

VDS = 0 V

TJ = 25C

Ciss

750
C, CAPACITANCE (pF)

VGS = 0 V

600
450

Ciss

Crss
300

Coss
150
Crss
0

10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4534

Motorola TMOS Power MOSFET Transistor Device Data

90
QT

10

75
VGS
Q1

Q2

60

45

30

ID = 6 A
TJ = 25C

2
VDS

Q3

0
0

6
8
10
QT, TOTAL CHARGE (nC)

12

15
0
14

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD6N20E
VDD = 100 V
ID = 6 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
10

tf

td(on)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
VGS = 0 V
TJ = 25C

5
4
3
2
1
0

0.5

0.6
0.7
0.8
0.9
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

Motorola TMOS Power MOSFET Transistor Device Data

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

4535

MTD6N20E
SAFE OPERATING AREA
60

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10

100 s
1.0

1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10 ms
dc

100
1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 6 A

50
40
30
20
10
0

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01
SINGLE PULSE
0.01
1.0E05

t1

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4536

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD6P10E
Motorola Preferred Device

TMOS POWER FET


6.0 AMPERES
100 VOLTS
RDS(on) = 0.66 OHM

PChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK

G
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

100

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GatetoSource Voltage Continuous


Nonrepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

6.0
3.9
18

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

50
0.4
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 )

EAS

180

mJ

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

2.50
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4537

MTD6P10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

124

Vdc
mV/C

10
100

100

nAdc

2.0

2.9
4.0

4.0

Vdc
mV/C

0.56

0.66

Ohm

3.6

4.8
4.2

gFS

1.5

3.0

mhos

Ciss

550

840

pF

Coss

154

240

Crss

27

56

td(on)

12

25

tr

29

60

td(off)

18

40

tf

20

QT

15.3

22

Q1

4.1

Q2

7.1

Q3

6.8

1.8
1.5

5.0

trr

112

ta

92

tb

20

QRR

0.603

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 50 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 80 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4538

Motorola TMOS Power MOSFET Transistor Device Data

MTD6P10E
TYPICAL ELECTRICAL CHARACTERISTICS
12

9V

10
8

8V

6
7V

TJ = 55C
25C
100C

8
6
4

6V

VDS 10 V

10

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

12

VGS = 10 V

TJ = 25C

5V
2

10

12

14

16

18

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

1.1
1.0
TJ = 100C

0.9
0.8
0.7

25C

0.6
0.5
55C
0.4
0.3

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.3
1.2

20

10

12

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 25C
0.9
0.8
0.7

VGS = 10 V

0.6
15 V

0.5
0.4

10

12

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

1.8
1.6

10

1.0

VGS = 10 V
ID = 3 A

VGS = 0 V

1.4

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2
1.0
0.8

TJ = 125C

0.6
0.4
50

25

25

50

75

100

125

150

10
120

100

80

60

40

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4539

MTD6P10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1600

C, CAPACITANCE (pF)

VGS = 0 V

VDS = 0 V

1400

TJ = 25C

Ciss

1200
1000
800
Crss

600

Ciss

400
Coss

200
0

Crss
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4540

Motorola TMOS Power MOSFET Transistor Device Data

90
QT

10
Q1

75

VGS

Q2

60

45

30

ID = 6 A
TJ = 25C

15
VDS

Q3

0
0

6
8
10
QT, TOTAL CHARGE (nC)

12

14

0
16

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD6P10E
VDD = 50 V
ID = 6 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
td(on)
tf

10

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
VGS = 0 V
TJ = 25C

5
4
3
2
1
0
0.50

0.75
1.0
1.25
1.50
1.75
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

2.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

Motorola TMOS Power MOSFET Transistor Device Data

reliable operation, the stored energy from circuit inductance


dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

4541

MTD6P10E
SAFE OPERATING AREA
200
VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s
1 ms
10 ms

1.0

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 6 A

160

120

80

40

100

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)
0.02

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4542

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD9N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


TMOS POWER FET
9.0 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD6N10

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

9.0
5.0
27

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 )

EAS

40

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4543

MTD9N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

103

Vdc
mV/C

10
100

100

nAdc

2.0

6.0

4.0

Vdc
mV/C

0.17

0.25

Ohm

2.43
2.40

gFS

4.0

mhos

Ciss

610

1200

pF

Coss

176

400

Crss

14

30

td(on)

8.8

20

tr

28

60

td(off)

16

30

tf

4.8

10

QT

14

21

Q1

5.2

Q2

3.2

Q3

6.6

0.98
0.9

1.8

trr

91

ta

71

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 4.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 9.0 Adc)
(ID = 4.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 50 Vdc, ID = 9.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 ))

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 80 Vdc, ID = 9.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 9.0 Adc, VGS = 0 Vdc)


(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Fi
(See
Figure 14)

((IS = 9.0 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

20

QRR

0.4

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4544

Motorola TMOS Power MOSFET Transistor Device Data

MTD9N10E
TYPICAL ELECTRICAL CHARACTERISTICS
18

18

14

8V
7V

12
10
8

6V

6
4

5V

2
0

25C

12
100C
10
8
6
4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

0.35
TJ = 100C

0.30
0.25

25C

0.20
0.15

55C
0.10
0

14

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0

10

0.45
0.40

6
8
12
10
ID, DRAIN CURRENT (AMPS)

14

16

18

0.25
TJ = 25C
0.23

0.21

0.19

VGS = 10 V

0.17
15 V
0.15
0

8
10
6
12
ID, DRAIN CURRENT (AMPS)

14

16

18

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.9

100
VGS = 0 V

VGS = 10 V
ID = 4.5 A

1.5

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.7

TJ = 55C

4V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

16
I D , DRAIN CURRENT (AMPS)

16
I D , DRAIN CURRENT (AMPS)

TJ = 25C

VGS = 10 V

1.3
1.1
0.9

TJ = 125C
10
100C

1.0
25C

0.7
0.5
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

0.1
30

80
90
40
60
50
70
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage


Current versus Voltage

4545

MTD9N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data
is used. In most cases, a satisfactory estimate of average
input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times
may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

C, CAPACITANCE (pF)

1000

VDS = 0

VGS = 0

TJ = 25C

Ciss

800
Ciss
600

Crss

400

Coss

200
Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4546

Motorola TMOS Power MOSFET Transistor Device Data

120
QT
100

10
VGS

Q2

80

Q1
60

6
4

ID = 9 A
TJ = 25C

40

20
Q3

VDS

0
14

0
0

12

4
6
8
10
QG, TOTAL GATE CHARGE (nC)

100
VDD = 50 V
ID = 9 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD9N10E

tr
td(off)

10
td(on)

tf

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


9
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

8
7
6
5
4
3
2
1
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4547

MTD9N10E
SAFE OPERATING AREA

10

40
VGS = 20 V
SINGLE
PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s
1 ms

1.0

10 ms
dc
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10
1.0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 9 A
32

24

16

0
25

100

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4548

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD10N10EL
Motorola Preferred Device

TMOS POWER FET


10 AMPERES
100 VOLTS
RDS(on) = 0.22 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

G
CASE 369A13, Style 2
DPAK Surface Mount

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

100

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

10
6.0
35

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Rating

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk, L = 1.0 mH, RG =25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
50

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4549

MTD10N10EL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

115

10
100

100

1.0

1.45
4.0

2.0

mV/C

0.17

0.22

Ohm

1.85

2.6
2.3

gFS

2.5

7.9

mhos

Ciss

741

1040

pF

Coss

175

250

Crss

18.9

40

td(on)

11

20

tr

74

150

td(off)

17

30

tf

38

80

QT

9.3

15

Q1

2.56

Q2

4.4

Q3

4.66

0.98
0.898

1.6

trr

124.7

ta

86

tb

38.7

QRR

0.539

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 5.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 50 Vdc, ID = 10 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 10 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 10 Adc, VGS = 0 Vdc)


(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4550

Motorola TMOS Power MOSFET Transistor Device Data

MTD10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20

7V

VGS = 10 V

TJ = 25C

VDS 5 V

5V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

20

4.5 V
15
4V
10
3.5 V
5

3V

55C
15
25C

TJ = 100C

10

2V
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.35
VGS = 10 V

100C
0.25
TJ = 25C
0.15
55C

0.05

10

15

20

0.25
TJ = 25C

VGS = 5 V

0.2

10 V
0.15

0.1
5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

10
15
ID, DRAIN CURRENT (AMPS)

20

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100
VGS = 5 V
ID = 5 A

VGS = 0 V

TJ = 125C

1.5
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2
3
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

10

100C

1
0

80
20
40
60
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage


Current versus Voltage

4551

MTD10N10EL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at a


voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the on
state when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1800

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

1600 C
iss
1400
1200
1000
800

Crss

Ciss

600
400

Coss

200
0
10

Crss
5

5
0
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4552

Motorola TMOS Power MOSFET Transistor Device Data

QT

75
VGS

60
45

Q2

Q1

VDS

Q3
0

30

TJ = 25C
ID = 10 A

15
0
10

1000

TJ = 25C
ID = 10 A
VDS = 100 V
VGS = 5 V

100
t, TIME (ns)

90

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTD10N10EL

tr
tf
td(off)
td(on)

10

10

100

RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

10
VGS = 0 V
TJ = 25C

0
0.5

0.6

0.7

0.8

0.9

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4553

MTD10N10EL
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

10
100 s
1 ms
10 ms

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10

50

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

ID = 10 A

40

30

20

10

100

25

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE

0.01
0.00001

t2
DUTY CYCLE, D = t1/t2
0.0001

0.001

0.01
t, TIME (ms)

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0

10

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4554

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
DPAK for Surface Mount or
Insertion Mount
Designer's

MTD12N06EZL

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.180 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS power FET is designed to withstand high
energy in the avalanche and mode and switch efficiently. This new
high energy device also offers a gatetosource zener diode
designed for 4 kV ESD protection (human body model).

ESD Protected
4 kV Human Body Model
400 V Machine Model
Avalanche Energy Capability
Internal SourceToDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

CASE 369A13, Style 2


DPAK Surface Mount
S
Symbol

Value

Unit

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 50 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
7.1
36

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

45
0.36
1.75

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

72

mJ

RJC
RJA
RJA

2.78
100
71.4

C/W

TL

260

DrainSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4555

MTD12N06EZL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

0.06

Vdc
mV/C

10
100

18

Vdc

500
100

nAdc
Adc

1.0

1.5
4.0

2.0

Vdc
mV/C

0.18

Ohm

2.6
2.3

gFS

3.0

6.8

mhos

Ciss

430

600

pF

Coss

224

310

Crss

51

100

td(on)

70

90

tr

436

540

td(off)

158

380

tf

186

340

QT

10.6

40

Q1

1.4

Q2

5.9

Q3

6.0

1.1
1.05

1.4

trr

325

ta

124

tb

201

QRR

2.013

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

Adc

IDSS

GateSource Breakdown Voltage


(VDS = 0 V, IG = 10 mA)
GateBody Leakage Current
(VGS = 10 Vdc, VDS = 0 V, TJ = 25C)
(VGS = 10 Vdc, VDS = 0 V, TJ = 150C)

IGSS

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 30 Vdc, ID = 12 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
res 8 & 9)
(See Fig
Figures
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4556

Motorola TMOS Power MOSFET Transistor Device Data

MTD12N06EZL
TYPICAL ELECTRICAL CHARACTERISTICS
24

VGS = 10 V

TJ = 25C

5V

I D , DRAIN CURRENT (AMPS)

8V

6V

18

12
4V
6

0
1

0.5

TJ = 55C
25C
12
100C
6

2.5

2.5

3.5

4.5

5.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5 V

0.13

TJ = 100C

0.11
25C

0.09

0.07

55C

0.05
0

12

18

24

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.15

1.5

0.096

TJ = 25C

VGS = 10 V
0.088

0.084

0.08

15 V

12

18

24

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

1.8
1.6
1.4

0.092

VGS = 0 V

VGS = 5 V
ID = 12 A
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

18

0
0

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS 10 V

7V
I D , DRAIN CURRENT (AMPS)

24

1.2
1
0.8
0.6

TJ = 125C

10

100C

0.4

25C

0.2
0
50

25

25

50

75

100

125

150

10

20

30

40

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

60

4557

MTD12N06EZL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1200
VDS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

1000
800
600
Ciss

400

Coss
200
Crss
0
0

10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4558

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

50
VGS

4
Q2

Q1

40
30

ID = 12 A
TJ = 25C

20
10

1
VDS

Q3

0
0

4
6
QT, TOTAL CHARGE (nC)

0
10

1000
VDD = 30 V
ID = 12 A
VGS = 5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD12N06EZL
tr
tf
td(off)
100
td(on)

10
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

10
8
6
4
2
0
0

0.2

0.4

0.6

0.8

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4559

MTD12N06EZL
SAFE OPERATING AREA
75
VGS = 20 V
SINGLE PULSE
TC = 25C

1 ms
10 ms
dc

100 s

10 s

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

ID = 12 A
60

45

30

15
0

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

25

100

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.05

0.1
0.02
0.01

t1

SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4560

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTD15N06V

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

TM

CASE 369A13, Style 2


DPAK Surface Mount
S

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

Symbol

Value

Unit

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse (tp 50 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
8.7
45

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

55
0.36
2.1

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

113

mJ

RJC
RJA
RJA

2.73
100
71.4

C/W

TL

260

DrainSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4561

MTD15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

67

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
5.0

4.0

Vdc
mV/C

0.08

0.12

Ohm

2.0

2.2
1.9

gFS

4.0

6.2

mhos

Ciss

469

660

pF

Coss

148

200

Crss

35

60

td(on)

7.6

20

tr

51

100

td(off)

18

40

tf

33

70

QT

14.4

20

Q1

2.8

Q2

6.4

Q3

6.1

1.05
1.5

1.6

trr

59.3

ta

46

tb

13.3

QRR

0.165

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 15 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4562

Motorola TMOS Power MOSFET Transistor Device Data

MTD15N06V
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

25

30

8V

VGS = 10 V
9V

TJ = 25C

7V

20
15

6V

10
5V

25C
TJ = 55C

20
15
10

10

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
0.15

TJ = 100C

0.10

25C
55C

0.05

25

10
15
20
ID, DRAIN CURRENT (AMPS)

30

0.13
TJ = 25C
0.11

VGS = 10 V

0.09

15 V
0.07

0.05

10

15

20

25

30

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

VGS = 0 V

VGS = 10 V
ID = 7.5 A
1.6
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.20

25

5
0

100C

VDS 10 V
I D , DRAIN CURRENT (AMPS)

30

1.2

0.8

0.4
50

TJ = 125C

10

TJ, JUNCTION TEMPERATURE (C)

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

25

25

50

75

100

125

150

175

Motorola TMOS Power MOSFET Transistor Device Data

60

4563

MTD15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

1200
Ciss
900

600

Ciss

Crss

300

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4564

Motorola TMOS Power MOSFET Transistor Device Data

QT

10

50
VGS

8
Q2

Q1

40
30

20
ID = 15 A
TJ = 25C

2
0

Q3
3

VDS
6

12

10
0
15

1000
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

60

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD15N06V

100
tr
tf
td(off)
10

td(on)

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


15

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
12

0
0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4565

MTD15N06V
SAFE OPERATING AREA
120

VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10
100 s
1 ms
10 ms

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

ID = 15 A

100
80
60
40
20
0

0.1

1.0

100

10

25

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02

t1

0.01
SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4566

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTD15N06VL

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

TMOS POWER FET


15 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

TM

CASE 369A13, Style 2


DPAK Surface Mount
S

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
12
53

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ 25C(1)

PD

60
0.4
2.1

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

113

mJ

RJC
RJA
RJA

2.5
100
71.4

C/W

TL

260

Rating
DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient(1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4567

MTD15N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

10
100

100

1.0

1.5
TBD

2.0

mV/C

0.075

0.085

Ohm

1.5
1.3

gFS

8.0

10

mhos

Ciss

630

880

pF

Coss

270

380

Crss

56

110

td(on)

26

50

tr

105

210

td(off)

80

160

tf

70

140

QT

12

20

Q1

3.0

Q2

8.0

Q3

10

1.0
0.9

1.6

trr

100

ta

55

tb

45

QRR

0.345

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 7.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5.0 Vdc, ID = 15 Adc)
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 15 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4568

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
High Density Power FET
DPAK for Surface Mount
Designer's

MTD20N03HDL
Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
20 AMPERES
30 VOLTS
RDS(on) = 0.035 OHM

NChannel EnhancementMode Silicon Gate


This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

30

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

30

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
16
60

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size

PD

74
0.6
1.75

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )

EAS

200

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.67
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4569

MTD20N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

30

43

10
100

100

1.0

1.5
5.0

2.0

0.034
0.030

0.040
0.035

0.55

0.8
0.7

10

13

Ciss

880

1260

Coss

300

420

Crss

80

112

td(on)

13

15.8

tr

212

238

td(off)

37

30

tf

84

96

QT

13.4

18.9

Q1

3.0

Q2

7.3

Q3

6.0

0.95
0.87

1.1

trr

33

ta

23

tb

10

QRR

33

4.5

7.5

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DraintoSource OnResistance


(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)

(Cpk 2.0) (3)

DraintoSource OnVoltage (VGS = 5.0 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)

VGS(th)

Vdc

RDS(on)

Ohm

VDS(on)

Forward Transconductance
(VDS = 5.0 Vdc, ID = 10 Adc)

mV/C

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
(VDD = 15 Vdc, ID = 20 Adc,
VGS = 5.0
5 0 Vdc,
Vdc
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 24 Vdc, ID = 20 Adc,


VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
(Cpk 2.0) (3)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
(See
Fi
15)
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A).

4570

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40

40
VGS = 10 V

I D , DRAIN CURRENT (AMPS)

8V
30

VDS 10 V

4.5 V

5V

I D , DRAIN CURRENT (AMPS)

TJ = 25C

4V

6V

20
3.5 V
10
3V

30

20

10
100C

2.5 V
0
1.0

0
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

TJ = 55C
1.4

1.8

2.2

2.6

3.0

3.4

3.8

4.2

VGS, GATETOSOURCE VOLTAGE (Volts)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5 V
0.044

TJ = 100C

0.036
25C
0.028
55C
0.020
8

24

16

32

40

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS, DRAINTOSOURCE VOLTAGE (Volts)

0.052

4.6

5.0

0.036
TJ = 25C
0.032

VGS = 5 V

0.028

10 V

0.024

0.020
0

16

24

32

40

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8
1.6

1000

VGS = 5 V
ID = 10 A

VGS = 0 V
TJ = 125C
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C

1.4
1.2
1.0

100
100C

10
25C

0.8
0.6
50

25

25

50

75

100

125

150

12

18

24

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (Volts)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

30

4571

MTD20N03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800
VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

2400
2000

Ciss

1600
1200

Crss
Ciss

800
Coss

400
0
10

Crss
0

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4572

Motorola TMOS Power MOSFET Transistor Device Data

28

12

24
QT

10

20

16

VGS

12
Q1

Q2

8
ID = 20 A
TJ = 25C 4

2
Q3
0

VDS
4

10

12

0
14

1000
VDD = 15 V
ID = 20 A
VGS = 5.0 V
TJ = 25C
t, TIME (ns)

14

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD20N03HDL

tr
100
tf

td(off)
10

td(on)
1

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

20

16

VGS = 0 V
TJ = 25C

12

4
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4573

MTD20N03HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

200
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C
100 s
10
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1

4574

1.0

dc

10

100

ID = 20 A
160

120

80

40

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4575

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
Power Field Effect Transistor
DPAK for Surface Mount
Designer's

MTD20N06HD
Motorola Preferred Device

TMOS POWER FET


20 AMPERES
60 VOLTS
RDS(on) = 0.045 OHM

NChannel EnhancementMode Silicon Gate


This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
16
60

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 0.3 mH, RG = 25 )

EAS

60

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4576

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

60

54

10
100

100

2.0

7.0

4.0

0.035

0.045

1.2
1.1

5.0

6.0

Ciss

607

840

Coss

218

290

Crss

55

110

td(on)

9.2

18

tr

61.2

122

td(off)

19

38

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 10 Adc)

(Cpk 2.0) (3)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)
Forward Transconductance
(VDS = 4.0 Vdc, ID = 10 Adc)

VGS(th)

Vdc

RDS(on)

mV/C
Ohm

VDS(on)

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

Vd VGS = 0 Vdc,
Vd
(VDS = 25 Vdc,
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 7)
((VDS = 48 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

tf

36

72

QT

17

24

Q1

3.4

Q2

7.75

Q3

7.46

0.95
0.88

1.0

trr

35.7

ta

24

tb

11.7

QRR

0.055

4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
(Cpk 8.0) (3)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A).

Motorola TMOS Power MOSFET Transistor Device Data

4577

MTD20N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
40

8V

32
TJ = 25C
24
6V
16

5V

30

20

10

0.5

TJ = 55C

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.044
0.040
0.036

25C

0.032
0.028
55C
0.024
0.020
10

20

30

40

0.040
TJ = 25C
0.038
VGS = 10 V

0.036
0.034
0.032

15 V

0.030
0.028
0

10

20

30

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (Volts)

0.052
0.048

VDS, DRAINTOSOURCE VOLTAGE (Volts)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C

100C
0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

7V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

40

9V

VGS = 10 V

40

1.6

1.4

VGS = 10 V
ID = 10 A

1.2

1.0

0.8
0.6
50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

4578

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1600
VDS = 0 V

1400

TJ = 25C

VGS = 0 V

C, CAPACITANCE (pF)

Ciss
1200
1000
800

Crss

Ciss

600
400

Coss

200

Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 6. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4579

60
QT
50

10
VGS

40

Q1

Q2
30

6
ID = 20 A
TJ = 25C

10

2
0

20

Q3
VDS
0

10

12

14

16

0
18

1000
VDD = 30 V
ID = 20 A
VGS = 10 V
TJ = 25C

tr

100
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD20N06HD

tf
td(off)
10

td(on)

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 7. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 8. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 10. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse
recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

20
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

18
16
14
12
10
8
6
4
2
0
0.50

0.58

0.66

0.74

0.82

0.90

0.98

VSD, SOURCETODRAIN VOLTAGE (Volts)

Figure 9. Diode Forward Voltage versus Current

4580

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 10. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy
rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents
below rated continuous ID can safely be assumed to equal
the values indicated.

60
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s
100 s
1 ms
10 ms
dc
1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0

10

100

ID = 20 A
50
40
30
20
10
0

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4581

MTD20N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4582

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTD20N06HDL

HDTMOS E-FET
High Density Power FET
DPAK for Surface Mount or
Insertion Mount

Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
20 AMPERES
60 VOLTS
RDS(on) = 0.045 OHM

NChannel EnhancementMode Silicon Gate


This advanced highcell density HDTMOS EFET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits, and inductive loads. The avalanche energy
capability is specified to eliminate the guesswork in designs where
inductive loads are switched, and to offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Available in Insertion Mount, Add 1 or 1 to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
12
60

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C (1)

PD

40
0.32
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Rating

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
200

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4583

MTD20N06HDL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

25

10
100

100

1.0

1.5
6.0

2.0

0.045
0.037

0.070
0.045

0.76

1.2
1.1

gFS

6.0

12

mhos

Ciss

863

1232

pF

Coss

216

300

Crss

53

73

td(on)

11

15

tr

151

190

td(off)

34

35

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc)

Vdc
mV/C
Ohm

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 30 Vdc, ID = 20 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc)

tf

75

98

QT

14.6

22

Q1

3.25

Q2

7.75

Q3

7.0

0.95
0.88

1.1

trr

22

ta

12

tb

34

QRR

0.049

4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 20 Adc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4584

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40
8V
6V
5V
4.5 V

30

4V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

40

VGS = 10 V

TJ = 25C

3.5 V

20

3V

10

VDS 10 V

30

20

100C

10

25C

2.5 V
0

0.2

0.6

0.4

0.8

1.0

1.2

1.4

1.6

1.8

0
1.5

2.0

TJ = 55C
2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 5 V
TJ = 100C

0.05
25C

0.03

55C

0.02
0.01
0
0

10

20

30

40

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.07

0.04

3.5

4.5

Figure 2. Transfer Characteristics

0.05
TJ = 25C
0.045

5V

0.04

0.035

VGS = 10 V

0.03
0.025
0

10

20

30

40

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

1.4

1000
VGS = 5 V
ID = 10 A

VGS = 0 V

I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.06

2.5

VGS, GATETOSOURCE VOLTAGE (Volts)

1.2

1.0

TJ = 125C

100

100C
10

25C

0.8
0.6
50

25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

10

20

30

40

50

60

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DraintoSource Leakage


Current versus Voltage

4585

MTD20N06HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
3000

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

2500 Ciss
2000
1500 C
rss
Ciss

1000
Coss

500
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4586

Motorola TMOS Power MOSFET Transistor Device Data

60

QT

50

10
VGS

VDS

40
30

6
Q1

Q2

ID = 20 A
TJ = 25C

4
2
0

20
10

Q3
0

10

12

14

0
16

1000
VDD = 30 V
ID = 20 A
VGS = 5 V
TJ = 25C

tr

100

tf

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD20N06HDL

td(off)
10

td(on)

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 10. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

20
VGS = 0 V
TJ = 25C

16

12

4
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4587

MTD20N06HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

200
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

100 s
10

1 ms
10 ms

1.0
0.1

4588

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0

dc
10

100

ID = 20 A
150

100

50

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0

10

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4589

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTD20N06V

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

TMOS POWER FET


20 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 369A13, Style 2


DPAK Surface Mount

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
13
70

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ 25C(1)

PD

60
0.4
2.1

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

200

mJ

RJC
RJA
RJA

2.5
100
71.4

C/W

TL

260

Rating
DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient(1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

4590

Motorola TMOS Power MOSFET Transistor Device Data

MTD20N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

10
100

100

2.0

2.8
TBD

4.0

mV/C

0.065

0.085

Ohm

2.0
1.9

gFS

6.0

8.0

mhos

Ciss

590

830

pF

Coss

180

250

Crss

40

80

td(on)

8.7

20

tr

77

150

td(off)

26

50

tf

46

90

QT

28

40

Q1

4.0

Q2

9.0

Q3

8.0

1.0
0.96

1.6

trr

60

ta

52

tb

8.0

QRR

0.172

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4591

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
High Density Power FET
DPAK for Surface Mount
Designer's

MTD20P03HDL
Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
19 AMPERES
30 VOLTS
RDS(on) = 0.099 OHM

PChannel EnhancementMode Silicon Gate


This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

CASE 369A13, Style 2


DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

30

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

30

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

19
12
57

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size

PD

75
0.6
1.75

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 19 Apk, L = 1.1 mH, RG = 25 )

EAS

200

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA
RJA

1.67
100
71.4

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4592

Motorola TMOS Power MOSFET Transistor Device Data

MTD20P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

30

15

10
100

100

1.0

1.5
4.0

2.0

120
90

99

0.94

2.2
1.9

5.0

6.0

Ciss

770

1064

Coss

360

504

Crss

130

182

td(on)

18

25.2

tr

178

246.4

td(off)

21

26.6

tf

72

98

QT

15

22.4

Q1

3.0

Q2

11

Q3

8.2

3.1
2.56

3.4

trr

78

ta

50

tb

28

QRR

0.209

4.5

7.5

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DraintoSource OnResistance


(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 9.5 Adc)

(Cpk 2.0) (3)

DraintoSource OnVoltage (VGS = 5.0 Vdc)


(ID = 19 Adc)
(ID = 9.5 Adc, TJ = 125C)
Forward Transconductance
(VDS = 8.0 Vdc, ID = 9.5 Adc)

VGS(th)

Vdc

RDS(on)

mV/C
m

VDS(on)

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 19 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 1.3 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 24 Vdc, ID =19 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
(Cpk 2.0) (3)

(IS = 19 Adc, VGS = 0 Vdc)


(IS = 19 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 15)
((IS = 19 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A).

Motorola TMOS Power MOSFET Transistor Device Data

4593

MTD20P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40

40
VGS = 10 V

24
4V
16
3.5 V
8

3V
2.5 V

0
1

0.16

100C

24

16

1.5

2.0

2.5

3.5

3.0

4.0

4.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5 V

0.14
TJ = 100C
0.12

0.10

25C

0.08

55C

0.06
0

25C

32

0
1.0

12

16

20

24

28

32

40

36

0.16

5.0

5.5

36

40

TJ = 25C

0.14

0.12
VGS = 5 V

0.10

0.08
10 V
0.06
0

12

16

20

24

28

32

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.3

100
VGS = 5 V
ID = 10 A

VGS = 0 V

TJ = 125C

1.2
I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)


R DS(on) , DRAINTOSOURCE RESISTANCE
(NORMALIZED)

I D , DRAIN CURRENT (AMPS)

4.5 V

TJ = 55C

5V

8V

32

VDS 5 V

6V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

1.1

1.0

10

100C

0.9
0.8
50

4594

25

25

50

75

100

125

150

12

16

20

24

28

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

32

Motorola TMOS Power MOSFET Transistor Device Data

MTD20P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800
VDS = 0 V

TJ = 25C

VGS = 0 V

C, CAPACITANCE (pF)

2400
2000

Ciss

1600
1200 C
rss

Ciss

800

Coss

400
0
10

Crss
0

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4595

35

QT

30

Q2

25
VGS

Q1
4

20

15
ID = 19 A
TJ = 25C

2
1
0

VDS

Q3
0

10

10

12

0
16

14

1000
VDD = 15 V
ID = 19 A
VGS = 5.0 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD20P03HDL

tr

tf

100

td(off)
td(on)
10

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

20
VGS = 0 V
TJ = 25C

16

12

4
0
0.3

0.7

1.1

1.5

1.9

2.3

2.7

3.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4596

Motorola TMOS Power MOSFET Transistor Device Data

MTD20P03HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

200
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
100 s
1 ms

10

10 ms
dc
1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

1.0

10

100

ID = 19 A
160

120

80

40

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4597

MTD20P03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4598

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET
High Density Power FET
DPAK for Surface Mount
Designer's

MTD20P06HDL
Motorola Preferred Device

TMOS POWER FET


LOGIC LEVEL
15 AMPERES
60 VOLTS
RDS(on) = 175 M

PChannel EnhancementMode Silicon Gate


This advanced highcell density HDTMOS EFET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

Ultra Low RDS(on), HighCell Density, HDTMOS


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
Surface Mount Package Available in 16 mm, 13inch/2500
Unit, Tape & Reel, Add T4 Suffix to Part Number

G
CASE 369A13, Style 2
DPAK
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
9.0
45

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C (1)

PD

72
0.58
1.75

Watts
W/C
Watts

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25 )

EAS

300

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)

RJC
RJA
RJA

1.73
100
71.4

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4599

MTD20P06HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

81.3

1.0
10

100

1.0

1.7
3.9

2.0

mV/C

143

175

2.3
1.6

3.0
2.0

gFS

9.0

11

mhos

pF

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(VGS = 5.0 Vdc, ID = 7.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance

Ciss

850

1190

Coss

210

290

Crss

66

130

td(on)

19

38

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 30 Vdc, ID = 15 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 5.0 Vdc)

tr

175

350

td(off)

41

82

tf

68

136

QT

20.6

29

Q1

3.7

Q2

7.6

Q3

8.4

2.5
1.9

3.0

trr

64

ta

50

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

14

QRR

0.177

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4600

Motorola TMOS Power MOSFET Transistor Device Data

MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
30

VGS = 10 V

TJ = 25C

30

9V

20
15

6V
10
5V
5

4V
0

0.40

VDS 5 V

25

25C

TJ = 55C
20
100C
15
10
5
0

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5 V

0.32

0.24
TJ = 100C
25C

0.16

55C
0.08

0
0

10

20

15

30

25

0.275

TJ = 25C

0.250
0.225
0.200
0.175
VGS = 5 V
0.150
10 V

0.125
0.100
0

10

15

20

30

25

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

1.8
1.6

VGS = 0 V

VGS = 5 V
ID = 7.5 A

1.4
I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

7V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

25

I D , DRAIN CURRENT (AMPS)

8V

1.2
1
0.8
0.6

TJ = 125C
10

100C

0.4
0.2
0
50

25

25

50

75

100

125

150

10

20

30

40

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

60

4601

MTD20P06HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2500

VDS = 0 V

TJ = 25C

VGS = 0 V

Ciss
C, CAPACITANCE (pF)

2000

1500
Crss

Ciss

1000

500
Coss

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4602

Motorola TMOS Power MOSFET Transistor Device Data

50
QT

45

40
35

4
VDS

30

VGS

25
Q1

Q2

15
10

1
0

20

ID = 15 A
TJ = 25C

Q3

5
8

12

16

0
24

20

1000
VDD = 30 V
ID = 15 A
VGS = 5.0 V
TJ = 25C

100

tr
tf

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD20P06HDL

td(off)
td(on)
10

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

15
VGS = 0 V
TJ = 25C

12

0
0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCETODRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4603

MTD20P06HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

300
VGS = 20 V
SINGLE PULSE
TC = 25C
100 s

10

1 ms
10 ms
dc

1.0

0.1
0.1

4604

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0

10

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

ID = 15 A
240

180

120

60

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTD20P06HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4605

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTD2955V

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.200 OHM

PChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 369A13, Style 2


DPAK Surface Mount

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
8.0
42

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ 25C(1)

PD

60
0.4
2.1

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

216

mJ

RJC
RJA
RJA

2.5
100
71.4

C/W

TL

260

Rating
DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient(1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

4606

Motorola TMOS Power MOSFET Transistor Device Data

MTD2955V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

10
100

100

2.0

2.8
TBD

4.0

mV/C

0.185

0.200

Ohm

2.9
2.8

gFS

3.0

5.0

mhos

Ciss

500

700

pF

Coss

200

280

Crss

40

80

td(on)

11

20

tr

38

80

td(off)

18

40

tf

26

50

QT

15

20

Q1

4.0

Q2

7.0

Q3

6.0

1.8
TBD

3.0

trr

114

ta

86

tb

28

QRR

0.553

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 12 Adc)
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4607

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTD3055V

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.15 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 369A13, Style 2


DPAK

G
S

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
7.3
37

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

48
0.32
1.75

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

72

mJ

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Rating
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltage Nonrepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size
Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
EFET, Designers and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4608

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

65

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
5.4

4.0

Vdc
mV/C

0.10

0.15

Ohm

1.3

2.2
1.9

gFS

4.0

5.0

mhos

Ciss

410

500

pF

Coss

130

180

Crss

25

50

td(on)

7.0

10

tr

34

60

td(off)

17

30

tf

18

50

QT

12.2

17

Q1

3.2

Q2

5.2

Q3

5.5

1.0
0.91

1.6

trr

56

ta

40

tb

16

QRR

0.128

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 15)
((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4609

MTD3055V
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
9V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

20

24

8V
I D , DRAIN CURRENT (AMPS)

24

7V
16
12

6V

8
5V
4

VDS 10 V

TJ = 55C
100C

20

25C

16
12
8
4

4V
0

0.3

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.2
TJ = 100C
0.15
25C
0.1
55C

0.05

8
12
16
ID, DRAIN CURRENT (AMPS)

20

24

0.15

10

TJ = 25C

0.14
0.13
0.12
VGS = 10 V

0.11
0.1

15 V
0.09
0.08

Figure 3. OnResistance versus Drain Current


and Temperature

8
16
12
ID, DRAIN CURRENT (AMPS)

20

24

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

100

VGS = 0 V

VGS = 10 V
ID = 6 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.25

R DS(on), DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

1.0

10
TJ = 125C

0.8

0.6
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4610

175

20
30
40
50
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

VDS = 0 V

C, CAPACITANCE (pF)

1000

VGS = 0 V

TJ = 25C

Ciss

800
600
Crss

Ciss

400
Coss

200

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4611

QT
50

10
VGS
Q1

Q2

40
30

6
4
2
0

20

ID = 12 A
TJ = 25C
VDS

Q3
0

10

11

12

10
0
13

1000
VDD = 30 V
ID = 12 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

60

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD3055V

100
tr
td(off)
tf
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


12

I S , SOURCE CURRENT (AMPS)

10

VGS = 0 V
TJ = 25C

8
6
4
2
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4612

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055V
SAFE OPERATING AREA
75

10 s

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s
1 ms
10 ms

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

50

25

0
10

1.0

ID = 12 A

100

25

50

75

100

125

150

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02
0.01

t1

SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4613

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTD3055VL

TMOS V
Power Field Effect Transistor
DPAK for Surface Mount

Motorola Preferred Device

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.18 OHM

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

CASE 369A13, Style 2


DPAK Surface Mount
S

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
20

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
8.0
42

Adc

Total Power Dissipation @ 25C


Derate above 25C
Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size

PD

48
0.32
1.75

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 175

72

mJ

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Rating
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
GateSource Voltag Single Pulse (tp 50 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient, when mounted to minimum recommended pad size
Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4614

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

62

Vdc
mV/C

10
100

100

nAdc

1.0

1.6
3.0

2.0

Vdc
mV/C

0.12

0.18

Ohm

1.6

2.6
2.5

gFS

5.0

8.8

mhos

Ciss

410

570

pF

Coss

114

160

Crss

21

40

td(on)

9.0

20

tr

85

190

td(off)

14

30

tf

43

90

QT

8.1

10

Q1

1.8

Q2

4.2

Q3

3.8

0.97
0.86

1.3

trr

55.7

ta

37

tb

18.7

QRR

0.116

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

3.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4615

MTD3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
24

16

I D , DRAIN CURRENT (AMPS)

4.5 V
4V

12
3.5 V
8
3V

20

100C

16
12
8

0
2.0

3.5

4.5

4.0

5.5

5.0

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.20

TJ = 100C

0.14

25C
55C

0.08

20

8
12
16
ID, DRAIN CURRENT (AMPS)

24

TJ = 25C
0.22

0.17

5V

0.12

VGS = 10 V
0.07

100

I DSS , LEAKAGE (nA)

1.5

1.0

0.5

25

50

75

100

125

150

8
12
16
ID, DRAIN CURRENT (AMPS)

20

24

VGS = 0 V

VGS = 5 V
ID = 6 A

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

25

6.0

0.27

Figure 3. OnResistance versus Drain Current


and Temperature

4616

3.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 5 V

0
50

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.26

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C
25C

0.32

0.02

VDS 10 V

2.5 V

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

24

5V

VGS = 10 V

TJ = 25C

175

10

TJ = 125C

1.0

100C

0.1

TJ, JUNCTION TEMPERATURE (C)

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

60

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1400
1200
C, CAPACITANCE (pF)

VGS = 0 V

VDS = 0 V

TJ = 25C

Ciss

1000
800
600

Ciss

Crss
400

Coss

200

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4617

60
QT
50

40
VGS
30
Q2

Q1
2

20
ID = 12 A
TJ = 25C

Q3
2

VDS
4

10
0
10

1000
VDD = 30 V
ID = 12 A
VGS = 5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTD3055VL

tr
tf

100

td(off)
10

td(on)

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


12

I S , SOURCE CURRENT (AMPS)

10

VGS = 0 V
TJ = 25C

8
6
4
2
0
0.50 0.55 0.60 0.65 0.70

0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4618

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTD3055VL
SAFE OPERATING AREA
75

VGS = 5 V
SINGLE PULSE
TC = 25C

10 s

10
100 s
1 ms
10 ms

1.0

ID = 12 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

50

25

0.1

0
1.0

0.1

10

25

100

50

75

100

125

150

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02

t1

0.01
SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4619

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTDF1N02HD

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
G
Miniature Micro8 Surface Mount Package Saves Board Space
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

SINGLE TMOS
POWER MOSFET
1.7 AMPERES
20 VOLTS
RDS(on) = 0.120 OHM

CASE 846A02, Style 2


Micro8
S
Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

1.9
1.7
14

Adc

0.625
5.0

Watts
mW/C

PD

1.25
10

Watts
mW/C

TJ, Tstg

55 to 150

Typ.

Max.

Unit

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (4)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (3)
Linear Derating Factor (3)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating

Symbol

Junction to Ambient, PCB Mount (1)


RJA
160
200
C/W
RJA
240
300
Junction to Ambient, PCB Mount (2)
RJA
80
100
Junction to Ambient, PBD Mount (3)
When mounted on FR4/G10 board using min. recommended footprint, based on PD in 1 die, 1 die operating. (VGS = 4.5 V, @ Steady State)
When mounted on FR4/G10 board using min. recommended footprint, based on PD in 1 die, both dies operating. (VGS = 4.5 V, @ Steady State)
When mounted on 1 inch square copper board, for comparison to the other SMD devices. (VGS = 4.5 V, @ Steady State)
Repetitive rating; pulse width limited by maximum junction temperature.

Thermal Resistance

(1)
(2)
(3)
(4)

DEVICE MARKING
BA

ORDERING INFORMATION
Device
MTDF1N02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4620

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

5.0

1.0
25

100

0.7

0.9
2.5

99
133

120
160

gFS

2.0

Mhos

Ciss

145

pF

Coss

90

Crss

38

td(on)

8.0

tr

27

td(off)

23

tf

34

td(on)

16

tr

79

td(off)

24

tf

31

QT

3.9

5.5

Q1

0.4

Q2

1.7

Q3

1.5

0.84
0.71

1.0

trr

29

ta

14

tb

15

QRR

0.018

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 1.7 Adc)
(VGS = 2.7 Vdc, ID = 0.85 Adc)

(Cpk 2.0)

(3)

(3)

Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 15 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 10 Vdc, ID = 1.7 Adc,


VGS = 4.5 Vdc, RG = 6 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 10 Vdc, ID = 0.85 Adc,


VGS = 2.7 Vdc, RG = 6 ) (1)

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 1.7 Adc,
VGS = 4.5 Vdc)

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 1.7 Adc, VGS = 0 Vdc) (1)


(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(IS = 1
1.7
7 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4621

MTDF1N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4

VDS 10 V

VGS = 10 V
4.5 V
2.7 V
2.3 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

1.9 V

2.1 V

1.7 V
1

1.5 V

2
100C
25C

TJ = 55C
0
0

1.2

0.8

0.4

1.6

1.5

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.6
ID = 1.7 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
0

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.15
2.7 V
TJ = 25C

0.13

0.11

VGS = 4.5 V

0.09

0.07

0.05
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

2.0
VGS = 4.5 V
ID = 1.7 A

VGS = 0 V
TJ = 125C

1.6
I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

0.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

0.8

100
100C
10
25C
1

0.4

0
50

4622

0.1
25

25

50

75

100

125

150

10

15

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800

C, CAPACITANCE (pF)

600

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

Crss
400

Coss

200

Ciss
0
10

Crss
5

0
VGS

10

15

20

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4623

18

QT

15

12

4
VDS

VGS
9

Q1

Q2
6

2
1
0

ID = 1.7 A
TJ = 25C

Q3
1

2
3
Qg, TOTAL GATE CHARGE (nC)

100

t, TIME (ns)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTDF1N02HD
VDD = 10 V
ID = 1.7 A
VGS = 4.5 V
TJ = 25C

10

tf
tr
td(off)
td(on)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
2.0

VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

1.6

1.2

0.8

0.4

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4624

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance

General Data and Its Use.


Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).

I D , DRAIN CURRENT (AMPS)

100

10

VGS = 8 V
SINGLE PULSE
TC = 25C
1 ms

100 s

10 ms
1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

4625

MTDF1N02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

1000

100

10

D = 0.5
0.2
0.1
0.05
0.02

P(pk)

0.01
1

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.1
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+01

1.0E+02

1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4626

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

1.85 (.072)
1.65 (.065)

0.35 (.013)
0.25 (.010)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

Motorola TMOS Power MOSFET Transistor Device Data

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

4627

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTDF1N03HD

Medium Power Surface Mount Products

TMOS Dual N-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
G
Miniature Micro8 Surface Mount Package Saves Board Space
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided

SINGLE TMOS
POWER MOSFET
1.7 AMPERES
30 VOLTS
RDS(on) = 0.120 OHM

CASE 846A02, Style 2


Micro8
S
Source1

Drain1

Gate1

Drain1

Source2

Drain2

Gate2

Drain2

Top View

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

VDSS
VDGR

30

Vdc

30

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

1.9
1.6
14

Adc

0.625
5.0

Watts
mW/C

PD

1.25
10

Watts
mW/C

TJ, Tstg

55 to 150

Typ.

Max.

Unit

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (4)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (3)
Linear Derating Factor (3)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating

Symbol

Junction to Ambient, PCB Mount (1)


RJA
160
200
C/W
RJA
240
300
Junction to Ambient, PCB Mount (2)
RJA
80
100
Junction to Ambient, PBD Mount (3)
When mounted on FR4/G10 board using min. recommended footprint, based on PD in 1 die, 1 die operating. (VGS = 10 V, @ Steady State)
When mounted on FR4/G10 board using min. recommended footprint, based on PD in 1 die, both dies operating. (VGS = 10 V, @ Steady State)
When mounted on 1 inch square copper board, for comparison to the other SMD devices. (VGS = 10 V, @ Steady State)
Repetitive rating; pulse width limited by maximum junction temperature.

Thermal Resistance

(1)
(2)
(3)
(4)

DEVICE MARKING
BB

ORDERING INFORMATION
Device
MTDF1N03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4628

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

30

29

1.0
25

100

1.0

1.6
3.7

96
135

120
160

gFS

1.0

2.0

Mhos

Ciss

140

pF

Coss

70

Crss

30

td(on)

7.5

tr

10

td(off)

22

tf

18

td(on)

7.0

tr

8.2

td(off)

22

tf

14.5

QT

5.0

7.0

Q1

0.5

Q2

1.65

Q3

1.3

0.84
0.7

1.0

trr

20

ta

12

tb

8.0

QRR

0.012

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 24 Vdc, VGS = 0 Vdc)
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 1.7 Adc)
(VGS = 4.5 Vdc, ID = 0.85 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc)

(3)

(3)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 15 Vdc, ID = 1.7 Adc,


VGS = 10 Vdc, RG = 6 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 15 Vdc, ID = 0.85 Adc,


VGS = 4.5 Vdc, RG = 6 ) (1)

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 1.7 Adc,
VGS = 10 Vdc)

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 1.7 Adc, VGS = 0 Vdc) (1)


(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(IS = 1
1.7
7 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4629

MTDF1N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V

6V
4.5 V

TJ = 25C

3.5 V

VDS 10 V

3.9 V
3

3.7 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3.3 V
3.1 V

2.9 V
1

2.7 V

100C

25C

2.5 V
2.3 V
0

0.5

1.5

0
1.5

2.5

3.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.6
ID = 1.7 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
0

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

4.5

0.18
TJ = 25C
0.16

VGS = 4.5

0.14

0.12
10 V

0.1
0.08
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

2.5
VGS = 10 V
ID = 0.85 A

VGS = 0 V

TJ = 125C

2.0
I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

TJ = 55C

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

1.0

10
100C

25C

0.5

0
50

4630

0.1
25

25

50

75

100

125

150

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

500

C, CAPACITANCE (pF)

400

300

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

Crss

200
Ciss
100

Coss

Crss
0
10

5
VGS

10

15

20

25

30

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4631

30
QT

10

25

20
VGS

VDS

15

6
4 Q1
2
0

Q2

10

ID = 1.7 A
TJ = 25C

Q3
1

4
2
3
Qg, TOTAL GATE CHARGE (nC)

100

t, TIME (ns)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTDF1N03HD

VDD = 15 V
ID = 1.7 A
VGS = 10 V
TJ = 25C

10

td(off)
tf
tr
td(on)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

VGS = 0 V
TJ = 25C

1.5

0.5

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4632

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance
General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

200

VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s
1 ms

10 ms
0.1

0.01
0.1

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

dc
10

160

120

80

40

0
100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

VDD = 30 V
VGS = 10 V
IL = 2.4 A
L = 69 mH

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4633

MTDF1N03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

1000

100

10

D = 0.5
0.2
0.1
0.05
0.02

P(pk)

0.01
1

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.1
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+01

1.0E+02

1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4634

Motorola TMOS Power MOSFET Transistor Device Data

MTDF1N03HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

1.85 (.072)
1.65 (.065)

0.35 (.013)
0.25 (.010)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

Motorola TMOS Power MOSFET Transistor Device Data

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

4635

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTE30N50E

ISOTOP TMOS E-FET.


Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


30 AMPERES
500 VOLTS
RDS(on) = 0.150 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche mode and switch efficiently. This new
energy design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, PWM motor controls, and other
inductive loads. The avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

4
1

2500 V RMS Isolated ISOTOP Package


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
Very Low Internal Parasitic Inductance
IDSS and VDS(on) Specified at Elevated Temperature
U.L. Recognized, File #E69369

3
2

G
SOT227B
S

1.
2.
3.
4.

Source
Gate
Drain
Source 2

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

500

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

30
12
80

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

250
2.0

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL= 30 Apk, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.5
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
3000

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are Motorola recommended choices for future use and best overall value.

4636

Motorola TMOS Power MOSFET Transistor Device Data

MTE30N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

560
566

10
200

100

2.0

3.2
7.0

4.0

mV/C

0.13

0.15

Ohms

4.1

5.0
7.0

gFS

17

mhos

Ciss

7200

10080

pF

Coss

775

1200

Crss

120

250

td(on)

32

60

tr

105

175

td(off)

160

275

tf

115

200

QT

235

350

Q1

35

Q2

110

Q3

65

0.95
0.88

1.2

trr

485

ta

312

tb

173

QRR

8.2

Internal Drain Inductance

LD

5.0

nH

Internal Source Inductance

LS

5.0

nH

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 30 Adc)
(VGS = 10 Vdc, ID = 15 Adc)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 30 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time
Gate Charge
(see fig
figure
re 8)
((VDS = 400 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4637

MTE30N50E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C
50

I D , DRAIN CURRENT (AMPS)

60

VGS = 10 V
8V
6V

40
30

5V

20

VDS 10 V

50

I D , DRAIN CURRENT (AMPS)

60

40
30
100C

20
10

10

25C

4V
0

TJ = 55C

0
0

4
8
2
6
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

0.35
VGS = 10 V
0.3
TJ = 100C
0.25
0.2
25C

0.15
0.1

55C

0.5
0
0

10

20
30
40
ID, DRAIN CURRENT (AMPS)

6.5

50

60

0.17
TJ = 25C
0.16

0.15
VGS = 10 V
0.14
15 V
0.13

0.12

Figure 3. OnResistance versus Drain Current


and Temperature

2.5

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 15 A

VGS = 0 V

TJ = 125C

2
1000

I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3
3.5
4
4.5
5.5
5
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.5

1.5

25

0
50
100
25
75
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4638

100
25C
10

0.5

0
50

100C

150

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTE30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

100000

24000
VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

20000

VGS = 0 V

16000
12000

Crss

Ciss

8000
Coss

4000
0
10

Crss
5

0
VGS

10

15

20

25

TJ = 25C

10000

Ciss

1000

Coss

100

10
10

Crss

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

4639

600
QT

10

500

VGS
Q1

400

Q2

300

200
ID = 30 A
TJ = 25C

2
0

VDS

Q3
0

50

100
150
Qg, TOTAL GATE CHARGE (nC)

200

100
0
250

10000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTE30N50E
VDD = 250 V
ID = 30 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf
tr

100

td(on)
10
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and


DrainToSource Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power aver-

aged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.

30

QRR, STORED CHARGE ( C)

I S , SOURCE CURRENT (AMPS)

dlS/dt = 100 A/s


VDD = 50 V
TJ = 25C

7
6
5
4
3
2

4640

12

18

24

30

VGS = 0 V
TJ = 25C
20

10

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

IS, SOURCE CURRENT (AMPS)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Stored Charge

Figure 11. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

MTE30N50E
SAFE OPERATING AREA
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

VGS = 20 V
SINGLE PULSE
TC = 25C
100 s

10

1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

10
100
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

3000
ID = 30 A
2500
2000
1500
1000
500
0

1000

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
D = 0.5
0.2
0.1
0.1

0.05
0.02
0.01
SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4641

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
ISOTOP TMOS E-FET.
Power Field Effect Transistor
Designer's

MTE53N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


53 AMPERES
500 VOLTS
RDS(on) = 0.080 OHM

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

4
1

2500 V RMS Isolated Isotop Package


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
Very Low Internal Parasitic Inductance
IDSS and VDS(on) Specified at Elevated Temperature
U. L. Recognized, File #E69369

3
2

D
SOT227B
1.
2.
3.
4.

Source
Gate
Drain
Source 2

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

53
33
210

Adc

Total Power Dissipation


Derate above 25C

PD

460
3.70

Watts
W/C

TJ, Tstg

40 to 150

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy
(VDD = 25 Vdc, VGS = 10 Vdc, IL= 53 Apk, L = 0.29 mH, RG =25)

EAS

mJ

RMS Isolation Voltage

VISO

2500

Vac

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.28
62.5

C/W

TL

260

400

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4642

Motorola TMOS Power MOSFET Transistor Device Data

MTE53N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

560
550

Vdc
mV/C

10
100

200

nAdc

2.0

3.2

4.0

Vdc
mV/C

63

80

mOhm

4.8
4.3

gFS

25

45

mhos

Ciss

14400

pF

Coss

1560

Crss

240

td(on)

67

tr

322

td(off)

362

tf

310

QT

474

Q1

86

Q2

206

Q3

148

0.95
0.90

1.3

trr

720

ta

460

tb

260

QRR

15

3.5
5.0

5.0

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 26.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = Vdc)


(ID = 53 Adc)
(ID = 26.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 26.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 53 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time
Gate Charge
((VDS = 400 Vdc, ID = 53 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 53 Adc, VGS = 0 Vdc)


(IS = 53 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 53 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to center of die)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4643

MTE53N50E
TYPICAL ELECTRICAL CHARACTERISTICS
120

VDS 10 V

7V

80

6V

60

100

I D , DRAIN CURRENT (AMPS)

100

I D , DRAIN CURRENT (AMPS)

120

VGS = 10 V
8V

TJ = 25C

5V

40

80
60

100C

40
25C
20

20
4V

TJ = 55C

0
0

3
5
2
4
6
7
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16
VGS = 10 V

TJ = 100C

0.12

0.08

25C

55C

0.04

0
0

40
60
80
ID, DRAIN CURRENT (AMPS)

20

100

120

0.085
TJ = 25C
0.08

0.075
VGS = 10 V
0.07
15 V

0.065

0.06

2.5

VGS = 0 V

VGS = 10 V
ID = 26.5 A

10000

100

120

TJ = 125C
100C

1000

100
25C
10

0.5

25

0
50
100
25
75
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4644

40
60
80
ID, DRAIN CURRENT (AMPS)

100000

1.5

0
50

20

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

3
4
5
VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTE53N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

60000

100000
VDS = 0 V

VGS = 0 V
10000

40000
30000

TJ = 25C
Ciss

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

50000

TJ = 25C

VGS = 0 V

Crss
Ciss

20000

1000

100

Coss

Crss

Coss

10000
Crss
0
10

0
VGS

10

15

20

25

VDS

10
10

100

1000

DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Figure 7b. High Voltage Capacitance Variation

4645

420
QT

10

350

VGS

Q1

280
210

Q2
ID = 53 A
TJ = 25C

140
70

2
0

VDS

Q3
0

100

200
300
Qg, TOTAL GATE CHARGE (nC)

400

0
500

10000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTE53N50E
VDD = 250 V
ID = 53 A
VGS = 10 V
TJ = 25C

1000

td(off)
tr
tf
td(on)

100

10
1

Figure 8. GateToSource and


DrainToSource Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power aver-

aged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.

60

I S , SOURCE CURRENT (AMPS)

50

VGS = 0 V
TJ = 25C

40
30
20
10
0
0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4646

Motorola TMOS Power MOSFET Transistor Device Data

MTE53N50E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100 s
1 ms

10

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

100
10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400
ID = 53 A

350
300
250
200
150
100
50
0

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

0.1

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1
0.05
0.02

0.01

CHIP
JUNCTION

0.01

0.0315
0.0318 F

0.001

0.1856
0.1239 F

0.0629
0.9536 F

SINGLE PULSE

0.0001
1.0E05

AMBIENT

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4647

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
ISOTOP TMOS E-FET.
Power Field Effect Transistor
Designer's

MTE125N20E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


125 AMPERES
200 VOLTS
RDS(on) = 0.015 OHM

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

4
1

2500 V RMS Isolated Isotop Package


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
Very Low Internal Parasitic Inductance
IDSS and VDS(on) Specified at Elevated Temperature
U.L. Recognized, File #E69369

3
2

D
SOT227B
1.
2.
3.
4.

Source
Gate
Drain
Source 2

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GateSource Voltage Continuous

VGS

20

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

125
79
500

Adc

Total Power Dissipation


Derate above 25C

PD

460
3.70

Watts
W/C

TJ, Tstg

40 to 150

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 125 Apk, L = 0.05mH, RG = 25 )

EAS

mJ
400

RMS Isolation Voltage

VISO

2500

Vac

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.28
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4648

Motorola TMOS Power MOSFET Transistor Device Data

MTE125N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

215
250

Vdc
mV/C

10
100

200

nAdc

2.0

3.0

4.0

Vdc
mV/C

12

15

mOhm

2.1
1.9

gFS

50

80

mhos

Ciss

14400

pF

Coss

3600

Crss

920

td(on)

72

tr

574

td(off)

327

tf

376

QT

510

Q1

100

Q2

245

Q3

158

1.00
1.00

1.5

trr

310

ta

220

tb

90

QRR

9.2

3.5
5.0

5.0

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 62.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = Vdc)


(ID = 125 Adc)
(ID = 62.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 62.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 125 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 160 Vdc, ID = 125 Adc,


VGS =10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 125 Adc, VGS = 0 Vdc)


(IS = 125 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 125 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4649

MTE125N20E
TYPICAL ELECTRICAL CHARACTERISTICS
210

160
TJ = 25C

VGS = 10 V

VDS 10 V

7V

8V

140

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

9V
6V

70

5V

120

80

100C

40

25C

4V
0

TJ = 55C

0
0

4
5
1
2
3
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.028
VGS = 10 V
0.024

TJ = 100C

0.02
25C
0.016
0.012
55C
0.008
0.004
0

40

80
120
ID, DRAIN CURRENT (AMPS)

160

200

0.02
TJ = 25C
0.018

VGS = 10 V

0.016
15 V
0.014

0.012

2.2

160

200

VGS = 0 V
TJ = 125C

10000

100C

1000

100
25C

10

0.6

25

25
75
0
50
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4650

80
120
ID, DRAIN CURRENT (AMPS)

100000
VGS = 10 V
ID = 62.5 A

1.4

0.2
50

40

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.8

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

5
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

50
100
150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

Figure 6. DrainToSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTE125N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

60000
VDS = 0 V

TJ = 25C

VGS = 0 V

C, CAPACITANCE (pF)

Ciss
40000
Crss
Ciss

20000
Coss
Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4651

120
QT

10

100

VGS
Q1

80

Q2

60
ID = 62.5 A
TJ = 25C

40
20

2
0

Q3
60
120

VDS
180 240
300
360 420
Qg, TOTAL GATE CHARGE (nC)

480

0
540

1000
VDD = 250 V
tr
ID = 125 A
tf
VGS = 10 V
td(off)
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTE125N20E

100
td(on)

10
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and


DrainToSource Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power aver-

aged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.

I S , SOURCE CURRENT (AMPS)

125
100

VGS = 0 V
TJ = 25C

75

50

25

0
0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4652

Motorola TMOS Power MOSFET Transistor Device Data

MTE125N20E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100 s

100
1 ms

10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

dc

100
10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400
ID = 125 A

350
300
250
200
150
100
50
0

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

1
D = 0.5
0.2
0.1

0.1
0.05
0.02

0.01

CHIP
JUNCTION

0.0174

0.1409

0.0 F

0.01

0.0994 F

0.1217
0.5750 F
AMBIENT

SINGLE PULSE
0.001
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4653

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
ISOTOP TMOS E-FET.
Power Field Effect Transistor
Designer's

MTE215N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


215 AMPERES
100 VOLTS
RDS(on) = 0.0055 OHM

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

4
1

2500 V RMS Isolated Isotop Package


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
Very Low Internal Parasitic Inductance
IDSS and VDS(on) Specified at Elevated Temperature
U. L. Recognized, File #E69369

3
2

D
SOT227B
1.
2.
3.
4.

Source
Gate
Drain
Source 2

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

215
136
860

Adc

Total Power Dissipation


Derate above 25C

PD

460
3.70

Watts
W/C

TJ, Tstg

40 to 150

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 215 Apk, L = 0.017 mH, RG = 25 ,)

EAS

mJ

RMS Isolation Voltage

VISO

2500

Vac

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.28
62.5

C/W

TL

260

400

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4654

Motorola TMOS Power MOSFET Transistor Device Data

MTE215N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

110
120

Vdc
mV/C

10
100

200

nAdc

2.0

3.0

4.0

Vdc
mV/C

4.6

5.5

mOhm

1.5
1.2

gFS

100

140

mhos

Ciss

15200

pF

Coss

6600

Crss

2400

td(on)

48

tr

490

td(off)

186

tf

384

QT

540

Q1

104

Q2

300

Q3

440

1.0
1.2

1.5

trr

145

ta

90

tb

55

QRR

4.6

3.5
5.0

5.0

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 107.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = Vdc)


(ID = 215 Adc)
(ID = 107.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 107.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 50 Vdc, ID = 215 Adc,


VGS = 10 Vdc
Vdc,
RG = 5.0 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 80 Vdc, ID = 215 Adc,


VGS =10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 215 Adc, VGS = 0 Vdc)


(IS = 215 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 215 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4655

MTE215N10E
TYPICAL ELECTRICAL CHARACTERISTICS
240

VGS = 10 V
9V

I D , DRAIN CURRENT (AMPS)

VDS 5 V

7V
8V

165
TJ = 25C

200

I D , DRAIN CURRENT (AMPS)

220

6V

110
5V
55

100C

160

25C

120
80
40

TJ = 55C

4V
0

0
0

0.5

1.5
2.5
1
2
3
3.5
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.018
VGS = 10 V

0.016
0.014
0.012

TJ = 100C
0.01
25C

0.008

55C

0.006
0.004
0

50

100
150
ID, DRAIN CURRENT (AMPS)

200

250

TJ = 25C
0.014

0.012

0.01
VGS = 10 V

0.008

15 V
0.006

100
150
ID, DRAIN CURRENT (AMPS)

200

250

100000
VGS = 0 V

VGS = 10 V
ID = 107.5 A

TJ = 125C

10000

1.2

100C

1000

0.8

100
25C
10

25

0
50
100
25
75
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4656

50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS, LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

1.6

0.6
50

0.016

Figure 3. OnResistance versus Drain Current


and Temperature

1.4

3
5
7
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

150

20
40
60
80
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTE215N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

60000
VDS = 0 V

VGS = 0 V

TJ = 25C

50000
C, CAPACITANCE (pF)

Ciss
40000
30000

Crss
Ciss

20000
Coss
10000
Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4657

120
QT

10

100

80
Q1

VGS

Q2

60

6
4

40
ID = 215 A
TJ = 25C

2
0

VDS

Q3
200

400
600
800
Qg, TOTAL GATE CHARGE (nC)

1000

20
0
1200

1000

tr
tf
td(off)

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTE215N10E

100
td(on)
VDD = 50 V
ID = 215 A
VGS = 10 V
TJ = 25C
10
1

Figure 8. GateToSource and


DrainToSource Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power aver-

I S , SOURCE CURRENT (AMPS)

220
200
180

aged over a complete switching cycle must not exceed


(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.

VGS = 0 V
TJ = 25C

160
140
120
100
80
60
40
20
0
0.5

0.7

0.9

1.1

1.3

1.5

1.7

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4658

Motorola TMOS Power MOSFET Transistor Device Data

MTE215N10E
SAFE OPERATING AREA
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
10 s

VGS = 20 V
SINGLE PULSE
TC = 25C

100 s

100

1 ms

10 ms
10
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400

300
250
200
150
100
50
0

100

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

0.1

ID = 215 A

350

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1
0.05
0.02

0.01

CHIP
JUNCTION

0.01

0.0307
0.0325 F

0.001

0.1127
0.1065 F

0.1366
0.6663 F

SINGLE PULSE

0.0001
1.0E05

AMBIENT

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4659

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP1N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


1.0 AMPERES
500 VOLTS
RDS(on) = 5.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation


Derate above 25C

PD

40
0.32

Watts
W/C

TJ, Tstg

55 to 150

EAS

45

mJ

RJC
RJA

3.13
62.5

TL

260

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS =10 Vdc, IL = 3.0 Apk, L =10 mH, RG = 25 )
Thermal Resistance
Junction to Case
Junction to Ambient, when surface mounted using minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

C/W

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4660

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

480

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
6.0

4.0

Vdc
mV/C

4.3

5.0

Ohm

4.5

6.0
5.30

gFS

0.5

0.9

mhos

Ciss

215

315

pF

Coss

30.2

42

Crss

6.7

12

td(on)

8.0

20

tr

9.0

10

td(off)

14

30

tf

17

30

QT

7.4

9.0

Q1

1.6

Q2

3.8

Q3

0.81
0.68

1.2

trr

145

ta

85

tb

60

QRR

0.702

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125 C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1 .0 Adc)
(ID = 0.5 Adc, TJ = 125 C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc,
TJ = 125 C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4661

MTP1N50E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

2.0
8V

6V

1.50
1.25
1.0
0.75
0.50

5V

0.25
0

10

1.25
1.0
0.75
0.50

TJ = 100C
25C

10

12

14

55C

0
2.0

16

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

1.75

2.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

6
25C
4
55C
2

0.4

0.8
1.2
ID, DRAIN CURRENT (AMPS)

1.6

2.0

6.0

TJ = 25C

5.5
5.0

VGS = 10 V

4.5
15 V
4.0
3.5
3.0

Figure 3. OnResistance versus Drain Current


and Temperature

2.5

0.25

0.50

0.75
1.25
1.0
1.50
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 0.5 A

VGS = 0 V

2.0

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.50

0.25

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

1.75
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

1.75

7V

VGS = 10 V

TJ = 25C

1.5

1.0

100C
100

25C

10

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4662

150

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

500

VDS = 0 V

450

VGS = 0 V

1000

TJ = 25C

VGS = 0 V
TJ = 25C

Ciss

350

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

400

300
250

Ciss

200
150
100

Crss

0
10

100

Coss
10
Crss

Coss

Crss

50

Ciss

1
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4663

360
QT

10

300

VGS
Q1

Q2

240

180

4
2
Q3
0

120

ID = 1 A
TJ = 25C

60

VDS

4
QT, TOTAL CHARGE (nC)

0
8

100
VDD = 250 V
ID =1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP1N50E

tf
td(off)
td(on)
tr

10

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C
0.8

0.6

0.4

0.2

0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4664

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N50E
SAFE OPERATING AREA
50

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

10 s

1.0
100 s
1 ms
10 ms

0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0

10

ID = 1 A
40

30

20

10
0

1000

100

25

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

0.05

P(pk)
0.02
0.01
t1

SINGLE PULSE

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E02

1.0E03

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t,TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4665

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP1N60E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


1.0 AMPERES
600 VOLTS
RDS(on) = 8.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

600

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation


Derate above 25C

PD

50
0.4

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

2.50
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4666

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

5.9

8.0

Ohm

6.4

9.6
8.4

gFS

0.5

0.8

mhos

Ciss

224

310

pF

Coss

27

40

Crss

6.0

10

td(on)

8.8

17.6

tr

6.8

13.6

td(off)

15

30

tf

20

40

QT

7.1

10

Q1

1.7

Q2

3.2

Q3

3.9

0.82
0.7

1.4

trr

464

ta

36

tb

428

QRR

0.629

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 300 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 300 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4667

MTP1N60E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

1.6

6V

1.4
1.2
1
0.8
0.6

5V

0.4
0.2

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.6

1.2

0.8

0.4

TJ = 55C

10

12

14

16

18

2.8

3.2

3.6

4.4

4.8

5.2

5.6

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

10
8

25C

6
4

55C

2
0.2

0.4

0.8
1.2 1.4
0.6
1
ID, DRAIN CURRENT (AMPS)

1.6

1.8

6.4 6.8

9
TJ = 25C

8.5
8
7.5
7

VGS = 10 V
6.5
15 V

6
5.5
5

0.2

0.4

0.6
0.8
1
1.2 1.4
ID, DRAIN CURRENT (AMPS)

1.6

1.8

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.4

1000
VGS = 0 V

VGS = 10 V
ID = 0.5 A
I DSS , LEAKAGE (nA)

2.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

14

20

Figure 3. OnResistance versus Drain Current


and Temperature

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

25C

100C

4V

16

VDS 10 V

7V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

1.8

VGS = 10 V

I D , DRAIN CURRENT (AMPS)

1.6
1.2
0.8

TJ = 125C
100C

100

10
25C

0.4
0
50

4668

25

25

50

75

100

125

150

100

200

300

400

500

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

600

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

500

VDS = 0 V

450

1000

TJ = 25C

VGS = 0 V
TJ = 25C

Ciss

400
350

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

VGS = 0 V

300
Ciss

250
Crss

200
150
100

100

10

Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Coss
Crss

Coss

50

Ciss

1
10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4669

600

QT
10

500
VGS

400
Q1

Q2

300

ID = 1 A
TJ = 25C

200

4
2

100
Q3

VDS
3

100
VDD = 300 V
ID = 1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP1N60E

tf
td(off)
td(on)

10

tr

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


1

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
0.8

0.6

0.4

0.2

0
0.5

0.54

0.58

0.62

0.66

0.7

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4670

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N60E
SAFE OPERATING AREA
50
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10
10 s

100 s
1 ms

0.1

dc
10 ms

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.001
1

0.1

100

10

ID = 1 A
40

30

20

10

1000

25

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01
SINGLE PULSE

0.01
1.0E05

t1

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4671

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP1N80E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

TMOS POWER FET


1.0 AMPERES
800 VOLTS
RDS(on) = 12 OHMS

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

Rating

VDSS

800

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

800

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
4.0

Adc

Total Power Dissipation


Derate above 25C

PD

48
0.38

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 )

EAS

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

2.63
62.5

C/W

TL

260

20

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4672

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

0.981

10
100

100

2.0

3.3
6.3

4.0

mV/C

10.3

12

Ohm

11

14.4
12.6

gFS

0.4

1.4

mhos

Ciss

297

420

pF

Coss

29

40

Crss

6.0

10

td(on)

9.0

20

tr

10

20

td(off)

20

40

tf

27

50

QT

9.6

14

Q1

2.1

Q2

4.2

Q3

4.7

0.82
0.7

1.2

trr

317

ta

56

tb

261

QRR

0.98

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 1.0 Adc)
(VGS = 10 Vdc, ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 400 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4673

MTP1N80E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

TJ = 25C

1.6

ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

2.0

VGS = 10 V
6V
8V

1.2

0.8
5V
0.4

VDS 10 V

1.6

1.2

0.8
TJ = 100C
0.4

25C

4V
0

10

15

0
2.0

20

55C
2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

18

VGS = 10 V

15

100C

12
TJ = 25C

9
6

55C

3
0

0.25

0.50

0.75

1.0

1.25

1.50

1.75

2.0

16
TJ = 25C
15
14
13
12

VGS = 10 V

11

15 V

10
9
0

0.4

ID, DRAIN CURRENT (AMPS)

2.5

1.6

2.0

1000
VGS = 10 V
ID = 0.5 A

VGS = 0 V
TJ = 125C

2
100
1.5

0.5

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4674

0.8
1.2
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

0
50

6.0

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

3.0
3.5
4.0
4.5
5.0
5.5
VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

100C

10
25C
1

0.1
0

100

200
300
400
500
600
700
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

700
600
500
400

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000

TJ = 25C
VGS = 0 V

Ciss

300
200

TJ = 25C
VGS = 0

Ciss

100
Coss
10
Crss

Coss
100
0

Crss
0

10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

4675

400
QT

10

300

VGS
8
6

200
Q1

Q2

4
ID = 1 A
100
TJ = 25C

2
0

VDS

Q3
0

4
6
QT, TOTAL CHARGE (nC)

0
10

100
VDD = 400 V
ID = 1 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP1N80E

tf
td(off)

10
tr

td(on)

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C
0.8

0.6

0.4

0.2

0
0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4676

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N80E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

1
100 s
1 ms
10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

100

20

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

ID = 1 A
15

10

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4677

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP1N100E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


1.0 AMPERES
1000 VOLTS
RDS(on) = 9.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

1000

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1000

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

1.0
0.8
3.0

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4678

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1.251

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
6.0

4.0

Vdc
mV/C

6.7

9.0

Ohm

4.86

9.0
9.9

gFS

0.9

1.32

mhos

Ciss

587

810

pF

Coss

59.6

120

Crss

12.2

25

td(on)

9.0

20

tr

12

25

td(off)

28

55

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 500 Vdc, ID = 1.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)

tf

34

70

QT

14.6

21

Q1

2.8

Q2

6.8

Q3

5.2

0.764
0.62

1.0

trr

655

ta

42

tb

613

QRR

0.957

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 1.0 Adc, VGS = 0 Vdc)


(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4679

MTP1N100E
TYPICAL ELECTRICAL CHARACTERISTICS
2.0

2.0
TJ = 25C

1.4

5V

1.2
1.0
0.8
0.6
0.4

10

12

14

16

18

0.6
0.4

TJ = 55C
2.4

2.8

3.2

3.6

4.0

4.4

4.8

Figure 2. Transfer Characteristics

TJ = 100C

10
8

25C

6
4
55C

2
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

5.2

5.6

8.0
TJ = 25C

7.8
7.6
7.4
7.2
7.0

VGS = 10 V

6.8
6.6

15 V

6.4
6.2
6.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0

1.8

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage
10000

2.8
2.4

TJ = 125C

VGS = 10 V
ID = 0.5 A

1000
100C

2.0
1.6
1.2
0.8

0
50

100
10
1.0

25C

0.1

0.4

VGS = 0 V
0.01
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4680

25C

0.8

Figure 1. OnRegion Characteristics

VGS = 10 V

1.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

12

1.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

16
14

1.4

0
2.0

20

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

1.6

0.2

4V

0.2

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

I D , DRAIN CURRENT (AMPS)

6V

1.6

VDS 10 V

1.8

VGS = 10 V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

1.8

150

100

200 300 400 500 600 700 800 900


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1200

1000

VGS = 0 V

Ciss VDS = 0 V

TJ = 25C
VGS = 0 V
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000
800
Ciss
600

Crss

400

Ciss

TJ = 25C

100
Coss
10

Crss

Coss

200
0
10

Crss
0

5
VGS

1
5

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4681

12

1000

480
QT

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VDD = 500 V
ID = 1 A
VGS = 10 V
TJ = 25C

400

320

VGS
Q1

Q2

240
ID = 1 A
TJ = 25C

4
2
VDS

0
0

tf
td(off)

0
4 5 6 7 8 9 10 11 12 13 14 15
QG, TOTAL GATE CHARGE (nC)

tr
td(on)

10

160
80

Q3

100

t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP1N100E

1
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

1.0
VGS = 0 V
TJ = 25C

0.8

0.6

0.4

0.2

0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4682

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP1N100E
SAFE OPERATING AREA
50
VGS = 20 V
SINGLE PULSE
TC = 25C
1.0

10 s
100 s
1 ms
10 ms

0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 1 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

40

30

20

10

0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)
0.05
0.02
t1

0.01
SINGLE PULSE
0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4683

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP2N40E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


2.0 AMPERES
400 VOLTS
RDS(on) = 3.5 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.5
6.0

Adc

Total Power Dissipation


Derate above 25C

PD

40
0.32

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 )

EAS

45

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

3.13
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4684

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

451

Vdc
mV/C

10
100

100

nAdc

2.0

3.2
7.0

4.0

Vdc
mV/C

3.1

3.5

Ohms

7.3

8.4
7.4

gFS

0.5

1.0

mhos

Ciss

229

320

pF

Coss

34

40

Crss

7.3

10

td(on)

8.0

16

tr

8.4

14

td(off)

12

26

tf

11

20

QT

8.6

12

Q1

2.6

Q2

3.2

Q3

5.0

0.88
0.76

1.2

trr

156

ta

99

tb

57

QRR

0.89

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 200 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 320 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4685

MTP2N40E
TYPICAL ELECTRICAL CHARACTERISTICS
4

TJ = 25C
VGS = 10 V

3.2

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

8V
7V

2.4

6V

1.6

0.8

VDS 10 V

25C

100C

5V

TJ = 55C
0

0
4

12

16

20

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

8
VGS = 10 V
TJ = 100C

25C

55C

0
0

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 25C

4.5

4
VGS = 10 V
3.5
15 V
3

2.5
0

0.5

1.5

2.5

3.5

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

2.5
2

VGS = 0 V

VGS = 10 V
ID = 1 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

TJ = 125C
100

0.5

0
50

4686

25

25

50

75

100

125

150

10

100

200

300

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

400

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9. ) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
500

VDS = 0 V

VGS = 0 V

1000

TJ = 25C

VGS = 0 V
TJ = 25C

Ciss

Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

400

300
Ciss
200

Crss

Coss
10
Crss

Coss

100
0
10

100

Crss
5

0
VGS

10

15

20

25

VDS

1
10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Figure 7. b. High Voltage Capacitance


Variation

4687

400
QT

10

300
8

VGS

Q1

200

Q2
ID = 2 A
TJ = 25C

100
2
0
0

Q3
2

VDS
4
6
QT, TOTAL CHARGE (nC)

100
VDD = 200 V
ID = 2 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP2N40E

td(off)
tf
tr

10

td(on)

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
1.5

0.5

0
0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4688

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12. ). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N40E
SAFE OPERATING AREA
45
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

100 s
1 ms
10 ms
dc

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

40

ID = 2 A

35
30
25
20
15
10
5
0

0.1

10

100

25

1000

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
P(pk)
0.1

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E01

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4689

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP2N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


2.0 AMPERES
500 VOLTS
RDS(on) = 3.6 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.6
6.0

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.5 Apk, L = 10 mH, RG = 25 )

EAS

61

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4690

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

2.7

4.0

Ohm

5.9

9.6
8.4

gFS

1.0

1.6

mhos

Ciss

323

450

pF

Coss

45

60

Crss

9.0

20

td(on)

8.0

16

tr

6.0

12

td(off)

16

32

tf

10

20

QT

11

15

Q1

2.0

Q2

5.4

Q3

5.1

0.82
0.69

1.6

trr

334

ta

62

tb

272

QRR

0.985

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4691

MTP2N50E
TYPICAL ELECTRICAL CHARACTERISTICS
4
VGS = 10 V

8V

7V

VDS 10 V

3.5

6V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C
3

5V
1

TJ = 55C

25C
100C

3
2.5
2
1.5
1
0.5

10

12

14

16

18

3.5

TJ = 100C

5
4

25C

3
2

55C

1
0.4

0.8

1.6
2.4 2.8
1.2
2
ID, DRAIN CURRENT (AMPS)

3.2

3.6

5.5

6.5

3.6

4.2
TJ = 25C
3.8

3.4

VGS = 10 V

15 V
2.6

0.4

0.8

1.2 1.6
2
2.8
2.4
ID, DRAIN CURRENT (AMPS)

3.2

1000
VGS = 0 V

VGS = 10 V
ID = 2 A
I DSS , LEAKAGE (nA)

1.6

1.2

0.8

4692

4.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

0.4
50

Figure 2. Transfer Characteristics

Figure 3. OnResistance versus Drain Current


and Temperature

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

VGS = 10 V

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

8
7

20

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25

25

50

75

100

125

150

TJ = 125C
100
100C
25C
10

50

100

150

200

250

300

350

400

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

450 500

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

700

1000
VDS = 0 V

VGS = 0 V

TJ = 25C

600

VGS = 0 V
TJ = 25C

Ciss

500
400

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

Ciss

Ciss

300
Crss

200

100

Coss
10
Crss

Coss

100
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

1
10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4693

450

16

400

14

350

12

300

QT

10

250
VGS

Q1

ID = 2 A
150
TJ = 25C
100

6
4
2
0

200

Q2

50

Q3
0

3
4
5
6
7
QT, TOTAL CHARGE (nC)

VDS
8

0
10

100
VDD = 250 V
ID = 2 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

18

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP2N50E

td(off)
10

tf
td(on)
tr

1
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

2
VGS = 0 V
TJ = 25C

1.6

1.2

0.8

0.4

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4694

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N50E
SAFE OPERATING AREA
80
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

100 s

1 ms
10 ms
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

60

40

20

1000

100

ID = 2 A

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Fifgure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4695

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP2N60E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

TMOS POWER FET


2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHMS

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

Rating

VDSS

600

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GatetoSource Voltage Continuous


Single Pulse (tp 50 s)

VGS

20
40

Vdc

Drain Current Continuous


Single Pulse (tp 10 s)

ID
IDM

2.0
9.0

Adc

Total Power Dissipation


Derate above 25C

PD

50
0.4

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 50 Vdc, VGS = 10 Vdc, L = 95 mH, RG = 25 , Peak IL = 2.0 Adc)

EAS

190

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

2.5
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4696

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

480

Vdc
mV/C

0.25
1.0

100

nAdc

100

nAdc

2.0

3.1
8.5

4.0

Vdc
mV/C

3.3

3.8

Ohm

8.2
8.4

gFS

1.0

mhos

Ciss

435

pF

Crss
Coss

56

9.2

td(on)
tr

12

21

td(off)
tf

30

24

QT

13

22

Q1

2.0

Q2

6.0

Q3

5.0

((IS = 2.0 Adc,, VGS = 0 Vdc))


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

VSD

1.0

1.6

0.9

(IS = 2.0 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

trr

340

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125C)
GateBody Leakage Current Forward (VGSF = 20 Vdc, VDS = 0 Vdc)
GateBody Leakage Current Reverse (VGSR = 20 Vdc, VDS = 0 Vdc)

IDSS

IGSSF
IGSSR

mA

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS 50 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Vd VGS = 0 Vdc,
Vd
(VDS = 25 Vdc,
f=1
1.0
0 MHz)

Reverse Transfer Capacitance


Output Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time

((VDD = 300 Vdc,, ID = 2.0 Adc,,


VGS = 10 Vdc, Rg = 18 )

TurnOff Delay Time


Fall Time
Gate Charge

((VDS = 400 Vdc,, ID = 2.0 Adc,,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Reverse Recovery Time

Vdc
ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source pin 0.25 from package to source bond pad.)

Ls

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4697

MTP2N60E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V

VDS 10 V

7V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

3
6V
2
5.5 V
1

4
TJ = 100C

55C
25C

5V
0

12

16

20

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

12
100C

VGS = 10 V

8
TJ = 25C

4
55C

1.5

4.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

4.5
TJ = 25C

4.3
4.1
3.9
3.7

VGS = 10 V

3.5
3.3

15 V

3.1
2.9
2.7
2.5
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

0.5

1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage
1000

2.5
VGS = 10 V
ID = 1 A

VGS = 0 V
TJ = 125C

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

10

1.5

100
100C

10

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4698

150

1
0

100
300
500
200
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800
700

VDS = 0 V

VGS = 0 V

Ciss

Ciss

500

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

600

400

Ciss
Crss

300
200

100
Coss
10
Crss
1

Coss
Crss

100
0
10

1000

TJ = 25C

10

15

20

25

0.1

TJ = 25C
VGS = 0
10

100

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

1000

4699

12

TJ = 25C
ID = 2 A

VDS

400
QT

9
6

VDS = 100 V
VDS = 250 V
VDS = 400 V

Q1

300
200

Q2
3

00

100

VGS
Q3
4

12

16

20

1000

TJ = 25C
ID = 2 A
VDS = 300 V
VGS = 10 V

100

td(off)

t, TIME (ns)

500

15

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTP2N60E
tf
tr

td(on)
10

1
1

10
100
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

1000

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4700

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N60E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms

10 ms
0.1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

200

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

Peak IL = 2 A
VDD = 50 V

150

100

50

0
25
100

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

1000

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4701

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP2P50E
Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


2.0 AMPERES
500 VOLTS
RDS(on) = 6.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

2.0
1.6
6.0

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 )

EAS

80

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4702

Motorola TMOS Power MOSFET Transistor Device Data

MTP2P50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

564

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
4.0

4.0

Vdc
mV/C

4.5

6.0

Ohm

9.5

14.4
12.6

gFS

1.5

2.9

mhos

Ciss

845

1183

pF

Coss

100

140

Crss

26

52

td(on)

12

24

tr

14

28

td(off)

21

42

tf

19

38

QT

19

27

Q1

3.7

Q2

7.9

Q3

9.9

2.3
1.85

3.5

trr

223

ta

161

tb

62

QRR

1.92

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 250 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 2.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 2.0 Adc, VGS = 0 Vdc)


(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4703

MTP2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4

3.5

VDS 10 V

7V
3.5

8V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25C

3
6V
2.5
2
1.5
5V

100C
TJ = 55C

2.5

25C
2
1.5
1
0.5

0.5
4V
0

12

20

16

24

4.5

5.5

6
25C
4
55C
2

0.5

2
2.5
1.5
3
ID, DRAIN CURRENT (AMPS)

3.5

6.5

6
TJ = 25C

5.75
5.5
5.25
5

VGS = 10 V

4.75
15 V
4.5
4.25
4

Figure 3. OnResistance versus Drain Current


and Temperature

0.5

1.5
2.5
2
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000
VGS = 0 V

VGS = 10 V
ID = 1 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on), DRAIN-TO-SOURCE RESISTANCE


(NORMALIZED)

Figure 2. Transfer Characteristics

1.5

4704

3.5

Figure 1. OnRegion Characteristics

TJ = 100C

0.5
50

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

28

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

25

25

50

75

100

125

150

100
100C

10
25C

50

100

150

200

250

300

350

400

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

450

500

Motorola TMOS Power MOSFET Transistor Device Data

MTP2P50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1600

C, CAPACITANCE (pF)

1400

VDS = 0 V

VGS = 0 V

1000

TJ = 25C

Ciss
C, CAPACITANCE (pF)

1800

1200
1000

Ciss

800
600

Crss

400
200
0
10

Ciss

100
Coss
10

Crss

Coss

Crss
5

VGS = 0 V
TJ = 25C

10

15

20

25

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

1
10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4705

300
QT

10

250
VGS

200
Q1

Q2

150

ID = 2 A
TJ = 25C

100

50
Q3

VDS
6

10

12

14

16

18

0
20

1000
VDD = 250 V
ID = 2 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

MTP2P50E

100
td(off)

tf

tr

td(on)

10
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

2
VGS = 0 V
TJ = 25C

1.6

1.2

0.8

0.4

0
0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4706

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP2P50E
SAFE OPERATING AREA
80
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10
10 s

100 s
1 ms
dc

10 ms

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

60

40

20

1000

100

ID = 2 A

25

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
P(pk)

0.05

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

0.02
0.01
t1

SINGLE PULSE

0.01
1.0E05

1.0E04

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4707

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP3N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This advanced high voltage TMOS EFET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

TMOS POWER FET


3.0 AMPERES
500 VOLTS
RDS(on) = 3.0 OHMS

Avalanche Energy Capability Specified at Elevated


Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive (tp 50 s)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

3.0
10

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

50
0.4

Watts
W/C

TJ, Tstg

65 to 150

WDSR (1)

mJ

WDSR (2)

210
33
5.0

RJC
RJA

2.5
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) VDD = 50 V, ID = 3.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4708

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

500

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

2.4

3.0

10
8.0

gFS

1.0

mhos

Ciss

435

pF

Coss

56

Crss

9.2

td(on)

14

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
(TJ = 125C)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 A)
(ID = 1.5 A, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

Ohm
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 V, ID 3.0 A,


RG = 18
, RL = 83 ,

VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 400 V,
V ID = 3.0
3 0 A,
A
VGS = 10 V)

GateDrain Charge

ns

tr

14

td(off)

30

tf

20

Qg

15

21

Qgs

2.5

Qgd

10

VSD

1.5

Vdc

ton

**

ns

trr

200

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage

(IS = 3.0 A)

Forward TurnOn Time


Reverse Recovery Time

(IS = 3.0
3 0 A,
A di/dt = 100 A/s)

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Indicates Pulse Test: Pulse Width = 300 s Max, Duty Cycle 2.0%.
** Limited by circuit inductance.

Motorola TMOS Power MOSFET Transistor Device Data

4709

MTP3N50E

6
TJ = 25C
I D, DRAIN CURRENT (AMPS)

VGS = 10 V
7V

4
6V

3
2
1

5V
4V

0
0

8
12
16
6
10
14
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8

50

I D, DRAIN CURRENT (AMPS)

VDS 10 V
4

2
100C
25C
TJ = 55C
0

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

6
TJ = 100C
4

25C
2
55C
0
3

VGS = 0
ID = 250 A

1.1

0.9

0.8

50

50

100

150

2.5
VGS = 10 V
ID = 1.5 A

1.5

0.5
50

25

25

50

75

100

125

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance versus Temperature

4710

150

Figure 4. Breakdown Voltage Variation


With Temperature

VGS = 10 V

125

TJ, JUNCTION TEMPERATURE (C)

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

VDS = VGS
ID = 0.25 mA

1.1

150

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N50E
SAFE OPERATING AREA INFORMATION
16

1 s

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

10

100 s

1 ms

0.1

0.01

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

12

8
TJ 150C
4

0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

600

500
100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

Figure 8. Maximum Rated Switching


Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA


1000

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

t, TIME (ns)

100

td(on)

tr

1
1

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

r(t), EFFECTIVE TRANSIENT THERMAL


RESISTANCE (NORMALIZED)

td(off)

tf

10

SWITCHING SAFE OPERATING AREA

1
0.7
0.5

VDD = 250 V
ID = 3 A
VGS = 10 V
TJ = 25C

1000

10
100
RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation


versus Gate Resistance

D = 0.5

0.3

0.2

0.2
0.1
0.1
0.07
0.05
0.03
0.02

P(pk)

0.05
0.02

t1

0.01
SINGLE PULSE

0.01
0.01

0.02 0.03 0.05

t2
DUTY CYCLE, D = t1/t2
0.1

0.2 0.3

0.5

10

20

30

RJC(t) = r(t) RJC


RJC = 2.5C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200 300

500

1000

t, TIME (ms)

Figure 10. Thermal Response


Motorola TMOS Power MOSFET Transistor Device Data

4711

MTP3N50E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of
Figure 12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VR for a given
commutation speed. It is applicable when waveforms similar
to those of Figure 11 are present. Full or half-bridge PWM DC
motor controllers are common applications requiring CSOA
data.
The time interval tfrr is the speed of the commutation cycle.
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit
impedances. Maximum device stress occurs during trr as the
diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances, Li in Motorolas test circuit are assumed
to be practical minimums.

15 V
VGS
0
IFM

dls/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM
VDS(pk)
VR

VDS

dVDS/dt
VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms


RGS

DUT

VR

4
I D, DRAIN CURRENT (AMPS)

IFM

IS

Li
VDS

+
3

20 V

VGS
2

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

di/dt 50 A/s
1

Figure 13. Commutating Safe Operating Area


Test Circuit
500
100
200
300
400
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

600
V(BR)DSS
Vds(t)

Figure 12. Commutating Safe Operating Area (CSOA)


IO
L
VDS
ID

ID(t)

C
4700 F
250 V
VDD

t
RGS
50

Figure 14. Unclamped Inductive Switching


Test Circuit
4712

VDD

WDSR

t, (TIME)

tP

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 15. Unclamped Inductive Switching


Waveforms
Motorola TMOS Power MOSFET Transistor Device Data

1000
TJ = 25C
VGS = 0

C, CAPACITANCE (pF)

800

600
Ciss
400
Crss
200
Coss

VDS = 0
0

5
5
15
0
10
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
10

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP3N50E
16
VDS = 100 V
250 V

TJ = 25C
ID = 3 A

12

400 V
8

Figure 16. Capacitance Variation

10
15
QG, TOTAL GATE CHARGE (nC)

25

Figure 17. Gate Charge versus


GateToSource Voltage

+18 V

VDD

1 mA
47 k
Vin

20

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

4713

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP3N60E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


3.0 AMPERES
600 VOLTS
RDS(on) = 2.2 OHMS

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Capability Specified at Elevated


Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO-220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

600

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

3.0
14

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

WDSR(1)

mJ

WDSR(2)

290
46
7.5

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) VDD = 50 V, ID = 3.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4714

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

600

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 Adc)
Zero Gate Voltage Drain Current
(VDS = 600 V, VGS = 0)
(VDS = 480 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

2.1

2.2

9.0
7.5

gFS

1.5

mhos

Ciss

770

pF

Coss

105

Crss

19

td(on)

23

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
(TJ = 125C)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.5 A)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 A)
(ID = 1.5 A, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 A)

Vdc

Ohms
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 300 V, ID 3.0 A,


RL = 100 ,
RG = 12
,
VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 420 V,
V ID = 3.0
3 0 A,
A
VGS = 10 V)

GateDrain Charge

ns

tr

34

td(off)

58

tf

35

Qg

28

31

Qgs

5.0

Qgd

17

VSD

1.4

Vdc

ton

**

ns

trr

400

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Forward TurnOn Time

(IS = 3.0 A, di/dt = 100 A/s)

Reverse Recovery Time


INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Pulse Test: Pulse Width = 300 s, Duty Cycle 2.0%.


** Limited by circuit inductance.

Motorola TMOS Power MOSFET Transistor Device Data

4715

MTP3N60E

I D, DRAIN CURRENT (AMPS)

VGS = 10 V

7V

4
6V
2
5V
0
0

8
12
16
6
10
14
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

18

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8
0.7
50

I D, DRAIN CURRENT (AMPS)

10
VDS 10 V

4
100C
2

TJ = 25C

55C

2
4
6
3
5
7
VGS, GATETOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE ONRESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

TJ = 25C
2
55C

0
4

1.1

VGS = 0
ID = 250 A

0.9

0.8

50

25

25

50

75

100

125

150

10

3
VGS = 10 V
ID = 2 A
2

0
50

25

25

50

75

100

125

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

4716

150

Figure 4. Breakdown Voltage Variation


With Temperature

125

TJ, JUNCTION TEMPERATURE (C)

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

VGS = 10 V

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

VDS = VGS
ID = 0.25 mA

1.1

150

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N60E
SAFE OPERATING AREA INFORMATION
16

VGS = 20 V
SINGLE PULSE
TC = 25C

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

100

10 s

10

100 s
10 ms

1 ms

dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

8
TJ 150C
4

100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

1000

600
200
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

800

Figure 8. Maximum Rated Switching


Safe Operating Area
The power averaged over a complete switching cycle must
be less than:

FORWARD BIASED SAFE OPERATING AREA


The FBSOA curves define the maximum draintosource
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

TJ(max) TC
RJC
10000
VDD = 300 V
ID = 3 A
VGS(on) = 10 V
TJ = 25C

t, TIME (ns)

1000

td(off)

tf

td(on)

100

SWITCHING SAFE OPERATING AREA

tr

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

10
1

1000

10
100
RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
0.5
0.3

D = 0.5
0.2

0.2
0.1
0.1
0.05

P(pk)

0.05
0.02

t1

0.03

t2
DUTY CYCLE, D = t1/t2

0.01

0.02
SINGLE PULSE
0.01
0.01

0.02

0.05

0.1

0.2

0.5

10

20

RJC(t) = r(t) RJC


RJC = 1.67C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1k

t, TIME (ms)

Figure 10. Thermal Response


Motorola TMOS Power MOSFET Transistor Device Data

4717

MTP3N60E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VR for a given
commutation speed. It is applicable when waveforms similar
to those of Figure 11 are present. Full or half-bridge PWM DC
motor controllers are common applications requiring CSOA
data.
The time interval tfrr is the speed of the commutation cycle.
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit
impedances. Maximum device stress occurs during trr as the
diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances, Li in Motorolas test circuit are assumed
to be practical minimums.

15 V
VGS
0
IFM

dlS/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms


RGS

DUT

VR

I D, DRAIN CURRENT (AMPS)

IFM

IS

Li
VDS

+
3

20 V

VGS
2

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

di/dt 60 A/s
1

Figure 13. Commutating Safe Operating Area


Test Circuit
0

200
400
600
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

800
V(BR)DSS
Vds(t)

Figure 12. Commutating Safe Operating Area (CSOA)


IO
L
VDS
ID

ID(t)

C
4700 F
250 V
VDD

t
RGS
50

Figure 14. Unclamped Inductive Switching


Test Circuit
4718

VDD

WDSR

t, (TIME)

tP

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 15. Unclamped Inductive Switching


Waveforms
Motorola TMOS Power MOSFET Transistor Device Data

MTP3N60E
TJ = 25C

1400

VGS = 0 V

1200
C, CAPACITANCE (pF)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

1600

1000
Ciss

Crss

800
600
400
200
0
10

VDS = 0 V

Coss
5

10

20

15

25

16
VDS = 100 V

TJ = 25C
ID = 3 A
12

250 V
420 V

15
25
10
20
30
Qg, TOTAL GATE CHARGE (nC)

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 16. Capacitance Variation

40

Figure 17. Gate Charge versus


GateToSource Voltage

+18 V

VDD

1 mA
Vin

35

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

4719

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP3N100E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


3.0 AMPERES
1000 VOLTS
RDS(on) = 4.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

1000

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1000

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

3.0
2.4
9.0

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 150 Vdc, VGS = 10 Vdc, IL = 7.0 Apk, L = 10 mH, RG = 25 )

EAS

245

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.00
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4720

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1.23

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
6.0

4.0

Vdc
mV/C

2.96

4.0

Ohm

4.97

12
10

gFS

2.0

3.56

mhos

Ciss

1316

1800

pF

Coss

117

260

Crss

26

75

td(on)

13

25

tr

19

40

td(off)

42

90

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)

tf

33

55

QT

32.5

45

Q1

6.0

Q2

14.6

Q3

13.5

0.794
0.63

1.1

trr

615

ta

104

tb

511

QRR

2.92

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 3.0 Adc, VGS = 0 Vdc)


(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4721

MTP3N100E
TYPICAL ELECTRICAL CHARACTERISTICS
6

6
5

VGS = 10 V

6V

VDS 10 V

5V

3
2

100C

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

4
25C

3
2

TJ = 55C

1
4V
0

6
8
10
12
14
16
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

20

2.4

6
TJ = 100C

4
25C
3

2
55C
1
1.0

1.5

2.0

2.5 3.0
3.5 4.0
4.5
ID, DRAIN CURRENT (AMPS)

5.0

5.5

6.0

4.8

5.2

5.6

6.0

5.5

6.0

TJ = 25C
3.6

VGS = 10 V

3.4

3.2

15 V

3.0

2.8
1.0

1.5

2.0

2.5 3.0 3.5 4.0 4.5


ID, DRAIN CURRENT (AMPS)

5.0

Figure 4. OnResistance versus Drain Current


and Gate Voltage

TJ = 125C

10000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

4.4

VGS = 0 V

VGS = 10 V
ID = 1.5 A

100C

1000

1.6

1.2

100
25C
10

0.8

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4722

4.0

100000

2.4

0.4
50

3.6

3.8

Figure 3. OnResistance versus Drain Current


and Temperature

2.0

3.2

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

VGS = 10 V

2.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

150

100

200 300 400 500 600 700 800 900 1000


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800

10000

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

Ciss
1000
C, CAPACITANCE (pF)

2000
C, CAPACITANCE (pF)

TJ = 25C

VGS = 0 V

2400

Ciss

1600
Crss
1200
800

Coss
400

100

Coss
Crss

10

Crss

0
10

1
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

25

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

4723

400

14

350
QT

12

300
250

10
8
Q1

Q2

150
ID = 3 A
TJ = 25C

4
2
0

200

VGS

50

Q3
0

100

VDS
8

24
12
16
20
QG, TOTAL GATE CHARGE (nC)

28

0
30

1000
VDD = 500 V
ID = 3 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP3N100E

100

10

td(off)
tf
tr
td(on)
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


3.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

2.5
2.0
1.5
1.0
0.5
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78 0.80

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4724

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N100E
SAFE OPERATING AREA
250

VGS = 20 V
SINGLE PULSE
TC = 25C

VAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
10 s

1.0

100 s
1 ms
10 ms

0.1

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

dc

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 3 A
200

150

100

50

0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05

t1

0.02

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4725

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's Data Sheet

MTP3N120E

TMOS E-FET.
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


3.0 AMPERES
1200 VOLTS
RDS(on) = 5.0 OHM

This advanced highvoltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls, and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Capability Specified at Elevated


Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to
Discrete Fast Recovery Diode

* See App. Note AN1327 Very Wide Input Voltage Range;


Offline Flyback Switching Power Supply

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

1200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1200

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 50 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

3.0
2.2
11

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 )

t150C)

EAS

Apk

mJ
101

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

RJC
RJA

1.0
62.5

C/W

TL

260

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4726

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N120E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1200

1.28

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

4.0

5.0

Ohm

18.0
15.8

gFS

2.5

3.1

mhos

Ciss

2130

2980

pF

Coss

1710

2390

Crss

932

1860

td(on)

13.6

30

tr

12.6

30

td(off)

35.8

70

tf

20.7

40

QT

31

40

Q1

8.0

Q2

11

Q3

14

0.80
0.65

1.0

trr

394

ta

118

tb

276

QRR

2.11

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1200 Vdc, VGS = 0 Vdc)
(VDS = 1200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 600 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 600 Vdc, ID = 3.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 3.0 Adc, VGS = 0 Vdc)


(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4727

MTP3N120E
TYPICAL ELECTRICAL CHARACTERISTICS
6

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VDS 10 V

VGS = 10 V

TJ = 25C

6V

4
3
2

5V

5
4

100C

3
2

25C

1
TJ = 55C

4V
0

12

18

24

30

3.0

3.4

3.8

4.2

5.0

5.4

5.8

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

25C

55C

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

6.2

5.4
TJ = 25C
5.0
VGS = 10 V
4.6
15 V
4.2

3.8

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

2.0

10,000
VGS = 0 V

VGS = 10 V
ID = 1.5 A

TJ = 125C

1,000
1.5

1.0

0.5

0
50

4728

4.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25

25

50

75

100

125

150

100C
100

25C
10

200

400

600

800

1000

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

1200

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N120E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800

10,000
VDS = 0 V

VGS = 0 V
TJ = 25C

Ciss

Ciss

2000
Crss

1600

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

2400

TJ = 25C

VGS = 0 V

Ciss

1200
800
Coss

1,000

Coss

100

Crss

400
Crss
0

10

0
VGS

10

15

20

VDS

25

10

10

100

1000

DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

Figure 7b. High Voltage Capacitance


Variation

4729

MTP3N120E
350

12

300
QT

10

250
200

8
Q2

Q1

VGS
150
ID = 3 A
TJ = 25C

4
2
0

50

VDS

Q3
8

12

16

100

24

20

28

0
32

1000

t, TIME (ns)

14

VGS, GATETOSOURCE VOLTAGE (VOLTS)

400

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

16

VDD = 600 V
ID = 3 A
VGS = 10 V
TJ = 25C

100

td(off)
tf
td(on)
tr

10

Qg, TOTAL GATE CHARGE (nC)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

3.0
VGS = 0 V
TJ = 25C

2.4

1.8

1.2

0.6

0
0.55

0.59

0.63

0.67

0.71

0.75

0.79

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4730

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP3N120E
SAFE OPERATING AREA
120
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1.0
1 ms
0.1

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0

10

100

1,000

ID = 3 A
100
80
60
40
20
0

10,000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01
SINGLE PULSE
0.01
1.0E05
1.0E04

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E01

1.0E02
t, TIME (s)

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4731

MTP3N120E

D1 D4
1N4007s

L1

H1
90VAC
600VAC

C1
0.1
1 kV

C4
0.1
1 kV

L1

+Vin

H2
C3
0.0047
3 kV

C2
0.0047
3 kV

EARTH
GND

C6
100 mF
450 V

C5
100 mF
450 V

R4

470 k
1/2 W

R3

470 k
1/2 W

R2

470 k
1/2 W

R1

470 k
1/2 W
INPUT GND

Figure 15. The AC Input/Filter Circuit Section

T1

C11
D8
100 mF
MBR370 10 V

+Vin
R9
R8

100 mF
20 V

D9
MUR430

Vaux

82 k, 1/2 W
R7

R6

R5

R16
100 k
1/2 W

10 mF
25 V
+

D10

+
C13

C9

LL

MUR1100

4
C7
220 pF

1
U2
1/2
MOC8102

R12 10 W
R15
680 W
C8
1000 pF

+5 V

C14
U2
MOC8102

D6

D7

U3
TL431

Q1
R13
1k

R20
120 W
C15
1.5 nF

R19
32.4 k

1.3 mF 7.5 k

C17
2.2 nF

MTP3N120E

UC3845BN

D5
3.3 V

C12

Vaux

7
R10
27 k

MUR130

C10

R11
1.8 k

1 nF
3 kV

+12 V

C16 R17
R21
2.49 k
GND

R14
1.2 W
1/2 W

INPUT GND

Figure 16. The DC/DC Converter Circuit Section

4732

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP4N40E

TMOS E-FET.
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET


4.0 AMPERES
400 VOLTS
RDS(on) = 1.8 OHM

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

400

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

4.0
2.9
12

Adc

Total Power Dissipation


Derate above 25C

PD

74
0.6

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 8.0 Apk, L = TBD mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.67
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
TBD

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4733

MTP4N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

Vdc
mV/C

10
100

100

nAdc

2.0

3.0

4.0

Vdc
mV/C

1.8

Ohms

12
10

gFS

TBD

TBD

mhos

Ciss

TBD

TBD

pF

Coss

TBD

TBD

Crss

TBD

TBD

td(on)

TBD

TBD

tr

TBD

TBD

td(off)

TBD

TBD

tf

TBD

TBD

QT

TBD

80

Q1

TBD

Q2

TBD

Q3

TBD

TBD
TBD

TBD

trr

TBD

ta

TBD

tb

TBD

QRR

TBD

TBD
TBD

TBD

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 4.0 Adc)
(ID = 2.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 200 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 320 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 4.0 Adc, VGS = 0 Vdc)


(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4734

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP4N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


4.0 AMPERES
500 VOLTS
RDS(on) = 1.5 OHMS

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

4.0
10

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

WDSR (1)

mJ

WDSR (2)

280
44
7.4

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) VDD = 50 V, ID = 4.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4735

MTP4N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

500

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 Adc)
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

1.3

1.5

7.5
6.0

gFS

1.5

mhos

Ciss

775

pF

Coss

84

Crss

19

td(on)

24

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
(TJ = 125C)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.0 A)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 4.0 Adc)
(ID = 2.0 A, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 A)

Vdc

Ohm
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 V, ID 4.0 A,


RG = 12
, RL = 62 ,

VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 400 V,
V ID = 4.0
4 0 A,
A
VGS = 10 V)

GateDrain Charge

ns

tr

34

td(off)

60

tf

36

Qg

27

32

Qgs

3.5

Qgd

14

VSD

1.4

Vdc

ton

**

ns

trr

760

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Forward TurnOn Time

(IS = 4.0 A, di/dt = 100 A/s)

Reverse Recovery Time


INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Indicates Pulse Test: Pulse Width = 300 s Max, Duty Cycle 2.0%.
** Limited by circuit inductance.

4736

Motorola TMOS Power MOSFET Transistor Device Data

MTP4N50E

I D, DRAIN CURRENT (AMPS)

TJ = 25C

VGS = 10 V

8V

7V

6V

5V
4V

4
8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8

50

Figure 1. OnRegion Characteristics

VBR(DSS), DRAINTOSOURCE BREAKDOWN


VOLTAGE (NORMALIZED)

I D, DRAIN CURRENT (AMPS)

VDS 10 V
6

2
25C
55C
0

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

1.1

2
1.6
25C
1.2
0.8
55C

0
4

VGS = 0
ID = 0.25 mA

0.9

0.8
50

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 100C

150

50

100

150

200

Figure 4. Breakdown Voltage Variation


With Temperature

VGS = 10 V

125

TJ, JUNCTION TEMPERATURE (C)

2.8

0.4

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

2.4

25

Figure 2. GateToSource Threshold Voltage


Variation With Temperature

TJ = 100C

VDS = VGS
ID = 0.25 mA

1.1

10

2.5

VGS = 10 V
ID = 2 A

1.5

0.5

0
50

50

100

150

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

200

4737

MTP4N50E
SAFE OPERATING AREA INFORMATION
10 s

12

0.1 ms

VGS = 20 V
SINGLE PULSE
TC = 25C

1 ms

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

14
I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

10

10
8
6
TJ 150C

4
2

dc

0
1

10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

100
200
300
400
500
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

600

Figure 8. Maximum Rated Switching


Safe Operating Area

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

The power averaged over a complete switching cycle must


be less than:
TJ(max) TC
RJC
10000
VDD = 250 V
ID = 4 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf
tr

t, TIME (ns)

FORWARD BIASED SAFE OPERATING AREA

td(on)
100

SWITCHING SAFE OPERATING AREA


The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

10
1

1000

10
100
RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
0.5
0.3

D = 0.5
0.2

0.2
0.1
0.1

P(pk)

0.05
0.05

0.02
t1

0.03
0.02

t2
DUTY CYCLE, D = t1/t2

0.01

SINGLE PULSE
0.01
0.01
0.02
0.05

0.1

0.2

0.5

2
5
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 1.67C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1000

Figure 10. Thermal Response

4738

Motorola TMOS Power MOSFET Transistor Device Data

MTP4N50E
2000
VGS, GATE SOURCE VOLTAGE (VOLTS)

16
TJ = 25C
VGS = 0

C, CAPACITANCE (pF)

1500

1000
Crss

Ciss

500
VDS = 0
0

Coss

TJ = 25C
ID = 4 A

VDS = 100 V

12

250 V
400 V

10

5
5
10
20
25
0
15
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

10

20
30
QG, TOTAL GATE CHARGE (nC)

40

50

Figure 12. Gate Charge versus


GateToSource Voltage

Figure 11. Capacitance Variation

COMMUTATING SAFE OPERATING AREA (CSOA)


The Commutating Safe Operating Area (CSOA) of
Figure 14 defines the limits of safe operation for commutated
sourcedrain current versus reapplied drain voltage when
the sourcedrain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when waveforms similar to those of Figure 13 are present. Full or half
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward sourcedrain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.

Stray inductances in Motorolas test circuit are assumed to


be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s.
15 V
VGS
0
IFM

dls/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM
VDS(pk)
VR

VDS

dVDS/dt
VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 15. Commutating Waveforms


6

I D, DRAIN CURRENT (AMPS)

RGS

DUT

VR
+

di/dt 75 A/s

IS
+

VGS
0

IFM

100
200
300
400
500
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 13. Commutating Safe Operating Area (CSOA)

Motorola TMOS Power MOSFET Transistor Device Data

Li
VDS

20 V

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

Figure 14. Commutating Safe Operating Area


Test Circuit
4739

MTP4N50E
V(BR)DSS
Vds(t)
IO
L
VDS

ID(t)

C
4700 F
250 V

ID

VDD

VDD

WDSR

Figure 16. Unclamped Inductive Switching


Test Circuit

t, (TIME)

tP

RGS
50

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 17. Unclamped Inductive Switching


Waveforms

RESISTIVE SWITCHING
VDD
ton
td(on)

RL
Vout
Vin
PULSE GENERATOR
Rgen

50

tf
90%

OUTPUT, Vout
INVERTED
10%
90%

50
INPUT, Vin

50%

50%
10%
PULSE WIDTH

* Note: The Mirror is shorted to the Kelvin terminal for this test.

Figure 18. Switching Test Circuit

Figure 19. Switching Waveforms

+18 V

VDD

1 mA
47 k
Vin

td(off)

tr
90%

DUT

z = 12

toff

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 20. Gate Charge Test Circuit

4740

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP4N80E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


4.0 AMPERES
800 VOLTS
RDS(on) = 3.0 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

800

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

800

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

4.0
2.9
12

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25 )

EAS

320

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.0
63

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

4741

MTP4N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

1.02

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

1.95

3.0

Ohm

8.24

12
10

gFS

2.0

4.3

mhos

Ciss

1320

2030

pF

Coss

187

400

Crss

72

160

td(on)

13

30

tr

36

90

td(off)

40

80

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 4.0 Adc)
(ID = 2.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 4.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 4.0 Adc,
VGS = 10 Vdc)

tf

30

75

QT

36

80

Q1

7.0

Q2

16.5

Q3

12

0.812
0.7

1.5

trr

557

ta

100

tb

457

QRR

2.33

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 4.0 Adc, VGS = 0 Vdc)


(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4742

Motorola TMOS Power MOSFET Transistor Device Data

MTP4N80E
TYPICAL ELECTRICAL CHARACTERISTICS
8
TJ = 25C

VGS = 10 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

6V

5
5V

4
3
2
1
0

6
5

100C

4
25C
3
2
TJ = 55C

4V
0

VDS 10 V

6
8
10
12
14
16
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

20

2.4

2.8
3.2
3.6
4.0
4.4
4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

4.6
VGS = 10 V
3.8

TJ = 100C

3.0
25C

2.2

1.4
55C
0.6
1

3
5
4
6
ID, DRAIN CURRENT (AMPS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.6
TJ = 25C

2.5
2.4
2.3
2.2

VGS = 10 V

2.1
2.0

15 V

1.9
1.8
1

3
4
5
6
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.2
VGS = 10 V
ID = 2 A

VGS = 0 V
TJ = 125C
1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.8

5.6

1.4

1.0

100C

100

25C

10

0.6

0.2
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100

300
500
600
200
400
700
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800

Figure 6. DrainToSource Leakage


Current versus Voltage

4743

MTP4N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2800

10000

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

TJ = 25C

VGS = 0 V

2400

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

1000
2000
Ciss

1600
Crss

1200
800

Coss

400

100

Coss
Crss

10

Crss
0
10

1
0

5
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4744

25

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

10

500
QT

1000
VDD = 400 V
ID = 4 A
VGS = 10 V
TJ = 25C

VGS
Q1

Q2

300

200
ID = 4 A
TJ = 25C

VDS

24
12
18
QG, TOTAL GATE CHARGE (nC)

30

100
tf
td(off)

100

2
Q3

t, TIME (ns)

400

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP4N80E

0
36

10

tr

td(on)
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


4.0

I S , SOURCE CURRENT (AMPS)

3.6
3.2

VGS = 0 V
TJ = 25C

2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4745

MTP4N80E
SAFE OPERATING AREA
350
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1.0

1 ms
10 ms
0.1

0.01

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 4 A
300
250
200
150
100
50
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05

t1

0.02

t2
DUTY CYCLE, D = t1/t2

0.01
0.01
1.0E05

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE
1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4746

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP5N40E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


5.0 AMPERES
400 VOLTS
RDS(on) = 1.0 OHM

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

5.0
12

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

WDSR (1)

mJ

WDSR (2)

290
46
7.4

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) VDD = 50 V, ID = 5.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4747

MTP5N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

400

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 Adc)
Zero Gate Voltage Drain Current
(VDS = 400 V, VGS = 0)
(VDS = 320 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

0.8

1.0

6.2
5.0

gFS

2.0

mhos

Ciss

775

pF

Coss

96

Crss

22

td(on)

24

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
(TJ = 125C)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 5.0 A)
(ID = 2.5 A, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc)

Vdc

Ohm
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 V, ID 5.0 A,


RG = 12
, RL = 50 ,

VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 320 V,
V ID = 5.0
5 0 A,
A
VGS = 10 V)

GateDrain Charge

tr

34

td(off)

60

tf

36

Qg

27

32

Qgs

3.5

Qgd

14

VSD

1.4

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage
Forward TurnOn Time

(IS = 5.0 A, di/dt = 100 A/s)

Reverse Recovery Time

ton
trr

Vdc
ns

**

660

3.5
4.5

7.5

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Indicates Pulse Test: Pulse Width = 300 s Max, Duty Cycle 2.0%.
** Limited by circuit inductance.

4748

Motorola TMOS Power MOSFET Transistor Device Data

MTP5N40E

10
VGS = 10 V

I D, DRAIN CURRENT (AMPS)

TJ = 25C

7V

6V

5V

2
4V
0

4
8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8

50

Figure 1. OnRegion Characteristics

VBR(DSS), DRAINTOSOURCE BREAKDOWN


VOLTAGE (NORMALIZED)

I D, DRAIN CURRENT (AMPS)

VDS 10 V
8

4
TJ = 25C
2
125C
0

55C

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.1

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C
0.8
55C
VGS = 10 V
0
4

VGS = 0
ID = 0.25 mA

0.9

0.8
0

50

100

200

150

Figure 4. Breakdown Voltage Variation


With Temperature

1.2

150

TJ, JUNCTION TEMPERATURE (C)

TJ = 100C

125

50

10

0.4

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

1.6

25

Figure 2. GateThreshold Voltage Variation


With Temperature

10

VDS = VGS
ID = 0.25 mA

1.1

10

2.5

VGS = 10 V
ID = 2.5 A

1.5

0.5

0
50

50

100

150

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

200

4749

MTP5N40E
SAFE OPERATING AREA INFORMATION
14
VGS = 20 V
SINGLE PULSE
TC = 25C

12
10 s

10

0.1 ms
1 ms

1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1

10 ms

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

100

10
8
6
TJ 150C

4
2

dc

0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

500

Figure 8. Maximum Rated Switching


Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA

10000
VDD = 250 V
ID = 5 A
VGS = 10 V
TJ = 25C

1000

tf
tr
td(on)

100

10
1

SWITCHING SAFE OPERATING AREA

td(off)

t, TIME (ns)

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

1000

10
100
RG, GATE RESISTANCE (OHMS)

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5

0.5
0.3

0.2

0.2

0.1
0.1
0.05

P(pk)

0.05

RJC(t) = r(t) RJC


RJC = 1.67C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

0.02
t1

0.03
0.02
0.01
0.01

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.02

0.05

0.1

0.2

0.5

2
5
t, TIME (ms)

10

20

50

100

200

500

1000

Figure 10. Thermal Response


4750

Motorola TMOS Power MOSFET Transistor Device Data

MTP5N40E
2000
VGS, GATE SOURCE VOLTAGE (VOLTS)

16
TJ = 25C
VGS = 0

C, CAPACITANCE (pF)

1500

1000

Crss

Ciss

500
VDS = 0 V
0

Coss

TJ = 25C
ID = 5 A

VDS = 100 V

12

200 V
320 V

10

5
5
10
20
25
0
15
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

10

20
30
Qg, TOTAL GATE CHARGE (nC)

40

50

Figure 12. Gate Charge versus


GateToSource Voltage

Figure 11. Capacitance Variation

COMMUTATING SAFE OPERATING AREA (CSOA)


The Commutating Safe Operating Area (CSOA) of
Figure 14 defines the limits of safe operation for commutated
sourcedrain current versus reapplied drain voltage when
the sourcedrain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or half
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward sourcedrain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.

Stray inductances in Motorolas test circuit are assumed to


be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s.
15 V
VGS
0
IFM

dls/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM
VDS(pk)
VR

VDS

dVDS/dt
VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 15. Commutating Waveforms


6

I D, DRAIN CURRENT (AMPS)

RGS

DUT

VR
+

di/dt 90 A/s

IS
+

VGS
0

IFM

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 13. Commutating Safe Operating Area (CSOA)

Motorola TMOS Power MOSFET Transistor Device Data

Li
VDS

20 V

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

Figure 14. Commutating Safe Operating Area


Test Circuit
4751

MTP5N40E
V(BR)DSS
Vds(t)
IO
L
VDS

ID(t)

C
4700 F
250 V

ID

VDD

VDD

WDSR

Figure 16. Unclamped Inductive Switching


Test Circuit

t, (TIME)

tP

RGS
50

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 17. Unclamped Inductive Switching


Waveforms

RESISTIVE SWITCHING
VDD
ton
td(on)

RL
Vout
Vin
PULSE GENERATOR
Rgen

50

tf
90%

OUTPUT, Vout
INVERTED
10%
90%

50
INPUT, Vin

50%

50%
10%
PULSE WIDTH

* Note: The Mirror is shorted to the Kelvin terminal for this test.

Figure 18. Switching Test Circuit

Figure 19. Switching Waveforms

+18 V

VDD

1 mA
47 k
Vin

td(off)

tr
90%

DUT

z = 12

toff

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 20. Gate Charge Test Circuit

4752

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP5P06V

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


5 AMPERES
60 VOLTS
RDS(on) = 0.450 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

5
4
18

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

40
0.27

Watts
W/C

TJ, Tstg
EAS

55 to 175

125

mJ

RJC
RJA

3.75
62.5

C/W

TL

260

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 5 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4753

MTP5P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

61.2

10
100

100

2.0

2.8
4.7

4.0

mV/C

0.34

0.45

Ohm

2.7
2.6

1.5

3.6

Ciss

367

510

Coss

140

200

Crss

29

60

td(on)

11

20

tr

26

50

td(off)

17

30

tf

19

40

QT

12

20

Q1

3.0

Q2

5.0

Q3

5.0

1.72
1.34

3.5

trr

97

ta

73

tb

24

QRR

0.42

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 5 Adc)
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 15 Vdc, ID = 2.5 Adc)

Vdc

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 5 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 5 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 5 Adc, VGS = 0 Vdc)


(IS = 5 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4754

Motorola TMOS Power MOSFET Transistor Device Data

MTP5P06V
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

VGS = 10V
8

10

8V

9V

7V

TJ = 25C
6V

4
5V
2

6
5
4
3
2

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.45
0.4

25C

0.35
0.3

0.4
TJ = 25C
VGS = 10 V

0.35

0.5

15 V

0.3

0.25

55C

0.25
0.2
1

4
5
6
7
ID, DRAIN CURRENT (AMPS)

10

0.2

Figure 3. OnResistance versus Drain Current


and Temperature

4
5
7
6
ID, DRAIN CURRENT (AMPS)

10

100

1.8
1.6

Figure 4. OnResistance versus Drain Current


and Gate Voltage

VGS = 0 V

VGS = 10 V
ID = 2.5 A

1.4
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.6
0.55

100C

25C

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 55C

4V
0

VDS 10 V

9
I D , DRAIN CURRENT (AMPS)

10

1.2
1
0.8
0.6

TJ = 125C

10

0.4
0.2
50

25

0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

175

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

50
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

4755

MTP5P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1000

VDS = 0 V

Ciss

900

TJ = 25C

C, CAPACITANCE (pF)

800
700
600

Crss

500
Ciss

400
300

Coss

200
100
0

Crss

VGS = 0 V
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4756

Motorola TMOS Power MOSFET Transistor Device Data

60
VGS
54

QT

48

8
7

Q2

Q1

42

36

30

24
18

3
2

Q3
VDS

1
0

TJ = 25C
ID = 5 A

12

10

12
6
0
14

100
TJ = 25C
ID = 5 A
VDD = 30 V
VGS = 10 V
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP5P06V

tr
td(off)
tf

10

td(on)

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


5
TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4757

MTP5P06V
SAFE OPERATING AREA
140

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10
100 s
1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 5 A
120
100
80
60
40
20
0

100

25

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4758

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP6N60E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET


6.0 AMPERES
600 VOLTS
RDS(on) = 1.2 OHMS

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

Rating

VDSS

600

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

6.0
4.6
18

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.0
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
405

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4759

MTP6N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.1

4.0

Vdc
mV/C

0.94

1.2

Ohms

6.0

8.6
7.6

gFS

2.0

5.5

mhos

Ciss

1498

2100

pF

Coss

158

220

Crss

29

60

td(on)

14

30

tr

19

40

td(off)

40

80

tf

26

55

QT

35.5

50

Q1

8.1

Q2

14.1

Q3

15.8

0.83
0.72

1.2

trr

266

ta

166

tb

100

QRR

2.5

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDS = 300 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge

((VDS = 300 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4760

Motorola TMOS Power MOSFET Transistor Device Data

MTP6N60E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12
VGS = 10 V

VDS 10 V

6V

10

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

7V
8V

8
6
5V
4

10
8
6
4
100C

2
4V
0

TJ = 55C
0

18

4
8
12
16
6
10
14
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

2.0

2.5
VGS = 10 V
2.0
TJ = 100C
1.5
25C
1.0
55C
0.5

6
4
8
ID, DRAIN CURRENT (AMPS)

12

10

6.0

TJ = 25C
1.3
1.2
1.1

VGS = 10 V

1.0
15 V
0.9
0.8
0

2.5

4
6
8
ID, DRAIN CURRENT (AMPS)

10

12

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 3 A

VGS = 0 V

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.0
4.0
5.0
3.5
4.5
5.5
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.4

Figure 3. OnResistance versus Drain Current


and Temperature

1.5

0.5

0
50

2.5

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

25C

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100C
100

25C

10

1
0

200
400
100
300
500
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

4761

MTP6N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3200

VDS = 0 V

VGS = 0 V

TJ = 25C

10000

TJ = 25C
VGS = 0 V

Ciss

1600

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

2400

Ciss

Crss

800

Ciss

1000

Coss

100

Crss
10

Coss
0
10

Crss
5

0
VGS

10

15

20

25

10

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

4762

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

300
QT

10
8

VGS
Q1

Q2

100

ID = 6 A
TJ = 25C

2
Q3
0

200

VDS
12

24

18

30

0
36

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP6N60E
VDD = 300 V
ID = 6 A
VGS = 10 V
TJ = 25C

100
td(off)
tf
tr
td(on)

10

10

QT, TOTAL CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
VGS = 0 V
TJ = 25C

5
4
3
2
1
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4763

MTP6N60E

I D , DRAIN CURRENT (AMPS)

100

EAS, SINGLE PULSE DRAINNTOSOURCE


AVALANCHE ENERGY (mJ)

SAFE OPERATING AREA


VGS = 20 V
SINGLE PULSE
TC = 25C
10 s
10
100 s
1 ms
1.0

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10

dc

100

450
ID = 6 A

400
350
300
250
200
150
100
50
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4764

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP6P20E
Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


6.0 AMPERES
200 VOLTS
RDS(on) = 1.0 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

6.0
3.9
21

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 )

EAS

180

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.67
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4765

MTP6P20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

211

Vdc
mV/C

10
100

100

nAdc

2.0

3.1
4.0

4.0

Vdc
mV/C

0.81

1.0

Ohm

6.0

7.2
6.3

gFS

1.5

3.8

mhos

Ciss

540

750

pF

Coss

128

180

Crss

40

90

td(on)

12

25

tr

32

65

td(off)

24

50

tf

16

30

QT

22

30

Q1

4.0

Q2

11

Q3

9.0

2.8
2.6

4.0

trr

188

ta

152

tb

36

QRR

1.595

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 100 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 160 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4766

Motorola TMOS Power MOSFET Transistor Device Data

MTP6P20E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12

8V

9V
8

7V
4
6V

10

12

14

100C

6
4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

1.6

1.2
25C
0.8
55C
0.4

4
6
8
ID, DRAIN CURRENT (AMPS)

10

12

1.4
TJ = 25C

1.2

VGS = 10 V
1.0
15 V

0.8

12

10

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000
VGS = 10 V
ID = 3.0 A

VGS = 0 V

1.5
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

2.0

25C

16

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

10

5V
0

VDS 10 V

VGS = 10 V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

1.0

0.5

0
50

25

25

50

75

100

125

150

125C

100

100C
10

1
200

160

120

80

40

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4767

MTP6P20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss
C, CAPACITANCE (pF)

1600

1200

Crss

800

Ciss

400
0
10

Coss
Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4768

Motorola TMOS Power MOSFET Transistor Device Data

160
QT

10
VGS
8

120

Q2

Q1

80

6
4

ID = 6.0 A
TJ = 25C

2
Q3
0

40

VDS
10
15
Qg, TOTAL GATE CHARGE (nC)

0
20

1000
VDD = 100 V
ID = 6.0 A
VGS = 10 V
TJ = 25C

100
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP6P20E

tr
td(off)
tf

10

25

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

td(on)

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
VGS = 0 V
TJ = 25C

5
4
3
2
1
0
0.5

1.0

1.5

2.0

2.5

3.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4769

MTP6P20E
SAFE OPERATING AREA
180
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms

1.0

10 ms
dc

0.1

0.01

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10

1.0

0.1

100

ID = 6.0 A

144

108

72

36
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
0.1
0.1 0.05

P(pk)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E02

1.0E03

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t,TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4770

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP7N20E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET


7.0 AMPERES
200 VOLTS
RDS(on) = 0.70 OHMS

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

200

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

7.0
3.8
21

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

50
0.4

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

2.5
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
74

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4771

MTP7N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

689

Vdc
mV/C

10
100

100

nAdc

2.0

3.1
7.1

4.0

Vdc
mV/C

0.46

0.7

Ohm

3.4

5.9
5.1

gFS

1.5

mhos

Ciss
Coss

342

480

pF

92

130

Crss

27

55

td(on)
tr

8.8

17.6

29

58

td(off)
tf

22

44

20

40.8

QT

13.7

21

Q1

3.3

Q2

6.6

Q3

5.9

1.02
0.9

1.2

trr
ta

138

93

tb
QRR

45

0.74

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 7.0 Adc)
(VGS = 10 Vdc, ID = 3.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 14 Vdc, ID = 3.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f=1
1.0
0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time

((VDD = 100 Vdc,, ID = 7.0 Adc,,


VGS = 10 Vdc, Rg = 9.1 )

TurnOff Delay Time


Fall Time
Gate Charge
(See Figure 8)

((VDS = 160 Vdc,, ID = 7.0 Adc,,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 7.0 Adc, VGS = 0 Vdc)


(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure 14)

((IS = 7.0 Adc,, VGS = 0 Vdc,,


dIS/dt = 100 A/s)

Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad.)

Ls

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.


(2) Switching characteristics are independent of operating junction temperature.

4772

Motorola TMOS Power MOSFET Transistor Device Data

MTP7N20E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V

14

9V

12

ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

14

8V

10
8

7V

6
4

6V

5V

12
TJ = 100C
10

25C

8
6
4

4
6
8
5
7
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.2
VGS = 10 V
1.0
100C

0.6

TJ = 25C

0.4

55C

0.2
0

10

12

14

0.7
TJ = 25C
0.65
0.6
VGS = 10 V

0.55
0.5

15 V

0.45
0.4
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

4
6
8
10
ID, DRAIN CURRENT (AMPS)

12

14

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

100

VGS = 0 V

VGS = 10 V
ID = 3.5 A

TJ = 125C

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

10

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.8

55C

12

10

VDS 10 V

1.5

100C
10

25C

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

1
0

50
100
150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

Figure 6. DrainToSource Leakage


Current versus Voltage

4773

MTP7N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

900

C, CAPACITANCE (pF)

750

VGS = 0 V

TJ = 25C

Ciss

600
Crss
450

Ciss

300
Coss

150
VDS = 0 V
0
10

Crss

0
5
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4774

Motorola TMOS Power MOSFET Transistor Device Data

QT

10

150
VGS

120

Q2

Q1
6

90
60

4
TJ = 25C
ID = 7 A

2
Q3
0

30

VDS
4

10

14

12

1000

TJ = 25C
ID = 7 A
VDS = 100 V
VGS = 10 V

100
t, TIME (ns)

180

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTP7N20E

tr
td(off)
10

tf

td(on)

10
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


7
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

6
5
4
3
2
1
0
0.5

0.6

0.7

0.8

0.9

1.0

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4775

MTP7N20E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1 ms
10 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10

dc
100

80

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

ID = 7 A

70
60
50
40
30
20
10
0

1000

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1

0.05

P(pk)
0.02

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4776

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP8N50E

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO-220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

8.0
24

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

WDSR(1)

mJ

WDSR(2)

510
82
13

RJC
RJA

1.0
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
(1) VDD = 50 V, ID = 8.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4777

MTP8N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

500

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 Adc)
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

0.67

0.8

7.2
6.4

gFS

4.0

mhos

Ciss

1200

pF

Coss

176

Crss

72

td(on)

25

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
(TJ = 125C)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 4.0 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 4.0 Adc)

Vdc

Ohm
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 V, ID = 8.0 A,


RD = 30
, RG = 9.1
91
,
VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 400 V,
V ID = 8.0
8 0 A,
A
VGS = 10 V)

GateDrain Charge

ns

tr

36

td(off)

75

tf

30

Qg

46

63

Qgs

10

Qgd

24

VSD

2.0

Vdc

ton

**

ns

trr

700

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Forward TurnOn Time

(IS = 8.0 A, di/dt = 100 A/s)

Reverse Recovery Time


INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from screw on tab to center of die)
(Measured from the drain lead 0.23 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

* Indicates Pulse Test: Pulse Width = 300 s, Duty Cycle = 2.0%.


** Limited by circuit inductance.

4778

Motorola TMOS Power MOSFET Transistor Device Data

MTP8N50E

I D, DRAIN CURRENT (AMPS)

15

VGS = 10 V

12

7V

TJ = 25C
6V

6
5V

0
0

8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8
0.7
50

20

I D, DRAIN CURRENT (AMPS)

VDS 10 V
15

10

100C

TJ = 25C

55C

3
5
7
2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.5
TJ = 25C

55C

0
5

10

15

20

RDS(on) , DRAINTOSOURCE ONRESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

150

1.1

VGS = 0
ID = 250 A

0.9

0.8

50

25

25

50

75

100

125

150

Figure 4. Breakdown Voltage Variation


With Temperature

VGS = 10 V

0.5

125

TJ, JUNCTION TEMPERATURE (C)

2.5

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

VDS = VGS
ID = 0.25 mA

1.1

2.5

VGS = 10 V
ID = 4 A

1.5

0.5
0
50

25

25

50

75

100

125

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

4779

MTP8N50E
SAFE OPERATING AREA INFORMATION
36

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

100

100 s

10

1 ms
10 ms
1

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

30
24
18
TJ 150C

12
6
0

100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

500
100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

600

Figure 8. Maximum Rated Switching


Safe Operating Area

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

The power averaged over a complete switching cycle must


be less than:
TJ(max) TC
RJC
10000
VDD = 250 V
ID = 8 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf

t, TIME (ns)

FORWARD BIASED SAFE OPERATING AREA

tr
td(on)
100

SWITCHING SAFE OPERATING AREA

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.
1
0.7
0.5
0.3
0.2

10
1

10
100
RG, GATE RESISTANCE (OHMS)

1000

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

D = 0.5

0.2
0.1

0.1
0.07
0.05

P(pk)
0.05
0.02

t1

0.03
0.02
0.01
0.01

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE
0.02

0.05

0.1

0.2

0.5

2
5
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 1C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1k

Figure 10. Thermal Response


4780

Motorola TMOS Power MOSFET Transistor Device Data

MTP8N50E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of
Figure 12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VR for a given
commutation speed. It is applicable when waveforms similar
to those of Figure 11 are present. Full or half-bridge PWM DC
motor controllers are common applications requiring CSOA
data.
The time interval tfrr is the speed of the commutation cycle.
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit
impedances. Maximum device stress occurs during trr as the
diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances, Li in Motorolas test circuit are assumed
to be practical minimums.

15 V
VGS
0
IFM

dlS/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms


RGS

DUT

VR

I D, DRAIN CURRENT (AMPS)

IFM

IS

Li
VDS

+
4

20 V

VGS

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

di/dt 100 A/s

Figure 13. Commutating Safe Operating Area


Test Circuit
0

100
200
300
400
500
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

600
V(BR)DSS
Vds(t)

Figure 12. Commutating Safe Operating Area (CSOA)


IO
L
VDS
ID

ID(t)

C
4700 F
250 V
VDD

t
RGS
50

Figure 14. Unclamped Inductive Switching


Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data

VDD

WDSR

t, (TIME)

tP

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 15. Unclamped Inductive Switching


Waveforms
4781

MTP8N50E
TJ = 25C
VGS = 0

2500
C, CAPACITANCE (pF)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

3000

Crss

2000
1500

Ciss

1000
500
Coss

VDS = 0 V
0

10

10

20

15

25

16
VDS = 100 V

TJ = 25C
ID = 8 A
12

250 V
400 V

20
40
60
Qg, TOTAL GATE CHARGE (nC)

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 16. Capacitance Variation

Figure 17. Gate Charge versus


GateToSource Voltage

+18 V

VDD

1 mA
47 k
Vin

80

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

4782

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP9N25E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


9.0 AMPERES
250 VOLTS
RDS(on) = 0.45 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

250

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

250

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

9.0
5.7
32

Adc

Total Power Dissipation


Derate above 25C

PD

80
0.64

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.56
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
122

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4783

MTP9N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

328

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.37

0.45

Ohm

3.5

5.4
4.7

gFS

3.0

5.2

mhos

Ciss

783

1100

pF

Coss

144

200

Crss

32

65

td(on)

10

20

tr

36

70

td(off)

27

55

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 4.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 125 Vdc, ID = 9.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 200 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)

tf

26

50

QT

26

40

Q1

4.8

Q2

12.7

Q3

9.2

0.9
0.81

1.5

trr

191

ta

126

tb

65

QRR

1.387

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 9.0 Adc, VGS = 0 Vdc)


(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4784

Motorola TMOS Power MOSFET Transistor Device Data

MTP9N25E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

18

VGS = 10 V

TJ = 25C

9V

15

VDS 10 V

8V
7V

I D , DRAIN CURRENT (AMPS)

18

12
9
6V
6
3

100C
9
6

0
0

10

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

1.2
VGS = 10 V
1.0
0.8
TJ = 100C
0.6
25C
0.4
0.2

55C

0
0

6
9
12
ID, DRAIN CURRENT (AMPS)

15

18

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C

12

5V

0.6
TJ = 25C

0.5

VGS = 10 V
0.4
15 V

0.3
0

Figure 3. OnResistance versus Drain Current


and Temperature

6
9
12
ID, DRAIN CURRENT (AMPS)

15

18

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

2.5

VGS = 0 V

VGS = 10 V
ID = 4.5 A
2.0

TJ = 125C

100
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C

15

1.5

1.0

100C
10
25C
1

0.5

0
50

0.1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

50
150
100
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

4785

MTP9N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

VDS = 0 V

1600
C, CAPACITANCE (pF)

VGS = 0 V

TJ = 25C

Ciss

1200

Ciss
Crss

800

Coss

400
0

Crss
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4786

Motorola TMOS Power MOSFET Transistor Device Data

240

12

180

QT
VGS

8
Q1

120

Q2

ID = 9 A
TJ = 25C

60

Q3
0

VDS
0

12
18
QG, TOTAL GATE CHARGE (nC)

24

0
30

1000

t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP9N25E
VDD = 250 V
ID = 9 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
10

tf

td(on)

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

9.0
VGS = 0 V
TJ = 25C

7.5
6.0
4.5
3.0
1.5
0
0.5

0.55

0.6
0.7
0.8
0.65
0.75
0.85
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.9

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4787

MTP9N25E
SAFE OPERATING AREA
125

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10

100 s
1

1 ms
10 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

dc

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 9 A
100

75

50

25
0

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE
0.01
0.00001

t2
DUTY CYCLE, D = t1/t2

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0

10

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4788

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP10N10E

TMOS IV
Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate


This advanced E series of TMOS power MOSFETs is designed
to withstand high energy in the avalanche and commutation
modes. These new energy efficient devices also offer drainto
source diodes with fast recovery times. Designed for low voltage,
high speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits where diode speed and commutating safe
operating area are critical, and offer additional safety margin
against unexpected voltage transients.

Internal SourcetoDrain Diode Designed to Replace External


Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode Unclamped Inductive Switching (UIS)
Energy Capability Specified at 100C
Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits

TMOS POWER FETs


10 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage

VGS

20

Vdc

Drain Current Continuous


Drain Current Pulsed

ID
IDM

10
25

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

65 to 150

RJC
RJA

1.67
62.5

C/W

TL

275

Operating and Storage Temperature Range

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4789

MTP10N10E
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Max

Unit

V(BR)DSS

100

Vdc

10
80

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0)
(VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125C)

IDSS

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.5
4.0

0.25

2.7
2.4

4.0

60
100
40

Ciss

600

Coss

400

Crss

100

td(on)

50

tr

80

td(off)

100

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 1.0 mA)
TJ = 100C

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 V)


(ID = 10 Adc)
(ID = 5.0 Adc, TJ = 100C)

VDS(on)

gFS

Forward Transconductance (VDS = 15 V, ID = 5.0 A)

Vdc

Ohm
Vdc

mhos

DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Unclamped DraintoSource Avalanche Energy See Figures 14 and 15
(ID = 25 A, VDD = 25 V, TC = 25C, Single Pulse, Nonrepetitive)
(ID = 10 A, VDD = 25 V, TC = 25C, P.W. 200 s, Duty Cycle 1%)
(ID = 4.0 A, VDD = 25 V, TC = 100C, P.W. 200 s, Duty Cycle 1%)

WDSR

mJ

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
S Figure
See
Fi
16

pF

SWITCHING CHARACTERISTICS* (TJ = 100C)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 25 V, ID = 5.0 A,
RG = 50 )
See Figure 9

Fall Time
Total Gate Charge
GateSource Charge
GateDrain Charge

(VDS = 0.8 Rated VDSS,


ID = Rated ID, VGS = 10 V)
S Figures
See
Fi
17 and
d 18

tf

80

Qg

15 (Typ)

30

Qgs

8.0 (Typ)

Qgd

7.0 (Typ)

VSD

1.4 (Typ)

1.7

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage
Forward TurnOn Time

(IS = Rated
R t d ID
VGS = 0)

Reverse Recovery Time

ton
trr

Vdc

Limited by stray inductance


70 (Typ)

3.5 (Typ)
4.5 (Typ)

7.5 (Typ)

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

4790

Motorola TMOS Power MOSFET Transistor Device Data

MTP10N10E

I D, DRAIN CURRENT (AMPS)

20

VGS = 10 V

8V

TJ = 25C

7V

16

6V

12

5V

4
4V
0

8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8
0.7
50

20

I D, DRAIN CURRENT (AMPS)

TJ = 55C
VDS = 10 V
VDS = 15 V
12

100C

8
+25C

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.4
TJ = 100C
25C
55C
0.1

150

1.6

VGS = 0 V
ID = 0.25 mA

1.2

0.8

0.4

0
50

50

100

150

200

Figure 4. Breakdown Voltage Variation


With Temperature

VGS = 10 V

125

TJ, JUNCTION TEMPERATURE (C)

0.5

0.2

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

0.3

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

16

VDS = VGS
ID = 1 mA

1.1

10

1.6

VGS = 10 V
ID = 5 mA

1.2

0.8

0.4

0
50

50

100

150

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

200

4791

MTP10N10E
SAFE OPERATING AREA INFORMATION
40

10 s
100 s

10

1 ms
VGS = 20 V
SINGLE PULSE
TC = 25C

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.3

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

30

TJ 150C

30

20

10

0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20
40
60
80
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

Figure 8. Maximum Rated Switching


Safe Operating Area

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.
SWITCHING SAFE OPERATING AREA

r(t), TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

The power averaged over a complete switching cycle must


be less than:
TJ(max) TC
RJC
1K
td(off)

VDD = 25 V
ID = 5 A
VGS = 10 V
TJ = 25C

500
300
200
t, TIME (ns)

FORWARD BIASED SAFE OPERATING AREA

1
0.7
0.5

100

100
70
50
30
20

tf
tr

td(on)

10
7
5
3
2
1
2 3

10
20 30 50 100 200 300 500
RG, GATE RESISTANCE (OHMS)

1K

Figure 9. Resistive Switching Time


versus Gate Resistance

D = 0.5

0.3

0.2

0.2
0.1
0.1
0.07
0.05
0.03

P(pk)

0.05
0.01

t1

t2
DUTY CYCLE, D = t1/t2

0.02
SINGLE PULSE
0.01
0.01
0.02 0.03 0.05

0.1

0.2 0.3

0.5

2 3
5
t, TIME (ms)

10

20

30

RJC(t) = r(t) RJC


RJC = 1.67C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200 300

500

1000

Figure 10. Thermal Response


4792

Motorola TMOS Power MOSFET Transistor Device Data

MTP10N10E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or halfbridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorolas test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s.

15 V
VGS
0
IFM
IS
10%

trr
ton

IRM
0.25 IRM
VDS(pk)
VR

VDS

dVDS/dt
VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms


RGS

VR
+

IFM

IS
+

20

20 V

VGS

Li
VDS

25

15

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

dIs/dt 400 A/s


10

Figure 13. Commutating Safe Operating Area


Test Circuit

5
0

DUT

30
IS , SOURCE CURRENT (AMPS)

dls/dt

90%

100
20
40
60
80
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

120
V(BR)DSS
Vds(t)

Figure 12. Commutating Safe Operating Area (CSOA)


IO
L
VDS
ID

ID(t)

C
4700 F
250 V
VDD

t
RGS
50

Figure 14. Unclamped Inductive Switching


Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data

VDD

WDSR

t, (TIME)

tP

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 15. Unclamped Inductive Switching


Waveforms
4793

MTP10N10E
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1250
TJ = 25C

Ciss
C, CAPACITANCE (pF)

1000
Coss
750

500

Ciss

250

Coss
Crss

0
20

10

10

20

30

10

50 V
80 V

4
ID = RATED ID
2

8
12
QG, TOTAL GATE CHARGE (nC)

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 16. Capacitance Variation

16

20

Figure 17. Gate Charge versus


GateToSource Voltage

+18 V

VDD

1 mA
47 k
Vin

TJ = 25C

VDS = 30 V

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

4794

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
Logic Level TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP10N10EL
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET


10 AMPERES
100 VOLTS
RDS(on) = 0.22 OHMS

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

100

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Continuous @ TC = 100C
Single Pulse (tp 10 s)

ID
ID
IDM

10
6.0
35

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C
Total Power Dissipation @ TC = 25C (1)

PD

40
0.32
1.75

Watts
W/C
Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 10 Adc, L = 1.0 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Junction to Ambient
Junction to Ambient (1)

RJC
RJA
RJA

3.13
100
71.4

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
50

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4795

MTP10N10EL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

115

10
100

100

1.0

1.45
4.0

2.0

mV/C

0.17

0.22

Ohm

1.85

2.6
2.3

gFS

5.0

7.9

mhos

Ciss
Coss

741

1040

pF

175

250

Crss

18.9

40

td(on)
tr

11

20

74

150

td(off)
tf

17

30

38

80

QT

9.3

15

Q1

2.56

Q2

4.4

Q3

4.6

0.98
0.898

1.6

trr
ta

124.7

86

tb
QRR

38.7

0.539

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 5.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 5.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f=1
1.0
0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

( DD = 50 Vdc,, ID = 10 Adc,,
(V
VGS = 5.0 Vdc, Rg = 9.1 )

Fall Time
Gate Charge
(See Figure 8)

((VDS = 80 Vdc,, ID = 10 Adc,,


VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 10 Adc, VGS = 0 Vdc)


(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 10 Adc,, VGS = 0 Vdc,,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad.)

Ls

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.


(2) Switching characteristics are independent of operating junction temperature.

4796

Motorola TMOS Power MOSFET Transistor Device Data

MTP10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20

7V

VGS = 10 V

TJ = 25C

VDS 5 V

5V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

20

4.5 V
15
4V
10
3.5 V
5

3V

55C
15
25C

TJ = 100C

10

2V
0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.35
VGS = 5 V

100C
0.25
TJ = 25C
0.15
55C

0.05

10

15

20

0.25
TJ = 25C

VGS = 5 V

0.2

10 V
0.15

0.1
5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

10
15
ID, DRAIN CURRENT (AMPS)

20

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100
VGS = 5 V
ID = 5 A

VGS = 0 V

TJ = 125C

1.5
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2
3
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

10

100C

1
0

80
20
40
60
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage


Current versus Voltage

4797

MTP10N10EL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1800

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

1600 Ciss
1400
1200
1000
800

Crss

Ciss

600
400

Coss

200
0
10

Crss
5

5
0
10
15
20
25
VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4798

Motorola TMOS Power MOSFET Transistor Device Data

QT

75
VGS

60
45

Q2

Q1

VDS

Q3
0

30

TJ = 25C
ID = 10 A

15

1000

TJ = 25C
ID = 10 A
VDS = 100 V
VGS = 5 V

100
t, TIME (ns)

90

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTP10N10EL

tr
tf
td(off)
td(on)

10

0
10

10
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

10
VGS = 0 V
TJ = 25C

0
0.5

0.6

0.7

0.8

0.9

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4799

MTP10N10EL
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C
10 s

10

100 s
1 ms

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

50

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10

ID = 10 A

40

30

20

10

100

25

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4800

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
High Energy Power FET
Designer's

MTP10N40E

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


10 AMPERES
400 VOLTS
RDS(on) = 0.55 OHMS

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

G
S

CASE 221A06, Style 5


TO-220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

10
40

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

65 to 150

WDSR(1)

mJ

WDSR(2)

520
83
13

RJC
RJA

1.0
62.5

C/W

TL

275

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)


Single Pulse DraintoSource Avalanche Energy TJ = 25C
Single Pulse DraintoSource Avalanche Energy TJ = 100C
Repetitive Pulse DraintoSource Avalanche Energy

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds
(1) VDD = 50 V, ID = 10 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4801

MTP10N40E
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

V(BR)DSS

400

Vdc

0.25
1.0

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
Zero Gate Voltage Drain Current
(VDS = 400 V, VGS = 0)
(VDS = 320 V, VGS = 0, TJ = 125C)

IDSS

mAdc

GateBody Leakage Current Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0
1.5

4.0
3.5

0.4

0.55

6.0
4.75

gFS

4.0

mhos

Ciss

1570

pF

Coss

230

Crss

55

td(on)

25

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
(TJ = 125C)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 5.0 A)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 5.0 A)
(ID = 2.5 A, TJ = 100C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 A)

Vdc

Ohms
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 V
V, VGS = 0,
0
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 200 V, ID 10 A,
RL = 20
, RG = 9.1
91
,
VGS(on) = 10 V)

Fall Time
Total Gate Charge
GateSource Charge

(VDS = 320 V,
V ID = 10 A,
A
VGS = 10 V)

GateDrain Charge

ns

tr

37

td(off)

75

tf

31

Qg

46

63

Qgs

10

Qgd

23

VSD

2.0

Vdc

ton

**

ns

trr

250

3.5
4.5

7.5

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage
Forward TurnOn Time

(IS = 10 A, di/dt = 100 A/s)

Reverse Recovery Time


INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

nH

* Pulse Test: Pulse Width = 300 s, Duty Cycle 2.0%.


** Limited by circuit inductance.

4802

Motorola TMOS Power MOSFET Transistor Device Data

MTP10N40E

20

VGS = 10 V

I D, DRAIN CURRENT (AMPS)

TJ = 25C

7V

16

12
6V
8

4
5V
0
0

8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8
0.7
50

25

I D, DRAIN CURRENT (AMPS)

VDS = 50 V
20

15

10
TJ = 25C
100C
0

55C

3
5
7
2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 100C
1

25C
0.5
55C

0
15

20

25

150

1.1

VGS = 0
ID = 250 A

0.9

0.8

50

25

25

50

75

100

125

150

Figure 4. Breakdown Voltage Variation


With Temperature

VGS = 10 V

10

125

TJ, JUNCTION TEMPERATURE (C)

1.5

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

1.2

Figure 3. Transfer Characteristics

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

VDS = VGS
ID = 0.25 mA

1.1

30

3
VGS = 10 V
ID = 5 A
2

0
50

25

25

50

75

100

125

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

4803

MTP10N40E
SAFE OPERATING AREA INFORMATION
45
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s

10

1 ms
1

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

100

30

TJ 150C

15

dc
0

100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

500

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

Figure 8. Maximum Rated Switching


Safe Operating Area

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

The power averaged over a complete switching cycle must


be less than:
TJ(max) TC
RJC
10000
VDD = 200 V
ID 10 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf
tr

t, TIME (ns)

FORWARD BIASED SAFE OPERATING AREA

td(on)
100

SWITCHING SAFE OPERATING AREA

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.
1
0.7
0.5

10
1

10
100
RG, GATE RESISTANCE (OHMS)

1000

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

D = 0.5

0.3

0.2

0.2

0.1
0.1
0.07
0.05

P(pk)

0.05
0.02

t1

0.03
0.02

t2
DUTY CYCLE, D = t1/t2

0.01

0.01
0.01

SINGLE PULSE
0.02

0.05

0.1

0.2

0.5

2
5
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 1C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1k

Figure 10. Thermal Response


4804

Motorola TMOS Power MOSFET Transistor Device Data

MTP10N40E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VR for a given
commutation speed. It is applicable when waveforms similar
to those of Figure 11 are present. Full or half-bridge PWM DC
motor controllers are common applications requiring CSOA
data.
The time interval tfrr is the speed of the commutation cycle.
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit
impedances. Maximum device stress occurs during trr as the
diode goes from conduction to reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances, Li in Motorolas test circuit are assumed
to be practical minimums.

15 V
VGS
0
IFM

dlS/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM

tfrr
VDS(pk)
VR
VDS

VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms


RGS

DUT

VR

12

I D, DRAIN CURRENT (AMPS)

IFM

IS

Li
VDS

+
9

20 V

VGS
6

VR = 80% OF RATED VDS


VdsL = Vf + Li dls/dt

di/dt 120 A/s


3

Figure 13. Commutating Safe Operating Area


Test Circuit
0

100
200
300
400
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

500
V(BR)DSS
Vds(t)

Figure 12. Commutating Safe Operating Area (CSOA)


IO
L
VDS
ID

ID(t)

C
4700 F
250 V
VDD

t
RGS
50

Figure 14. Unclamped Inductive Switching


Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data

VDD

WDSR

t, (TIME)

tP

1 LI 2
O
2

V(BR)DSS
V(BR)DSS VDD

Figure 15. Unclamped Inductive Switching


Waveforms
4805

MTP10N40E
TJ = 25C

VGS = 0 V

3000
C, CAPACITANCE (pF)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

3500

2500
2000

Crss

Ciss

1500
1000
500
0
10

VDS = 0 V
5

Coss
5

10

15

20

25

16
VDS = 100 V

TJ = 25C
ID = 10 A
12

250 V
320 V

20
40
60
QG, TOTAL GATE CHARGE (nC)

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 16. Capacitance Variation

Figure 17. Gate Charge versus


GateToSource Voltage

+18 V

VDD

1 mA
47 k
Vin

80

10 V

15 V

SAME
DEVICE TYPE
AS DUT

100 k

2N3904

0.1 F

2N3904
100 k
47 k

100

FERRITE
BEAD

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

4806

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP12N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Designed to Eliminate the Need for External Zener Transient
Suppressor Absorbs High Energy in the Avalanche Mode
Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET


12 AMPERES
100 VOLTS
RDS(on) = 0.16 OHM

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse (tp 50 s)

VGS

20
40

Vdc

Drain Current Continuous


Drain Current Single Pulse (tp 10 s)

ID
IDM

12
30

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

79
0.53

Watts
W/C

TJ, Tstg

55 to 175

EAS

290

mJ

RJC
RJA

1.9
62.5

C/W

TL

260

Operating and Storage Temperature Range

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ 175C)


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 , Peak IL = 12 A)
(See Figures 15, 16 and 17)

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4807

MTP12N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

110

Vdc
mV/C

10
100

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 250 Adc)
Temperature Coefficient (positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 V, VGS = 0)
(VDS = 100 V, VGS = 0, TJ = 150C)

IDSS

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

2.0

3.0
6.0

4.0

mV/C

0.125

0.16

Ohm

1.5
1.4

2.4
1.92

gFS

4.0

5.0

mhos

Ciss

600

pF

Crss

70

Coss

230

td(on)

10

tr

64

td(off)

21

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS 15 V, ID = 6.0 A)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance

(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
S Figure
See
Fi
14

SWITCHING CHARACTERISTICS (TJ = 100C)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 50 V, ID = 12 A,
VGS = 10 V
V, RG = 12 )
See Figure 7

Fall Time

tf

30

QT

18

26

Q1

4.0

Q2

10

Q3

8.0

( S = 12 A, VGS = 0))
(I
(IS = 12 A, VGS = 0, TJ = 150C)

VSD

1.0

2.5

0.83

(IS = 12 A, VGS = 0,
dIS/dt = 100 A/s, VR = 50 V)

trr

110

3.5
4.5

7.5

Gate Charge
(VDS = 80 V, ID = 12 A,
VGS = 10 Vdc)
See Figures 5 and 6

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage

Reverse Recovery Time

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

4808

Motorola TMOS Power MOSFET Transistor Device Data

MTP12N10E
TYPICAL ELECTRICAL CHARACTERISTICS
24

24
VGS = 10 V

VDS 15 V

9V

20

I D, DRAIN CURRENT (AMPS)

8V
16
7V
12
6V

5V

12
8
4
0

2
3
4
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

0.6
VGS = 10 V
0.5
0.4
0.3
TJ = 100C

0.2

25C
0.1

55C

0
0

9
12
15
18
ID, DRAIN CURRENT (AMPS)

21

2.2
VGS = 10 V
ID = 6 A

2
1.8
1.6
1.4
1.2
1
0.8
0.6
50

24

25

15 V

1 mA

10 V

0.1 F

2N3904
2N3904

100 k
47 k

100 k

100

FERRITE
BEAD

SAME
DEVICE
TYPE
AS DUT

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 5. Gate Charge Test Circuit

Motorola TMOS Power MOSFET Transistor Device Data

VGS, GATETOSOURCE VOLTAGE (VOLTS)

47 k

VDD

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

175

Figure 4. OnResistance Variation


with Temperature

Figure 3. OnResistance versus Drain Current

+18 V

10

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100C

25C
16

Vin

TJ = 55C

20

20

100
ID = 12 A
VDS = 80 V
TJ = 25C

VDS

16

80

12

60
QT

40

Q1
Q2

VGS

20
Q3

0
0

10
15
Qg, TOTAL GATE CHARGE (nC)

20

0
25

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

I D, DRAIN CURRENT (AMPS)

TJ = 25C

Figure 6. GateToSource and


DrainToSource Voltage versus Gate Charge

4809

MTP12N10E
SAFE OPERATING AREA INFORMATION
FORWARD BIASED SAFE OPERATING AREA
The power averaged over a complete switching cycle must
be less than:
TJ(max) TC
RJC
1000

100

tf

td(off)

10

The switching safe operating area (SOA) of Figure 9 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, BVDSS. The
switching SOA shown in Figure 9 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.

1
10

100
RG, GATE RESISTANCE (OHMS)

1000

Figure 7. Resistive Switching Time


versus Gate Resistance
40

1000

100

VGS = 20 V
SINGLE PULSE
TC = 25C

OPERATION LIMITED IN THIS


AREA BY RDS(on)

10

10 ms

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

tr

td(on)

SWITCHING SAFE OPERATING AREA

100 s
1 ms

dc
1

0.1

VDD = 50 V
ID = 12 A
VGS = 10 V
TJ = 25C

t, TIME (ns)

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 175C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

30

20
TJ 175C
10

0
0.1

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 8. Maximum Rated Forward Biased


Safe Operating Area

20
40
60
80
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

120

Figure 9. Maximum Rated Switching


Safe Operating Area

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5

0.5
0.3
0.2

0.2
0.1

0.1

P(pk)

0.05
0.05

0.02
t1

0.03

t2
DUTY CYCLE, D = t1/t2

0.01

0.02
SINGLE PULSE
0.01
0.01

0.02

0.05

0.1

0.2

0.5

2
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 1.9C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1000

Figure 10. Thermal Response


4810

Motorola TMOS Power MOSFET Transistor Device Data

MTP12N10E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the
source-drain diode has undergone forward bias. The curve
shows the limitations of IFM and peak VDS for a given rate of
change of source current. It is applicable when waveforms
similar to those of Figure 11 are present. Full or half-bridge
PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak draintosource voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at rated BVDSS to ensure that the CSOA
stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorolas test circuit are assumed to
be practical minimums.

15 V
VGS
0
IFM

dls/dt

90%
IS
10%

trr
ton

IRM
0.25 IRM
VDS(pk)
VR

VDS

dVDS/dt
VdsL

Vf

MAX. CSOA
STRESS AREA

Figure 11. Commutating Waveforms

IS , SOURCETODRAIN CURRENT (AMPS)

15

RGS
TJ 175C
IS = 12 A
dIs/dt 100 A/s
VR 100 V

12

VR
+

IFM

IS

20 V

VGS

20

40
60
80 100 120 140 160
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

180

DUT

200

Figure 12. Commutating Safe Operating


Area (CSOA)

Motorola TMOS Power MOSFET Transistor Device Data

Li
VDS

VR = 80% OF RATED BVDSS


VdsL = Vf + Li dls/dt

Figure 13. Commutating Safe Operating Area


Test Circuit

4811

EAS , SINGLE PULSE AVALANCHE ENERGY (mJ)

MTP12N10E
300

2000

VGS = 0 V

VDS = 0 V

PEAK IL = 12 A
VDD = 25 V

250

C, CAPACITANCE (pF)

1500

200

150

1000
Ciss

100

500
Coss
Crss
0
15

15

30

45

60

50
0

25

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 14. Capacitance Variation

75
100
125
150
50
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 15. Maximum Avalanche Energy versus


Starting Junction Temperature
BVDSS

L
VDS
IL
IL(t)
VDD
t

RG
VDD
tP

Figure 16. Unclamped Inductive Switching


Test Circuit

4812

t, (TIME)

Figure 17. Unclamped Inductive Switching


Waveforms

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP12P10

Power Field Effect Transistor

PChannel EnhancementMode Silicon Gate


This TMOS Power FET is designed for medium voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.

Silicon Gate for Fast Switching Speeds Switching Times


Specified at 100C
Designers Data IDSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
Rugged SOA is Power Dissipation Limited
SourcetoDrain Diode Characterized for Use With Inductive Loads

TMOS POWER FET


12 AMPERES
100 VOLTS
RDS(on) = 0.3 OHM

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage Nonrepetitive (tp 50 s)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Pulsed

ID
IDM

12
28

Adc

Total Power Dissipation


Derate above 25C

PD

75
0.6

Watts
W/C

TJ, Tstg

65 to 150

RJC
RJA

1.67
62.5

C/W

TL

260

Operating and Storage Temperature Range

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4813

MTP12P10
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Max

Unit

V(BR)DSS

100

Vdc

10
100

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0)
(VDS = Rated VDSS, VGS = 0, TJ = 125C)

Adc

IDSS

GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)

IGSSF

100

nAdc

GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)

IGSSR

100

nAdc

Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA)


TJ = 100C

VGS(th)

2.0
1.5

4.5
4.0

Vdc

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

0.3

Ohm

DrainSource OnVoltage (VGS = 10 V)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 100C)

VDS(on)

4.2
3.8

gFS

2.0

mhos

Ciss

920

pF

Coss

575

Crss

200

td(on)

50

tr

150

td(off)

150

tf

150

Qg

33 (Typ)

50

ON CHARACTERISTICS*

Forward Transconductance (VDS = 15 V, ID = 6.0 A)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance

(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
S Figure
See
Fi
10

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS* (TJ = 100C)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 25 V, ID = 0.5 Rated ID,


RG = 50 )
See Figures 12 and 13

Fall Time
Total Gate Charge
GateSource Charge
GateDrain Charge

(VDS = 0.8 Rated VDSS,


ID = Rated ID, VGS = 10 V)
S Fi
See
Figure 11

Qgs

16 (Typ)

Qgd

17 (Typ)

VSD

4.0 (Typ)

5.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage
Forward TurnOn Time

(IS = Rated
R t d I D,
VGS = 0)

Reverse Recovery Time

ton

Vdc

Limited by stray inductance

trr

300 (Typ)

ns

Internal Drain Inductance


(Measured from the contact screw on the header closer
to the source pin and the center of the die)

Ld

5.0 (Typ)

nH

Internal Source Inductance


(Measured from the source pin, 0.25 from the package
to the source bond pad)

Ls

12.5 (Typ)

3.5 (Typ)
4.5 (Typ)

7.5 (Typ)

INTERNAL PACKAGE INDUCTANCE (TO204)

INTERNAL PACKAGE INDUCTANCE (TO220)


Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

Ld

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

Ls

nH

* Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

4814

Motorola TMOS Power MOSFET Transistor Device Data

MTP12P10

20

VGS = 20 V

I D, DRAIN CURRENT (AMPS)

18
16

10 V

TJ = 25C
8V

14
12

7V

10
8

6V

6
4

5V

2
0

2
3
4
5
6
7
8
9
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS

1.2

0.9

0.8

50

I D, DRAIN CURRENT (AMPS)

25C

16

TJ = 55C

100C

12

8
VDS = 20 V

8
12
16
VGS, GATETOSOURCE VOLTAGE (VOLTS)

20

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.4

25C

55C

0.1

12

16

20

24

28

32

150

1.6

VGS = 0
ID = 0.25 mA

1.2

0.8

0.4

0
50

75

25

50

75

100

125

150

Figure 4. Normalized Breakdown Voltage


versus Temperature

TJ = 100C

0.2

125

TJ, JUNCTION TEMPERATURE (C)

0.5

0.3

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

VGS = 15 V

25

Figure 2. GateThreshold Voltage Variation


With Temperature
VBR(DSS), DRAINTOSOURCE BREAKDOWN VOLTAGE
(NORMALIZED)

Figure 1. OnRegion Characteristics

20

VDS = VGS
ID = 1 mA

1.1

36

40

1.8
VGS = 10 V
ID = 6 A

1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
50

25

25

50

75

100

125

150

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4815

MTP12P10
SAFE OPERATING AREA INFORMATION
50

1 ms

10

I D, DRAIN CURRENT (AMPS)

I D, DRAIN CURRENT (AMPS)

10 s
0.1 ms

10 ms
VGS = 20 V
SINGLE PULSE
TC = 25C

dc

MTM/MTP12P06
RDS(on) LIMIT
PACKAGE LIMIT
THERMAL LIMIT MTM/MTP12P10

40

30

20
MTM/MTP12P06

10

MTM/MTP12P10

1
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased


Safe Operating Area

10

30
50
70
20
40
60
80
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

90

100

Figure 8. Maximum Rated Switching


Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA

SWITCHING SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource


voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, Transient Thermal ResistanceGeneral Data
and Its Use provides detailed instructions.

The switching safe operating area (SOA) of Figure 8 is the


boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn
on and turnoff of the devices for switching times less than
one microsecond.
The power averaged over a complete switching cycle must
be less than:
TJ(max) TC
RJC

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1
D = 0.5

0.5
0.3

0.2

0.2
0.1
0.1

P(pk)

0.05
0.05

0.02

0.03

t1

0.02

t2
DUTY CYCLE, D = t1/t2

0.01
SINGLE PULSE

0.01
0.01

0.02

0.05

0.1

0.2

0.5

2
5
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 1.67C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
50

100

200

500

1000

Figure 9. Thermal Response

4816

Motorola TMOS Power MOSFET Transistor Device Data

MTP12P10
0
TC = 25C
VGS = 0
f = 1 MHz

1200
C, CAPACITANCE (pF)

VGS, GATE SOURCE VOLTAGE (VOLTS)

1600

Ciss
800
Coss

400

Crss
0

10

30

20
VDS, SOURCETODRAIN VOLTAGE (VOLTS)

40

TJ = 25C
ID = 12 A

2
4
6
8
10
VDS = 30 V

12

50 V
14
16

80 V
0

10

15

20

25

30

35

40

45

50

Qg, TOTAL GATE CHARGE (nC)

Figure 10. Capacitance Variation

Figure 11. Gate Charge versus


GateToSource Voltage

RESISTIVE SWITCHING
VDD
ton
td(on)

RL

tr
90%

Vout
Vin
PULSE GENERATOR
Rgen

50

DUT

z = 50

OUTPUT, Vout

toff
td(off)

10%
90%

50
INPUT, Vin

Motorola TMOS Power MOSFET Transistor Device Data

50%

50%
10%

INVERTED

Figure 12. Switching Test Circuit

tf
90%

PULSE WIDTH

Figure 13. Switching Waveforms

4817

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP15N06V

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse (tp 50 s)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
8.7
45

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

55
0.5

Watts
W/C

TJ, Tstg
EAS

55 to 175

113

mJ

RJC
RJA

2.73
62.5

C/W

TL

260

DrainSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4818

Motorola TMOS Power MOSFET Transistor Device Data

MTP15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

67

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
5.0

4.0

Vdc
mV/C

0.08

0.12

Ohm

2.0

2.2
1.9

gFS

4.0

6.2

mhos

Ciss

469

660

pF

Coss

148

200

Crss

35

60

td(on)

7.6

20

tr

51

100

td(off)

18

40

tf

33

70

QT

14.4

20

Q1

2.8

Q2

6.4

Q3

6.1

1.05
1.5

1.6

trr

59.3

ta

46

tb

13.3

QRR

0.165

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 15 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4819

MTP15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30

I D , DRAIN CURRENT (AMPS)

7V

20
15

6V

10
5V

25C

15
10

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V

TJ = 100C

0.14

25C
0.08
55C

25

10
15
20
ID, DRAIN CURRENT (AMPS)

30

0.13
TJ = 25C
0.11

VGS = 10 V

0.09

15 V

0.07

0.05

Figure 3. OnResistance versus Drain Current


and Temperature

10
15
20
ID, DRAIN CURRENT (AMPS)

25

30

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100

VGS = 0 V

VGS = 10 V
ID = 7.5 A
1.6
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

55C

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.20

0.02

25

5
0

TJ = 100C

VDS 10 V

9V

25

I D , DRAIN CURRENT (AMPS)

30

8V

VGS = 10 V

TJ = 25C

1.2

0.8

0.4
50

4820

25

25

50

75

100

125

150

175

TJ = 125C

10

TJ, JUNCTION TEMPERATURE (C)

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

60

Motorola TMOS Power MOSFET Transistor Device Data

MTP15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

1200
Ciss
900

600

Ciss

Crss

300

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4821

QT
50

10
VGS

40

Q2

Q1
6

30

20

ID = 15 A
TJ = 25C

2
0

Q3
3

VDS
6

12

10
0
15

1000
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

60

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP15N06V

100
tr
tf
td(off)
10

td(on)

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


15

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
12

0
0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4822

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP15N06V
SAFE OPERATING AREA
120

VGS = 10 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10
100 s
1 ms
10 ms

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

10

1.0

0.1

ID = 15 A
100
80
60
40
20
0
25

100

50

75

100

125

150

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2

0.1

0.1
0.05

P(pk)
0.02

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4823

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP15N06VL

TMOS V
Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


15 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

15
12
53

Adc

Total Power Dissipation


Derate above 25C

PD

60
0.40

Watts
W/C

TJ, Tstg
EAS

55 to 175

113

mJ

RJC
RJA

2.5
62.5

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GatetoSource Voltage Nonrepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4824

Motorola TMOS Power MOSFET Transistor Device Data

MTP15N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

1.0

1.5
TBD

2.0

mV/C

0.075

0.085

Ohm

1.5
1.3

gFS

8.0

10

mhos

Ciss

630

880

pF

Coss

270

380

Crss

56

110

td(on)

26

50

tr

105

210

td(off)

80

160

tf

70

140

QT

12

20

Q1

3.0

Q2

8.0

Q3

10

1.0
0.9

1.6

trr

100

ta

55

tb

45

QRR

0.345

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 7.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5.0 Vdc, ID = 15 Adc)
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 15 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 15 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)


(IS = 15 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die.)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4825

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP16N25E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

250

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

250

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

16
10
56

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25 )

EAS

384

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.0
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4826

Motorola TMOS Power MOSFET Transistor Device Data

MTP16N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

333

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.17

0.25

Ohm

3.6

4.8
4.2

gFS

3.0

7.0

mhos

Ciss

1558

2180

pF

Coss

281

390

Crss

130

260

td(on)

15

30

tr

64

130

td(off)

56

110

tf

44

90

QT

53.4

70

Q1

9.3

Q2

27.5

Q3

17.1

0.915
1.39

1.5

trr

234

ta

170

tb

64

QRR

2.165

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 16 Adc)
(ID = 8.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 125 Vdc, ID = 16 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 16 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 16 Adc, VGS = 0 Vdc)


(IS = 16 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4827

MTP16N25E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

32

VGS = 10 V

TJ = 25C

VDS 10 V

8V
I D , DRAIN CURRENT (AMPS)

32

7V
24

6V

16

24

16

8
TJ = 55C

100C

5V

25C
0

Figure 2. Transfer Characteristics

TJ = 100C

0.4
0.3

25C

0.2
0.1

55C

10
15
20
25
ID, DRAIN CURRENT (AMPS)

30

35

0.26
TJ = 25C
0.22
VGS = 10 V
0.18

15 V

0.14

0.1

16

24

32

40

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

3.0

1000
VGS = 10 V
ID = 8 A

VGS = 0 V
TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

0.5

2.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.6

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

2.0
1.5
1.0

100
100C

10
25C

0.5
0
50

4828

25

25

50

75

100

125

150

50

100

150

200

250

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

300

Motorola TMOS Power MOSFET Transistor Device Data

MTP16N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

4000
Ciss
3000

2000

Ciss

Crss

1000
0
10

Coss
Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4829

200
QT
VGS

150

Q2

Q1

100

ID = 16 A
TJ = 25C

3
Q3
0

10

50

VDS
40
20
30
QT, TOTAL CHARGE (nC)

0
50

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP16N25E
VDD = 250 V
ID = 16 A
VGS = 10 V
TJ = 25C

100

tr
td(off)
tf
10

60

td(on)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

16
VGS = 0 V
TJ = 25C
12

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4830

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP16N25E
SAFE OPERATING AREA
400
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

10

100 s

1 ms
10 ms

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1

10

1.0

300

200

100

1000

100

ID = 16 A

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E02

1.0E03

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t,TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4831

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP20N06V

TMOS V
Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TMOS POWER FET


20 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
13
70

Adc

Total Power Dissipation


Derate above 25C

PD

60
0.40

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )

EAS

200

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

2.5
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4832

Motorola TMOS Power MOSFET Transistor Device Data

MTP20N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

2.0

2.8
TBD

4.0

Vdc
mV/C

0.065

0.085

Ohm

2.0
1.9

gFS

6.0

8.0

mhos

Ciss

590

830

pF

Coss

180

250

Crss

40

80

td(on)

8.7

20

tr

77

150

td(off)

26

50

tf

46

90

QT

28

40

Q1

4.0

Q2

9.0

Q3

8.0

1.0
0.96

1.6

trr

60

ta

52

tb

8.0

QRR

0.172

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4833

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP20N20E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


20 AMPERES
200 VOLTS
RDS(on) = 0.16 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Continuous
Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

20
12
60

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )

EAS

600

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.00
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4834

Motorola TMOS Power MOSFET Transistor Device Data

MTP20N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

263

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.12

0.16

Ohm

3.84
3.36

gFS

8.0

11

mhos

Ciss

1880

2700

pF

Coss

378

535

Crss

68

100

td(on)

17

40

tr

86

180

td(off)

50

100

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 100 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 160 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

tf

60

120

QT

54

75

Q1

12

Q2

24

Q3

22

1.0
0.82

1.35

trr

239

ta

136

tb

103

QRR

2.09

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4835

MTP20N20E
TYPICAL ELECTRICAL CHARACTERISTICS
40

40
VGS = 10 V

8V

VDS 10 V

35

9V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C

7V

30

20
6V
10

TJ = 55C
25C

30
25

100C

20
15
10

5V
5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5

0
1

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.35
VGS = 10 V
0.30
TJ = 100C

0.25
0.20
0.15

25C

0.10
55C
0.05
4

12
20
28
16
24
ID, DRAIN CURRENT (AMPS)

32

36

40

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.17
TJ = 25C
0.16
0.15
0.14
VGS = 10 V
0.13
0.12
15 V

0.11
0.10
0

36

40

TJ = 125C

1000

1.2

0.8

100C
100
25C

10

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4836

32

VGS = 0 V

VGS = 10 V
ID = 10 A

1.6

0.4
50

12
16
20
24
28
ID, DRAIN CURRENT (AMPS)

10000

2.4

2.0

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

150

50
150
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP20N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

4000

3000

Crss
Ciss

2000

1000
0
10

Coss

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4837

10
Q1

150

VGS

Q2

120

90

6
ID = 20 A
TJ = 25C

60
30

2
Q3
0

1000

180
QT

10

VDS
30
20
40
QG, TOTAL GATE CHARGE (nC)

50

0
60

VDD = 100 V
ID = 20 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLT)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP20N20E

100
tr
tf
td(off)
td(on)
10

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

20

16

VGS = 0 V
TJ = 25C

12

0
0.50 0.55

0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95


VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4838

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current
(ID), in accordance with industry custom. The energy rating
must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below
rated continuous ID can safely be assumed to equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP20N20E
SAFE OPERATING AREA

10

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s
1 ms
10 ms

1.0

dc
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600
ID = 20 A
500
400
300
200
100
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4839

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTP23P06V

Designer's

TMOS
Power Field Effect Transistor

Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


23 AMPERES
60 VOLTS
RDS(on) = 0.120 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

23
15
81

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

90
0.60

Watts
W/C

TJ, Tstg
EAS

55 to 175

794

mJ

RJC
RJA

1.67
62.5

C/W

TL

260

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4840

Motorola TMOS Power MOSFET Transistor Device Data

MTP23P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

60.5

Vdc
mV/C

10
100

100

nAdc

2.0

2.8
5.3

4.0

Vdc
mV/C

0.093

0.12

Ohm

3.3
3.2

5.0

11.5

Ciss

1160

1620

Coss

380

530

Crss

105

210

td(on)

13.8

30

tr

98.3

200

td(off)

41

80

tf

62

120

QT

38

50

Q1

7.0

Q2

18

Q3

14

2.2
1.8

3.5

trr

142.2

ta

100.5

tb

41.7

QRR

0.804

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 11.5 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 23 Adc)
(VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 10.9 Vdc, ID = 11.5 Adc)

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 23 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 23 Adc, VGS = 0 Vdc)


(IS = 23 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 23 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4841

MTP23P06V
TYPICAL ELECTRICAL CHARACTERISTICS
40
VGS = 10V

I D , DRAIN CURRENT (AMPS)

TJ = 25C
40

8V
9V
7V

30
6V

20

10

VDS 10 V

35
I D , DRAIN CURRENT (AMPS)

50

5V

TJ = 55C
25C

30
100C

25
20
15
10
5

4V
0

TJ = 100C

25C

0.1
0.08

55C
0.06
0.04
0.02
5

10

15
20
25
30
ID, DRAIN CURRENT (AMPS)

35

40

45

Figure 2. Transfer Characteristics

0.12

0.12
TJ = 25C
0.115
0.11
0.105

VGS = 10 V

0.1
0.095
15 V

0.09
0.085
0.08

Figure 3. OnResistance versus Drain Current


and Temperature

10

15
20
30
35
25
ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

100
VGS = 0 V

VGS = 10 V
ID = 11.5 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

0.14

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16

10

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2
1
0.8
0.6

TJ = 125C

10

0.4
0.2
0
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4842

175

50
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP23P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
4000

C, CAPACITANCE (pF)

Ciss
3000

VGS = 0 V

VDS = 0 V

TJ = 25C

Crss

2000
Ciss
1000
Coss
Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4843

30
QT

9
8

27
24

Q2

Q1

VGS

21

18

15

12
9

3
2
Q3

1
0

TJ = 25C
ID = 23 A

VDS
10

15

25

20

30

35

6
3
0
40

1000

t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP23P06V
TJ = 25C
ID = 23 A
VDD = 30 V
VGS = 10 V

100

tr
tf
td(off)
td(on)

10

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

25
TJ = 25C
VGS = 0 V

20

15

10

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4844

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP23P06V
SAFE OPERATING AREA
800

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

10

1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

600
500
400
300
200
100
0

0.1
0.1

ID = 23 A

700

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

25

100

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.10
0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4845

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP27N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


27 AMPERES
100 VOLTS
RDS(on) = 0.07 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Device Marking: MTP27N10E

G
S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

100

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

27
17
95

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

104
0.83

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 75 Vdc, VGS = 10 Vdc, IL = 27 Apk, L = 0.3 mH, RG = 25 )

EAS

109

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.2
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

4846

Motorola TMOS Power MOSFET Transistor Device Data

MTP27N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

120

Vdc
mV/C

10
100

100

nAdc

2.0

3.1
7.0

4.0

Vdc
mV/C

0.058

0.07

2.3
2.0

gFS

6.0

11

mhos

pF

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0) (3)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 13.5 Adc)

(Cpk 2.0) (3)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 27 Adc)
(VGS = 10 Vdc, ID = 13.5 Adc, TJ = 125C)
Forward Transconductance (VDS = 7.7 Vdc, ID = 13.5 Adc)

VGS(th)

RDS(on)

Ohm

VDS(on)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

Vd VGS = 0 Vdc,
Vd
(VDS = 25 Vdc,
f = 1.0 MHz)

Transfer Capacitance

Ciss

1131

1580

Coss

468

660

Crss

186

370

td(on)

13

30

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 50 Vdc, ID = 27 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 80 Vdc, ID = 27 Adc,
VGS = 10 Vdc)

tr

142

280

td(off)

29

60

tf

59

120

QT

41

60

Q1

9.0

Q2

25

Q3

22

1.0
0.94

1.5

trr

126

ta

98

tb

28

QRR

0.685

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 27 Adc, VGS = 0 Vdc)


(IS = 27 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 27 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4847

MTP27N10E
TYPICAL ELECTRICAL CHARACTERISTICS
60

60
TJ = 25C

I D , DRAIN CURRENT (AMPS)

9V

50

I D , DRAIN CURRENT (AMPS)

VDS 10 V

VGS = 10 V

40
8V
30
7V
20
6V

25C

50
100C
40
30

TJ = 55C

20
10

10
5V
0

0
0

3
4
5
6
7
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

0.14
VGS = 10 V
0.12
TJ = 100C

0.1
0.08

25C
0.06
55C

0.04
0.02
0
0

10

20
40
30
ID, DRAIN CURRENT (AMPS)

50

60

0.08
TJ = 25C

0.075
0.07

VGS = 10 V

0.065
0.06
0.055

15 V

0.05
0.045
0.04
0

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.4

1000
VGS = 10 V
ID = 13.5 A

VGS = 0 V
TJ = 125C

1.8
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

2.2
2.0

10

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

4
5
6
7
8
9
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.6
1.4
1.2
1.0
0.8
0.6

100

100C
10

0.4
0.2
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4848

150

2
4
6
8
3
5
7
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP27N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

3500

C, CAPACITANCE (pF)

3000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

2500
2000
Ciss

1500
1000

Crss
Coss

500
0
15

Crss
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4849

60

TJ = 25C
ID = 27 A

54

QT

48
VGS

7
6

Q1

42
36

Q2

30

24

18

12

1
0

10

VDS

Q3

25
15
20
30
35
QG, TOTAL GATE CHARGE (nC)

40

0
45

1000

t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP27N10E
VDD = 50 V
ID = 27 A
VGS = 10 V
TJ = 25C

100

tf
td(off)
td(on)

10

tr

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

25
20
15
10
5
0
0.6

0.65

0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05


VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.1

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4850

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP27N10E
SAFE OPERATING AREA

100

120
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
10 s

100 s
1 ms

1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.01
0.1

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 27 A
100
80
60
40
20
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

t1

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4851

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP30N06VL

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


30 AMPERES
60 VOLTS
RDS(on) = 0.050 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

30
20
105

Adc

Total Power Dissipation


Derate above 25C

PD

90
0.6

Watts
W/C

TJ, Tstg
EAS

55 to 175

154

mJ

RJC
RJA

1.67
62.5

C/W

TL

260

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 30 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4852

Motorola TMOS Power MOSFET Transistor Device Data

MTP30N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

63

Vdc
mV/C

10
100

100

nAdc

1.0

1.5
4.0

2.0

Vdc
mV/C

0.033

0.05

Ohm

1.8
1.73

gFS

13

21

Mhos

Ciss

1130

1580

pF

Coss

360

500

Crss

95

190

td(on)

14

30

tr

260

520

td(off)

54

110

tf

108

220

QT

27

40

Q1

Q2

17

Q3

15

0.98
0.89

1.6

trr

86.4

ta

49.6

tb

36.8

QRR

0.228

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 15 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5 Vdc, ID = 30 Adc)
(VGS = 5 Vdc, ID = 15 Adc, TJ = 150 C)

VDS(on)

Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS = 5 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 48 Vdc, ID = 30 Adc,


VGS = 5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 150 C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4853

MTP30N06VL
TYPICAL ELECTRICAL CHARACTERISTICS

50

I D , DRAIN CURRENT (AMPS)

60

VGS = 10 V
8V

TJ = 25C

6V
5V

40

4V

30
20

3V

25C
100C

40
30
20

0
0

0.08

10

Figure 2. Transfer Characteristics

0.06

TJ = 100C

0.05
0.04

25C

0.03
0.02

55C

0.01
0
0

10

20
30
40
ID, DRAIN CURRENT (AMPS)

60

50

0.06
TJ = 25C
0.05
VGS = 5 V

0.04

10 V

0.03
0.02
0.01
0

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000
VGS = 0 V

VGS = 5 V
ID = 15 A

TJ = 125C

1.4

I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

0.07

1.6

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

50

10

10
0

TJ = 55C

VDS 10 V
I D , DRAIN CURRENT (AMPS)

60

1.2
1
0.8
0.6

100
100C
10

0.4
0.2
0
50

1
25

25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4854

175

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP30N06VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
5000

C, CAPACITANCE (pF)

4500 C
iss
4000

VDS = 0 V

VGS = 0 V

TJ = 25C

3500
3000

Crss

2500
2000
1500

Ciss

1000
500

Coss

Crss

0
10

5
VGS

0
VDS

10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4855

30

4.5

27

24

QT

3.5

VGS

Q2

Q1

21
18

2.5

15

12

1.5

Q3

1
0.5
0

10

15

6
3

VDS
0

TJ = 25C
ID = 30 A

0
25

20

1000
TJ = 25C
ID = 30 A
VDD = 30 V
VGS = 5 V
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP30N06VL

tr
tf

100

td(off)
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


30

I S , SOURCE CURRENT (AMPS)

25

TJ = 25C
VGS = 0 V

20
15
10
5
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4856

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP30N06VL
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

160

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10 s

100 s

10

1 ms
10 ms
dc

1
0.1

10

ID = 30 A

140
120
100
80
60
40
20
0

100

25

50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.05

0.10
0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4857

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP30P06V

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


30 AMPERES
60 VOLTS
RDS(on) = 0.080 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

30
19
105

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

125
0.83

Watts
W/C

TJ, Tstg
EAS

55 to 175

450

mJ

RJC
RJA

1.2
62.5

C/W

TL

260

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 30 Apk, L = 1.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4858

Motorola TMOS Power MOSFET Transistor Device Data

MTP30P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

62

Vdc
mV/C

10
100

100

nAdc

2.0

2.6
5.3

4.0

Vdc
mV/C

0.067

0.08

Ohm

2.0

2.9
2.8

5.0

7.9

Ciss

1562

2190

Coss

524

730

Crss

154

310

td(on)

14.7

30

tr

25.9

50

td(off)

98

200

tf

52.4

100

QT

54

80

Q1

9.0

Q2

26

Q3

20

2.3
1.9

3.0

trr

175

ta

107

tb

68

QRR

0.965

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 30 Adc)
(VGS = 10 Vdc, ID = 15 Adc, TJ = 150C)

VDS(on)

Forward Transconductance
(VDS = 8.3 Vdc, ID = 15 Adc)

Vdc

gFS

Mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4859

MTP30P06V
TYPICAL ELECTRICAL CHARACTERISTICS
60

60
TJ = 25C

40
30

6V

20
5V

10
0

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

7V

4V
0

25C

40
30

TJ = 55C

20

Figure 2. Transfer Characteristics

0.1
0.08

25C

0.06
55C
0.04
0.02

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

0.08
TJ = 25C
VGS = 10 V

0.07

15 V
0.06

0.05

0.04

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
40
ID, DRAIN CURRENT (AMPS)

50

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

100
VGS = 0 V

VGS = 10 V
ID = 15 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

TJ = 100C

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.12

50

12

10

100C

10

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

9V

VGS = 10V

50

VDS 10 V

8V

1.2
1
0.8
0.6

10
100C

0.4
0.2
0
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4860

175

50
60
10
20
30
40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

70

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP30P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
Ciss

C, CAPACITANCE (pF)

5000
4000

VGS = 0 V

VDS = 0 V

TJ = 25C

Crss

3000
Ciss

2000

Coss
1000
Crss

0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4861

30
VGS
27

QT

24

8
Q2

Q1

21

18

15

12

VDS

1
0

TJ = 25C
ID = 30 A

Q3

10

20

30

40

50

6
3
0
60

1000

t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP30P06V
TJ = 25C
ID = 30 A
VDD = 30 V
VGS = 10 V

100

td(off)
tf
tr
td(on)

10

1
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


30
TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

25
20
15
10
5
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4862

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP30P06V
SAFE OPERATING AREA
450

VGS = 20 V
SINGLE PULSE
TC = 25C

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
10 s
100 s

10

1 ms

10 ms
dc

ID = 30 A

400
350
300
250
200
150
100
50
0

1
0.1

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

25

100

50

75

100

125

150

175

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.10

P(pk)

0.05
0.02
0.01

t1

SINGLE PULSE

0.01
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4863

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTP33N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


33 AMPERES
100 VOLTS
RDS(on) = 0.06 OHM

This advanced TMOS EFET is designed to withstand high


energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Continuous
NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Voltage Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

33
20
99

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 33 Apk, L = 1.000 mH, RG = 25 )

EAS

545

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.00
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

4864

Motorola TMOS Power MOSFET Transistor Device Data

MTP33N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

118

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.04

0.06

Ohm

1.6

2.4
2.1

gFS

8.0

mhos

Ciss

1830

2500

pF

Coss

678

1200

Crss

559

1100

td(on)

18

40

tr

164

330

td(off)

48

100

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 25C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 33 Adc)
(ID = 16.5 Adc, TJ = 25C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 16.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 50 Vdc, ID = 33 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 33 Adc,
VGS = 10 Vdc)

tf

83

170

QT

52

110

Q1

12

Q2

32

Q3

24

1.0
0.98

2.0

trr

144

ta

108

tb

36

QRR

0.93

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 33 Adc, VGS = 0 Vdc)


(IS = 33 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 33 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4865

MTP33N10E
TYPICAL ELECTRICAL CHARACTERISTICS
90

90
I D , DRAIN CURRENT (AMPS)

80

9V

70
60

8V

50
40

7V
30
20

6V

10

5V
2

4
6
8
3
5
7
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 55C
25C

70
60

100C

50
40
30
20
10

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0
0

VDS 10 V

80

VGS = 10 V
I D , DRAIN CURRENT (AMPS)

TJ = 25C

10

Figure 2. Transfer Characteristics

0.09
VGS = 10 V
0.08
TJ = 100C

0.07
0.06
0.05

25C

0.04
55C

0.03
0.02
6

12

18 24 30 36 42 48
ID, DRAIN CURRENT (AMPS)

54

66

60

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.053
TJ = 25C

0.051
0.049
0.047

VGS = 10 V

0.045
0.043
0.041
0.039

15 V

0.037
5

2.0
1.8

17

23
35 41
29
47
ID, DRAIN CURRENT (AMPS)

53

59

65

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 16.5 A

1.6

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

11

1.4
1.2
1.0

1000

TJ = 125C

100C
100
25C

0.8
0.6
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4866

150

10
20

30

50
70
40
60
80
90
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP33N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000
4500
C, CAPACITANCE (pF)

4000
3500

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

Crss

3000
2500

Ciss

2000
1500

Coss

1000
500
0
10

Crss
0

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4867

12

120

VGS

QT

100

10
Q2
8

80

Q1

60

40
20

Q3

2
0

1000

140
TJ = 25C
ID = 33 A

VDS
0

10

20
30
40
QG, TOTAL GATE CHARGE (nC)

50

0
60

VDD = 50 V
ID = 33 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

14

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP33N10E

tr
100
tf
td(off)

td(on)
10

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


33
VGS = 0 V
TJ = 25C

30
I S , SOURCE CURRENT (AMPS)

27
24
21
18
15
12
9
6
3
0
0.5

0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.05

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4868

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP33N10E
SAFE OPERATING AREA
550
VGS = 20 V
SINGLE PULSE
TC = 25C

100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100 s

10

1 ms
1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

0.01

0.1

1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

ID = 33 A

450
400
350
300
250
200
150
100
50
0
25

100

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
0.1
P(pk)

0.1
0.05

t1

0.02

t2
DUTY CYCLE, D = t1/t2

0.01
0.01
1.0E05

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE
1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4869

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP35N06ZL

HDTMOS E-FET.
Power Field Effect Transistor
NChannel EnhancementMode Silicon Gate

TMOS POWER FET


35 AMPERES
60 VOLTS
RDS(on) = 26 m

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode
ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

G
CASE 221A06, Style 5
TO220AB
S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Continuous @ TC = 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

35
22.8
105

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

94
0.63

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 5.0 Vdc, Peak IL = 35 Apk, L = 0.3 mH, RG = 25 )

EAS

184

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.6
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

4870

Motorola TMOS Power MOSFET Transistor Device Data

MTP35N06ZL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

52

Vdc
mV/C

10
100

5.0

Adc

1.0

1.5
4.0

2.0

Vdc
mV/C

22

26

0.78
0.7

1.1
1.0

gFS

10

12

mhos

Ciss

1600

pF

Coss

560

Crss

140

td(on)

40

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Cpk 3.0)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk 3.0)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(Cpk 2.0)
(VGS = 5.0 Vdc, ID = 11.5 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 5.0 Vdc)


(ID = 23 Adc)
(ID = 11.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 4.0 Vdc, ID = 11.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 23 Adc,


5 0 Vdc,
Vdc
VGS(on) = 5.0
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc,
VGS = 5.0 Vdc)

tr

250

td(off)

130

tf

170

QT

45

Q1

8.0

Q2

22

Q3

19

0.92
0.81

1.1

trr

43

ta

24

tb

20

QRR

0.055

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 23 Adc, VGS = 0 Vdc)


(IS = 23 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 23 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4871

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Designer's

Data Sheet

MTP36N06V

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


32 AMPERES
60 VOLTS
RDS(on) = 0.04 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage Nonrepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous @ 25 C


Drain Current Continuous @ 100 C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

32
22.6
112

Adc

Total Power Dissipation @ 25 C


Derate above 25 C

PD

90
0.6

Watts
W/C

TJ, Tstg
EAS

55 to 175

205

mJ

RJC
RJA

1.67
62.5

C/W

TL

260

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 32 Apk, L = 0.1 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4872

Motorola TMOS Power MOSFET Transistor Device Data

MTP36N06V
ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

61

Vdc
mV/C

10
100

100

nAdc

2.0

2.6
6.0

4.0

Vdc
mV/C

0.034

0.04

Ohm

1.25

1.54
1.47

gFS

5.0

7.83

mhos

Ciss

1220

1700

pF

Coss

337

470

Crss

74.8

150

td(on)

14

30

tr

138

270

td(off)

54

100

tf

91

180

QT

39

50

Q1

7.0

Q2

17

Q3

13

1.03
0.94

2.0

trr

92

ta

64

tb

28

QRR

0.332

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150 C)

VDS(on)

Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 48 Vdc, ID = 32 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 32 Adc, VGS = 0 Vdc)


(IS = 32 Adc, VGS = 0 Vdc, TJ = 150 C)

Reverse Recovery Time


((IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4873

MTP36N06V
TYPICAL ELECTRICAL CHARACTERISTICS
72

TJ = 100C

VDS 10 V
7V

9V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

72

VGS = 10 V

TJ = 25C
54
8V

6V
36

5V

18

25C

54

36

18
55C

4V
0

0.1

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

25C

0.04

TJ = 25C

0.044

0.06

VGS = 10 V

0.036

55C
0.02
0
0

0.052

0.08

18

36
54
ID, DRAIN CURRENT (AMPS)

72

0.028

15 V

Figure 3. OnResistance versus Drain Current


and Temperature

18

36
54
ID, DRAIN CURRENT (AMPS)

72

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8

1000
VGS = 0 V

VGS = 10 V
ID = 16 A

TJ = 125C
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.4
1.2
1

100
100C

10

25C

0.8
0.6
50

1
25

25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4874

175

10
20
40
50
30
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP36N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
4000

C, CAPACITANCE (pF)

VDS = 0 V
3000

VGS = 0 V

TJ = 25C

Ciss

2000
Ciss

Crss
1000

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4875

QT
25

10
VGS

20

Q2

Q1

15

6
4
Q3

2
0

10

TJ = 25C
ID = 32 A

VDS
0

10

15

20

25

30

35

40

1000
TJ = 25C
ID = 32 A
VDD = 30 V
VGS = 10 V
t, TIME (ns)

30

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP36N06V

tr
tf

100

td(off)
td(on)

10

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


32

I S , SOURCE CURRENT (AMPS)

TJ = 25C
VGS = 0 V
24

16

0
0.5 0.55

0.6 0.65

0.7 0.75

0.8 0.85 0.9

0.95

1.05

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4876

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP36N06V
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

225

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
10 s

100 s

10

1 ms
10 ms
dc

1
0.1

175
150
125
100
75
50
25
0

100

10

ID = 32 A

200

25

50

75

100

125

175

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.10 0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4877

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
Power Field Effect Transistor
Designer's

MTP50P03HDL
Motorola Preferred Device

PChannel EnhancementMode Silicon Gate

TMOS POWER FET


LOGIC LEVEL
50 AMPERES
30 VOLTS
RDS(on) = 0.025 OHM

This advanced highcell density HDTMOS power FET is


designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S

CASE 221A06, Style 5


TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

30

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

30

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

50
31
150

Adc

Total Power Dissipation


Derate above 25C

PD

125
1.0

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 )

EAS

1250

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient, when mounted with the minimum recommended pad size

RJC
RJA

1.0
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4878

Motorola TMOS Power MOSFET Transistor Device Data

MTP50P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

30

26

10
100

100

1.0

1.5
4.0

2.0

0.020

0.025

0.83

1.5
1.3

15

20

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 3.0) (3)

Static DraintoSource OnResistance


(VGS = 5.0 Vdc, ID = 25 Adc)

(Cpk 3.0) (3)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 50 Adc)
(ID = 25 Adc, TJ = 125C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)

VGS(th)

Vdc

RDS(on)

mV/C
Ohm

VDS(on)

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)

Transfer Capacitance

Ciss

3500

4900

Coss

1550

2170

Crss

550

770

td(on)

22

30

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 15 Vdc, ID = 50 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
RG = 2.3 ))

Fall Time
Gate Charge
(S Figure
(See
Fi
8)

((VDS = 24 Vdc, ID = 50 Adc,


VGS = 5.0 Vdc)

tr

340

466

td(off)

90

117

tf

218

300

QT

74

100

Q1

13.6

Q2

44.8

Q3

35

2.39
1.84

3.0

trr

106

ta

58

tb

48

QRR

0.246

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

Reverse Recovery Time


(S Figure
(See
Fi
15)

(IS =50 Adc, VGS = 0 Vdc)


(IS = 50 Adc, VGS = 0 Vdc, TJ = 125C)

((IS = 50 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4879

MTP50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100

VGS = 10 V
8V

TJ = 25C

80

VDS 10 V

5V
4.5 V

6V
4V

60
3.5 V

40

3V

20

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

100

TJ = 55C
25C

100C

80

60

40

20

2.5 V
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.3

2.7

3.1

3.5

3.9

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 5.0 V
0.027
0.025

TJ = 100C

0.023
25C
0.021
0.019
55C

0.017
0

20

40

60

80

100

4.3

0.022
TJ = 25C

VGS = 5 V

0.021
0.020
0.019
0.018
0.017
10 V
0.016
0.015

20

40

60

80

100

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.35

1.25

1.9

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.029

0.015

0
1.5

2.0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1000
VGS = 5 V
ID = 25 A

VGS = 0 V

I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.15

1.05

TJ = 125C
100

0.95
100C
0.85
50

4880

10
25

25

50

75

100

125

150

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

30

Motorola TMOS Power MOSFET Transistor Device Data

MTP50P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

14000

VGS = 0 V

VDS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

12000
Ciss

10000
8000

6000 C
rss
Ciss

4000
2000

Crss

0
10

0
VGS

10

Coss

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4881

30
QT

5
Q1

25

VGS

Q2

20

15

10

ID = 50 A
TJ = 25C

5
Q3

10

VDS

20

30

40

50

60

1000

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP50P03HDL
ID = 50 A
TJ = 25C

tr
tf
td(off)

100

td(on)

0
80

70

VDD = 30 V
VGS = 10 V

10

10

QT, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

50
VGS = 0 V
TJ = 25C
40

30

20

10
0
0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4882

Motorola TMOS Power MOSFET Transistor Device Data

MTP50P03HDL
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance
General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
VGS = 20 V
SINGLE PULSE
TC = 25C
100
100 s
1 ms
10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

dc

1400
ID = 50 A

1200
1000
800
600
400
200
0

1.0

10

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4883

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

MTP50P03HDL
1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05

0.1

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4884

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP52N06V

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

52
41
182

Adc

Total Power Dissipation


Derate above 25C

PD

165
1.10

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 )

EAS

406

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.91
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4885

MTP52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
TBD

4.0

Vdc
mV/C

0.019

0.022

Ohm

1.4
1.2

gFS

17

25

mhos

Ciss

1700

2380

pF

Coss

500

700

Crss

150

300

td(on)

15

30

tr

130

260

td(off)

68

140

tf

70

140

QT

70

80

Q1

10

Q2

30

Q3

20

1.0
0.9

1.5

trr

90

ta

80

tb

10

QRR

0.3

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 26 Adc)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 52 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 52 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 52 Adc, VGS = 0 Vdc)


(IS = 52 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4886

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP52N06VL

TMOS V
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


52 AMPERES
60 VOLTS
RDS(on) = 0.025 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

VDSS
VDGR
VGS
VGSM

60

Vdc

60

Vdc

15
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

52
41
182

Adc

Total Power Dissipation


Derate above 25C

PD

165
1.10

Watts
W/C

TJ, Tstg
EAS

55 to 175

406

mJ

RJC
RJA

0.91
62.5

C/W

TL

260

Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
GatetoSource Voltage Nonrepetitive (tp 10 ms)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 52 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

4887

MTP52N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

1.0

1.5
TBD

2.0

Vdc
mV/C

0.022

0.025

Ohm

1.5
1.3

gFS

17

30

Mhos

Ciss

1600

2240

pF

Coss

550

770

Crss

170

340

td(on)

18

40

tr

370

740

td(off)

90

180

tf

170

340

QT

45

60

Q1

12

Q2

22

Q3

18

1.0
0.9

1.5

trr

93

ta

65

tb

28

QRR

0.3

3.5
4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = .25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 26 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 5 Vdc, ID = 52 Adc)
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 30 Vdc, ID = 52 Adc,


VGS = 5 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 48 Vdc, ID = 52 Adc,


VGS = 5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 52 Adc, VGS = 0 Vdc)


(IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C)

Reverse Recovery Time


((IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4888

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP55N06Z

TMOS E-FET.
Power Field Effect Transistor
NChannel EnhancementMode Silicon Gate

TMOS POWER FET


55 AMPERES
60 VOLTS
RDS(on) = 16 m

This advanced high voltage TMOS EFET is designed to


withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a draintosource diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Capability Specified at Elevated
Temperature
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Low Stored Gate Charge for Efficient Switching
Internal SourcetoDrain Diode Designed to Replace External
Zener Transient SuppressorAbsorbs High Energy in the
Avalanche Mode
ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

G
CASE 221A06, Style 5
TO220AB
S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Continuous @ TC = 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

55
35.5
165

Adc

Total Power Dissipation @ TC = 25C


Derate above 25C

PD

136
0.91

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 )

EAS

454

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.1
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4889

MTP55N06Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

53

Vdc
mV/C

10
100

5.0

Adc

2.0

3.0
6.0

4.0

Vdc
mV/C

14

16

0.825
0.74

1.2
1.0

gFS

12

15

mhos

Ciss

1390

1950

pF

Coss

520

730

Crss

119

238

td(on)

27

54

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Cpk 2.0)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk 2.0)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance


(Cpk 2.0)
(VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 30 Adc)
(ID = 15 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 4.0 Vdc, ID = 15 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 30 Adc,


VGS(on) = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

tr

157

314

td(off)

116

232

tf

126

252

QT

40

56

Q1

7.0

Q2

18

Q3

15

0.93
0.82

1.1

trr

57

ta

32

tb

25

QRR

0.11

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4890

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET.
Power Field Effect Transistor
Designer's

MTP60N06HD
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


60 AMPERES
60 VOLTS
RDS(on) = 0.014 OHM

This advanced highcell density HDTMOS power FET is


designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
CASE 221A06, Style 5
TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
30

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

60
42.3
180

Adc

Total Power Dissipation


Derate above 25C

PD

150
1.0

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 )

EAS

540

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.0
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4891

MTP60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

60

71

10
100

100

2.0

3.0
7.0

4.0

0.011

0.014

1.0
0.9

15

20

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current


(VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 3.0) (3)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 30 Adc)

(Cpk 3.0) (3)

DraintoSource OnVoltage (VGS = 10 Vdc)


(ID = 60 Adc)
(ID = 30 Adc, TJ = 125C)

VGS(th)

Vdc

RDS(on)

Ohm

VDS(on)

Forward Transconductance
(VDS = 5.0 Vdc, ID = 30 Adc)

mV/C

Vdc

gFS

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)

Transfer Capacitance

Ciss

1950

2800

Coss

660

924

Crss

147

300

td(on)

14

26

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 60 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 ))

Fall Time
Gate Charge
(S Fi
(See
Figure 8)

((VDS = 48 Vdc, ID = 60 Adc,


VGS = 10 Vdc)

tr

197

394

td(off)

50

102

tf

124

246

QT

51

71

Q1

12

Q2

24

Q3

21

0.99
0.89

1.2

trr

60

ta

36

tb

24

QRR

0.143

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

Reverse Recovery Time


(S Fi
(See
Figure 15)

(IS = 60 Adc, VGS = 0 Vdc)


(IS = 60 Adc, VGS = 0 Vdc, TJ = 125C)

((IS = 60 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4892

Motorola TMOS Power MOSFET Transistor Device Data

MTP60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120

120

I D , DRAIN CURRENT (AMPS)

9V
80

TJ = 25C

60

6V

40
5V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

100C

25C
TJ = 55C

2.8

3.6

4.4

5.2

6.0

6.8

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C
0.016
0.014
25C

0.012
0.010

55C

0.008
20

30

40

50

60

70

80

90

100 110 120

7.6

0.0132
TJ = 25C
0.0128
0.0124
0.0120
VGS = 10 V

0.0116
0.0112
0.0108

15 V

0.0104
0.0100

10

20

30

40

50

60

70

80

90

100 110 120

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

1.8
1.6

VGS = 0 V

VGS = 10 V
ID = 30 A

TJ = 125C
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

40

VGS, GATETOSOURCE VOLTAGE (Volts)

0.018

10

60

0
2.0

5.0

VGS = 10 V

80

VDS, DRAINTOSOURCE VOLTAGE (Volts)

0.020

0.006

100

20

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

100

20

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

7V

8V

VGS = 10 V

1.4
1.2
1.0

100
100C
25C
10

0.8
0.6
50

1
25

25

50

75

100

125

150

10

20

30

40

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (Volts)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

60

4893

MTP60N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

5000

VDS = 0 V

VGS = 0 V
TJ = 25C

Ciss
C, CAPACITANCE (pF)

4000

3000
Crss

Ciss

2000
Coss
1000
Crss
0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4894

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

10

50
VGS

40
Q1

Q2

30

20

ID = 60 A
TJ = 25C

10

2
Q3
0

VDS
16

24

32

40

48

0
56

1000
VDD = 30 V
ID = 60 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP60N06HD

tr
tf

100

td(off)

td(on)
10

10

QT, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

60
50

VGS = 0 V
TJ = 25C

40
30
20
10
0
0.5

0.6

0.7

0.8

0.9

1.0

VSD, SOURCETODRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4895

MTP60N06HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance
General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
VGS = 20 V
SINGLE PULSE
TC = 25C
10 s

100

100 s
10

1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

4896

1.0

10 ms
dc
10

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

600
ID = 60 A
500
400
300
200
100
0

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

MTP60N06HD
1.0
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4897

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advanced Information

MTP75N03HDL

HDTMOS E-FET
High Density Power FET

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


LOGIC LEVEL
75 AMPERES
RDS(on) = 9.0 mOHM
25 VOLTS

This advanced highcell density HDTMOS EFET is designed to


withstand high energy in the avalanche and commutation modes.
This new energy efficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, and inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

Ultra Low RDS(on), HighCell Density, HDTMOS


SPICE Parameters Available
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

25

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

25

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse (tp 10 ms)

VGS

15
20

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

75
59
225

Adc

Total Power Dissipation


Derate above 25C

PD

150
1.0

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 )

EAS

280

mJ

Thermal Resistance Junction to Case


Junction to Ambient

RJC
RJA

1.0
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4898

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

25

Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(Cpk 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mA)
Temperature Coefficient (Positive)

V(BR)DSS

Vdc
mV/C

Zero Gate Voltage Drain Current


(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V)

IGSS

Adc

100
500

100

1.0

1.5

2.0

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk 3.0) (3)
(VDS = VGS, ID = 0.25 mA)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance


(Cpk 2.0) (3)
(VGS = 5.0 Vdc, ID = 37.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125C)

VDS(on)

Vdc
mV/C
m

Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc)

6.0

9.0

0.68
0.6

gFS

15

55

mhos

Ciss

4025

5635

pF

Coss

1353

1894

Crss

307

430

td(on)

24

48

tr

493

986

td(off)

60

120

tf

149

300

QT

61

122

Q1

14

28

Q2

33

66

Q3

27

54

0.97
0.87

1.1

trr

58

ta

27

tb

30

QRR

0.088

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 15 Vdc, ID = 75 Adc,


VGS = 5.0
5 0 Vdc,
Vdc
Rg = 4.7 )

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 75 Adc, VGS = 0 Vdc)


(IS = 75 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 75 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4899

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V

5V

I D , DRAIN CURRENT (AMPS)

8V
120

150

4.5 V TJ = 25C
I D , DRAIN CURRENT (AMPS)

150

4V

6V

90
3.5 V
60
3V

30

VDS 10 V

120

90

60
100C

TJ = 55C

2.5 V
0

0.2

0.4 0.6 0.8


1
1.2
1.4 1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.8

0
1.5

TJ = 100C

25C

55C
0.004

0.002

30

60

90

120

150

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS = 5 V

0.006

2
2.5
3
3.5
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

4.5

Figure 2. Transfer Characteristics

0.01

0.009
TJ = 25C
0.008

0.007

VGS = 5 V

0.006
10 V
0.005

0.004

ID, DRAIN CURRENT (AMPS)

50
100
75
ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

25

10000

1.6

1.2

0.8

125

150

TJ = 125C

VGS = 10 V
ID = 37.5 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.008

25C

30

100C

1000

100

10

0.4

25C
VGS = 0 V

50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

4900

150

5
10
15
20
25
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

30

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

15000

C, CAPACITANCE (pF)

12000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

9000
Crss
Ciss

6000

Coss

3000
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4901

28

24
QT
20

5
Q2

Q1

VGS
16
12

3
TJ = 25C
ID = 75 A

4
VDS

Q3

0
0

10

50
20
30
40
QT, TOTAL GATE CHARGE (nC)

60

0
70

10000

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP75N03HDL

tr

1000

TJ = 25C
ID = 75 A
VDD = 15 V
VGS = 5 V

tf
td(off)
td(on)

100

10
1

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

75
TJ = 25C
VGS = 0 V

60

45

30

15

0
0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

4902

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N03HDL
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

280

1000

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100
100 s
1 ms
10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

dc

10

100

ID = 75 A

240
200
160
120
80
40
0
25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

4903

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05
1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4904

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET
Power Field Effect Transistor
Designer's

MTP75N05HD
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


75 AMPERES
RDS(on) = 9.5 m
50 VOLTS

This advanced highcell density HDTMOS EFET is designed to


withstand high energy in the avalanche and commutation modes.
This new energyefficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

Ultra Low RDS(on), HighCell Density, HDTMOS


SPICE Parameters Available
Diode is Characterized for Use in Bridge Circuits
Diode Exhibits High Speed, Yet Soft Recovery
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified

G
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

50

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

50

Vdc

GateSource Voltage Continuous

VGS

20

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

75
65
225

Adc

Total Power Dissipation


Derate above 25C

PD

150
1

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vpk, IL = 75 Apk, L = 0.177 mH, RG = 25 )

EAS

500

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.00
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

4905

MTP75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

50

54.9

Vdc
mV/C

10
100

100

nAdc

2.0

6.3

4.0

Vdc
mV/C

7.0

9.5

0.86
0.64

gFS

15

mhos

Ciss

2600

2900

pF

Coss

1000

1100

Crss

230

275

td(on)

15

30

tr

170

340

td(off)

70

140

tf

100

200

QT

71

100

Q1

13

Q2

33

Q3

26

0.97
0.88

1.1

trr

57

ta

40

tb

17

QRR

0.17

3.5
4.5

7.5

OFF CHARACTERISTICS
(Cpk 2.0)(3)

DrainSource Breakdown Voltage


(VGS = 0 V, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 50 Vdc, VGS = 0)
(VDS = 50 Vdc, VGS = 0, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

(Cpk 1.5)(3)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 37.5 Adc)

(Cpk 3.0)(3)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 150C)

VGS(th)

RDS(on)

mW

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance

(VDS = 25 Vdc, VGS = 0,


f = 1.0 MHz)
(Cpk 2.0)
2 0)(2)

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 25 Vdc, ID = 75 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 40 Vdc, ID = 75 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 75 Adc, VGS = 0)


(IS = 75 Adc, VGS = 0, TJ = 150C)
(Cpk 10)(2)

Reverse Recovery Time


((IS = 37.5 Adc, VGS = 0,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4906

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS(1)
160

160
TJ = 25C

120
100
80

6V

60
40
5V

20
0

0.5

1.5

2.5

3.5

60
TJ = 55C

100C

40

25C
0

140

160

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.012
TJ = 100C
0.01
25C

0.008
0.006

55C

0.004

20

40

60

80

100

120

140

0.009
TJ = 25C
0.008

VGS = 10 V

0.007
15 V
0.006

0.005

20

40

60

80

100

120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 37.5 A
1.5

I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

80

4.5

VGS = 10 V

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.014

0.002

120

20

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

140
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

140

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

7V

VGS = 10 V

1000

TJ = 125C

100

100C

10

0.5

25C
0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

150

15
10
20
25 30
35 40
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

45

50

Figure 6. DrainToSource Leakage


Current versus Voltage

(1)Pulse Tests: Pulse Width 250 s, Duty Cycle 2%.

Motorola TMOS Power MOSFET Transistor Device Data

4907

MTP75N05HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with boardmounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

8000
VDS = 0

VGS = 0

TJ = 25C

C, CAPACITANCE (pF)

7000
6000

Ciss

5000
4000

Crss
Ciss

3000
2000

Coss
1000
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4908

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

10

50

VGS

40

Q2

Q1
6

30

20
VDS

TJ = 25C
ID = 75 A

2
0

Q3
25
50
QT, TOTAL GATE CHARGE (nC)

10
0
75

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP75N05HD
TJ = 25C
ID = 75 A
VDD = 35 V
VGS = 10 V

100

tr
tf
td(off)

td(on)
10

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
40

80

60

30
I S , SOURCE CURRENT (AMPS)

I S , SOURCE CURRENT (AMPS)

di/dt = 300 A/s

TJ = 25C
VGS = 0 V

70

50
40
30
20
10

STANDARD CELL DENSITY


trr
HIGH CELL DENSITY
trr
tb
ta

20
10
0
10
20
30

0
0

0.1

0.2 0.3
0.4 0.5
0.6 0.7 0.8
0.9
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

40
120 100 80

60 40 20
0
t, TIME (ns)

20

40

60

80

Figure 11. Reverse Recovery Time (trr)

4909

MTP75N05HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr,tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100

500

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
10 s

100 s

10

1 ms
10 ms
1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

dc

1
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

ID = 75 A
400

300
200

100

25

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

50

75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

D = 0.5

0.2
0.1
0.1
0.05
P(pk)

0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


RJC = 1.0C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 14. Thermal Response

4910

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
HDTMOS E-FET
High Density Power FET
Designer's

MTP75N06HD
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


75 AMPERES
RDS(on) = 10.0 mOHM
60 VOLTS

This advanced highcell density HDTMOS EFET is designed to


withstand high energy in the avalanche and commutation modes.
This new energy efficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, and inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

Ultra Low RDS(on), HighCell Density, HDTMOS


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
D

G
CASE 221A06, Style 5
TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse

VGS

20
30

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

75
50
225

Adc

Total Power Dissipation


Derate above 25C

PD

150
1.0

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 )

EAS

500

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

1.0
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4911

MTP75N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

68
60.4

10
100

5.0

100

2.0

3.0
8.38

4.0

8.3

10

0.7
0.53

0.9
0.8

gFS

15

32

mhos

pF

OFF CHARACTERISTICS
(Cpk 2.0) (3)

DrainSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

(Cpk 5.0) (3)

Static DrainSource OnResistance


(VGS = 10 Vdc, ID = 37.5 Adc)

(Cpk 2.0) (3)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125C)

VGS(th)

Vdc

RDS(on)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc)

mV/C

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance

Ciss

2800

3920

Coss

928

1300

Crss

180

252

td(on)

18

26

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 30 Vdc, ID = 75 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 75 Adc,
VGS = 10 Vdc)

tr

218

306

td(off)

67

94

tf

125

175

QT

71

100

Q1

16.3

Q2

31

Q3

29.4

0.97
0.88

1.1

trr

56

ta

44

tb

12

QRR

0.103

3.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 75 Adc, VGS = 0 Vdc)


(IS = 75 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 75 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4912

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
150

I D , DRAIN CURRENT (AMPS)

7V

100
75
6V
50
25
0

VDS 10 V

125
100

5V

75
50

25C

100C
25

TJ = 55C
0

0.5

1.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 25C
VGS = 10 V

0.014

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.016

TJ = 100C

0.012
0.010
25C
0.008
55C

0.006
0.004
0

50

25

100

75

125

150

0.012

TJ = 25C

0.011
0.010
VGS = 10 V
0.009
15 V

0.008
0.007
0.006
0

25

50

75

100

125

150

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

1.9

VGS = 0 V

VGS = 10 V
ID = 37.5 A

TJ = 125C

1.6
I DSS, LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

9V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

125

150

8V

VGS = 10 V

TJ = 25C

1.3

100
100C

10
25C

0.7
50

25

25

50

75

100

125

150

10

20

30

40

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

60

4913

MTP75N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

7000

VDS = 0 V

VGS = 0 V

TJ = 25C

6000
C, CAPACITANCE (pF)

Ciss
5000
4000
3000

Ciss
Crss

2000
Coss
1000
Crss
0
10

5
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4914

Motorola TMOS Power MOSFET Transistor Device Data

60
QT

10

50
VGS

Q1

40

Q2

30

20

ID = 75 A
TJ = 25C

10

2
Q3
0

10

VDS
20

30

40

50

60

70

0
80

1000
VDS = 30 V
ID = 75 A
VGS = 10 V
TJ = 25C
tr
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP75N06HD

tf

100

td(off)

td(on)
10

10

QT, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

75
VGS = 0 V
TJ = 25C
50

25

0
0.5

0.58

0.66

0.74

0.82

0.9

0.98

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4915

MTP75N06HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal Resistance General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

I D , DRAIN CURRENT (AMPS)

VGS = 20 V
SINGLE PULSE
TC = 25C
10 s
100
100 s
10

1 ms
10 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

4916

1.0

dc

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

500

1000

1
0.1

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

ID = 75 A
375

250

125

0
10

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTP75N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

TYPICAL ELECTRICAL CHARACTERISTICS


1.0
D = 0.5

0.2
0.1
0.1

P(pk)

0.05
0.02

t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4917

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTP2955V

TMOS V
Power Field Effect Transistor

PChannel EnhancementMode Silicon Gate


TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.200 OHM

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET

S
CASE 221A06, Style 5
TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

60

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

15
25

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
8.0
42

Adc

Total Power Dissipation


Derate above 25C

PD

60
0.40

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 )

EAS

216

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

2.5
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4918

Motorola TMOS Power MOSFET Transistor Device Data

MTP2955V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

TBD

Vdc
mV/C

10
100

100

nAdc

2.0

2.8
TBD

4.0

Vdc
mV/C

0.185

0.200

Ohm

2.9
2.8

gFS

3.0

5.0

mhos

Ciss

500

700

pF

Coss

200

280

Crss

40

80

td(on)

11

20

tr

38

80

td(off)

18

40

tf

26

50

QT

15

20

Q1

4.0

Q2

7.0

Q3

6.0

1.8
TBD

3.0

trr

114

ta

86

tb

28

QRR

0.553

4.5

7.5

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 12 Adc)
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4919

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTP3055V

Designer's

TMOS
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.15 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors
Features Common to TMOS V and TMOS EFETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
7.3
37

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

48
0.32

Watts
W/C

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 )

EAS

72

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

3.13
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4920

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

65

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
5.4

4.0

Vdc
mV/C

0.10

0.15

Ohm

1.3

2.2
1.9

gFS

4.0

5.0

mhos

Ciss

410

500

pF

Coss

130

180

Crss

25

50

td(on)

7.0

10

tr

34

60

td(off)

17

30

tf

18

50

QT

12.2

17

Q1

3.2

Q2

5.2

Q3

5.5

1.0
0.91

1.6

trr

56

ta

40

tb

16

QRR

0.128

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 15)
((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4921

MTP3055V
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
9V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

20

24

8V
I D , DRAIN CURRENT (AMPS)

24

7V
16
12

6V

8
5V

VDS 10 V

TJ = 55C

20

25C
100C

16
12
8
4

4
4V
0

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.25
0.20
TJ = 100C
0.15
25C
0.10
55C
0.05

12
8
16
ID, DRAIN CURRENT (AMPS)

20

24

10

0.15
TJ = 25C
0.14
0.13
0.12
VGS = 10 V
0.11
0.10
15 V
0.09
0.08

Figure 3. OnResistance versus Drain Current


and Temperature

12
16
8
ID, DRAIN CURRENT (AMPS)

20

24

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.6

100
VGS = 0 V

VGS = 10 V
ID = 6 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.4

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.30

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.2

1.0

10

TJ = 125C

0.8

0.6
50

25

0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

4922

175

10
30
40
20
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

60

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1200

VDS = 0 V

C, CAPACITANCE (pF)

1000

VGS = 0 V

TJ = 25C

Ciss

800
600
Crss

Ciss

400
Coss

200

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4923

60
QT

10

50
Q1

VGS

Q2

40

30

20

ID = 12 A
10
TJ = 25C

Q3
0

VDS
5

10

11

12

0
13

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP3055V
VDD = 30 V
ID = 12 A
VGS = 10 V
TJ = 25C

100
tr
td(off)
tf

10

td(on)

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


12
dIS/dt = 100 A/s
VDD = 25 V
TJ = 25C

0.12

10
I S , SOURCE CURRENT (AMPS)

QRR , STORED CHARGE (C)

0.13

0.11

0.10

0.09

0.08

10

12

VGS = 0 V
TJ = 25C

8
6
4
2
0
0.50 0.55 0.60

IS, SOURCE CURRENT (AMPS)

0.65 0.70 0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Stored Charge

Figure 11. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4924

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055V
SAFE OPERATING AREA
75

VGS = 20 V
SINGLE PULSE
TC = 25C

10 s

10
100 s
1 ms
1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

50

25

0
10

1.0

ID = 12 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100

25

50

75

100

125

175

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2

0.1

0.1
0.05

P(pk)

0.02
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4925

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
V

MTP3055VL

Designer's

TMOS
Power Field Effect Transistor

Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


12 AMPERES
60 VOLTS
RDS(on) = 0.18 OHM

TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

TM

New Features of TMOS V


Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS


Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS EFET

CASE 221A06, Style 5


TO220AB
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage Continuous


GateSource Voltage Single Pulse (tp 50 s)

VGS
VGSM

15
20

Vdc
Vpk

Drain Current Continuous @ 25C


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

12
8.0
42

Adc

Total Power Dissipation @ 25C


Derate above 25C

PD

48
0.32

Watts
W/C

Apk

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG =25 )

EAS

72

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

3.13
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

4926

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

62

Vdc
mV/C

10
100

100

nAdc

1.0

1.6
3.0

2.0

Vdc
mV/C

0.12

0.18

Ohm

1.6

2.6
2.5

gFS

5.0

8.8

mhos

Ciss

410

570

pF

Coss

114

160

Crss

21

40

td(on)

9.0

20

tr

85

190

td(off)

14

30

tf

43

90

QT

8.1

10

Q1

1.8

Q2

4.2

Q3

3.8

0.97
0.86

1.3

trr

55.7

ta

37

tb

18.7

QRR

0.116

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 15 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 5.0 Vdc)


(ID = 12 Adc)
(ID = 6.0 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 30 Vdc, ID = 12 Adc,


VGS = 5
5.0
0 Vdc,
Vdc
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc,
VGS = 5.0 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 12 Adc, VGS = 0 Vdc)


(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

4927

MTP3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
24

16

I D , DRAIN CURRENT (AMPS)

4.5 V
4V

12
3.5 V
8
3V

20

100C

16
12
8

0
2.0

3.5

4.0

4.5

5.5

5.0

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.20

TJ = 100C

0.14

25C
55C

0.08

20

8
12
16
ID, DRAIN CURRENT (AMPS)

24

TJ = 25C
0.22

0.17
5V
0.12

0.07

VGS = 10 V

100

I DSS , LEAKAGE (nA)

1.5

25

25

50

75

100

125

150

175

8
12
16
ID, DRAIN CURRENT (AMPS)

20

24

VGS = 0 V

VGS = 5 V
ID = 6 A

0.5

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1.0

6.0

0.27

Figure 3. OnResistance versus Drain Current


and Temperature

4928

3.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 5 V

0
50

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.26

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

TJ = 55C
25C

0.32

0.02

VDS 10 V

2.5 V

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

24

5V

VGS = 10 V

TJ = 25C

TJ = 125C

10

100C

1.0

0.1

TJ, JUNCTION TEMPERATURE (C)

30
10
20
40
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

60

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1400
1200
C, CAPACITANCE (pF)

VGS = 0 V

VDS = 0 V

TJ = 25C

Ciss

1000
800
600

Ciss

Crss
400

Coss

200

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4929

60
QT
50

40
VGS
30
Q2

Q1
2

20

ID = 12 A
TJ = 25C
0

Q3
2

VDS
4

10
0
10

1000
VDD = 30 V
ID = 12 A
VGS = 5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP3055VL

tr
tf

100

td(off)
10

td(on)

1
1

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


12

I S , SOURCE CURRENT (AMPS)

10

VGS = 0 V
TJ = 25C

8
6
4
2
0
0.50 0.55 0.60 0.65 0.70

0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

4930

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

MTP3055VL
SAFE OPERATING AREA
75
VGS = 5 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s

10
100 s
1 ms
10 ms

1.0

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

ID = 12 A

50

25

0.1

0
0.1

1.0

25

100

10

50

75

100

125

175

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2

0.1

0.1
0.05
P(pk)

0.02
0.01
SINGLE PULSE

0.01
1.0E05

t1

t2
DUTY CYCLE, D = t1/t2
1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4931

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTSF1P02HD

Medium Power Surface Mount Products

TMOS Single P-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
Miniature Micro8 Surface Mount Package Saves Board Space
G
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) *

SINGLE TMOS
POWER FET
1.8 AMPERES
20 VOLTS
RDS(on) = 0.16 OHM

D
CASE 846A02, Style 1
Micro8

Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

1.8
1.6
14.4

Adc

1.8
14.3

Watts
mW/C

PD

0.78
6.25

Watts
mW/C

TJ, Tstg

55 to 150

Symbol

Typ.

Max.

Unit

RJA
RJA

55
125

70
160

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (2)
Drain Current Continuous @ TA = 70C (2)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating
Thermal Resistance Junction to Ambient, PCB Mount (1)
Thermal Resistance Junction to Ambient, PCB Mount (2)

* Negative signs for PChannel device omitted for clarity.


(1) When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
AB

ORDERING INFORMATION
Device
MTSF1P02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4932

Motorola TMOS Power MOSFET Transistor Device Data

MTSF1P02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

20

12.8

1.0
10

100

0.6

0.8
2.5

120
160

160
190

gFS

2.0

4.0

Mhos

Ciss

440

pF

Coss

300

Crss

150

td(on)

15

tr

35

td(off)

55

tf

75

td(on)

20

tr

93

td(off)

50

tf

75

QT

11

22

Q1

0.7

Q2

5.5

Q3

3.8

1.24
0.9

2.0

trr

120

ta

33

tb

87

QRR

0.223

OFF CHARACTERISTICS
(Cpk 2.0)

DrainSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

(3)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 1.8 Adc)
(VGS = 2.7 Vdc, ID = 0.9 Adc)

(3)

Forward Transconductance (VDS = 10 Vdc, ID = 0.9 Adc)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 10 Vdc, ID = 1.8 Adc,


VGS = 4.5 Vdc, RG = 6.0 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

( DD = 10 Vdc, ID = 0.9 Adc,


(V
VGS = 2.7 Vdc, RG = 6.0 ) (1)

Fall Time
Gate Charge
((VDS = 10 Vdc, ID = 1.8 Adc,
VGS = 4.5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 1.8 Adc, VGS = 0 Vdc) (1)


(IS = 1.8 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 1.8 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s) (1)
Reverse Recovery Stored Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4933

MTSF1P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 4.5 V
2.7 V
2V

1.6

1.8 V
TJ = 25C

1.6

1.7 V

1.9 V

VDS 10 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

1.2

1.2

1.6 V
0.8

TJ = 100C

0.8

1.5 V
0.4

25C

0.4
55C

1.4 V
0

1.2
0.4
0.8
1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
0.4

ID = 1.8 A
TJ = 25C

0.4
0.3
0.2
0.1
0
0

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.6
0.5

Figure 2. Transfer Characteristics

0.18
TJ = 25C
2.7 V
0.16

0.14

4.5 V

0.12

0.1
0

0.5

1.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GateToSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.0

1000

VGS = 0 V

VGS = 2.7 V
ID = 1.8 A

TJ = 125C

1.5
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.8
1.2
1.6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.0

0.5

0
50

4934

25

25

50

75

100

125

150

100

100C

10

25C

12

16

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

20

Motorola TMOS Power MOSFET Transistor Device Data

MTSF1P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2000

C, CAPACITANCE (pF)

Ciss

VDS = 0 V

TJ = 25C

VGS = 0 V

1500

1000

Crss
Ciss

500

Coss
Crss
0
10

0
VGS

10

15

20

VDS

VDS, DRAINTOSOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

4935

18
QT

5
4

15
12

VGS

VDS

9
Q1

Q2

2
1
0

Q3

ID = 1.8 A
TJ = 25C
3

0
12

1000
VDD = 10 V
ID = 1.8 A
VGS = 4.5 V
TJ = 25C
t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTSF1P02HD

100

tf
td(off)
tr
td(on)

10
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

The switching characteristics of a MOSFET body diode


are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

I S , SOURCE CURRENT (AMPS)

1.6

VGS = 0 V
TJ = 25C

1.2

0.8

0.4

0
0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

4936

Motorola TMOS Power MOSFET Transistor Device Data

MTSF1P02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance
General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

10

360
VGS = 8 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

1 ms
10 ms

1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

280
240
200
160
120
80
40
0

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Motorola TMOS Power MOSFET Transistor Device Data

VDD = 16 V
VGS = 5 V
IL = 6 A
L = 20 mH

320

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

4937

MTSF1P02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

1000

100

10

D = 0.5
0.2
0.1
0.05
P(pk)

0.02
0.01
1

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.1
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+01

1.0E+02

1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4938

Motorola TMOS Power MOSFET Transistor Device Data

MTSF1P02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

1.85 (.072)
1.65 (.065)

0.35 (.013)
0.25 (.010)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

Motorola TMOS Power MOSFET Transistor Device Data

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

4939

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

MTSF2P02HD

Medium Power Surface Mount Products

TMOS Single P-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
Miniature Micro8 Surface Mount Package Saves Board Space G
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) *

SINGLE TMOS
POWER FET
2.4 AMPERES
20 VOLTS
RDS(on) = 0.090 OHM

D
CASE 846A02, Style 1
Micro8

Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

2.4
2.2
19

Adc

1.8
14.3

Watts
mW/C

PD

0.78
6.25

Watts
mW/C

TJ, Tstg

55 to 150

Typ.

Max.

Unit

55
125

70
160

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (1)
Drain Current Continuous @ TA = 70C (1)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating

Symbol

Thermal Resistance Junction to Ambient, PCB Mount (1)


RJA
RJA
Thermal Resistance Junction to Ambient, PCB Mount (2)
* Negative signs for PChannel device omitted for clarity.
(1) When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
AD

ORDERING INFORMATION
Device
MTSF2P02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

4940

Motorola TMOS Power MOSFET Transistor Device Data

MTSF2P02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)(1)
Symbol

Characteristic

Min

Typ

Max

Unit

20

TBD

TBD
TBD

2.0
25

TBD

100

0.7

TBD
TBD

TBD
TBD

90
130

gFS

2.6

TBD

Mhos

Ciss

TBD

pF

Coss

TBD

Crss

TBD

td(on)

TBD

tr

TBD

td(off)

TBD

tf

TBD

td(on)

TBD

tr

TBD

td(off)

TBD

tf

TBD

QT

TBD

TBD

Q1

TBD

Q2

TBD

Q3

TBD

TBD
TBD

1.0

trr

TBD

ta

TBD

tb

TBD

QRR

TBD

OFF CHARACTERISTICS
(Cpk 2.0)

DrainSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 2.4 Adc)
(VGS = 2.7 Vdc, ID = 1.2 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 10 Vdc, ID = 1.2 Adc)

(3)

(3)

(1)

VGS(th)

Vdc

RDS(on)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 15 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 10 Vdc, ID = 2.4 Adc,


VGS = 4.5 Vdc, RG = 6.0 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

( DD = 10 Vdc, ID = 1.2 Adc,


(V
VGS = 2.7 Vdc, RG = 6.0 ) (1)

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 2.4 Adc,
VGS = 4.5 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 2.4 Adc, VGS = 0 Vdc) (1)


(IS = 2.4 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 2.4 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s) (1)
Reverse Recovery Stored Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

4941

MTSF2P02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

0.35 (.013)
0.25 (.010)

1.85 (.072)
1.65 (.065)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

4942

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTSF3N02HD

Medium Power Surface Mount Products

TMOS Single N-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
Miniature Micro8 Surface Mount Package Saves Board Space
Extremely Low Profile (<1.1mm) for thin applications such as
G
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

SINGLE TMOS
POWER MOSFET
3.8 AMPERES
20 VOLTS
RDS(on) = 0.040 OHM

D
CASE 846A02, Style 1
Micro8

Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

20

Vdc

20

Vdc

VGS
ID
ID
IDM
PD

8.0

Vdc

3.8
3.5
30

Adc

1.8
14.3

Watts
mW/C

PD

0.78
6.25

Watts
mW/C

TJ, Tstg

55 to 150

Typ.

Max.

Unit

55
125

70
160

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (2)
Drain Current Continuous @ TA = 70C (2)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating

Symbol

Thermal Resistance Junction to Ambient, PCB Mount (1)


RJA
RJA
Thermal Resistance Junction to Ambient, PCB Mount (2)
(1) When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
AC

ORDERING INFORMATION
Device
MTSF3N02HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4943

MTSF3N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

20

16

1.0
25

100

0.7

0.78
2.65

30
40

40
50

gFS

4.0

7.5

Mhos

Ciss

475

pF

Coss

255

Crss

110

td(on)

9.5

tr

45

td(off)

50

tf

62

td(on)

19

tr

130

td(off)

38

tf

47

QT

12

17

Q1

1.0

Q2

5.0

Q3

3.5

0.83
0.68

1.0

trr

46

ta

23

tb

23

QRR

0.05

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 4.5 Vdc, ID = 3.8 Adc)
(VGS = 2.7 Vdc, ID = 1.9 Adc)

(Cpk 2.0)

Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc)

(3)

VGS(th)

(3)

Vdc

RDS(on)

(1)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 15 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 10 Vdc, ID = 3.8 Adc,


VGS = 4.5 Vdc, RG = 6 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 10 Vdc, ID = 1.9 Adc,


VGS = 2.7 Vdc, RG = 6 ) (1)

Fall Time
Gate Charge
((VDS = 16 Vdc, ID = 3.8 Adc,
VGS = 4.5 Vdc)

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 3.8 Adc, VGS = 0 Vdc) (1)


(IS = 3.8 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(IS = 3
3.8
8 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4944

Motorola TMOS Power MOSFET Transistor Device Data

MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
8

I D , DRAIN CURRENT (AMPS)

1.7 V

4
3

1.5 V

6
5
4
3

25C
1

0.4

0.8

1.6

1.2

TJ = 55C

1
0

VDS 10 V

1.9 V

100C
1

1.6

1.8

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 3.8 V
TJ = 25C
0.05

0.04

0.03

0.02

0.01
0

6
2
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.06
TJ = 25C
0.05
VGS = 2.7 V

0.04

4.5 V
0.03

0.02

0.01

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

2.0
VGS = 4.5 V
ID = 1.9 A

VGS = 0 V

1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.06

1.0

0.5

0
50

1.2

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 25C

VGS = 10 V
4.5 V
2.9 V
2.5 V
2.3 V
2.1 V

100
100C
10

0.1
25

25

50

75

100

125

150

TJ = 125C

25C

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4945

MTSF3N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2500

TJ = 25C
VGS = 0 V

Ciss

C, CAPACITANCE (pF)

2000
Crss
1500

1000
Ciss
Coss

500
0

0
VGS

Crss
4

12

16

20

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4946

Motorola TMOS Power MOSFET Transistor Device Data

18
QT

VGS

VDS

4
3

Q1

15
12
9

Q2

2
1
0

ID = 3.8 A
TJ = 25C

Q3
3

6
9
Qg, TOTAL GATE CHARGE (nC)

0
15

12

1000

VDD = 10 V
ID = 3.8 A
VGS = 4.5 V
TJ = 25C

100
t, TIME (ns)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTSF3N02HD

tr

tf
td(off)
td(on)

10

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
3

0
0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4947

MTSF3N02HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased.
Curves are based upon maximum peak junction temperature
and a case temperature (TC) of 25C. Peak repetitive pulsed
power limits are determined by using the thermal response data
in conjunction with the procedures discussed in AN569, Tran-

I D , DRAIN CURRENT (AMPS)

100

10

VGS = 8 V
SINGLE PULSE
TC = 25C

sient Thermal Resistance General Data and Its Use.


Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the
transition time (t r, t f ) does not exceed 10 s. In addition
the total power averaged over a complete switching cycle
must not exceed (T J(MAX) T C )/(RJC ).

100 s
1 ms
10 ms

1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4948

Motorola TMOS Power MOSFET Transistor Device Data

MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

1000

100

10

D = 0.5
0.2
0.1
0.05
P(pk)

0.02
0.01
1

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.1
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+01

1.0E+02

1.0E+03

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4949

MTSF3N02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

1.85 (.072)
1.65 (.065)

0.35 (.013)
0.25 (.010)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

4950

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTSF3N03HD

Medium Power Surface Mount Products

TMOS Single N-Channel


Field Effect Transistor

Motorola Preferred Device

Micro8 devices are an advanced series of power MOSFETs


which utilize Motorolas High Cell Density HDTMOS process to
achieve lowest possible onresistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dcdc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
Miniature Micro8 Surface Mount Package Saves Board Space
Extremely Low Profile (<1.1mm) for thin applications such as
G
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

SINGLE TMOS
POWER MOSFET
3.7 AMPERES
30 VOLTS
RDS(on) = 0.040 OHM

D
CASE 846A02, Style 1
Micro8

Source

Drain

Source

Drain

Source

Drain

Gate

Drain

Top View

Rating

Symbol

Value

Unit

VDSS
VDGR

30

Vdc

30

Vdc

VGS
ID
ID
IDM
PD

20

Vdc

3.7
3.2
30

Adc

1.8
14.3

Watts
mW/C

PD

0.78
6.25

Watts
mW/C

TJ, Tstg

55 to 150

Symbol

Typ.

Max.

Unit

RJA
RJA

55
125

70
160

C/W

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25C (2)
Drain Current Continuous @ TA = 70C (2)
Drain Current Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range

Apk

THERMAL RESISTANCE
Rating
Thermal Resistance Junction to Ambient, PCB Mount (1)
Thermal Resistance Junction to Ambient, PCB Mount (2)

(1) When mounted on 1 inch square FR4 or G10 board (VGS = 10 V, @ Steady State)
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.

DEVICE MARKING
AA

ORDERING INFORMATION
Device
MTSF3N03HDR2

Reel Size

Tape Width

Quantity

13

12 mm embossed tape

4000 units

This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

4951

MTSF3N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

30

27

1.0
25

100

1.0

1.5
4.5

35
45

40
60

gFS

2.0

Mhos

Ciss

420

pF

Coss

190

Crss

65

td(on)

7.0

tr

19

td(off)

32

tf

36

td(on)

7.0

tr

11

td(off)

29

tf

23

QT

18.5

26

Q1

1.4

Q2

5.5

Q3

7.1

0.82
0.7

1.0

trr

28

ta

14

tb

14

QRR

0.028

OFF CHARACTERISTICS
(Cpk 2.0)

DraintoSource Breakdown Voltage


(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

(1) (3)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 24 Vdc, VGS = 0 Vdc)
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

(Cpk 2.0)

Static DraintoSource OnResistance


(VGS = 10 Vdc, ID = 3.7 Adc)
(VGS = 4.5 Vdc, ID = 1.9 Adc)

(Cpk 2.0)

(3)

VGS(th)

(3)

Vdc

RDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc)

mV/C
m

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDS = 15 Vdc, ID = 3.7 Adc,


VGS = 10 Vdc, RG = 6 ) (1)

Fall Time
TurnOn Delay Time
Rise Time
TurnOff Delay Time

((VDD = 15 Vdc, ID = 1.9 Adc,


VGS = 4.5 Vdc, RG = 6 ) (1)

Fall Time
Gate Charge
((VDS = 24 Vdc, ID = 3.7 Adc,
VGS = 10 Vdc)

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 3.7 Adc, VGS = 0 Vdc) (1)


(IS = 3.7 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(IS = 3
3.7
7 Ad
Adc, VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (1)
Reverse Recovery Storage Charge

VSD

Vdc

ns

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

4952

Motorola TMOS Power MOSFET Transistor Device Data

MTSF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
4.5 V

6
TJ = 25C

VDS 10 V

2.9 V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

3.3 V
3.1 V

2.7 V
3
2

2.5 V

2.3 V

5
4
3
100C
2

25C
TJ = 55C

2.1 V
0

0.5

1.5

2.5

3.5

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

ID = 3.7 A
TJ = 25C

0.5
0.4
0.3
0.2
0.1
0
0

4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.06
TJ = 25C
0.055
VGS = 4.5

0.05
0.045
0.04

10 V
0.035
0.03
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus


GatetoSource Voltage

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1000

2.0

VGS = 0 V

VGS = 10 V
ID = 1.9 A

TJ = 125C

1.5

I DSS , LEAKAGE (nA)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.6

1.0

0.5

0
50

1.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100
100C
10
25C
1

0.1
25

25

50

75

100

125

150

10

15

20

30

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation


with Temperature

Figure 6. DraintoSource Leakage Current


versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

4953

MTSF3N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1500

C, CAPACITANCE (pF)

1200

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

900
Crss
600

Ciss
Coss

300
Crss
0
10

5
VGS

10

15

20

25

30

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4954

Motorola TMOS Power MOSFET Transistor Device Data

30
QT
25

10

20

8
VDS

VGS
15

10

4
Q1

Q2

2
0

Q3
3

ID = 3.7 A
TJ = 25C
12
15
6
9
Qg, TOTAL GATE CHARGE (nC)

1000

0
21

18

VDD = 15 V
ID = 3.7 A
VGS = 10 V
TJ = 25C

100
t, TIME (ns)

12

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTSF3N03HD

tf
td(off)
tr

10

td(on)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
3

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

4955

MTSF3N03HD
di/dt = 300 A/s

Standard Cell Density


trr

I S , SOURCE CURRENT

High Cell Density


trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance
General Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAIN-TO-SOURCE


AVALANCHE ENERGY (mJ)

250

100
I D , DRAIN CURRENT (AMPS)

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

100 s
1 ms
10 ms

1
dc
0.1

0.01
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

4956

200

150

100

50

0
100

VDD = 30 V
VGS = 5 V
IL = 9 A
L = 5 mH

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

MTSF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS

Rthja(t), EFFECTIVE TRANSIENT


THERMAL RESISTANCE

1000

100

10

D = 0.5
0.2
0.1
0.05
P(pk)

0.02
0.01
1

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.1
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01
t, TIME (s)

1.0E+00

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+01

1.0E+02

1.0E+03

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

4957

MTSF3N03HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)

2.05 (.080)
1.95 (.077)
PIN
NUMBER 1

4.10 (.161)
3.90 (.154)

1.85 (.072)
1.65 (.065)

0.35 (.013)
0.25 (.010)

5.55 (.218)
5.45 (.215)

12.30
11.70
(.484)
(.461)

3.50 (.137)
3.30 (.130)

1.60 (.063)
1.50 (.059)
TYP.

FEED DIRECTION

8.10 (.318)
7.90 (.312)

1.50 (.059)
1.30 (.052)

SECTION AA

5.40 (.212)
5.20 (.205)

SECTION BB
NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724)
MAX.
NOTE 3

13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.

NOTES:
1. CONFORMS TO EIA4811.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

4958

50.0
(1.97)
MIN.

14.4 (.57)
12.4 (.49)
NOTE 4

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
Designer's

MTV6N100E
TMOS POWER FET
6.0 AMPERES
1000 VOLTS
RDS(on) = 1.5 OHM

NChannel EnhancementMode Silicon Gate


The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltageblocking capability without degrading
performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drainto
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both acdc and dcdc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.

G
CASE 43301, Style 2
D3PAK Surface Mount

Robust High Voltage Termination


S
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13inch/500 Unit Tape & Reel, Add RL Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

Symbol

Value

Unit

1000

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDSS
VDGR

1000

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

6.0
4.2
18

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C (1)

PD

178
1.43
2.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

DraintoSource Voltage

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 6.0 Apk, L = 27.77 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

mJ
720

RJC
RJA
RJA

0.70
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4959

MTV6N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1270

10
100

100

2.0

3.0
7.0

4.0

mV/C

1.28

1.5

Ohm

7.9

14.4
9.5

gFS

4.0

7.2

mhos

Ciss

3000

4210

pF

Coss

219

440

Crss

43

90

td(on)

27

45

tr

29

65

td(off)

93

170

tf

43

95

QT

66

100

Q1

12.5

Q2

25.9

Q3

26

0.81
0.64

1.0

trr

735

ta

188

tb

547

QRR

4.7

4.5

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 3.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 500 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Fig
Figure
re 8)

((VDS = 400 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4960

Motorola TMOS Power MOSFET Transistor Device Data

MTV6N100E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12
VGS = 10 V

VDS 10 V

6V
5V

8
6
4

100C

8
6
25C
4
2

2
0

10

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C
10

TJ = 55C

4V
2

6
10
14
18
8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
4

0
2.0

20

2.4

2.9
TJ = 100C

2.5
2.1
1.7
25C
1.3
0.9
55C
0.5
0

4
6
8
ID, DRAIN CURRENT (AMPS)

10

4.0

4.4

4.8

5.2

12

TJ = 25C

1.52
1.48
1.44
1.40

VGS = 10 V

1.36

15 V

1.32
1.28
1.24
0

7
8
9
4
5
6
ID, DRAIN CURRENT (AMPS)

10

11

12

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.8

100000
VGS = 10 V
ID = 3 A

VGS = 0 V

TJ = 125C

10000
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.6

1.56

Figure 3. OnResistance versus Drain Current


and Temperature

2.4

3.2

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

VGS = 10 V

2.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

2.0

100C

1000

1.6
1.2

25C
10

0.8
0.4
50

100

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

100

200

300

400

500

600

700

800

900 1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

4961

MTV6N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

7000
Ciss

VGS = 0 V

10000

TJ = 25C

5000
4000
Crss

Ciss

3000
2000
1000
0

5
VGS

4962

TJ = 25C

1000

Coss
100
Crss

Coss

Crss
0
10

VGS = 0 V
Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

6000

VDS = 0 V

10

15

20

25

VDS

10

10

100

1000

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

400
ID = 6 A
TJ = 25C

14
12

350
300

QT

10

250
VGS

8
Q1

200

Q2

150

100

2
0

10

50

VDS

Q3
20

30

40

50

60

70

1000
VDD = 480 V
ID = 6 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV6N100E

100

tr
10

QG, TOTAL GATE CHARGE (nC)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

6
IS = 6 A
dlS/dt = 100 A/s
VDD = 25 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

QRR, STORED CHARGE ( C)

tf

td(on)

td(off)

VGS = 0 V
TJ = 25C

5
4
3
2
1
0
0.50

0.54

ID, DRAIN CURRENT (AMPS)

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Stored Charge

Figure 11. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4963

MTV6N100E
SAFE OPERATING AREA
800
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0

100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 6 A

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

700
600
500
400
300
200
100
0
25

1000

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E05

t1

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E04

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4964

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
Designer's

MTV10N100E

TMOS POWER FET


10 AMPERES
1000 VOLTS
RDS(on) = 1.3 OHM

NChannel EnhancementMode Silicon Gate


The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltageblocking capability without degrading
performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drainto
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both acdc and dcdc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount

Robust High Voltage Termination


S
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13inch/500 Unit Tape & Reel, Add RL Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Total Power Dissipation @ TC = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 10 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

1000

Vdc

1000

Vdc

VGS
ID
ID
IDM

20

Vdc

10
6.2
30

Adc

PD

250
2.0
3.57

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Apk

C
mJ

500
RJC
RJA
RJA

0.5
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4965

MTV10N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1254

10
100

100

2.0

3.0
7.0

4.0

mV/C

1.07

1.3

Ohm

11

15
15.3

gFS

8.0

10

mhos

Ciss

3500

5600

pF

Coss

264

530

Crss

52

90

td(on)

29

60

tr

57

120

td(off)

118

240

tf

70

140

QT

100

120

Q1

18.4

Q2

33

Q3

36.7

0.885
0.8

1.1

trr

885

ta

220

tb

667

QRR

8.0

4.5

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 10 Vdc, ID = 5.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 500 Vdc, ID = 10 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 10 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 10 Adc, VGS = 0 Vdc)


(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4966

Motorola TMOS Power MOSFET Transistor Device Data

MTV10N100E
TYPICAL ELECTRICAL CHARACTERISTICS
20
TJ = 25C

VDS 10 V

VGS = 10 V
6V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

16

12
5V
8

16

12

8
100C
25C

TJ = 55C

4V
0

12

16

0
2.8

20

VGS = 10 V

TJ = 100C

1.6
25C

1.2
0.8

55C
0.4
0

12

3.6

4.8

5.2

5.6

16

20

TJ = 25C
1.4
1.32
VGS = 10 V

1.24

15 V

1.16
1.08
1.0

12

16

20

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.8

100000
VGS = 10 V
ID = 5 A

VGS = 0 V

TJ = 125C

10000
2

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

4.4

1.48

ID, DRAIN CURRENT (AMPS)

2.4

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.4

3.2

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.6
1.2
0.8

100

10

0.4
0
50

100C

1000

25

25

50

75

100

125

150

25C

100 200

300

400

500

600

700

800

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

900 1000

4967

MTV10N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

8000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

TJ = 25C

Ciss

6000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

7000

10000

VGS = 0 V

5000
Crss

4000

Ciss

3000
2000

1000

Coss
100
Crss

Coss

1000
Crss
0

10

0
VGS

10

15

20

25

10

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8a. Capacitance Variation

4968

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

560
QT

12

480

10

400
VGS

320
Q1

Q2

240
TJ = 25C 160
ID = 10 A
80

4
2
0

VDS

Q3
0

10

20

30

40

50

60

70

80

90

1000

t, TIME (ns)

14

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV10N100E
VDD = 480 V
ID = 10 A
VGS = 10 V
TJ = 25C

100

td(off)
tf
tr
td(on)

0
100

10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

10
TJ = 25C
VGS = 0 V

IS = 10 A
dlS/dt = 100 A/s
VDD = 25 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

QRR, STORED CHARGE ( C)

10

100

10

0
0.5

ID, DRAIN CURRENT (AMPS)

0.66
0.82
0.58
0.74
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.9

Figure 11. Diode Forward Voltage versus Current

Figure 10. Stored Charge

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4969

MTV10N100E
SAFE OPERATING AREA

10

500

10 s

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

1 ms
10 ms
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

100

400

300

200

100

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

dc

ID = 10 A

D = 0.5
0.2

0.1

0.1
0.05
0.02

0.01

P(pk)

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4970

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTV16N50E

TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount

TMOS POWER FET


16 AMPERES
500 VOLTS
RDS(on) = 0.40 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
speed switching applications in power supplies, converters, PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

500

Vdc

500

Vdc

VGS
ID
ID
IDM

20

Vdc

16
9.0
60

Adc

PD

180
1.4
2.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Apk

C
mJ

860
RJC
RJA
RJA

0.7
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4971

MTV16N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

520

250
1000

100

2.0

3.2
7.0

4.0

mV/C

0.32

0.40

Ohm

6.7
5.6

gFS

5.0

mhos

Ciss

3200

4480

pF

Coss

400

560

Crss

320

448

td(on)

28

60

tr

80

160

td(off)

80

160

tf

60

120

QT

65

Q1

17

Q2

47

Q3

34

1.0
0.9

1.6

trr

390

ta

245

tb

145

QRR

5.35

5.0

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 16 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 16 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 16 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 16 Adc, VGS = 0 Vdc)


(IS = 16 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4972

Motorola TMOS Power MOSFET Transistor Device Data

MTV16N50E
TYPICAL ELECTRICAL CHARACTERISTICS

16
14
12
10
8
5V

6
4
2

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

12
10
8
100C

6
4

10

25C
TJ = 55C
0

0.6
0.5
0.4

25C

0.3
0.2

55C

0.1
0.0
5

25
10
15
20
ID, DRAIN CURRENT (AMPS)

30

35

0.4
TJ = 25C
0.35

VGS = 10 V

0.3

15 V

0.25

0.2

0.15

25
10
15
20
ID, DRAIN CURRENT (AMPS)

30

35

Figure 4. OnResistance versus Drain Current


and Gate Voltage

100000

2.5

10

Figure 2. Transfer Characteristics

Figure 3. OnResistance versus Drain Current


and Temperature

VGS = 0 V

VGS = 10 V
ID = 8 A

TJ = 125C

10000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

TJ = 100C

2.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

14

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.8
0.7

16

4V
0

VDS 10 V

18

6V

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

20

7V

VGS = 10 V
9V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

20
18

1.5

100C

1000

1.0

0.5

0
50

25

0
25
50
100
75
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

25C
100

10

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

4973

MTV16N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
7000

VDS = 0 V

10000

VGS = 0 V

TJ = 25C

VGS = 0 V

TJ = 25C

5000
4000

Crss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

6000 Ciss

Ciss

3000
2000

Ciss
1000

Coss
100
Crss

Coss

1000
0
10

Crss
5

0
VGS

10
10

15

20

25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 9a. Low Voltage Capacitance Variation

4974

10

100

1000

VDS
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 9b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

15

500
QT

300
Q2

1000

td(off)

td(on)

200

6
TJ = 25C
ID = 16 A

3
Q3
0

TJ = 25C
ID = 16 A
VDD = 250 V
VGS = 10 V

400
VGS

Q1

10000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV16N50E

10

20

40

50

60

70

80

90

tr

100

VDS
30

100

0
100

tf
10
1

10

100

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

1000

14
TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

12
10
8
6
4
2
0

0.2
0.6
0.4
0.8
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4975

MTV16N50E
SAFE OPERATING AREA
900

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s

1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

700
600
500
400
300
200
100
0
25

1000

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area
1

ID = 16 A

800

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1

0.1

0.05
0.02
P(pk)

0.01

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4976

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
Designer's

MTV20N50E
TMOS POWER FET
20 AMPERES
500 VOLTS
RDS(on) = 0.240 OHM

NChannel EnhancementMode Silicon Gate


The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltageblocking capability without degrading
performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drainto
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both acdc and dcdc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount

Robust High Voltage Termination


S
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13inch/500 Unit Tape & Reel, Add RL Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating

Symbol

Value

Unit

VDSS
VDGR

500

Vdc

500

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS

20
40

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
14.1
60

Adc

Total Power Dissipation


Derate above 25C
Total Power Dissipation @ TC = 25C (1)

PD

250
2.0
3.57

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)

Operating and Storage Temperature Range


Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 10 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

mJ
2000

RJC
RJA
RJA

0.5
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4977

MTV20N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

583

10
100

100

2.0

3.0
7.0

4.0

mV/C

0.23

0.24

Ohm

4.75

6.0
6.0

gFS

11

16.2

mhos

Ciss

3880

6950

pF

Coss

452

920

Crss

96

140

td(on)

29

55

tr

90

165

td(off)

97

190

tf

84

170

QT

100

132

Q1

20

Q2

44

Q3

36

0.916
0.81

1.1

trr

431

ta

272

tb

159

QRR

6.67

4.5

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4978

Motorola TMOS Power MOSFET Transistor Device Data

MTV20N50E
TYPICAL ELECTRICAL CHARACTERISTICS
40

7V

VDS

8V

32

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

40

VGS = 10 V

TJ = 25C

6V
24

16
5V

w 10 V

32

24
100C

16
25C

TJ = 55C
0

10

12

14

16

18

0
2.5

20

4.5

5.5

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
0.5

TJ = 100C

0.4
0.3

25C

0.2
55C
0.1
0
0

10

30
20
ID, DRAIN CURRENT (AMPS)

40

6.5

0.32
TJ = 25C
0.30
0.28
0.26

VGS = 10 V

0.24

15 V

0.22
0.2

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
ID, DRAIN CURRENT (AMPS)

40

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.4

10000
VGS = 10 V
ID = 10 A

VGS = 0 V
TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

3.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.6

2.0

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.6
1.2
0.8

1000

100C

100

10
25C

0.4
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

50

100 150 200 250 300 350 400 450


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

4979

MTV20N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

9000

10000

8000

TJ = 25C

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

Ciss

7000
C, CAPACITANCE (pF)

VGS = 0 V

VDS = 0 V

6000
5000

Ciss

Crss

4000
3000

Ciss
1000

Coss

100

2000
1000
0

10

0
VGS

Crss

Coss

Crss
10

15

20

25

10

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10a. Capacitance Variation

4980

10

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

QT
8

400

VGS
Q1

Q2

300

200
ID = 20 A
TJ = 25C

10

20

100

VDS

Q3
0

1000

500

30
40
50
60
70
QG, TOTAL GATE CHARGE (nC)

80

90

0
100

tf

td(on)

10
1

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

20
IS = 20 A
dlS/dt = 100 A/s
VDD = 50 V
TJ = 25C

6
5

I S , SOURCE CURRENT (AMPS)

QRR, STORED CHARGE ( C)

tr

100

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

4
3
2
1
0

td(off)

VDD = 250 V
ID = 20 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV20N50E

10

12

14

16

18

20

ID, DRAIN CURRENT (AMPS)

16

TJ = 25C
VGS = 0 V

12

0
0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 0.86 0.9
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.94

Figure 11. Diode Forward Voltage versus Current

Figure 10. Stored Charge

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4981

MTV20N50E
SAFE OPERATING AREA
2000
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10
100 s
1 ms
10 ms

1.0

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

10
1.0
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 20 A
1600

1200

800

400
0
25

1000

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2

0.1

0.1
0.05
0.02

0.01

P(pk)

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

4982

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTV25N50E

TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount

TMOS POWER FET


25 AMPERES
500 VOLTS
RDS(on) = 0.200 OHM

NChannel EnhancementMode Silicon Gate


The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltageblocking capability without degrading
performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drainto
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both acdc and dcdc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount

Robust High Voltage Termination


S
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13inch/500 Unit Tape & Reel, Add RL Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 25 Apk, L = 3.0 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

500

Vdc

500

Vdc

VGS
ID
ID
IDM

20

Vdc

25
15.8
88

Adc

PD

250
2.0

Watts
W/C

TJ, Tstg
EAS

55 to 150

Apk

mJ
938

RJC
RJA
RJA

0.5
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4983

MTV25N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

0.51

10
100

100

2.0

2.9
7.0

4.0

mV/C

0.19

0.2

Ohm

5.4

6.0
5.3

gFS

11

17

mhos

Ciss

4700

6580

pF

Coss

520

728

Crss

200

280

td(on)

37

70

tr

137

280

td(off)

118

240

tf

112

230

QT

132

180

Q1

29

Q2

63

Q3

61

0.9
0.79

1.1

trr

501

ta

332

tb

170

QRR

9.42

5.0

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 12.5 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 25 Adc)
(VGS = 10 Vdc, ID = 12.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 12.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 25 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 25 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 25 Adc, VGS = 0 Vdc)


(IS = 25 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 25 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4984

Motorola TMOS Power MOSFET Transistor Device Data

MTV25N50E
TYPICAL ELECTRICAL CHARACTERISTICS
50

7V

VDS

8V

9V

40

30

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

50

VGS = 10 V

TJ = 25C

6V

20

10

5V

w 10 V

40

30
100C

20
25C

10

TJ = 55C

4V
0

12

16

Figure 2. Transfer Characteristics

0.35
0.30
0.25

25C

0.20
0.15
0.10

55C

0.05
0
10

20
30
ID, DRAIN CURRENT (AMPS)

40

50

2.5

0.28
TJ = 25C
0.26

0.24

VGS = 10 V
15 V

0.22

0.20

0.18

Figure 3. OnResistance versus Drain Current


and Temperature

10

20
30
ID, DRAIN CURRENT (AMPS)

40

50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 12.5 A

TJ = 125C
100C

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 1. OnRegion Characteristics

TJ = 100C

2.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.45
0.40

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1000

1.5

1.0

100

25C

0.5

0
50

0
50
100
TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

10

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

4985

MTV25N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

10000
9000

VDS = 0 V

100000

VGS = 0 V

TJ = 25C

8000
7000
Crss

6000
5000

Ciss

4000
3000
2000
1000
0
10

TJ = 25C

10000
Ciss
1000
Coss
100

Crss

Coss

Crss
VGS

4986

VGS = 0 V

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

12000
11000

10
5

10

15

20

25

10

100

1000

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11a. Capacitance Variation

Figure 11b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

12

600
QT

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

1000

500
VGS

400
VDS

300

Q2

Q1

25

50
75
100
Qg, TOTAL GATE CHARGE (nC)

125

td(on)
100

100

Q3
0

tr
tf

200

TJ = 25C
ID = 25 A

td(off)

TJ = 25C
ID = 25 A
VDD = 250 V
VGS = 10 V
t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV25N50E

0
150

10
1

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

I S , SOURCE CURRENT (AMPS)

25
TJ = 25C
VGS = 0 V

20

15

10

5.0

0
0.54

0.62
0.78
0.70
0.86
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

0.94

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4987

MTV25N50E
SAFE OPERATING AREA
1000
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms
dc

1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800
700
600
500
400
300
200
100
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0

ID = 25 A

900

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2

0.1

0.1
0.05
0.02

0.01

P(pk)

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4988

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

MTV32N20E

TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount

TMOS POWER FET


32 AMPERES
200 VOLTS
RDS(on) = 0.075 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
speed switching applications in power supplies, converters, PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 M)
GatetoSource Voltage Continuous
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ 25C
Derate above 25C
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 1.58 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

200

Vdc

200

Vdc

VGS
ID
ID
IDM

20

Vdc

32
19
128

Adc

PD

180
1.44
2.0

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Apk

C
mJ

810
RJC
RJA
RJA

0.7
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Motorola TMOS Power MOSFET Transistor Device Data

4989

MTV32N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

247

250
1000

100

nAdc

2.0

3.0
8.0

4.0

Vdc
mV/C

0.064

0.075

Ohm

2.1

3.0
2.7

gFS

12

20

mhos

Ciss

3600

5000

pF

Coss

130

250

Crss

690

1000

td(on)

25

50

tr

120

240

td(off)

75

150

tf

91

182

QT

85

120

Q1

12

Q2

40

Q3

30

1.1
0.9

2.0

trr

280

ta

195

tb

85

QRR

2.94

5.0

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 100 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.2 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 160 Vdc, ID = 32 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 32 Adc, VGS = 0 Vdc)


(IS = 32 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4990

Motorola TMOS Power MOSFET Transistor Device Data

MTV32N20E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

50

VGS = 10 V

TJ = 25C

9V

VDS
I D , DRAIN CURRENT (AMPS)

100

80
8V
60
7V
40
6V
20

w 10 V

TJ = 55C

100C

25C

40

30

20

10

5V
1

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C
0.12
0.10
0.08

25C

0.06
55C

0.04
0.02
0
8

16

40
24
32
48
ID, DRAIN CURRENT (AMPS)

56

64

2.5

10

0.10
TJ = 25C
0.09

0.08
VGS = 10 V

0.07

15 V
0.06

0.05

Figure 3. OnResistance versus Drain Current


and Temperature

16

40
48
24
32
ID, DRAIN CURRENT (AMPS)

56

64

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 16 A

TJ = 125C

2.0

I DSS , LEAKAGE (mA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16
0.14

10

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1000

1.5

1.0

100
100C
25C

0.5
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

10

50
100
150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

200

Figure 6. DrainToSource Leakage


Current versus Voltage

4991

MTV32N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
10000

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

8000
Crss
6000

4000

Ciss

2000
Coss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4992

Motorola TMOS Power MOSFET Transistor Device Data

200

16

TJ = 25C
ID = 32 A
VDS = 160 V

VDS

180
160
140

12

120

QT

100
VGS

80

Q2

Q1

60

40
Q3

0
0

10

20

30
40
50
60
70
QT, TOTAL CHARGE (nC)

80

90

20
0
100

1000

t, TIME (ns)

20

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV32N20E

100

tr

td(on)

tf

10

1.0
1.0

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

TJ = 25C
VGS = 0 V

30
I S , SOURCE CURRENT (AMPS)

td(off)

TJ = 25C
ID = 32 A
VDD = 100 V
VGS = 10 V

20

10

0.2
0.6
0.4
0.8
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4993

MTV32N20E
SAFE OPERATING AREA
10 s

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

0.1 ms
1.0 ms

10

10 ms

VGS = 20 V
SINGLE PULSE
TC = 25C

1.0

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
1.0

10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600
450
300
150
0
25

1000

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area
1.0

ID = 32 A

750

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1

0.1

0.05
0.02

0.01

P(pk)

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E02

1.0E01

1.0E+00

1.0E+01

1.0E+02

RJC(t) = r(t) RJC


RJC = 0.7C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+03

1.0E+04

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

4994

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
Designer's

MTV32N25E
TMOS POWER FET
32 AMPERES
250 VOLTS
RDS(on) = 0.08 OHM

NChannel EnhancementMode Silicon Gate


The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltageblocking capability without degrading
performance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drainto
source diode with a fast recovery time. Designed for low voltage,
high speed switching applications in surface mount PWM motor
controls and both acdc and dcdc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.

D
NChannel

G
CASE 43301, Style 2
D3PAK Surface Mount

Robust High Voltage Termination


S
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13inch/500 Unit Tape & Reel, Add RL Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 M)
GateSource Voltage Continuous
Drain Current Continuous
Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation @ 25C
Derate above 25C
Total Power Dissipation @ TA = 25C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 8.8 mH, RG = 25 )
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient (1)
Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Symbol

Value

Unit

VDSS
VDGR

250

Vdc

250

Vdc

VGS
ID
ID
IDM

20

Vdc

32
25
96

Adc

PD

250
2.0
3.57

Watts
W/C
Watts

TJ, Tstg
EAS

55 to 150

Apk

C
mJ

600
RJC
RJA
RJA

0.5
62.5
35

C/W

TL

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Motorola TMOS Power MOSFET Transistor Device Data

4995

MTV32N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

380

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.69

0.08

Ohm

2.25

2.6
2.5

gFS

11

20

mhos

Ciss

3800

5320

pF

Coss

750

1020

Crss

240

370

td(on)

31

60

tr

133

266

td(off)

93

186

tf

108

216

QT

97

136

Q1

22

Q2

43

Q3

41

1.0
0.92

1.5

trr

312

ta

220

tb

93

QRR

3.6

4.5

13

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 125 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 32 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 32 Adc, VGS = 0 Vdc)


(IS = 32 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


((IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

4996

Motorola TMOS Power MOSFET Transistor Device Data

MTV32N25E
TYPICAL ELECTRICAL CHARACTERISTICS
64

VGS = 10 V

TJ = 25C

VDS = 10 V

8V

56
I D , DRAIN CURRENT (AMPS)

9V
48
40

6V
32
24
16

5V

25C
100C

48
40
32
24
16
8

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.14

TJ = 100C

0.12
0.1
25C

0.08
0.06

55C

0.04
0.02
8

16

24
32
40
48
ID, DRAIN CURRENT (AMPS)

64

56

0.084
TJ = 25C
0.08

0.076
VGS = 10 V
0.072
15 V
0.068

0.064

Figure 3. OnResistance versus Drain Current


and Temperature

16

40
48
24
32
ID, DRAIN CURRENT (AMPS)

56

64

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 16 A

TJ = 125C

1.6

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

1.2

0.8

0.4
50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16

10

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 55C

56

7V

I D , DRAIN CURRENT (AMPS)

64

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100C
100

10

25C

50
100
150
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

4997

MTV32N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000

C, CAPACITANCE (pF)

7000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

6000
5000
Ciss

4000
3000

Crss

2000

Coss

1000
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4998

Motorola TMOS Power MOSFET Transistor Device Data

12

300
QT

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 25C
ID = 32 A
VDD = 125 V
VGS = 10 V

250
VGS

200

Q2

Q1
6

150

100

TJ = 25C
ID = 32 A

2
0

1000

Q3
0

10

50

VDS
30

20

40

50

60

70

80

90

0
100

t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTV32N25E

10
1

10

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

32
TJ = 25C
VGS = 0 V

IS = 32 A
dlS/dt = 100 A/s
VDD = 25 V
TJ = 25C

3.4

I S , SOURCE CURRENT (AMPS)

QRR, STORED CHARGE ( C)

td(off)

td(on)

2.8

2.2

1.6

tr
tf

100

12

16

20

24

28

32

24

16

0
0.5

0.55

ID, DRAIN CURRENT (AMPS)

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95


VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

Figure 10. Stored Charge

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

4999

MTV32N25E
SAFE OPERATING AREA
600

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

10

1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

10
1
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 32 A
500
400
300
200
100
0
25

1000

Figure 12. Maximum Rated Forward Biased


Safe Operating Area

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1

0.1

0.05
0.02
P(pk)

0.01

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 15. Diode Reverse Recovery Waveform

41000

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 With Isolated Mounting Hole
Designer's

MTW6N100E
Motorola Preferred Device

TMOS POWER FET


6.0 AMPERES
1000 VOLTS
RDS(on) = 1.5 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

CASE 340F03, Style 1


TO247AE
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

1000

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1000

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

6.0
4.2
18

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.43

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 50 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 27.77 mH, RG = 25 )

EAS

720

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.70
40

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41001

MTW6N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1,270

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

1.28

1.5

Ohm

8.0

14.4
12.6

gFS

4.0

7.2

mhos

Ciss

3000

4210

pF

Coss

219

440

Crss

43

90

td(on)

27

45

tr

29

65

td(off)

93

170

tf

43

95

QT

66

100

Q1

12.5

Q2

25.9

Q3

26

0.808
0.64

1.0

trr

735

ta

188

tb

547

QRR

4.7

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 3.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 500 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 ))

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Figure 8)

(VDS = 800 Vdc, ID = 6.0 Adc,


VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)


(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Fi
(See
Figure 14)

((IS = 6.0 Adc, VGS = 0 Vdc,


dIS/dt = 100 A/s)

Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41002

Motorola TMOS Power MOSFET Transistor Device Data

MTW6N100E
TYPICAL ELECTRICAL CHARACTERISTICS
12

12
VGS = 10 V

VDS 10 V

6V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C
10

5V
8
6
4

100C

8
6
25C
4
2

2
0

10

TJ = 55C

4V
0

6
8
10
12
14
16
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

20

2.4

2.9
TJ = 100C

2.5
2.1
1.7
25C
1.3
0.9
55C
0.5
0

6
8
4
ID, DRAIN CURRENT (AMPS)

10

12

4.4

4.8

5.2

TJ = 25C

1.52
1.48
1.44
1.40

VGS = 10 V

1.36

15 V

1.32
1.28
1.24
0

7
8
9
4
5
6
ID, DRAIN CURRENT (AMPS)

10

11

12

Figure 4. OnResistance versus Drain Current


and Gate Voltage

VGS = 0 V

VGS = 10 V
ID = 3 A

TJ = 125C

10000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

4.0

100000

2.8

2.0
1.6
1.2

100C
1000

100
25C
10

0.8
0.4
50

3.6

1.56

Figure 3. OnResistance versus Drain Current


and Temperature

2.4

3.2

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

VGS = 10 V

2.8

VGS, GATETOSOURCE VOLTAGE (VOLTS)

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

100

200 300 400 500 600 700 800 900 1000


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

41003

MTW6N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

10000

C, CAPACITANCE (pF)

6000

VDS = 0 V

Ciss

VGS = 0 V

TJ = 25C

VGS = 0 V
C, CAPACITANCE (pF)

7000

5000
4000
Crss

Ciss

3000
2000
1000
0

5
VGS

10

Coss

100

Crss

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41004

TJ = 25C

1000

Coss

Crss
0
10

Ciss

10
10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

400
ID = 6 A
TJ = 25C

14
12

350
300

QT

10

250

200

VGS
Q1

Q2

150
100

4
2
0

10

50

VDS

Q3
20

30

40

50

60

70

1000
VDD = 480 V
ID = 6 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

16

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW6N100E

100
td(off)

tf

td(on)
tr
10
1

10

QG, TOTAL GATE CHARGE (nC)

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

6
VGS = 0 V
TJ = 25C

5
4
3
2
1
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41005

MTW6N100E
SAFE OPERATING AREA

10

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

10 s
100 s

1.0

1 ms
10 ms
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0

700

500
400
300
200
100
0
25

1000

100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 6 A

600

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E05

t1

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41006

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 With Isolated Mounting Hole
Designer's

MTW7N80E
Motorola Preferred Device

TMOS POWER FET


7.0 AMPERES
800 VOLTS
RDS(on) = 1.0 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

800

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

800

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

7.0
5.1
21

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.43

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD =100 Vdc, VGS = 10 Vdc, IL = 21 Apk, L = 3.0 mH, RG = 25 )

EAS

661

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.70
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41007

MTW7N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

1,030

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.87

1.0

Ohm

6.8

10
10.5

gFS

4.0

7.63

mhos

Ciss

3000

4160

pF

Coss

244

490

Crss

46

90

td(on)

20

40

tr

37

85

td(off)

84

165

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 7.0 Adc)
(ID = 3.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 3.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 7.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 7.0 Adc,
VGS = 10 Vdc)

tf

49

105

QT

70

105

Q1

13

Q2

28

Q3

23

0.817
0.7

1.14

trr

651

ta

164

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 7.0 Adc, VGS = 0 Vdc)


(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 7.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

487

QRR

4.78

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41008

Motorola TMOS Power MOSFET Transistor Device Data

MTW7N80E
TYPICAL ELECTRICAL CHARACTERISTICS
14

14
VGS = 10 V

I D , DRAIN CURRENT (AMPS)

12

VDS 10 V
12

7V

10

I D , DRAIN CURRENT (AMPS)

TJ = 25C

6V

8
6
4
2
0

8
12
16
6
10
14
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10
8
6

25C

4
TJ = 55C

5V
0

100C

18

0
2.0

20

2.4

2.8
3.2
3.6
4.0
4.4
4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

2.0
VGS = 10 V

1.8

TJ = 100C

1.6
1.4
1.2
1.0

25C

0.8
0.6
55C
0.4
0.2

6
8
10
ID, DRAIN CURRENT (AMPS)

12

14

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

1.08
TJ = 25C
1.04
1.00
0.96
VGS = 10 V

0.92

15 V

0.88
0.84
0.80

8
4
6
10
ID, DRAIN CURRENT (AMPS)

14

12

100000

2.4

VGS = 0 V

VGS = 10 V
ID = 3.5 A

10000

1.6
1.2
0.8

TJ = 125C
100C

1000

100
25C
10

0.4
0
50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

2.0

5.6

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

100

200
300
500
700
400
600
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

800

Figure 6. DrainToSource Leakage


Current versus Voltage

41009

MTW7N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

7000

VDS = 0 V

Ciss

10000

VGS = 0 V

TJ = 25C

VGS = 0 V

Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

6000
5000
4000
3000

Ciss

Crss

2000

Coss
100

Coss

Crss
0

5
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41010

1000

Crss

1000
0
10

TJ = 25C

25

10
10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

600
QT

10

500

400

VGS

Q1

300

Q2

200

2
VDS

Q3

0
0

10

20

30

40

100

ID = 7 A
TJ = 25C
50

60

0
70

1000
VDD = 400 V
ID = 7 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW7N80E

100
td(off)
tf
tr
td(on)
10
1

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

7
VGS = 0 V
TJ = 25C

6
5
4
3
2
1
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41011

MTW7N80E
SAFE OPERATING AREA
700
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms
dc

0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

1.0

10

100

ID = 7 A

600
500
400
300
200
100
0

1000

50

25

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

75

100

150

125

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

t1

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41012

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW8N60E
Motorola Preferred Device

TMOS POWER FET


8.0 AMPERES
600 VOLTS
RDS(on) = 0.55 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

G
S
CASE 340F03, Style 1
TO247AE

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

600

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

8.0
6.4
24

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.43

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 24 Apk, L = 3.0 mH, RG = 25 )

EAS

864

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.70
40

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

41013

MTW8N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

695

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.46

0.55

Ohm

3.2

4.8
4.6

gFS

4.0

8.5

mhos

Ciss

2480

3470

pF

Coss

247

346

Crss

56

120

td(on)

23.6

50

tr

37.6

70

td(off)

80

170

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 4.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 4.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 300 Vdc, ID = 8.0 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 300 Vdc, ID = 8.0 Adc,
VGS = 10 Vdc)

tf

48

95

QT

67

100

Q1

17

Q2

26

Q3

27

0.829
0.71

1.1

trr

381

ta

225

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 8.0 Adc, VGS = 0 Vdc)


(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 8.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

156

QRR

4.61

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41014

Motorola TMOS Power MOSFET Transistor Device Data

MTW8N60E
TYPICAL ELECTRICAL CHARACTERISTICS
16

16
TJ = 25C

VGS = 10 V

12
10
8

5V

6
4
2
0

3
4
5
6
7
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100C
12
10
8
6

25C

4
2

4V
0

VDS 10 V

14

6V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

14

TJ = 55C

0
2.0

10

2.4

2.8
3.2
3.6 4.0
4.4 4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.86
VGS = 10 V
0.76

TJ = 100C

0.66
0.56
25C

0.46
0.36
0.26
0.16

55C
2

6
10
8
12
ID, DRAIN CURRENT (AMPS)

14

16

0.46
TJ = 25C

0.45
0.44
0.43

VGS = 10 V

0.42
0.41

15 V
0.40
0.39
0.38

6 7 8 9 10 11 12 13 14 15 16
ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.8

10000
TJ = 125C

VGS = 10 V
ID = 4 A

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

2.4

6.0

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

5.6

2.0
1.6
1.2

100C

100

10
25C
1.0

0.8

VGS = 0 V
0.4
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

0.1

200
400
100
300
500
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage


Current versus Voltage

41015

MTW8N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

7000

10000
VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

Ciss
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

6000

VGS = 0 V

5000
4000
3000

Ciss

Crss

2000
1000
0
10

0
VGS

1000

Coss
100
Crss

Coss

Crss

TJ = 25C

10

15

20

VDS

25

10
10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41016

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

450
ID = 8 A
TJ = 25C

16

400

14

350

12

300

QT

10

250
VGS

8
Q2

Q1

200
150

100

2
0

10

50

VDS

Q3
20

30

40

50

60

0
70

1000
VDD = 300 V
ID = 8 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

18

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW8N60E

100
td(off)
tf
tr
td(on)
10
1

10

100

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


8
I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

6
5
4
3
2
1
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

0.86

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41017

MTW8N60E
SAFE OPERATING AREA
900
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10
100
1.0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 8 A

800
700
600
500
400
300
200
100
0
25

1000

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
0.00001

0.0001

t1

t2
DUTY CYCLE, D = t1/t2
0.001

0.01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

0.1

1.0

10

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41018

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW10N100E
Motorola Preferred Device

TMOS POWER FET


10 AMPERES
1000 VOLTS
RDS(on) = 1.3 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transient.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

CASE 340F03, Style 1


TO247AE
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

1000

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

1000

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

10
6.2
30

Adc

Total Power Dissipation


Derate above 25C

PD

250
2.0

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 )

EAS

500

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.50
40

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41019

MTW10N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1,254

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

1.10

1.3

Ohm

11

15
15.3

gFS

8.0

10

mhos

Ciss

3500

5600

pF

Coss

264

530

Crss

52

90

td(on)

29

60

tr

57

120

td(off)

118

240

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 10 Adc)
(ID = 5.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 500 Vdc, ID = 10 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 10 Adc,
VGS = 10 Vdc)

tf

70

140

QT

100

120

Q1

18.4

Q2

33

Q3

36.7

0.885
0.8

1.1

trr

885

ta

220

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 10 Adc, VGS = 0 Vdc)


(IS = 10 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

667

QRR

8.0

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41020

Motorola TMOS Power MOSFET Transistor Device Data

MTW10N100E
TYPICAL ELECTRICAL CHARACTERISTICS
20

20
TJ = 25C

6V

16
14
12
10

5V
8
6
4
2
0

16
14
12
10
25C

8
6

100C

0
2.0

8 10 12 14 16 18 20 22 24 26 28 30
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
6

2.4

2.4
TJ = 100C

2.0
1.6
25C

1.2
0.8

55C
0.4
0

12
8
6
10
14
ID, DRAIN CURRENT (AMPS)

16

18

20

6.0

18

20

TJ = 25C
1.48
1.40
1.32
1.24

VGS = 10 V

1.16
15 V
1.08
1.00
0

6
8
10
12
14
ID, DRAIN CURRENT (AMPS)

16

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.8

100000
VGS = 0 V

VGS = 10 V
ID = 5 A

TJ = 125C

10000

2.0

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

5.6

1.56

Figure 3. OnResistance versus Drain Current


and Temperature

2.4

2.8 3.2 3.6


4.0
4.4 4.8
5.2
VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

VGS = 10 V

TJ = 55C

4V
0

VDS 10 V

18
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

18

VGS = 10 V

1.6
1.2
0.8

100C
1000
100
25C
10

0.4
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

100

200 300 400 500 600 700 800 900 1000


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage


Current versus Voltage

41021

MTW10N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

8000

10000

VGS = 0 V

VDS = 0 V

Ciss

TJ = 25C

VGS = 0 V

Ciss

6000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

7000

5000
4000

Crss

Ciss

3000
2000

TJ = 25C

1000

Coss
100
Crss

1000
0
10

Crss

Crss

10
0

5
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41022

25

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

560
QT

12

480

10

400
VGS

8
Q1

320

Q2

240

160

ID = 10 A
TJ = 25C

80
Q3

VDS

0
0

10

20

30

40

50

60

70

80

90

0
100

1000
VDD = 500 V
ID = 10 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

14

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW10N100E

100
td(off)
tf
tr
td(on)
10
1

10

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


10
I S , SOURCE CURRENT (AMPS)

9
8

VGS = 0 V
TJ = 25C

7
6
5
4
3
2
1
0
0.50 0.54 0.58

0.62 0.66

0.70 0.74

0.78 0.82 0.86

0.90

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41023

MTW10N100E
SAFE OPERATING AREA
500
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C

10

10 s
100 s

1.0

1 ms
10 ms
0.1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

ID = 10 A
400

300

200

100

0.01
0.1

100
1.0
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E05

1.0E04

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

t1

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

1.0E01

1.0E+100

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41024

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW14N50E
Motorola Preferred Device

TMOS POWER FET


14 AMPERES
500 VOLTS
RDS(on) = 0.40 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Designed to Replace External Zener Transient Suppressor


Absorbs High Energy in the Avalanche Mode
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

CASE 340F03, Style 1


TO247AE
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous

VGS

20

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

14
9.0
60

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.44

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C


(VDD = 50 Vdc, VGS = 10 Vpk, IL = 14 Apk, L = 8.8 mH, RG = 25 )

EAS

860

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.7
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

41025

MTW14N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

520

Vdc
mV/C

250
1000

100

nAdc

2.0

3.2
7.0

4.0

Vdc
mV/C

0.32

0.40

Ohm

6.7
5.6

gFS

5.0

mhos

Ciss

2510

3510

pF

Coss

280

392

Crss

67

94

td(on)

28

60

tr

80

160

td(off)

80

160

tf

60

120

QT

65

85

Q1

17

Q2

47

Q3

34

VSD

1.0
0.9

1.6

Vdc

trr

390

ns

ta

245

tb

145

QRR

5.35

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

5.0

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 V, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0)
(VDS = 500 Vdc, VGS = 0, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 14 Adc)
(ID = 7.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 7.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0,
0
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 14 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time
Gate Charge
((VDS = 400 Vdc, ID = 14 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage

((IS = 14 Adc, VGS = 0))


(IS = 14 Adc, VGS = 0, TJ = 125C)

Reverse Recovery Time


((IS = 14 Adc, VGS = 0,
dIS/dt = 100 A/s, VGS = 0)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE

*Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


Switching characteristics are independent of operating junction temperature.

41026

Motorola TMOS Power MOSFET Transistor Device Data

MTW14N50E
TYPICAL ELECTRICAL CHARACTERISTICS
20
TJ = 25C

14
12
10
8
VGS = 5 V

6
4
2
0

TJ = 100C

25C

6
4

10

VGS = 10V

0.6
TJ = 100C
0.4
TJ = 25C
0.2

TJ = 55C

8
12
16
20
ID, DRAIN CURRENT (AMPS)

28

24

10

0.36
TJ = 25C

0.34
0.32
0.30
0.28

VGS = 10 V

0.26

VGS = 15 V

0.24
0.22
0.20

8
12
16
20
ID, DRAIN CURRENT (AMPS)

24

28

Figure 4.OnResistance versus Drain Current

100000
I DSS , DRAIN-TO-SOURCE LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

2.5

0.38

Figure 3.OnResistance versus Drain Current

2.0

1.5

1.0
VGS = 10 V
ID = 7 A

0.5
0
50

55C

Figure 2. Transfer Characteristics

0.8

10

Figure 1. OnRegion Characteristics

1.0

0.0

12

2
3
4
5
6
7
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

14

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

16

4V

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VDS 10 V

18

6V

16

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

18

20

7V

10 V

50
100
150
TJ, JUNCTION TEMPERATURE (C)

200

Figure 5.OnResistance Variation


With Temperature

Motorola TMOS Power MOSFET Transistor Device Data

VGS = 0 V
20000
10000

TJ = 125C

2000
1000

TJ = 100C

200
100

TJ = 25C

20
10

100
200
300
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6.DrainToSource Leakage


Current versus Voltage

41027

MTW14N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 10) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

8000
7000

10000

TJ = 25C

VDS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

2000

6000
5000
4000
Ciss

3000
2000

0
10

1000

200

Coss

100
Crss

Coss

1000

20

Crss
5

0
VGS

VGS = 0 V
Ciss

VGS = 0 V

10

15

20

25

VDS

10

20
10
100 200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Low Voltage Capacitance Variation

41028

Figure 7b. High Voltage Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

500
TJ = 25C
ID = 14 A
VDS = 400 V

VDS

12

QT

400

300

9
Q1
6

200

Q2
VGS

10

Q3
20

30

40

50

60

70

100

80

90

0
100

10000

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

15

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW14N50E

td(off)

TJ = 25C
ID = 14 A
VDD = 250 V
VGS = 10 V

2000
1000

td(on)
200
100

tr

20

tf

10

10

20

100

200

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

1000

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

14
TJ = 25C
VGS = 0 V
dIS/dt = 100 A/s

12
10
8
6
4
2
0

0.2
0.4
0.6
0.8
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive
pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in
AN569, Transient Thermal ResistanceGeneral Data and Its
Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10s. In addition the total power averaged
over a complete switching cycle must not exceed (TJ(MAX)
TC)/(RJC).
A Power MOSFET designated EFET can be safely used in
switching circuits with unclamped inductive loads. For reliable

Motorola TMOS Power MOSFET Transistor Device Data

operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41029

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C

20

10 s
100 s

10

1 ms
2

10 ms

1
THERMAL LIMIT
PACKAGE LIMIT
RDS(on) LIMIT

0.2
0.1

dc

20
10
100 200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

MTW14N50E
900
800

600
500
400
300
200
100
0

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

25

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

PEAK ID = 14 A
VDD = 50 V

700

D = 0.5
= 0.2

0.2
0.1

= 0.1
= 0.05
= 0.02
= 0.01

0.02
0.01

RJC(t) = r(t) RJC


RJC = 0.7C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

SINGLE PULSE

0.002

DUTY CYCLE, D = t1/t2


P(pk)
t1

t2

0.001
0.01

0.02

0.1

0.2

2
t, TIME (ms)

10

20

100

200

1000

Figure 13. Thermal Response

41030

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW16N40E
Motorola Preferred Device

TMOS POWER FET


16 AMPERES
400 VOLTS
RDS(on) = 0.24 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

G
S
CASE 340F03, Style 1
TO247AE

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ 100C
Single Pulse (tp 10 s)

ID
ID
IDM

16
9.0
56

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.4

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 6.8 mH, RG = 25 )

EAS

870

mJ

Thermal Resistance

RJC
RJA

0.70
40

C/W

TL

260

Operating and Storage Temperature Range

Junction to Case
Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41031

MTW16N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

420

Vdc
mV/C

0.25
1.0

100

2.0

3.0
7.0

4.0

mV/C

0.225

0.24

Ohm

4.8
4.3

gFS

8.0

10

mhos

Ciss

2570

3600

pF

Coss

330

460

Crss

82

164

td(on)

29

50

tr

62

70

td(off)

76

170

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 320 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

mAdc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 16 Adc)
(ID = 8.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 200 Vdc, ID = 16 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 320 Vdc, ID = 16 Adc,
VGS = 10 Vdc)

tf

57

95

QT

66

93

Q1

17

Q2

31

Q3

30

1.0
0.9

1.6

trr

340

ta

228

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 16 Adc, VGS = 0 Vdc)


(IS = 16 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Fig
Figure
re 9)
((IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

112

QRR

4.3

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

5.0

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41032

Motorola TMOS Power MOSFET Transistor Device Data

MTW16N40E
TYPICAL ELECTRICAL CHARACTERISTICS
40
TJ = 25C VGS = 10 V

8V

VDS = 50 V
35

7V

25
20

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

30

6.5 V

15

6V

10
5
0

4.5 V

30
25
20
15
100C

10
5

4
8
12
6
10
14 16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

18

20

2
4
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.75
VGS = 10 V
0.6
TJ = 100C
0.45
25C

0.3

0.15

55C

10
20
15
ID, DRAIN CURRENT (AMPS)

30

25

0.32
TJ = 25C
0.30
0.28
0.26

VGS = 10 V

0.24
15 V

0.22
0.20

12
16
20
24
ID, DRAIN CURRENT (AMPS)

28

32

Figure 4. OnResistance versus Drain Current


and Gate Voltage

3.0

1000

VGS = 0 V

VGS = 10 V
ID = 8 A

TJ = 125C
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

2.5

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

TJ = 55C

25C

2.0
1.5
1.0

100
100C

10

0.5
0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

150

1.0

50

100
200
300
350
150
250
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400

Figure 6. DrainToSource Leakage


Current versus Voltage

41033

MTW16N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

10000

5000
4500

Ciss

TJ = 25C

VGS = 0 V

TJ = 25C

VGS = 0 V

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

4000
3500
3000
2500

Ciss

Crss

2000
1500

Ciss

Coss

1000

Crss

1000
500 VDS = 0 V
Crss
0
5
5
10
0
VGS
VDS

Coss
10

15

20

25

100

50

100

150

200

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41034

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

350
ID = 16 A
TJ = 25C

12

280

QT
VGS

210

Q2

Q1

140

70

Q3
VDS
0

10

15

20

25

30

35

40

45

50

55

60 65

10000

VDD = 200 V
ID = 16 A
VGS = 10 V
TJ = 25C

1000
t, TIME (ns)

15

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW16N40E

td(off)
100

tr
tf
td(on)

10
1

10

1000

100

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


8
I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C

6
5
4
3
2
1
0
0.50

0.54

0.58

0.62

0.66

0.70

0.74

0.78

0.82

0.86

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41035

MTW16N40E
SAFE OPERATING AREA

I D , DRAIN CURRENT (AMPS)

VGS = 20 V
SINGLE PULSE
TC = 25C

20

10 s
100 s

10

1 ms
2
10 ms

1
THERMAL LIMIT
PACKAGE LIMIT
RDS(on) LIMIT

0.2
0.1

dc

10
100 200
20
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

900

100

ID = 16 A

800
700
600
500
400
300
200
100
0

1000

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
P(pk)

0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
0.00001

0.0001

t1

t2
DUTY CYCLE, D = t1/t2
0.001

0.01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

0.1

1.0

10

t, TIME (ms)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41036

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW20N50E
Motorola Preferred Device

TMOS POWER FET


20 AMPERES
500 VOLTS
RDS(on) = 0.24 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

CASE 340F03, Style 1


TO247AE
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
14.1
60

Adc

Total Power Dissipation


Derate above 25C

PD

250
2.0

Watts
W/C

Rating

Apk

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 10 mH, RG = 25 )

EAS

2000

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.50
40

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

41037

MTW20N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

583

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.20

0.24

Ohm

5.75

6.0
6.0

gFS

11

16.2

mhos

Ciss

3880

6950

pF

Coss

452

920

Crss

96

140

td(on)

29

55

tr

90

165

td(off)

97

190

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 20 Adc)
(ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

tf

84

170

QT

100

132

Q1

20

Q2

44

Q3

36

0.916
0.81

1.1

trr

431

ta

272

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)

VSD

Vdc

ns

tb

159

QRR

6.67

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

5.0

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Reverse Recovery Stored Charge


INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41038

Motorola TMOS Power MOSFET Transistor Device Data

MTW20N50E
TYPICAL ELECTRICAL CHARACTERISTICS
40

VDS 10 V

8V

32

24

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

40

9V

VGS = 10 V

TJ = 25C

7V

16
6V
8

32

24

16

100C
25C

TJ = 55C

5V
0

6
10
14
18
4
8
12
16
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0 2.4

20

0.6
VGS = 10 V
0.5

TJ = 100C

0.4
25C

0.3
0.2

55C
0.1
0
0

16
24
12
20
28
ID, DRAIN CURRENT (AMPS)

32

40

36

TJ = 25C
0.32

0.30
VGS = 10 V

0.28

15 V

0.26

0.24
0

2.4

16
24
12
20
28
ID, DRAIN CURRENT (AMPS)

32

36

40

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 10 A

VGS = 0 V
TJ = 125C
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

6.8

0.34

Figure 3. OnResistance versus Drain Current


and Temperature

2.0

6.4

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0


VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.6
1.2
0.8

1000

100C

100

10
25C

0.4
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

50

100 150 200 250 300 350 400 450


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

41039

MTW20N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

9000

10000

8000

VGS = 0 V

TJ = 25C

Ciss

Ciss
C, CAPACITANCE (pF)

7000
C, CAPACITANCE (pF)

TJ = 25C

VGS = 0 V

VDS = 0 V

6000
5000
Ciss

Crss

4000
3000

1000

Coss

100

2000
Crss

1000
0

Crss
10

Coss
5

0
VGS

10

15

20

25

VDS

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41040

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

QT
8

400

VGS
Q1

Q2

300

200
ID = 20 A
TJ = 25C

10

20

100

VDS

Q3
0

1000

500

30
40
50
60
70
QG, TOTAL GATE CHARGE (nC)

80

90

0
100

td(off)

VDD = 250 V
ID = 20 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW20N50E
tr
tf

100
td(on)

10
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

20

16

VGS = 0 V
TJ = 25C

12

0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41041

MTW20N50E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

100 s
1 ms

1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

2000
1800

1400
1200
1000
800
600
400
200

0.01
0.1

1.0
100
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

ID = 20 A

1600

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.1
0.05

P(pk)

0.02
0.01

0.01
t1

SINGLE PULSE
0.001
1.0E05

t2
DUTY CYCLE, D = t1/t2

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41042

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW24N40E
Motorola Preferred Device

TMOS POWER FET


24 AMPERES
400 VOLTS
RDS(on) = 0.16 OHM

NChannel EnhancementMode Silicon Gate


This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

400

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

400

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

24
17.7
72

Adc

Total Power Dissipation


Derate above 25C

PD

250
2.0

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )

EAS

600

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.50
40

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

41043

MTW24N40E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

400

360

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.13

0.16

Ohm

4.5
4.3

gFS

11

17

mhos

Ciss

4000

5600

pF

Coss

530

740

Crss

112

220

td(on)

32

60

tr

96

204

td(off)

99

194

tf

92

186

QT

98

160

Q1

24

Q2

38

Q3

40

0.94
0.9

1.5

trr

372

ta

244

tb

128

QRR

5.3

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 12 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 24 Adc)
(ID = 12 Adc, TJ =125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 12 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD 200= Vdc, ID = 24 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 320 Vdc, ID = 24 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 24 Adc, VGS = 0 Vdc)


(IS = 24 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 24 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41044

Motorola TMOS Power MOSFET Transistor Device Data

MTW24N40E
TYPICAL ELECTRICAL CHARACTERISTICS
50

50
VDS 10 V

VGS = 10 V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

TJ = 25C
40

9V
8V

7V
30

6V

20
5V

10

40

30

20
25C

10
100C

4V
0
0

2.0
4.0
6.0
8.0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0

10

0.4
VGS = 10 V

0.35
0.3

TJ = 100C

0.25
0.2
25C

0.15
0.1

55C

0.05
0
0

10

20
30
ID, DRAIN CURRENT (AMPS)

7.0

40

50

TJ = 25C
0.18
0.17
0.16
VGS = 10 V

0.15

15 V
0.14
0.13
0.12
0

3.0

10

20
30
ID, DRAIN CURRENT (AMPS)

40

50

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 12 A

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

6.5

0.19

Figure 3. OnResistance versus Drain Current


and Temperature

2.5

3.0 3.5 4.0 4.5 5.0 5.5 6.0


VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

TJ = 55C
2.5

2.0
1.5
1.0

100C
100

10
25C

0.5
0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100
200
300
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

400

Figure 6. DrainToSource Leakage


Current versus Voltage

41045

MTW24N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

9000

10000

Ciss

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

7000
6000
5000

VGS = 0 V
TJ = 25C

TJ = 25C

VDS = 0 V
VGS = 0 V

8000

Ciss

Crss

4000
3000

Ciss

1000
Coss
100

Crss

2000
1000
0
10

Coss
Crss
0

5
VGS

10
5

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41046

10

100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

12
10

VDD = 200 V
ID = 24 A
VGS = 10 V
TJ = 25C

VGS
Q1

400

Q2
ID = 24 A
TJ = 25C

300

t, TIME (ns)

500

tr
tf

100

td(off)

200

4
2
0

1000

600
QT

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW24N40E

td(on)

100

Q3
20

VDS
40

60

0
100

80

10

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


24
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

20
16
12
8
4
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41047

MTW24N40E
SAFE OPERATING AREA
700
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

10

1 ms
10 ms
DC

1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1
0.1

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500
400
300
200
100
0
25

1000

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0

ID = 24 A

600

150

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5

0.2
0.1
0.1
0.05
0.02

0.01

P(pk)

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E02
t, TIME (s)

1.0E03

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41048

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

MTW32N20E
Motorola Preferred Device

TMOS POWER FET


32 AMPERES
200 VOLTS
RDS(on) = 0.075 OHM

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

200

Vdc

GateSource Voltage Continuous

VGS

20

Vdc

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

32
19
128

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.44

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 50 Vdc, VGS = 10 Vpk, IL = 32 Apk, L = 1.58 mH, RG = 25 )

EAS

810

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.7
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

41049

MTW32N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

247

Vdc
mV/C

250
1000

100

nAdc

2.0

8.0

4.0

Vdc
mV/C

0.064

0.075

Ohm

3.0
2.7

gFS

12

mhos

Ciss

3600

5000

pF

Coss

130

250

Crss

690

1000

td(on)

25

50

tr

120

240

td(off)

75

150

tf

91

182

QT

85

120

Q1

12

Q2

40

Q3

30

1.1
0.9

2.0

trr

280

ta

195

tb

85

QRR

2.94

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

5.0

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 V, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0)
(VDS = 200 Vdc, VGS = 0, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 32 Adc)
(ID = 16 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0,
0
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS*
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 100 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 6.2 )

Fall Time
Gate Charge
((VDS = 160 Vdc, ID = 32 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS*


Forward OnVoltage

(IS = 32 Adc, VGS = 0)


(IS = 16 Adc, VGS = 0, TJ = 125C)

Reverse Recovery Time


((IS = 32 Adc, VGS = 0,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

* Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


Switching characteristics are independent of operating junction temperature.

41050

Motorola TMOS Power MOSFET Transistor Device Data

MTW32N20E
YPICAL ELECTRICAL CHARACTERISTICS
100

TJ = 55C

9V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

50

VGS = 10 V

TJ = 25C
80

8V
60
7V
40
6V
20

100C

VDS 10 V

40

25C

30

20

10

5V
2

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.14

TJ = 100C

0.12
0.1
0.08

25C

0.06
55C

0.04
0.02
8

24

16

32

40

48

56

64

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.16

10

10

0.1
TJ = 25C
0.09

0.08
VGS = 10 V
0.07
15 V
0.06

0.05

16

24

32

40

48

56

64

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

10000
VGS = 0 V

VGS = 10 V
ID = 16 A
2

I DSS, LEAKAGE (mA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

2000

TJ = 125C

1000

200
100
100C
20

0.5
50

25

25

50

75

100

125

150

10

25C
0

50

100

150

200

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

41051

MTW32N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at a


voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the on
state when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by L di/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
10000

VDS = 0

VGS = 0

TJ = 25C

C, CAPACITANCE (pF)

8000
Crss
6000

4000

Ciss

2000
Coss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41052

Motorola TMOS Power MOSFET Transistor Device Data

200

16

TJ = 25C
ID = 32 A
VDS = 160 V

VDS

180
160
140

12

120

QT

100
80

Q2

Q1

VGS

60
40

20

Q3
0

10

20

30
40
50
60
70
QT, TOTAL CHARGE (nC)

80

90

0
100

1000

td(off)

TJ = 25C
ID = 32 A
VDD = 100 V
VGS = 10 V

200
t, TIME (ns)

20

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW32N20E

100

tr
tf

td(on)

20
10

2
1

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

10
20
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

TJ = 25C
VGS = 0 V

I S , SOURCE CURRENT (AMPS)

30

20

10

0.2
0.4
0.6
0.8
1
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define the
maximum simultaneous draintosource voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive
pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in
AN569, Transient Thermal ResistanceGeneral Data and Its
Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10s. In addition the total power averaged
over a complete switching cycle must not exceed (TJ(MAX)
TC)/(RJC).
A Power MOSFET designated EFET can be safely used in
switching circuits with unclamped inductive loads. For reliable

Motorola TMOS Power MOSFET Transistor Device Data

operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41053

MTW32N20E
VGS = 20 V
SINGLE PULSE
TC = 25C

200
100

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10 s
.1

20
10

1
10

2
1

dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.2
0.1

10
100 200
20
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

750
600
450
300
150
0
25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

0.2
0.1

0.01

0.002
0.001
0.01

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

D = 0.5
0.2
0.1
0.05
P(pk)

0.02
0.02

ID = 32 A

0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.02

0.1

0.2

2
t, TIME (ms)

10

20

RJC(t) = r(t) RJC


RJC = 0.7C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

100

200

1000

Figure 13. Thermal Response

41054

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

MTW32N25E
Motorola Preferred Device

TMOS POWER FET


32 AMPERES
250 VOLTS
RDS(on) = 0.08 OHM

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

250

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

250

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

32
25
96

Adc

Total Power Dissipation


Derate above 25C

PD

250
2.0

Watts
W/C

TJ, Tstg

55 to 150

Rating

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.50
40

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
600

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

41055

MTW32N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

250

300
380

Vdc
mV/C

10
100

100

2.0

7.0

4.0

mV/C

0.07

0.08

Ohm

2.2

2.6
2.5

gFS

11

20

mhos

Ciss

3800

5350

pF

Coss

726

1020

Crss

183

370

td(on)

31

60

tr

133

266

td(off)

93

186

tf

108

216

QT

97

136

Q1

22

Q2

43

Q3

41

1.0
0.92

1.5

trr

312

ta

220

tb

93

QRR

3.6

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 32 Adc)
(ID = 16 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD= 125 Vdc, ID = 32 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 32 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 32 Adc, VGS = 0 Vdc)


(IS = 32 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41056

Motorola TMOS Power MOSFET Transistor Device Data

MTW32N25E
TYPICAL ELECTRICAL CHARACTERISTICS
64

8V

48
40

6V

32
24
16

5V

25C

48
100C

40
32
24
16

3
5
7
4
6
8
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

7
3
4
5
6
VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.16

VGS = 10 V

0.14

TJ = 100C

0.12
0.1
0.08

25C

0.06
55C

0.04

16

32
48
24
40
ID, DRAIN CURRENT (AMPS)

56

64

0.084

TJ = 25C

0.08

0.076
VGS = 10 V
0.072
15 V
0.068

0.064

2.0

16

24
40
32
48
ID, DRAIN CURRENT (AMPS)

56

64

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 10 V
ID = 2.0 A

VGS = 0 V
TJ = 125C
1000

1.6

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

1.2

0.8

0.4
50

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.02

TJ = 55C

8
0

VDS 10 V

56

9V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

56

64

7V

VGS = 10 V

TJ = 25C

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100C
100

10

25C

50
150
100
200
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

250

Figure 6. DrainToSource Leakage


Current versus Voltage

41057

MTW32N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

C, CAPACITANCE (pF)

td(on) = RG Ciss In [VGG/(VGG VGSP)]


td(off) = RG Ciss In (VGG/VGSP)

8000

VDS = 0 V

7000

Ciss

VGS = 0 V

TJ = 25C

6000
5000
4000

Ciss

Crss

3000
2000

0
10

Coss

Crss

1000
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41058

Motorola TMOS Power MOSFET Transistor Device Data

300
QT

10

250
VGS

200
Q1

Q2

150

100
ID = 32 A
TJ = 25C

2
Q3
0

10

20

VDS
30

40

60

50

70

80

90

50
0
100

1000
VDD = 125 V
ID = 32 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW32N25E

tr
tf
td(off)

100

td(on)
10

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


32

I S , SOURCE CURRENT (AMPS)

VGS = 0 V
TJ = 25C
24

16

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41059

MTW32N25E
SAFE OPERATING AREA
600
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

10
1 ms
10 ms
dc

1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

ID = 32 A
500
400
300
200
100

0.1
0.1

1.0

1000

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

10

D = 0.5
0.2
0.1

0.1

0.05
0.02

0.01

P(pk)
0.01
SINGLE PULSE

t1

t2
DUTY CYCLE, D = t1/t2
0.001
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41060

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

MTW35N15E
Motorola Preferred Device

TMOS POWER FET


35 AMPERES
150 VOLTS
RDS(on) = 0.05 OHM

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

150

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

150

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

35
26.9
105

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.45

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )

EAS

600

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.70
62.5

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41061

MTW35N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

150

210

Vdc
mV/C

10
100

100

nAdc

2.0

7.0

4.0

Vdc
mV/C

0.05

Ohm

1.45

1.8
1.7

gFS

11

18

mhos

Ciss

3600

5040

pF

Coss

855

1170

Crss

165

330

td(on)

28

56

tr

170

346

td(off)

90

180

tf

103

210

QT

98

137

Q1

19

Q2

49

Q3

40

0.95
0.9

1.5

trr

200

ta

167

tb

32

QRR

1.63

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 150 Vdc, VGS = 0 Vdc)
(VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 17.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 35 Adc)
(ID = 17.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 17.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 75 Vdc, ID = 35 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 120 Vdc, ID = 35 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 35 Adc, VGS = 0 Vdc)


(IS = 35 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 35 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41062

Motorola TMOS Power MOSFET Transistor Device Data

MTW35N15E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

60

70

VGS = 10 V
9.0 V

TJ = 25C

8.0 V
7.0 V

50
40
30

6.0 V

20
5.0 V

10
0

1.0

0.5

1.5

2.0

2.5

3.0

40
30
20
100C

4.0

6.0

5.0

Figure 2. Transfer Characteristics

TJ = 100C

0.05
25C
0.04
0.03

55C

0.02
0.01
10

50
20
30
40
ID, DRAIN CURRENT (AMPS)

70

60

0.047
TJ = 25C
0.045
0.043
VGS = 10 V
0.041
0.039
15 V
0.037
0.035

Figure 3. OnResistance versus Drain Current


and Temperature

2.5

10

1000
VGS = 0 V

2.0
I DSS , LEAKAGE (nA)

100

1.0

50
20
30
40
ID, DRAIN CURRENT (AMPS)

70

60

Figure 4. OnResistance versus Drain Current


and Gate Voltage

VGS = 10 V
ID = 17.5 A

1.5

8.0

7.0

Figure 1. OnRegion Characteristics

0.06

RDS(on), DRAIN-TO-SOURCE RESISTANCE


(NORMALIZED)

TJ = 55C
3.0

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.07

TJ = 125C

100C

10

1.0

0.5

0
50

25C

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

50

0
2.0

4.0

3.5

0.09
0.08

VDS 10 V

60

10

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

I D , DRAIN CURRENT (AMPS)

70

25C

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

0.1

100
50
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

150

Figure 6. DrainToSource Leakage


Current versus Voltage

41063

MTW35N15E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
space

10000

VDS = 0 V

VGS = 0 V

TJ = 25C

C, CAPACITANCE (pF)

8000

6000
Crss
Ciss

4000

2000

Coss
Crss

0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41064

Motorola TMOS Power MOSFET Transistor Device Data

120
QT

10

100

VGS
Q2

Q1

8.0

80
60

6.0
4.0

40

TJ = 25C
ID = 35 A

20

2.0
VDS

Q3
0

20

60

40

80

0
100

1000
VDD = 75 V
ID = 35 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW35N15E

tr
100

tf
td(off)

td(on)
10

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

35
VGS = 0 V
TJ = 25C

30
25
20
15
10
5
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41065

MTW35N15E
SAFE OPERATING AREA

600
VGS = 20 V
SINGLE PULSE
TC = 25C

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
10 s
10

100 s

1.0

10 ms
DC

1 ms

0.1

1.0

10

100

ID = 35 A
500
400
300
200
100
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.05
0.2
0.1
0.1 0.05

P(pk)
0.02
0.01

t1

SINGLE PULSE

0.01
1.0E05

1.0E04

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02
t, TIME (s)

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41066

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's

NChannel EnhancementMode Silicon Gate


This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

MTW45N10E
Motorola Preferred Device

TMOS POWER FET


45 AMPERES
100 VOLTS
RDS(on) = 0.035 OHM

Avalanche Energy Specified


SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

CASE 340F03, Style 1


TO247AE
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

45
34.6
135

Adc

Total Power Dissipation


Derate above 25C

PD

180
1.44

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 25 Vdc, VGS = 10 Vdc, IL = 45 Apk, L = 0.8 mH, RG = 25 )

EAS

810

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.70
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

41067

MTW45N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

116

Vdc
mV/C

10
100

100

2.0

7.0

4.0

mV/C

0.027

0.035

Ohm

1.13

2.16
1.53

gFS

12

mhos

Ciss

3480

5000

pF

Coss

1240

2000

Crss

315

650

td(on)

25

50

tr

234

470

td(off)

83

170

tf

116

240

QT

106

220

Q1

26

Q2

54

Q3

44

1.09
1.04

1.635

trr

166

ta

118

tb

48

QRR

1.1

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 22.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 45 Adc)
(ID = 22.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 22.5 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD= 50 Vdc, ID = 45 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 45 Adc,
VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 45 Adc, VGS = 0 Vdc)


(IS = 45 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 45 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41068

Motorola TMOS Power MOSFET Transistor Device Data

MTW45N10E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

I D , DRAIN CURRENT (AMPS)

80
70

90

VGS = 10 V

8V

7V

9V

60
6V

50
40
30

5V

20
4V

10
0

0.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VDS 10 V

80
I D , DRAIN CURRENT (AMPS)

90

TJ = 55C

70

25C

60
50
100C

40
30
20
10

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
VGS, GATETOSOURCE VOLTAGE (VOLTS)

5.0

Figure 2. Transfer Characteristics

0.05
VGS = 10 V
TJ = 100C

0.04

25C

0.03

55C

0.02

0.01

10

20

40
60
30
50
ID, DRAIN CURRENT (AMPS)

70

80

90

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.032
TJ = 25C
0.030
VGS = 10 V
0.028

0.026
15 V
0.024

0.022

2.0

20

40
60
30
50
ID, DRAIN CURRENT (AMPS)

70

80

90

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000
VGS = 0 V

VGS = 10 V
ID = 22.5 A
1000

1.6

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

Figure 3. OnResistance versus Drain Current


and Temperature

10

1.2

0.8

TJ = 125C

100

100C

10
25C

0.4
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

1.0

20
40
60
80
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

Figure 6. DrainToSource Leakage


Current versus Voltage

41069

MTW45N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

10000

C, CAPACITANCE (pF)

8000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

6000

4000

Crss

Ciss
Coss

2000

Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41070

Motorola TMOS Power MOSFET Transistor Device Data

120

QT

10

100
VGS

Q2

80

Q1
6

60

40

2
0

10

20

ID = 45 A
TJ = 25C

VDS

Q3
30

40

50

60

80

70

90

100

20
0
110

1000
VDD = 50 V
ID = 45 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTW45N10E

tr
100

tf
td(off)

td(on)
10

10

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

45
VGS = 0 V
40 T = 25C
J
35
30
25
20
15
10
5
0
0.5

0.56 0.62 0.68 0.74 0.80 0.86 0.92 0.98 1.04

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41071

MTW45N10E
SAFE OPERATING AREA
1000
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10 s

100

100 s
10

1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0

1.0
0.1

10 ms
DC

ID = 45 A
800

600

400

200
0

100

10

25

50

75

100

150

125

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE


TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
0.1
P(pk)

0.1 0.05
0.02
0.01

t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41072

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY14N100E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


14 AMPERES
1000 VOLTS
RDS(on) = 0.80 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls, and
other inductive loads. The avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.

Avalanche Energy Specified


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S
CASE 340G02, STYLE 1
TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

1000

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

1000

Vdc

GatetoSource Voltage Continuous


Single Pulse (tp 50 s)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ TC = 100C
Single Pulse (tp 10 s)

ID
ID
IDM

14
8.7
49

Adc

Total Power Dissipation


Derate above 25C

PD

300
2.4

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 14 Apk, L = 10 mH, RG = 25 )

EAS

980

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
30

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Apk

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

41073

MTY14N100E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

1000

1.0

10
100

100

2.0

3.3
9.0

4.0

mV/C

0.67

0.8

Ohm

12.3

13.4
11.8

gFS

10

12

Ciss

7230

Coss

462

Crss

61

td(on)

49

tr

98

td(off)

132

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0, ID = 0.250 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
V/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.250 mAdc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 14 Adc)
(VGS = 10 Vdc, ID = 7.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS 15 Vdc, ID = 7.0 Adc)

Vdc

Vdc

mhos

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance

pF

SWITCHING CHARACTERISTICS (2)


TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 500 Vdc, ID = 14 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 500 Vdc, ID = 14 Adc,
VGS = 10 Vdc)

ns

tf

83

QT

142

Q1

34

Q2

46

Q3

56

1.36
1.26

1.5

trr

831

ta

364

tb

467

QRR

15.3

4.5

13

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 14 Adc, VGS = 0 Vdc)


(IS = 14 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 14 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41074

Motorola TMOS Power MOSFET Transistor Device Data

MTY14N100E
TYPICAL ELECTRICAL CHARACTERISTICS
20

30
6V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

18

VDS 10 V

VGS = 10 V

TJ = 25C

16
8V

14
12

5V

10
8
6
4

TJ = 55C

25
20
25C
15
100C
10
5

2
2

10

12

14

16

18

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

0.8

25C

0.4

55C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.6

1.2

20

12

16

20

28

24

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.85
TJ = 25C
0.8

0.75
VGS = 10 V
0.7
15 V
0.65
0.6

12

16

20

28

24

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

100000

VGS = 10 V
ID = 7 A

VGS = 0 V

100C

1000

1.5

1.0

0.5

0
50

TJ = 125C

10000

2.0

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100

25C

10

25

25

50

75

100

125

150

100

200

300

400

500

600

700

800

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

900 1000

41075

MTY14N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

15000

VDS = 0 V

100000

TJ = 25C

VGS = 0 V

TJ = 25C

Ciss

12000

Ciss

10000
9000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

VGS = 0 V

Ciss

Crss
6000

3000

1000
Coss
100
Crss

Coss
0
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41076

25

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

420
QT

10

350
VGS

280

Q1

210

Q2
TJ = 25C
ID = 14 A

140
70

2
0

VDS

Q3
0

25

50

75

100

125

1000
VDD = 1000 V
ID = 14 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY14N100E

0
150

100
td(off)
tr
tf
td(on)
10

Qg, TOTAL GATE CHARGE (nC)

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GatetoSource and DraintoSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

100

DRAINTOSOURCE DIODE CHARACTERISTICS


15
VGS = 0 V
TJ = 25C
I S , SOURCE CURRENT (AMPS)

12

0
0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41077

MTY14N100E
SAFE OPERATING AREA

10

1000

10 s

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s

1 ms
10 ms
0.1

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

0.01
0.1

10

dc

100

ID = 14 A
800

600

400

200
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
P(pk)

0.05

0.1

0.02
0.01
t1

SINGLE PULSE

t2
DUTY CYCLE, D = t1/t2
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41078

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY16N80E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


16 AMPERES
800 VOLTS
RDS(on) = 0.50 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S
CASE 340G02, STYLE 1
TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

800

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

800

Vdc

GatetoSource Voltage Continuous


NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Continuous @ TC = 100C
Single Pulse (tp 10 s)

ID
ID
IDM

16
11
55

Adc

Total Power Dissipation


Derate above 25C

PD

300
2.4

Watts
W/C

TJ, Tstg

55 to 150

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
30

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
1280

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

41079

MTY16N80E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

800

570

10
100

100

2.0

3.0
9.0

4.0

mV/C

0.42

0.5

Ohm

7.3

9.4
8.4

gFS

10

15

mhos

Ciss

7220

10110

pF

Coss

508

710

Crss

65

130

td(on)

52

100

tr

112

200

td(off)

122

240

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Vdc
mV/C
Adc

nAdc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 16 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS 15 Vdc, ID = 8.0 Adc)

Vdc

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 400 Vdc, ID = 16 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time
Gate Charge
(S Fi
(See
Figure 8)
((VDS = 400 Vdc, ID = 16 Adc,
VGS = 10 Vdc)

tf

100

200

QT

146

200

Q1

39

Q2

48

Q3

53

0.9
0.79

1.2

trr

995

ta

428

tb

567

QRR

20

4.5

13

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 16 Adc, VGS = 0 Vdc)


(IS = 16 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH
nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41080

Motorola TMOS Power MOSFET Transistor Device Data

MTY16N80E
TYPICAL ELECTRICAL CHARACTERISTICS

I D , DRAIN CURRENT (AMPS)

16

VGS = 10 V

TJ = 25C

8V

24

VDS 10 V

6V
I D , DRAIN CURRENT (AMPS)

32

16
5V
8

100C

12

8
25C
4
TJ = 55C

4V
2

10

12

14

16

18

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.9
VGS = 10 V
TJ = 100C
0.6

25C
0.3
55C
0

20

32

24

16

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.6
TJ = 25C

0.5
VGS = 10 V

15 V
0.4

12

16

20

24

28

32

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

100000

VGS = 10 V
ID = 8 A

VGS = 0 V

100C

1000

1.5

1.0

0.5

0
50

TJ = 125C

10000

2.0

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

100
25C
10

25

25

50

75

100

125

150

100

200

300

400

500

600

700

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

800

41081

MTY16N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

VDS = 0 V

12000

Ciss

8000

Crss

VGS = 0 V

100000

TJ = 25C

TJ = 25C

VGS = 0 V
10000
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

16000

Ciss

4000

Ciss

1000
Coss
100

Crss

Coss
0
10

Crss
5

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41082

25

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

400
QT

10

VGS

300

8
Q1

Q2
200

6
4

100

TJ = 25C
ID = 16 A

2
Q3
0

25

50

75

100

VDS
125

0
150

1000
VDD = 400 V
ID = 16 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY16N80E
td(off)
tr
tf
td(on)
100

10

Qg, TOTAL GATE CHARGE (nC)

40
60
20
RG, GATE RESISTANCE (OHMS)

Figure 8. GatetoSource and DraintoSource


Voltage versus Total Charge

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

80

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

16
VGS = 0 V
TJ = 25C
12

0
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41083

MTY16N80E
SAFE OPERATING AREA
1400

10 s

VGS = 20 V
SINGLE PULSE
TC = 25C
10

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100

100 s
1 ms
10 ms
dc

1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

0.1
0.1

10

100

ID = 16 A

1200
1000
800
600
400
200
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.05

0.1

P(pk)

0.02
0.01

t1

SINGLE PULSE
0.01
0.00001

t2
DUTY CYCLE, D = t1/t2
0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41084

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY20N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


20 AMPERES
500 VOLTS
RDS(on) = 0.26 OHM

This high voltage MOSFET uses an advanced termination


scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.

Robust High Voltage Termination


Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

G
S
CASE 340G02, Style 1
TO264

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DraintoSource Voltage

VDSS

500

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

500

Vdc

GatetoSource Voltage Continuous


GatetoSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous


Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)

ID
ID
IDM

20
13.9
60

Adc

Total Power Dissipation


Derate above 25C

PD

250
2.0

Watts
W/C

TJ, Tstg

55 to 150

Rating

Operating and Storage Temperature Range

Apk

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 10 mH, RG = 25 )

EAS

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.50
40

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

mJ
2000

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

41085

MTY20N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

583

Vdc
mV/C

10
100

100

nAdc

2.0

3.0
7.0

4.0

Vdc
mV/C

0.22

0.26

Ohm

4.75

6.2
6.5

gFS

11

16.2

mhos

Ciss

3880

6980

pF

Coss

452

920

Crss

96

140

td(on)

29

60

tr

90

170

td(off)

97

190

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 20 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 20 Adc,
VGS = 10 Vdc)

tf

84

170

QT

100

140

Q1

20

Q2

44

Q3

36

0.92
0.81

1.1

trr

431

ta

272

tb

159

QRR

6.67

3.5
4.5

7.5

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)


(IS = 20 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE


Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

nH

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41086

Motorola TMOS Power MOSFET Transistor Device Data

MTY20N50E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

40

VGS = 10 V

VDS 10 V

9V

32

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

40

8V
7V

6V

24

16
5V

32

24

16

100C
25C

TJ = 55C
0

4
8
12
16
6
10
14
18
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0
2.0 2.4

20

0.6
VGS = 10 V
0.5

TJ = 100C

0.4
25C

0.3
0.2

55C
0.1
0
0

16
24
12
20
28
ID, DRAIN CURRENT (AMPS)

32

40

36

TJ = 25C
0.32

0.30
VGS = 10 V

0.28

0.26

15 V

0.24
0

16
24
12
20
28
ID, DRAIN CURRENT (AMPS)

32

36

40

Figure 4. OnResistance versus Drain Current


and Gate Voltage

10000

2.4
VGS = 10 V
ID = 10 A

VGS = 0 V
TJ = 125C
I DSS , LEAKAGE (nA)

R DS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

6.8

0.34

Figure 3. OnResistance versus Drain Current


and Temperature

2.0

6.4

Figure 2. Transfer Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0


VGS, GATETOSOURCE VOLTAGE (VOLTS)

1.6
1.2
0.8

1000

100C

100

10
25C

0.4
0
50

1
25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with


Temperature

Motorola TMOS Power MOSFET Transistor Device Data

50

100 150 200 250 300 350 400 450


VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

500

Figure 6. DrainToSource Leakage


Current versus Voltage

41087

MTY20N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

9000

VDS = 0 V

8000

VGS = 0 V

C, CAPACITANCE (pF)

Ciss

6000
5000

Ciss

Crss

4000
3000
2000

1000

Coss

100

Coss

1000
0

TJ = 25C

Ciss

7000
C, CAPACITANCE (pF)

10000

TJ = 25C

VGS = 0 V

Crss

Crss
10

0
VGS

10

15

20

25

VDS

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41088

Figure 7b. High Voltage CapacitanceVariation

Motorola TMOS Power MOSFET Transistor Device Data

500
QT

400

VGS
Q1

Q2

300

200

4
ID = 20 A
TJ = 25C
2

100
VDS

Q3
0

10

20

30
40
50
60
70
QT, TOTAL GATE CHARGE (nC)

80

90

0
100

1000
td(off)

VDD = 250 V
ID = 20 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

10

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY20N50E
tr
tf

100

10

td(on)

Figure 8. GateToSource and DrainToSource


Voltage versus Total Gate Charge

10
RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

20

16

VGS = 0 V
TJ = 25C

12

4
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41089

MTY20N50E
SAFE OPERATING AREA
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
VGS = 20 V
SINGLE PULSE
TC = 25C

10

100 s
1 ms

1.0

10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.1

2000
ID = 20 A
1600

1200

800

400

0.01
0.1

1.0
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1000

25

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE

D = 0.5
0.2
0.1
0.1
0.05

P(pk)

0.02
0.01

0.01
t1

SINGLE PULSE
0.001
1.0E05

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E04

1.0E02
t, TIME (s)

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41090

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY25N60E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


25 AMPERES
600 VOLTS
RDS(on) = 0.21 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Specified


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D

CASE 340G02, STYLE 1


TO264
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

600

Vdc

DrainGate Voltage (RGS = 1 M)

VDGR

600

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Single Pulse (tp 10 s)

ID
IDM

25
65

Adc
Apk

Total Power Dissipation


Derate above 25C

PD

300
2.38

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 25 Apk, L = 10 mH, RG = 25 )

EAS

3000

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41091

MTY25N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

600

714

Vdc
mV/C

10
200

100

nAdc

Vdc
mV/C

0.21

Ohm

5.2

6
7

gFS

18

mhos

Ciss

7300

10220

pF

Coss

700

1100

Crss

110

250

td(on)

32

60

tr

90

175

td(off)

170

300

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 250 A)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 12.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 25 Adc)
(ID = 12.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 12.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 300 Vdc, ID = 25 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time

ns

tf

110

200

QT

240

350

Q1

30

Q2

110

Q3

65

0.9
0.8

1.2

trr

620

ta

310

tb

310

QRR

10.42

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

7.5

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 480 Vdc, ID = 25 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 25 Adc, VGS = 0 Vdc)


(IS = 25 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 25 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41092

Motorola TMOS Power MOSFET Transistor Device Data

MTY25N60E
TYPICAL ELECTRICAL CHARACTERISTICS
50

50

40

VDS 10 V
I D , DRAIN CURRENT (AMPS)

TJ = 25C
I D , DRAIN CURRENT (AMPS)

6V

VGS = 10 V

8V
5V

30

20

10

40

30

20

100C
TJ = 55C

10

4V
2

10

12

14

16

18

20

2.5

3.5

4.5

5.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.5
VGS = 10 V

TJ = 100C

0.4

0.3
25C
0.2
55C

0.1

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

10

20

30

40

50

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C
0

0.26
TJ = 25C
0.24

0.22

VGS = 10 V
15 V

0.2

0.18

10

20

30

40

50

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

10000
VGS = 10 V
ID = 12.5 A

TJ = 125C
1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

100C
100
VGS = 0 V
25C

10

0.5

0
50

25

25

50

75

100

125

150

100

200

300

400

500

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

600

41093

MTY25N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

24000
VDS = 0 V

VGS = 0 V

Ciss

20000

TJ = 25C

TJ = 25C
Ciss

10000
16000

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

100000

VGS = 0 V

Crss

12000

Ciss
8000
Coss

4000

1000
Coss
100

Crss

Crss
0

10

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41094

25

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

600
QT

10

500

400

VGS

300

Q2
Q1

TJ = 25C
ID = 25 A

4
2
0

200
100

VDS

Q3
0

50

100

150

0
250

200

10000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY25N60E
VDD = 300 V
ID = 25 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf
tr

100

td(on)
10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate Charge versus GatetoSource Voltage

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

25
VGS = 0 V
TJ = 25C

20

15

10

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41095

MTY25N60E
SAFE OPERATING AREA
3000
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

10

100 s
1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

0.1
0.1

10

100

ID = 25 A
2500
2000
1500
1000
500
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41096

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY30N50E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


30 AMPERES
500 VOLTS
RDS(on) = 0.15 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Specified


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D

CASE 340G02, STYLE 1


TO264
S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Symbol

Value

Unit

DrainSource Voltage

VDSS

500

Vdc

DrainGate Voltage (RGS = 1 M)

VDGR

500

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Single Pulse (tp 10 s)

ID
IDM

30
80

Adc
Apk

Total Power Dissipation


Derate above 25C

PD

300
2.38

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 10 mH, RG = 25 )

EAS

3000

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41097

MTY30N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

500

566

Vdc
mV/C

10
200

100

nAdc

Vdc
mV/C

0.15

Ohm

4.1

5
7

gFS

17

mhos

Ciss

7200

10080

pF

Coss

775

1200

Crss

120

250

td(on)

32

60

tr

105

175

td(off)

160

275

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 250 A)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 15 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 30 Adc)
(ID = 15 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 250 Vdc, ID = 30 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time

ns

tf

115

200

QT

235

350

Q1

35

Q2

110

Q3

65

0.95
0.88

1.2

trr

485

ta

312

tb

173

QRR

8.2

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 30 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 30 Adc, VGS = 0 Vdc)


(IS = 30 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41098

Motorola TMOS Power MOSFET Transistor Device Data

MTY30N50E
TYPICAL ELECTRICAL CHARACTERISTICS
60

60
VGS = 10 V

TJ = 25C

VDS 10 V

6V
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

50
8V
40
30

5V

20

50
40
30
20

100C
TJ = 55C

10

10

25C

4V
0

10

12

3.5

4.5

5.5

6.5

0.2
25C

0.15
0.1

55C
0.05
10

20

30

40

50

60

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

TJ = 100C

2.5

Figure 1. OnRegion Characteristics

0.25

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS = 10 V

0.3

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.35

0.17
TJ = 25C
0.16

0.15
VGS = 10 V
0.14

15 V

0.13

0.12

10

20

30

40

50

60

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2.5

10000
TJ = 125C

VGS = 10 V
ID = 15 A

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.5

0.5

0
50

25

25

50

75

100

125

150

100C

100

VGS = 0 V

25C

10

100

200

300

400

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

500

41099

MTY30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

24000
VDS = 0 V

VGS = 0 V

Ciss

10000

16000
12000

TJ = 25C

TJ = 25C
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

20000

100000

VGS = 0 V

Crss
Ciss

8000
Coss

4000

Ciss

1000
Coss
100

Crss

Crss
0

10

0
VGS

10

15

20

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

41100

25

10

10

100

1000

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance


Variation

Motorola TMOS Power MOSFET Transistor Device Data

600
QT

10

500

400

VGS

300

Q2
Q1

TJ = 25C
ID = 30 A

4
2
0

200
100

VDS

Q3
0

50

100

150

0
250

200

10000

t, TIME (ns)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

MTY30N50E
VDD = 250 V
ID = 30 A
VGS = 10 V
TJ = 25C

1000

td(off)
tf
tr

100

td(on)
10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate Charge versus GatetoSource Voltage

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

30
VGS = 0 V
TJ = 25C
20

10

0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41101

MTY30N50E
SAFE OPERATING AREA
3000
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

100
10 s

10

100 s
1 ms
10 ms

dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

0.1
0.1

10

100

2500

ID = 30 A

2000
1500
1000
500
0

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
P(pk)

0.05

0.1
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41102

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY55N20E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


55 AMPERES
200 VOLTS
RDS(on) = 0.028 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Specified


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

CASE 340G02, STYLE 1


TO264
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1 M)

VDGR

200

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Single Pulse (tp 10 s)

ID
IDM

55
165

Adc
Apk

Total Power Dissipation


Derate above 25C

PD

300
2.38

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 110 Apk, L = 0.3 mH, RG = 25 )

EAS

3000

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41103

MTY55N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

200

250

Vdc
mV/C

10
200

100

nAdc

Vdc
mV/C

0.028

Ohm

1.3

1.6
1.8

gFS

30

37

mhos

Ciss

7200

10080

pF

Coss

1800

2520

Crss

460

920

td(on)

33

66

tr

200

400

td(off)

150

300

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 250 A)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 27.5 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 55 Adc)
(ID = 27.5 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 27.5 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1 MHz)

Reverse Transfer Capacitance


SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDD = 100 Vdc, ID = 55 Adc,


VGS = 10 Vdc
Vdc,
RG = 4.7 )

Fall Time

ns

tf

170

340

QT

245

343

Q1

33

Q2

128

Q3

79

0.75
1.1

1.2

trr

310

ta

220

tb

90

QRR

4.6

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Gate Charge
(See Fig
Figure
re 8)
((VDS = 160 Vdc, ID = 55 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 55 Adc, VGS = 0 Vdc)


(IS = 55 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


Fig re 14)
(See Figure
((IS = 55 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41104

Motorola TMOS Power MOSFET Transistor Device Data

MTY55N20E
TYPICAL ELECTRICAL CHARACTERISTICS
120

120
VDS 10 V

7V

100

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

8V

VGS = 10 V

TJ = 25C

9V
80
6V
60
40
5V

100
80
60
40
100C

TJ = 55C

20

20
4V
0.5

1.5

2.5

3.5

2.5

3.5

4.5

5.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.05
VGS = 10 V

TJ = 100C

0.04

0.03
25C
0.02
55C
0.01

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

40

60

80

100

120

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

25C
0

6.5

0.027
TJ = 25C
0.026
VGS = 10 V

0.025

0.024
15 V
0.023

0.022

20

40

60

80

100

120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

2
1.75

10000
VGS = 0 V

VGS = 10 V
ID = 27.5 A

1.5

TJ = 125C

1000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.25
1
0.75
0.5

100C

100

10

25C

0.25
0
50

25

25

50

75

100

125

150

50

100

150

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

200

41105

MTY55N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

24000
VDS = 0 V

C, CAPACITANCE (pF)

20000

VGS = 0 V

TJ = 25C

Ciss

16000
Crss

12000

Ciss
8000
Coss
4000
Crss
0
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41106

Motorola TMOS Power MOSFET Transistor Device Data

240

10

200

QT

160

VGS
Q2

120

Q1
TJ = 25C
ID = 55 A

4
2
0

80
40

VDS

Q3
0

50

100

150

0
250

200

1000
VDD = 100 V
ID = 55 A
VGS = 10 V
TJ = 25C
t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY55N20E

100

tr
tf
td(off)

td(on)
10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate Charge versus GatetoSource Voltage

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


60

I S , SOURCE CURRENT (AMPS)

50

VGS = 0 V
TJ = 25C

40
30
20
10
0
0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41107

MTY55N20E
SAFE OPERATING AREA
3000
EAS, SINGLE PULSE DRAINTOSOURCE
AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000
VGS = 20 V
SINGLE PULSE
TC = 25C
100
10 s
100 s

10

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

1
0.1

1 ms
10 ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

dc

10

100

ID = 55 A

2000

1000

1000

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1

P(pk)

0.05
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41108

Motorola TMOS Power MOSFET Transistor Device Data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Data Sheet
TMOS E-FET.
Power Field Effect Transistor
Designer's

MTY100N10E
Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

TMOS POWER FET


100 AMPERES
100 VOLTS
RDS(on) = 0.011 OHM

This advanced TMOS power FET is designed to withstand high


energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.

Avalanche Energy Specified


Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

CASE 340G02, STYLE 1


TO264
S
Symbol

Value

Unit

DrainSource Voltage

VDSS

100

Vdc

DrainGate Voltage (RGS = 1 M)

VDGR

100

Vdc

GateSource Voltage Continuous


GateSource Voltage NonRepetitive (tp 10 ms)

VGS
VGSM

20
40

Vdc
Vpk

Drain Current Continuous @ TC = 25C


Drain Current Single Pulse (tp 10 s)

ID
IDM

100
300

Adc
Apk

Total Power Dissipation


Derate above 25C

PD

300
2.38

Watts
W/C

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C


(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 )

EAS

250

mJ

Thermal Resistance Junction to Case


Thermal Resistance Junction to Ambient

RJC
RJA

0.42
40

C/W

TL

260

Rating

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

41109

MTY100N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

100

115

Vdc
mV/C

10
200

100

nAdc

2.0

Vdc
mV/C

0.011

Ohm

1.0

1.2
1.0

gFS

30

49

mhos

Ciss

7600

10640

pF

Coss

3300

4620

Crss

1200

2400

td(on)

48

96

tr

490

980

td(off)

186

372

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 250 A)
Temperature Coefficient (Positive)

V(BR)DSS

Zero Gate Voltage Drain Current


(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)

VGS(th)

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 50 Adc)

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)


(ID = 100 Adc)
(ID = 50 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1 MHz)

Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time

(VDD = 50 Vdc, ID = 100 Adc,


VGS = 10 Vdc
Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time

ns

tf

384

768

QT

270

378

Q1

50

Q2

150

Q3

118

1
0.9

1.2

trr

145

ta

90

tb

55

QRR

2.34

Internal Drain Inductance


(Measured from the drain lead 0.25 from package to center of die)

LD

4.5

nH

Internal Source Inductance


(Measured from the source lead 0.25 from package to source bond pad)

LS

13

nH

Gate Charge
(S Fi
(See
Figure 8)
((VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)

nC

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage

(IS = 100 Adc, VGS = 0 Vdc)


(IS = 100 Adc, VGS = 0 Vdc, TJ = 125C)

Reverse Recovery Time


(S Figure
Fi
(See
14)
((IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.


(2) Switching characteristics are independent of operating junction temperature.

41110

Motorola TMOS Power MOSFET Transistor Device Data

MTY100N10E
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
9V

160

120

TJ = 25C

8V

7V

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

200

120
6V

80

40

VDS 10 V

100
80
60
40

100C

20

5V

TJ = 55C
25C

10

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

VGS = 10 V
TJ = 100C

0.014
0.012
25C
0.01
0.008
55C
50

150

100

200

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.016

0.006

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.018

10

0.011
TJ = 25C

VGS = 10 V

0.0105
0.01
0.0095

15 V

0.009
0.0085
0.008

50

100

150

200

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


and Temperature

Figure 4. OnResistance versus Drain Current


and Gate Voltage

1.8
1.6

1000000
VGS = 0 V

VGS = 10 V
ID = 50 A

100000
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE


(NORMALIZED)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

1.4
1.2
1

1000

100C

100

25C

10

0.8
0.6
50

TJ = 125C

25

25

50

75

100

125

150

20

40

60

80

100

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with


Temperature

Figure 6. DrainToSource Leakage


Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

120

41111

MTY100N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at


a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

24000
VDS = 0 V

VGS = 0 V
TJ = 25C

C, CAPACITANCE (pF)

20000
Ciss
16000
12000

Crss
Ciss

8000
Coss
4000
Crss
0

10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

41112

Motorola TMOS Power MOSFET Transistor Device Data

120
QT

10

100
VGS

80
Q2

Q1
6

60
TJ = 25C
ID = 100 A

4
2
0

40
20

VDS

Q3
0

50

100

150

0
300

250

200

10000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTY100N10E
VDD = 50 V
ID = 100 A
VGS = 10 V
TJ = 25C

1000

tr
tf
td(off)

100

td(on)
10

10
RG, GATE RESISTANCE (OHMS)

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate Charge versus GatetoSource Voltage

100

Figure 9. Resistive Switching Time


Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

I S , SOURCE CURRENT (AMPS)

100
VGS = 0 V
TJ = 25C

80

60

40

20

0
0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA


The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral
Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

41113

MTY100N10E
SAFE OPERATING AREA
250
VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE


AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10 s

100
100 s
1 ms
10

10 ms
dc

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

1
0.1

10

ID = 100 A
200

150

100

50

100

25

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased


Safe Operating Area

Figure 12. Maximum Avalanche Energy versus


Starting Junction Temperature

1
D = 0.5
0.2
0.1

P(pk)

0.05

0.1
0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE

0.01
1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

RJC(t) = r(t) RJC


D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

41114

Motorola TMOS Power MOSFET Transistor Device Data

Section Five
Surface Mount Package Information
Tape and Reel Specifications

Table of Contents
Page
Surface Mount Package Information . . . . . . . . . . . . . . . . 52
Power Dissipation for a Surface Mount Device . . . . . 52
Solder Stencil Guidelines . . . . . . . . . . . . . . . . . . . . . . . 53
Soldering Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical Solder Heating Profile . . . . . . . . . . . . . . . . . . . 54
Footprints for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . 55
Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . 56
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embossed Tape and Reel Data . . . . . . . . . . . . . . . . . . 57

Motorola TMOS Power MOSFET Transistors Device Data

51

INFORMATION FOR USING SURFACE MOUNT PACKAGES


RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad

geometry, the packages will self align when subjected to a


solder reflow process.

The power dissipation for a surface mount device is a


function of the drain/collector pad size. These can vary from
the minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =

TJ(max) TA
RJA

The values for the equation are found in the maximum


ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25C, one can
calculate the power dissipation of the device. For example, for
a SOT223 device, PD is calculated as follows.

RJA , THERMAL RESISTANCE, JUNCTION


TO AMBIENT (C/W)

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE


160
Board Material = 0.0625
G10/FR4, 2 oz Copper

140

TA = 25C

0.8 Watts
120
1.5 Watts

1.25 Watts*
100

80
0.0

*Mounted on the DPAK footprint


0.2

0.4
0.6
A, AREA (SQUARE INCHES)

0.8

1.0

Figure 1. Thermal Resistance versus Drain Pad


Area for the SOT223 Package (Typical)

The 156C/W for the SOT223 package assumes the use


of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 800 milliwatts. There
are other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the area
of the drain/collector pad. By increasing the area of the
drain/collector pad, the power dissipation can be increased.
Although the power dissipation can almost be doubled with
this method, area is taken up on the printed circuit board which
can defeat the purpose of using surface mount technology.
For example, a graph of RJA versus drain pad area is shown
in Figures 1, 2 and 3.

Another alternative would be to use a ceramic substrate or


an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.

Board Material = 0.0625


G10/FR4, 2 oz Copper
1.75 Watts

80
TA = 25C

60
3.0 Watts

40
5.0 Watts

20
0

4
6
A, AREA (SQUARE INCHES)

10

Figure 2. Thermal Resistance versus Drain Pad


Area for the DPAK Package (Typical)
RJA , THERMAL RESISTANCE, JUNCTION
TO AMBIENT (C/W)

PD = 150C 25C = 800 milliwatts


156C/W

RJA , THERMAL RESISTANCE, JUNCTION


TO AMBIENT (C/W)

100

70
Board Material = 0.0625
G10/FR4, 2 oz Copper
60

TA = 25C

2.5 Watts

50
3.5 Watts
40
5 Watts

30
20

6
8
10
12
A, AREA (SQUARE INCHES)

14

16

Figure 3. Thermal Resistance versus Drain Pad


Area for the D2PAK Package (Typical)

Surface Mount Information


52

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES


Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SOT223,
SO8 and Micro8, the stencil opening should be the same as
the pad size or a 1:1 registration. This is not the case with the
DPAK, D2PAK and D3PAK packages. If a 1:1 opening is used
to screen solder onto the drain pad, misalignment and/or
tombstoning may occur due to an excess of solder. For these
two packages, the opening in the stencil for the paste should
be approximately 50% of the tab area. The opening for the
leads is still a 1:1 registration. Figure 4 shows a typical stencil
for the DPAK, D2PAK and D3PAK packages. The pattern of the
opening in the stencil for the drain pad is not critical as long as

it allows approximately 50% of the pad to be covered with


paste.

SOLDER PASTE
OPENINGS

STENCIL

Figure 4. Typical Stencil for DPAK,


D2PAK and D3PAK Packages

SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and soldering
should be 100C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference should be a maximum of 10C.
The soldering temperature and time should not exceed
260C for more than 10 seconds.

Motorola TMOS Power MOSFET Transistors Device Data

When shifting from preheating to soldering, the maximum


temperature gradient shall be 5C or less.

After soldering has been completed, the device should be


allowed to cool naturally for at least three minutes.
Gradual cooling should be used since the use of forced
cooling will increase the temperature gradient and will
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK and
D3PAK are not recommended for wave soldering.

Surface Mount Information


53

TYPICAL SOLDER HEATING PROFILE


For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make up
a heating profile for that particular circuit board. On machines
controlled by a computer, the computer remembers these
profiles from one operating session to the next. Figure 5 shows
a typical heating profile for use when soldering a surface
mount device to a printed circuit board. This profile will vary
among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
line on the graph shows the actual temperature that might be

STEP 1
PREHEAT
ZONE 1
RAMP
200C

STEP 2
STEP 3
VENT
HEATING
SOAK ZONES 2 & 5
RAMP

DESIRED CURVE FOR HIGH


MASS ASSEMBLIES

experienced on the surface of a test board at or near a central


solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 189C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder
joints.

STEP 4
STEP 5
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SOAK
SPIKE

STEP 6
VENT

STEP 7
COOLING
205 TO 219C
PEAK AT
SOLDER JOINT

170C
160C

150C
150C

100C

SOLDER IS LIQUID FOR


40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)

140C

100C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50C

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 5. Typical Solder Heating Profile

Surface Mount Information


54

Motorola TMOS Power MOSFET Transistor Device Data

Footprints for Soldering


0.15
3.8

0.060
1.52
0.079
2.0

0.275
7.0

0.155
4.0

0.024
0.6

0.091
2.3

0.091
2.3

0.079
2.0

0.050
1.270

0.059
1.5

inches
mm

SO8

0.248
6.3

0.059
1.5

0.059
1.5

inches
mm

SOT223

0.33
8.38
0.165
4.191
0.08
2.032

0.42
10.66

0.24
6.096

0.04
1.016

0.100
2.54

0.118
3.0

0.063
1.6
0.190
4.826

0.243
6.172

0.12
3.05
0.63
17.02

inches
mm
inches

D2PAK

0.531
13.5

DPAK

0.864
21.95

1.04
(0.041)

mm

0.38 8X
(0.015)

8X

0.197
5.0
0.118
3.0

0.653
16.6

0.215
5.45

0.5
12.7
inches

D3PAK

3.20
(0.126)

4.24
(0.167)

5.28
(0.208)

0.65
(0.0256) 6X

mm

Micro8

Motorola TMOS Power MOSFET Transistors Device Data

Surface Mount Information


55

Tape and Reel Specifications


Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the
shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure
cavity for the product when sealed with the peelback cover tape.

Two Reel Sizes Available (7 and 13)


Used for Automatic Pick and Place Feed Systems
Minimizes Product Handling
EIA 481, 1, 2

Micro8, SO8 and SOT223 in 12 mm Tape


DPAK in 16 mm Tape
D2PAK in 24 mm Tape
D3PAK in 24 mm Tape

Use the standard device title and add the required suffix as listed in the option table on the following page. Note that the individual
reels have a finite number of devices depending on the type of product contained in the tape. Also note the minimum lot size is
one full reel for each line item, and orders are required to be in increments of the single reel quantity.

SOT223

SO8

DPAK

12 mm

12 mm

16 mm

D2PAK

D3PAK

Micro8

24 mm

24 mm

12 mm

DIRECTION
OF FEED

EMBOSSED TAPE AND REEL ORDERING INFORMATION

Package

Tape Width
(mm)

Pitch
mm
(inch)

Reel Size
mm
(inch)

Devices Per Reel


and Minimum
Order Quantity

Device
Suffix

DPAK

16

8.0 0.1 (.315 .004)

330

(13)

2,500

T4

D2PAK

24

16.0 0.1 (.630 .004)

330

(13)

800

T4

D3PAK

24

24.0 0.1 (.944 .004)

330

(13)

500

RL

SO8

12
12

8.0 0.1 (.315 .004)

178
330

(7)
(13)

500
2,500

R1
R2

SOT223

12
12

8.0 0.1 (.315 .004)

178
330

(7)
(13)

1,000
4,000

T1
T3

Micro8

12

8.0 0.1 (.315 .004)

330

(13)

4000

R2

Tape and Reel Specifications


56

Motorola TMOS Power MOSFET Transistor Device Data

EMBOSSED TAPE AND REEL DATA FOR DISCRETES


CARRIER TAPE SPECIFICATIONS
P0

P2

10 Pitches Cumulative Tolerance on Tape


0.2 mm
( 0.008)
E

Top Cover
Tape

A0

K0

B1

B0

See
Note 1

For Machine Reference Only


Including Draft and RADII
Concentric Around B0

D1
For Components
2.0 mm x 1.2 mm and Larger

Center Lines
of Cavity

Embossment

User Direction of Feed


* Top Cover Tape
Thickness (t1)
0.10 mm
(.004) Max.

Bar Code Label


R Min
Tape and Components
Shall Pass Around Radius R
Without Damage
Bending Radius
10

Embossed Carrier
100 mm
(3.937)

Maximum Component Rotation

Embossment
1 mm Max

Typical Component
Cavity Center Line
Tape
1 mm
(.039) Max
Typical Component
Center Line

250 mm
(9.843)

Camber (Top View)


Allowable Camber To Be 1 mm/100 mm Nonaccumulative Over 250 mm

DIMENSIONS
Tape
Size

B1 Max

D1

P0

P2

R Min

T Max

W Max

12 mm

8.2 mm
(.323)

1.5 mm Min
(.060)

1.75 0.1 mm
(.069 .004)

5.5 0.05 mm
(.217 .002)

6.4 mm Max
(.252)

4.0 0.1 mm
(.157 .004)

2.0 0.1 mm
(.079 .002)

30 mm
(1.18)

0.6 mm
(.024)

12 .30 mm
(.470 .012)

16 mm

12.1 mm
(.476)

1.5 + 0.1 mm
0.0
(.059
.0 + .004
.004
0.0)

7.5 0.10 mm
(.295 .004)

7.9 mm Max
(.311)

16.3 mm
(.642)

24 mm

20.1 mm
(.791)

11.5 0.1 mm
(.453 .004)

11.9 mm Max
(.468)

24.3 mm
(.957)

Metric dimensions govern English are in parentheses for reference only.


NOTE 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within .05 mm min. to .50 mm max.,
NOTE 1: the component cannot rotate more than 10 within the determined cavity.
NOTE 2: Pitch information is contained in the Embossed Tape and Reel Ordering Information on pg. 56.

Motorola TMOS Power MOSFET Transistors Device Data

Tape and Reel Specifications


57

EMBOSSED TAPE AND REEL DATA FOR DISCRETES

T Max
Outside Dimension
Measured at Edge

1.5 mm Min
(.06)
A

13.0 mm 0.5 mm
(.512 .002)

20.2 mm Min
(.795)

50 mm Min
(1.969)

Full Radius

Size

A Max

12 mm

330 mm
(12.992)

12.4 mm + 2.0 mm, 0.0


(.49 + .079, 0.00)

18.4 mm
(.72)

16 mm

360 mm
(14.173)

16.4 mm + 2.0 mm, 0.0


(.646 + .078, 0.00)

22.4 mm
(.882)

24 mm

360 mm
(14.173)

24.4 mm + 2.0 mm, 0.0


(.961 + .070, 0.00)

30.4 mm
(1.197)

Inside Dimension
Measured Near Hub

T Max

Reel Dimensions
Metric Dimensions Govern English are in parentheses for reference only

Tape and Reel Specifications


58

Motorola TMOS Power MOSFET Transistor Device Data

Section Six
Package Outline Dimensions
and Footprints

Motorola TMOS Power MOSFET Transistors Device Data

Package Outline Dimensions


61

Package Outline Dimensions and Footprints

T
B

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

SEATING
PLANE

F
T

4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

Q
1 2 3

H
K
Z
L

STYLE 5:
PIN 1.
2.
3.
4.

GATE
DRAIN
SOURCE
DRAIN

STYLE 9:
PIN 1.
2.
3.
4.

GATE
COLLECTOR
EMITTER
COLLECTOR

G
D
CASE 221A06
(TO220AB)
ISSUE Y

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

0.15
3.8
0.079
2.0
A
F
0.091
2.3

0.248
6.3

0.091
2.3

B
1

0.079
2.0
D

0.059
1.5

G
J

0.059
1.5

0.059
1.5

inches
mm

SOT223 FOOTPRINT

C
0.08 (0003)

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

K
STYLE 3:
PIN 1.
2.
3.
4.

GATE
DRAIN
SOURCE
DRAIN

CASE 318E04
(SOT223)
ISSUE H

Package Outline Dimensions


62

INCHES
DIM MIN
MAX
A
0.249
0.263
B
0.130
0.145
C
0.060
0.068
D
0.024
0.035
F
0.115
0.126
G
0.087
0.094
H 0.0008 0.0040
J
0.009
0.014
K
0.060
0.078
L
0.033
0.041
M
0_
10 _
S
0.264
0.287

MILLIMETERS
MIN
MAX
6.30
6.70
3.30
3.70
1.50
1.75
0.60
0.89
2.90
3.20
2.20
2.40
0.020
0.100
0.24
0.35
1.50
2.00
0.85
1.05
0_
10 _
6.70
7.30

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)

0.25 (0.010)

Q
T B M

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.

E
B

C
4

U
A

R
1

D
0.25 (0.010)

Y Q

0.25 (0.010)

T B

STYLE 1:
PIN 1.
2.
3.
4.

T
C
E

U
N
A
1

Y
P
K

F 2 PL
G
D

INCHES
MIN
MAX
0.803
0.823
0.608
0.628
0.185
0.205
0.043
0.051
0.059
0.064
0.071
0.086
0.215 BSC
0.101
0.113
0.019
0.027
0.613
0.633
0.286
0.295
0.122
0.133
0.138
0.145
0.130
0.150
0.209 BSC
0.120
0.134

J
H

3 PL

0.25 (0.010)

Y Q

CASE 340G02
(TO264)
ISSUE E

Motorola TMOS Power MOSFET Transistors Device Data

GATE
DRAIN
SOURCE
DRAIN

STYLE 4:
PIN 1.
2.
3.
4.

GATE
COLLECTOR
EMITTER
COLLECTOR

MILLIMETERS
MIN
MAX
20.40
20.90
15.44
15.95
4.70
5.21
1.09
1.30
1.50
1.63
1.80
2.18
5.45 BSC
2.56
2.87
0.48
0.68
15.57
16.08
7.26
7.50
3.10
3.38
3.50
3.70
3.30
3.80
5.30 BSC
3.05
3.40

CASE 340F03
(TO247)
ISSUE E

DIM
A
B
C
D
E
F
G
H
J
K
L
P
Q
R
U
V

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.

DIM
A
B
C
D
E
F
G
H
J
K
L
N
P
Q
R
U
W

MILLIMETERS
MIN
MAX
2.8
2.9
19.3
20.3
4.7
5.3
0.93
1.48
1.9
2.1
2.2
2.4
5.45 BSC
2.6
3.0
0.43
0.78
17.6
18.8
11.0
11.4
3.95
4.75
2.2
2.6
3.1
3.5
2.15
2.35
6.1
6.5
2.8
3.2

STYLE 1:
PIN 1. GATE
2. DRAIN
3. SOURCE

INCHES
MIN
MAX
1.102
1.142
0.760
0.800
0.185
0.209
0.037
0.058
0.075
0.083
0.087
0.102
0.215 BSC
0.102
0.118
0.017
0.031
0.693
0.740
0.433
0.449
0.156
0.187
0.087
0.102
0.122
0.137
0.085
0.093
0.240
0.256
0.110
0.125
STYLE 5:
PIN 1. GATE
2. COLLECTOR
3. EMITTER

Package Outline Dimensions


63

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)


SEATING
PLANE

T
C

B
V

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

R
4

S
1

K
F

J
L

H
D

0.165
4.191

2 PL

0.13 (0.005)

0.100
2.54

INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020

0.030
0.050
0.138

DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z

0.118
3.0

STYLE 2:
PIN 1.
2.
3.
4.

0.063
1.6
0.190
4.826

MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51

0.77
1.27
3.51

0.243
6.172

GATE
DRAIN
SOURCE
DRAIN

inches
mm

DPAK FOOTPRINT
CASE 369A13
(DPAK)
ISSUE W

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

C
E

STYLE 2:
PIN 1.
2.
3.
4.

B
4

DIM
A
B
C
D
E
G
H
J
K
S
V

GATE
DRAIN
SOURCE
DRAIN

A
1

0.33
8.38

T
SEATING
PLANE

INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055

MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40

K
J

G
D

0.08
2.032

3 PL

0.13 (0.005)

0.42
10.66

0.24
6.096

0.04
1.016
0.12
3.05
0.63
17.02
CASE 418B02
(D2PAK)
ISSUE B

Package Outline Dimensions


64

D2PAK FOOTPRINT

inches
mm

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)


SEATING
PLANE

T
B

W
R

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

DIM
A
B
C
D
E
F
G
H
J
K
L
N
P
Q
R
S
U
V
W
X
Y

Y
V
N

U
L

2 PL

D 2 PL
0.13 (0.005)

STYLE 2:
PIN 1.
2.
3.
4.

0.531
13.5

0.864
21.95
0.197
5.0

GATE
DRAIN
SOURCE
DRAIN

INCHES
MIN
MAX
0.588
0.592
0.623
0.627
0.196
0.200
0.048
0.052
0.058
0.062
0.078
0.082
0.430 BSC
0.105
0.110
0.018
0.022
0.150
0.160
0.058
0.062
0.353
0.357
0.078
0.082
0.053
0.057
0.623
0.627
0.313
0.317
0.028
0.032
0.050

0.054
0.058
0.050
0.060
0.104
0.108

MILLIMETERS
MIN
MAX
14.94
15.04
15.82
15.93
4.98
5.08
1.22
1.32
1.47
1.57
1.98
2.08
1.092 BSC
2.67
2.79
0.46
0.56
3.81
4.06
1.47
1.57
8.97
9.07
1.98
2.08
1.35
1.45
15.82
15.93
7.95
8.05
0.71
0.81
1.27

1.37
1.47
1.27
1.52
2.64
2.74

0.118
3.0
0.653
16.6

0.215
5.45

inches

0.5
12.7

mm

D3PAK FOOTPRINT
CASE 43301
ISSUE B

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

B
1

F
A

NOTE 2

C
J

T
N

SEATING
PLANE

D
H

G
0.13 (0.005)

T A

DIM
A
B
C
D
F
G
H
J
K
L
M
N

MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC

10_
0.76
1.01

STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC

10_
0.030
0.040

AC IN
DC + IN
DC IN
AC IN
GROUND
OUTPUT
AUXILIARY
VCC

CASE 62605
ISSUE K

Motorola TMOS Power MOSFET Transistors Device Data

Package Outline Dimensions


65

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)

14

NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.

A
F

DIM
A
B
C
D
F
G
H
J
K
L
M
N

L
C
J

N
H

SEATING
PLANE

K
M

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039

MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01

CASE 64606
ISSUE L

28

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

15

DIM
A
B
C
D
F
G
H
J
K
L
M
N

14

A
N

F
D

SEATING
PLANE

MILLIMETERS
MIN
MAX
36.45
37.21
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02

INCHES
MIN
MAX
1.435
1.465
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040

CASE 71002
ISSUE B

Package Outline Dimensions


66

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)

A
M
1
4

0.25 (0.010)

4X

X 45 _

B
M

NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.

M_
G

DIM
A
B
C
D
F
G
J
K
M
P
R

T
K

SEATING
PLANE
8X

D
0.25 (0.010)

STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1

STYLE 12:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN

T B

STYLE 13:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN

STYLE 14:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

NSOURCE
NGATE
PSOURCE
PGATE
PDRAIN
PDRAIN
NDRAIN
NDRAIN

0.060
1.52

0.275
7.0

0.155
4.0

0.024
0.6

0.050
1.270

inches
mm

SO8 FOOTPRINT
CASE 75105
(SO8)
ISSUE P

Motorola TMOS Power MOSFET Transistors Device Data

Package Outline Dimensions


67

PACKAGE OUTLINE DIMENSIONS AND FOOTPRINTS (continued)

A
16

8X

P
0.010 (0.25)

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

16X

0.010 (0.25)

T A

F
DIM
A
B
C
D
F
G
J
K
M
P
R

R X 45 _
C
T
14X

SEATING
PLANE

MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75

INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029

CASE 751G02
ISSUE A

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION D DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

PIN 1 ID

DIM
A
B
C
D
G
H
J
K
L

MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10

1.10
0.25
0.40
0.65 BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70

INCHES
MIN
MAX
0.114
0.122
0.114
0.122

0.043
0.010
0.016
0.026 BSC
0.002
0.006
0.005
0.009
0.187
0.199
0.016
0.028

G
D 8 PL
0.08 (0.003)

T B

0.38 8X
(0.015)

1.04
(0.041)
8X

SEATING
PLANE

0.038 (0.0015)

C
J

H
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN

STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.

3.20
(0.126)

SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1

5.28
(0.208)

0.65
(0.0256) 6X
CASE 846A02
ISSUE B

Package Outline Dimensions


68

4.24
(0.167)

MICRO8 FOOTPRINT

Motorola TMOS Power MOSFET Transistor Device Data

H
B

Q
G
M N

D
E
F
Recommended screw torque: 1.3
Maximum screw torque: 1.5 Nm

" 0.2 Nm
SOT227B

Motorola TMOS Power MOSFET Transistors Device Data

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.

DIM
A
B
C
D
E
F
G
H
L
M
N
P
Q
R
S

MILLIMETERS
MIN
MAX
31.50
31.70
7.80
8.20
4.10
4.30
14.90
15.10
30.10
30.30
38.00
38.20
4.00

11.80
12.20
8.90
9.10
12.60
12.80
25.20
25.40
1.95
2.05
4.10

0.75
0.85
5.50

STYLE 1:
PIN 1.
2.
3.
4.

INCHES
MIN
MAX
1.240
1.248
0.307
0.322
0.161
0.169
0.586
0.590
1.185
1.193
1.496
1.503
0.157

0.464
0.480
0.350
0.358
0.496
0.503
0.992
1.000
0.076
0.080
0.157

0.030
0.033
0.217

SOURCE
GATE
DRAIN
SOURCE 2

Package Outline Dimensions


69

Package Outline Dimensions


610

Motorola TMOS Power MOSFET Transistor Device Data

Section Seven
Distributors and Sales Offices

Motorola TMOS Power MOSFET Transistors Device Data

Distributors and Sales Offices


71

5/1/96

MOTOROLA AUTHORIZED DISTRIBUTOR & WORLDWIDE SALES OFFICES


NORTH AMERICAN DISTRIBUTORS
FAI . . . . . . . . . . . . . . . . . . . . . . . . (408)4340369
Future Electronics . . . . . . . . . . . . (408)4341122

UNITED STATES
ALABAMA
Huntsville

Santa Clara

Arrow/Schweber Electronics . . . (205)8376955


FAI . . . . . . . . . . . . . . . . . . . . . . . . (205)8379209
Future Electronics . . . . . . . . . . . (205)8302322
Hamilton/Hallmark . . . . . . . . . . . (205)8378700
Newark . . . . . . . . . . . . . . . . . . . . (205)8379091
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (205)8301119

ARIZONA
Phoenix

Sierra Madre
PENSTOCK . . . . . . . . . . . . . . . . (818)3556775

Sunnyvale
Hamilton/Hallmark . . . . . . . . . . . (408)4353500
PENSTOCK . . . . . . . . . . . . . . . . (408)7300300
Time Electronics . . . . . . . . . . 1800789TIME

Thousand Oaks
Newark . . . . . . . . . . . . . . . . . . . . (805)4491480

FAI . . . . . . . . . . . . . . . . . . . . . . . . (602)7314661
Future Electronics . . . . . . . . . . . (602)9687140
Hamilton/Hallmark . . . . . . . . . . . . (602)4143000
Wyle Electronics . . . . . . . . . . . . (602)8047000

Tempe
Arrow/Schweber Electronics . . . (602)4310030
Newark . . . . . . . . . . . . . . . . . . . . (602)9666340
PENSTOCK . . . . . . . . . . . . . . . . (602)9671620
Time Electronics . . . . . . . . . . 1800789TIME

CALIFORNIA
Agoura Hills

Torrance
Time Electronics . . . . . . . . . . 1800789TIME

Tustin
Time Electronics . . . . . . . . . . 1800789TIME

Woodland Hills
Hamilton/Hallmark . . . . . . . . . . . (818)5940404
Richardson Electronics . . . . . . (615)5945600

COLORADO
Lakewood

Belmont
Richardson Electronics . . . . . . (415)5929225

Calabassas
Arrow/Schweber Electronics . . . (818)8809686
Wyle Electronics . . . . . . . . . . . . (818)8809000

FAI . . . . . . . . . . . . . . . . . . . . . . . . (303)2371400
Future Electronics . . . . . . . . . . . (303)2322008
Newark . . . . . . . . . . . . . . . . . . . . (303)3734540

Englewood
Arrow/Schweber Electronics . . . (303)7990258
Hamilton/Hallmark . . . . . . . . . . (303)7901662
PENSTOCK . . . . . . . . . . . . . . . . (303)7997845
Time Electronics . . . . . . . . . . 1800789TIME

Thornton
Wyle Electronics . . . . . . . . . . . . (303)4579953

Chatsworth
Time Electronics . . . . . . . . . . 1800789TIME

Costa Mesa
Hamilton/Hallmark . . . . . . . . . . . (714)7894100

CONNECTICUT
Bloomfield

Hamilton/Hallmark . . . . . . . . . . . (310)5582000

Garden Grove
Newark . . . . . . . . . . . . . . . . . . . . (7148934909

Irvine

Newark . . . . . . . . . . . . . . . . . . . . (203)2431731
FAI . . . . . . . . . . . . . . . . . . . . . . . . (203)2501319
Future Electronics . . . . . . . . . . . (203)2500083
Hamilton/Hallmark . . . . . . . . . . (203)2712844

Southbury
(714)5870404
(714)7534778
(714)4531515
(714)7539953
(714)8639953

Los Angeles
FAI . . . . . . . . . . . . . . . . . . . . . . . . (818)8791234
Wyle Electronics . . . . . . . . . . . . (818)8809000

Manhattan Beach
PENSTOCK . . . . . . . . . . . . . . . . (310)5468953

Mountain View
Richardson Electronics . . . . . . (415)9606900

Newberry Park
PENSTOCK . . . . . . . . . . . . . . . . (805)3756680

Palo Alto
Newark . . . . . . . . . . . . . . . . . . . . (415)8126300

Riverside
Newark . . . . . . . . . . . . . . . . . . . . . (909)7841101

Rocklin
Hamilton/Hallmark . . . . . . . . . . (916)6324500

Sacramento
FAI . . . . . . . . . . . . . . . . . . . . . . . . (916)7827882
Newark . . . . . . . . . . . . . . . . . . . . (916)5651760
Wyle Electronics . . . . . . . . . . . . (916)6385282

San Diego
Arrow/Schweber Electronics . . (619)5654800
FAI . . . . . . . . . . . . . . . . . . . . . . . . (619)6232888
Future Electronics . . . . . . . . . . . (619)6252800
Hamilton/Hallmark . . . . . . . . . . . (619)5717540
Newark . . . . . . . . . . . . . . . . . . . . . (619)4538211
PENSTOCK . . . . . . . . . . . . . . . . (619)6239100
Wyle Electronics . . . . . . . . . . . . (619)5659171

San Jose
Arrow/Schweber Electronics . . . (408)4419700
Arrow/Schweber Electronics . . . (408)4286400

Distributors and Sales Offices


72

Duluth
Arrow/Schweber Electronics . . . (404)4971300
Hamilton/Hallmark . . . . . . . . . . (404)6234400

Norcross
Future Electronics . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . .
PENSTOCK . . . . . . . . . . . . . . . .
Wyle Electronics . . . . . . . . . . . .

(770)4417676
(770)4481300
(770)7349990
(770)4419045

IDAHO
Boise
FAI . . . . . . . . . . . . . . . . . . . . . . . . (208)3768080

ILLINOIS
Addison
Wyle Laboratories . . . . . . . . . . . (708)6200969
Hamilton/Hallmark . . . . . . . . . . . (708)7977322

Chicago
FAI . . . . . . . . . . . . . . . . . . . . . . . . (708)8430034
Newark Electronics Corp. . . . . (312)7845100

Hoffman Estates
Future Electronics . . . . . . . . . . . (708)8821255

Itasca
Arrow/Schweber Electronics . . (708)2500500

LaFox
Richardson Electronics . . . . . . (708)2082401

Palatine
PENSTOCK . . . . . . . . . . . . . . . . (708)9343700

Schaumburg

Cheshire

Culver City

FAI . . . . . . . . . . . . . . . . . . . . . . . . (404)4474767
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . (404)4419045

Bensenville

Denver

Future Electronics . . . . . . . . . . . (818)8650040


Time Electronics Corporate . . 1800789TIME

Arrow/Schweber Electronics . .
FAI . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . .
Wyle Laboratories Corporate . . .
Wyle Electronics . . . . . . . . . . . .

Wyle Electronics . . . . . . . . . . . . (408)7272500

GEORGIA
Atlanta

Time Electronics . . . . . . . . . . 1800789TIME

Wallingfort
Arrow/Schweber Electronics . . . (203)2657741

FLORIDA
Altamonte Springs

Newark . . . . . . . . . . . . . . . . . . . . (708)3108980
Time Electronics . . . . . . . . . . 1800789TIME

INDIANA
Indianapolis
Arrow/Schweber Electronics . . . (317)2992071
Hamilton/Hallmark . . . . . . . . . . (317)5753500
FAI . . . . . . . . . . . . . . . . . . . . . . . . (317)4690441
Future Electronics . . . . . . . . . . . (317)4690447
Newark . . . . . . . . . . . . . . . . . . . . (317)2590085
Time Electronics . . . . . . . . . . 1800789TIME

Ft. Wayne

Future Electronics . . . . . . . . . . . (407)8657900

Clearwater
FAI . . . . . . . . . . . . . . . . . . . . . . . . (813)5301665
Future Electronics . . . . . . . . . . . (813)5301222

Deerfield Beach
Arrow/Schweber Electronics . . . (305)4298200
Wyle Electronics . . . . . . . . . . . . (305)4200500

Ft. Lauderdale
FAI . . . . . . . . . . . . . . . . . . . . . . . . (305)4289494
Future Electronics . . . . . . . . . . . (305)4364043
Hamilton/Hallmark . . . . . . . . . . . (305)4845482
Newark . . . . . . . . . . . . . . . . . . . . . (305)4861151
Time Electronics . . . . . . . . . . 1800789TIME

Lake Mary
Arrow/Schweber Electronics . . . (407)3339300

Largo/Tampa/St. Petersburg
Hamilton/Hallmark . . . . . . . . . . . (813)5475000
Newark . . . . . . . . . . . . . . . . . . . . (813)2871578
Wyle Electronics . . . . . . . . . . . . (813)5763004
Time Electronics . . . . . . . . . . 1800789TIME

Orlando
FAI . . . . . . . . . . . . . . . . . . . . . . . . (407)8659555

Tallahassee
FAI . . . . . . . . . . . . . . . . . . . . . . . . (904)6687772

Tampa
PENSTOCK . . . . . . . . . . . . . . . . (813)2477556

Winter Park
Hamilton/Hallmark . . . . . . . . . . (407)6573300
PENSTOCK . . . . . . . . . . . . . . . . . (407)6721114
Richardson Electronics . . . . . . (407)6441453

Newark . . . . . . . . . . . . . . . . . . . . (219)4840766
PENSTOCK . . . . . . . . . . . . . . . . (219)4321277

IOWA
Cedar Rapids
Newark . . . . . . . . . . . . . . . . . . . . (319)3933800
Time Electronics . . . . . . . . . . 1800789TIME

KANSAS
Kansas City
FAI . . . . . . . . . . . . . . . . . . . . . . . . (913)3816800

Lenexa
Arrow/Schweber Electronics . . . (913)5419542
Hamilton/Hallmark . . . . . . . . . . (913)6637900

Olathe
PENSTOCK . . . . . . . . . . . . . . . . (913)8299330

Overland Park
Future Electronics . . . . . . . . . . . (913)6491531
Newark . . . . . . . . . . . . . . . . . . . . (913)6770727
Time Electronics . . . . . . . . . . 1800789TIME

MARYLAND
Baltimore
FAI . . . . . . . . . . . . . . . . . . . . . . . . (410)3120833

Columbia
Arrow/Schweber Electronics . . . (301)5967800
Future Electronics . . . . . . . . . . . (410)2900600
Hamilton/Hallmark . . . . . . . . . . (410)7203400
Time Electronics . . . . . . . . . . 1800789TIME
PENSTOCK . . . . . . . . . . . . . . . . (410)2903746
Wyle Electronics . . . . . . . . . . . . (410)3124844

Hanover
Newark . . . . . . . . . . . . . . . . . . . . (410)7126922

Motorola TMOS Power MOSFET Transistor Device Data

5/1/96

AUTHORIZED DISTRIBUTORS continued


UNITED STATES continued
MASSACHUSETTS
Boston
Arrow/Schweber Electronics . . . (508)6580900
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (508)7793111

Bolton
Future Corporate . . . . . . . . . . . . (508)7793000

Burlington
PENSTOCK . . . . . . . . . . . . . . . . (617)2299100
Wyle Electronics . . . . . . . . . . . . (617)2719953

Norwell
Richardson Electronics . . . . . . (617)8715162

Peabody
Time Electronics . . . . . . . . . . 1800789TIME
Hamilton/Hallmark . . . . . . . . . . (508)5329893

Woburn
Newark . . . . . . . . . . . . . . . . . . . . (617)9358350

MICHIGAN
Detroit
FAI . . . . . . . . . . . . . . . . . . . . . . . . (313)5130015
Future Electronics . . . . . . . . . . . (616)6986800

Grand Rapids
Newark . . . . . . . . . . . . . . . . . . . . (616)9546700

Livonia
Arrow/Schweber Electronics . . . (810)4550850
Future Electronics . . . . . . . . . . . (313)2615270
Hamilton/Hallmark . . . . . . . . . . (313)4165800
Time Electronics . . . . . . . . . . 1800789TIME

Troy
Newark . . . . . . . . . . . . . . . . . . . . (810)5832899

MINNESOTA
Bloomington
Wyle Electronics . . . . . . . . . . . . . . (612)8532280

Burnsville
PENSTOCK . . . . . . . . . . . . . . . . . (612)8827630

Eden Prairie
Arrow/Schweber Electronics . . . (612)9415280
FAI . . . . . . . . . . . . . . . . . . . . . . . . (612)9470909
Future Electronics . . . . . . . . . . . (612)9442200
Hamilton/Hallmark . . . . . . . . . . (612)8812600
Time Electronics . . . . . . . . . . 1800789TIME

Minneapolis
Newark . . . . . . . . . . . . . . . . . . . . (612)3316350

Earth City
Hamilton/Hallmark . . . . . . . . . . (314)2915350

MISSOURI
St. Louis
Arrow/Schweber Electronics . . . (314)5676888
Future Electronics . . . . . . . . . . . (314)4696805
FAI . . . . . . . . . . . . . . . . . . . . . . . . (314)5429922
Newark . . . . . . . . . . . . . . . . . . . . (314)4539400
Time Electronics . . . . . . . . . . 1800789TIME

NEW JERSEY
Bridgewater
PENSTOCK . . . . . . . . . . . . . . . . (908)5759490

Cherry Hill
Hamilton/Hallmark . . . . . . . . . . . . (609)4240110

East Brunswick
Newark . . . . . . . . . . . . . . . . . . . . (908)9376600

Fairfield
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (201)3311133

Long Island
FAI . . . . . . . . . . . . . . . . . . . . . . . . (516)3483700

Marlton
Arrow/Schweber Electronics . . . (609)5968000
FAI . . . . . . . . . . . . . . . . . . . . . . . . (609)9881500
Future Electronics . . . . . . . . . . . (609)5964080

Pinebrook
Arrow/Schweber Electronics . . . (201)2277880
Wyle Electronics . . . . . . . . . . . . . (201)8828358

Parsippany
Future Electronics . . . . . . . . . . . (201)2990400
Hamilton/Hallmark . . . . . . . . . . (201)5151641

Wayne
Time Electronics . . . . . . . . . . 1800789TIME

Hamilton/Hallmark . . . . . . . . . . (503)5266200
Wyle Electronics . . . . . . . . . . . . (503)6437900

NEW MEXICO
Albuquerque
Alliance Electronics . . . . . . . . . (505)2923360
Hamilton/Hallmark . . . . . . . . . . . (505)8281058
Newark . . . . . . . . . . . . . . . . . . . . (505)8281878

NEW YORK
Bohemia
Newark . . . . . . . . . . . . . . . . . . . . (516)5674200

Hauppauge
Arrow/Schweber Electronics . . .
Future Electronics . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . .
PENSTOCK . . . . . . . . . . . . . . . .

(516)2311000
(516)2344000
(516)4347400
(516)7249580

Konkoma
Hamilton/Hallmark . . . . . . . . . . (516)7370600

Melville
Wyle Laboratories . . . . . . . . . . . (516)2938446

Pittsford
Newark . . . . . . . . . . . . . . . . . . . . (716)3814244

Rochester
Arrow/Schweber Electronics . . . (716)4270300
Future Electronics . . . . . . . . . . . (716)3879550
FAI . . . . . . . . . . . . . . . . . . . . . . . . (716)3879600
Hamilton/Hallmark . . . . . . . . . . . (716)2722740
Richardson Electronics . . . . . . . (716)2641100
Time Electronics . . . . . . . . . . 1800789TIME

Rockville Centre
Richardson Electronics . . . . . . (516)8724400

Syracuse
FAI . . . . . . . . . . . . . . . . . . . . . . . . (315)4514405
Future Electronics . . . . . . . . . . . (315)4512371
Newark . . . . . . . . . . . . . . . . . . . . (315)4574873
Time Electronics . . . . . . . . . . 1800789TIME

NORTH CAROLINA
Charlotte
FAI . . . . . . . . . . . . . . . . . . . . . . . . (704)5489503
Future Electronics . . . . . . . . . . . . (704)5471107
Richardson Electronics . . . . . . (704)5489042

Raleigh
Arrow/Schweber Electronics . . . (919)8763132
FAI . . . . . . . . . . . . . . . . . . . . . . . . (919)8760088
Future Electronics . . . . . . . . . . . . (919)7907111
Hamilton/Hallmark . . . . . . . . . . (919)8720712
Newark . . . . . . . . . . . . . . . . . . . . (919)7817677
Time Electronics . . . . . . . . . . 1800789TIME

OHIO
Centerville
Arrow/Schweber Electronics . . . (513)4355563

Cleveland
FAI . . . . . . . . . . . . . . . . . . . . . . . . (216)4460061
Newark . . . . . . . . . . . . . . . . . . . . (216)3919330
Time Electronics . . . . . . . . . . 1800789TIME

Columbus
Newark . . . . . . . . . . . . . . . . . . . . (614)3260352
Time Electronics . . . . . . . . . . 1800789TIME

Dayton
FAI . . . . . . . . . . . . . . . . . . . . . . . . (513)4276090
Future Electronics . . . . . . . . . . . (513)4260090
Hamilton/Hallmark . . . . . . . . . . (513)4396735
Newark . . . . . . . . . . . . . . . . . . . . (513)2948980
Time Electronics . . . . . . . . . . 1800789TIME

Mayfield Heights
Future Electronics . . . . . . . . . . . (216)4496996

Solon
Arrow/Schweber Electronics . . . (216)2483990
Hamilton/Hallmark . . . . . . . . . . . (216)4981100

Worthington
Hamilton/Hallmark . . . . . . . . . . (614)8883313

OKLAHOMA
Tulsa
FAI . . . . . . . . . . . . . . . . . . . . . . . . (918)4921500
Hamilton/Hallmark . . . . . . . . . . (918)4596000
Newark . . . . . . . . . . . . . . . . . . . . (918)2525070

OREGON
Beaverton
Arrow/Almac Electronics Corp. . (503)6298090
Future Electronics . . . . . . . . . . . (503)6459454

Motorola TMOS Power MOSFET Transistors Device Data

Portland
FAI . . . . . . . . . . . . . . . . . . . . . . . . (503)2975020
Newark . . . . . . . . . . . . . . . . . . . . (503)2971984
PENSTOCK . . . . . . . . . . . . . . . . (503)6461670
Time Electronics . . . . . . . . . . 1800789TIME

PENNSYLVANIA
Coatesville
PENSTOCK . . . . . . . . . . . . . . . . (610)3839536

Ft. Washington
Newark . . . . . . . . . . . . . . . . . . . . (215)6541434

Mt. Laurel
Wyle Electronics . . . . . . . . . . . . . (609)4399110

Montgomeryville
Richardson Electronics . . . . . . (215)6280805

Philadelphia
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (609)4399110

Pittsburgh
Arrow/Schweber Electronics . . . (412)9636807
Newark . . . . . . . . . . . . . . . . . . . . (412)7884790
Time Electronics . . . . . . . . . . 1800789TIME

TENNESSEE
Franklin
Richardson Electronics . . . . . . (615)7914900

Knoxville
Newark . . . . . . . . . . . . . . . . . . . . (615)5886493

TEXAS
Austin
Arrow/Schweber Electronics . . . (512)8354180
Future Electronics . . . . . . . . . . . (512)5020991
FAI . . . . . . . . . . . . . . . . . . . . . . . . (512)3466426
Hamilton/Hallmark . . . . . . . . . . (512)2193700
Newark . . . . . . . . . . . . . . . . . . . . (512)3380287
PENSTOCK . . . . . . . . . . . . . . . . (512)3469762
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . (512)8339953

Benbrook
PENSTOCK . . . . . . . . . . . . . . . . (817)2490442

Carollton
Arrow/Schweber Electronics . . . (214)3806464

Dallas
FAI . . . . . . . . . . . . . . . . . . . . . . . . (214)2317195
Future Electronics . . . . . . . . . . . (214)4372437
Hamilton/Hallmark . . . . . . . . . . (214)5534300
Newark . . . . . . . . . . . . . . . . . . . . (214)4582528
Richardson Electronics . . . . . . (214)2393680
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . (214)2359953

El Paso
FAI . . . . . . . . . . . . . . . . . . . . . . . . (915)5779531

Ft. Worth
Allied Electronics . . . . . . . . . . . . (817)3365401

Houston
Arrow/Schweber Electronics . . . (713)6476868
FAI . . . . . . . . . . . . . . . . . . . . . . . . (713)9527088
Future Electronics . . . . . . . . . . . . (713)7851155
Hamilton/Hallmark . . . . . . . . . . (713)7816100
Newark . . . . . . . . . . . . . . . . . . . . (713)8949334
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . (713)8799953

Richardson
PENSTOCK . . . . . . . . . . . . . . . . (214)4799215

San Antonio
FAI . . . . . . . . . . . . . . . . . . . . . . . . (210)7383330

UTAH
Salt Lake City
Arrow/Schweber Electronics . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . .
Wyle Electronics . . . . . . . . . . . .

(801)9736913
(801)4679696
(801)4674448
(801)2662022
(801)2615660
(801)9749953

West Valley City


Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . (801)9749953

Distributors and Sales Offices


73

5/1/96

AUTHORIZED DISTRIBUTORS continued


UNITED STATES continued

CANADA
ALBERTA
Calgary

WASHINGTON
Bellevue
Almac Electronics Corp. . . . . .
Newark . . . . . . . . . . . . . . . . . . . .
PENSTOCK . . . . . . . . . . . . . . . .
Richardson Electronics . . . . . .

(206)6439992
(206)6419800
(206)4542371
(206)6467224

Mississauga
PENSTOCK . . . . . . . . . . . . . . . . (905)4030724

Ottawa

Electro Sonic Inc. . . . . . . . . . . (403)2559550


FAI . . . . . . . . . . . . . . . . . . . . . . . . (403)2915333

Arrow Electronics . . . . . . . . . . .
Electro Sonic Inc. . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . .

BRITISH COLUMBIA
Future Electronics . . . . . . . . . . . (403)2505550
Hamilton/Hallmark . . . . . . . . . . . (800)6635500

Edmonton

Bothell
Future Electronics . . . . . . . . . . . (206)4893400

Redmond
Hamilton/Hallmark . . . . . . . . . . . (206)8827000
Time Electronics . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (206)8811150

Toronto

FAI . . . . . . . . . . . . . . . . . . . . . . . . (403)4385888
Future Electronics . . . . . . . . . . . (403)4382858
Hamilton/Hallmark . . . . . . . . . . (800)6635500

Arrow Electronics . . . . . . . . . . .
Electro Sonic Inc. . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . .
Richardson Electronics . . . . . .

Saskatchewan
Hamilton/Hallmark . . . . . . . . . . (800)6635500

Vancouver

Seattle
FAI . . . . . . . . . . . . . . . . . . . . . . . . (206)4856616
Wyle Electronics . . . . . . . . . . . . . . (206)8811150

WISCONSIN
Brookfield
Arrow/Schweber Electronics . . . (414)7920150
Future Electronics . . . . . . . . . . . (414)8790244
Wyle Electronics . . . . . . . . . . . . (414)5219333

Milwaukee
FAI . . . . . . . . . . . . . . . . . . . . . . . . (414)7929778
Time Electronics . . . . . . . . . . 1800789TIME

New Berlin
Hamilton/Hallmark . . . . . . . . . . (414)7807200

Wauwatosa
Newark . . . . . . . . . . . . . . . . . . . . (414)4539100

Arrow Electronics . . . . . . . . . . . (604)4212333


Electro Sonic Inc. . . . . . . . . . . . . (604)2732911
FAI . . . . . . . . . . . . . . . . . . . . . . . . (604)6541050
Future Electronics . . . . . . . . . . . . (604)2941166
Hamilton/Hallmark . . . . . . . . . . . (604)4204101

(905)6707769
(416)4941666
(905)6129888
(905)6129200
(905)5646060
(905)6702888
(905)7956300

QUEBEC
Montreal

MANITOBA
Winnipeg
Electro Sonic Inc. . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . .

(613)2266903
(613)7288333
(613)8208244
(613)8208313
(613)2261700

(204)7833105
(204)7863075
(204)9441446
(800)6635500

ONTARIO
Kanata
PENSTOCK . . . . . . . . . . . . . . . . (613)5926088

Arrow Electronics . . . . . . . . . . . . (514)4217411


FAI . . . . . . . . . . . . . . . . . . . . . . . . (514)6948157
Future Electronics . . . . . . . . . . . (514)6947710
Hamilton/Hallmark . . . . . . . . . . . (514)3351000
Richardson Electronics . . . . . . (514)7481770

Quebec City
Arrow Electronics . . . . . . . . . . . (418)6874231
FAI . . . . . . . . . . . . . . . . . . . . . . . . (418)6825775
Future Electronics . . . . . . . . . . . (418)8776666

INTERNATIONAL DISTRIBUTORS
AUSTRALIA
AVNET VSI Electronics (Australia) . . . . . . . (61)2
8781299
Veltek Australia Pty Ltd . . . . . (61)3 95749300

AUSTRIA
EBV Austria . . . . . . . . . . . . . . . . (43) 1 8941774
Elbatex GmbH . . . . . . . . . . . . . . . . (43) 1 866420
Spoerle Austria . . . . . . . . . . . . (43) 1 31872700

BELGIUM
Diode Spoerle . . . . . . . . . . . . . . (32) 2 725 4660
EBV Belgium . . . . . . . . . . . . . . . (32) 2 716 0010

CHINA
Advanced Electronics Ltd. . . . (852)2 3053633
AVNET WKK Components Ltd. (852)2 3578888
China El. App. Corp. Xiamen Co
. . . . . . . . . . . . . . . . . . . . . . . . (86)592 5132489
Nanco Electronics Supply Ltd. . . . . . . . . (852) 2
3335121
Qing Cheng Enterprises Ltd. (852) 2 4934202

DENMARK
Arrow Exatec . . . . . . . . . . . . . . (45) 44 927000
Avnet Nortec A/S . . . . . . . . . . . (45) 44 880800
EBV Denmark . . . . . . . . . . . . . . . (45) 39690511

ESTONIA
Arrow Field Eesti . . . . . . . . . . . . . (372) 6503288
Avnet Baltronic . . . . . . . . . . . . . . (372) 6397000

FINLAND
Arrow Field OY . . . . . . . . . . . . . (35) 807 775 71
Avnet Nortec OY . . . . . . . . . . . . (35) 806 13181

FRANCE
Arrow Electronique . . . . . . . . (33) 1 49 78 49 78
Avnet Components . . . . . . . . (33) 1 49 65 25 00
EBV France . . . . . . . . . . . . . . (33) 1 64 68 86 00
Future Electronics . . . . . . . . . . . (33)1 69821111
Newark . . . . . . . . . . . . . . . . . . . (33)130954060
SEI/Scaib . . . . . . . . . . . . . . . . (33) 1 69 19 89 00

Distributors and Sales Offices


74

GERMANY

NORWAY

Avnet E2000 . . . . . . . . . . . . . . (49) 89 4511001


EBV Elektronik GmbH . . . . . . (49) 89 991140
Future Electronics GmbH . . . (49) 89957 270
Jermyn GmbH . . . . . . . . . . . . . . (49) 64315080
Newark . . . . . . . . . . . . . . . . . . . (49)215470011
Sasco Semiconductor . . . . . . . . (49) 8946110
Spoerle Electronic . . . . . . . . . . (49) 61033040

HOLLAND
EBV Holland . . . . . . . . . . . . . . (31) 3465 623 53
Diode Spoerle BV . . . . . . . . . . . (31) 4054 5430

HONG KONG
AVNET WKK Components Ltd. (852)2 3578888
Nanshing Clr. & Chem. Co. Ltd (852)2 3335121

INDIA
Canyon Products Ltd . . . . . . (91) 80 5587758

Arrow Tahonic A/S . . . . . . . . . . . (47)2237 8440


Avnet Nortec A/S Norway . . . . (47) 66 846210

PHILIPPINES
Alexan Commercial . . . . . . . . . (63) 22419493

SINGAPORE
Future Electronics . . . . . . . . . . . . (65) 4791300
Strong Pte. Ltd . . . . . . . . . . . . . . (65) 2763996
Uraco Technologies Pte Ltd. . . . (65) 5457811

SPAIN
Amitron Arrow . . . . . . . . . . . . . (34) 1 304 30 40
EBV Spain . . . . . . . . . . . . . . . . (34) 1 804 32 56
Selco S.A. . . . . . . . . . . . . . . . . (34) 1 637 10 11

SWEDEN
ArrowTh:s . . . . . . . . . . . . . . . . . . (46) 8 362970
Avnet Nortec AB . . . . . . . . . . . (46) 8 629 14 00

SWITZERLAND

INDONESIA
P.T. Ometraco . . . . . . . . . . . . (62) 21 6196166

ITALY
Avnet Adelsy SpA . . . . . . . . . . . . . (39) 2 381901
EBV Italy . . . . . . . . . . . . . . . . . . . . (39) 2 660961
Silverstar SpA . . . . . . . . . . . . . . (39) 2 66 12 51

JAPAN
AMSC Co., Ltd. . . . . . . . . . . . 81422546800
Fuji Electronics Co., Ltd. . . . . 81338141411
Marubun Corporation . . . . . . 81336398951
Nippon Motorola Micro Elec. . 81332807300
OMRON Corporation . . . . . . 81337799053
Tokyo Electron Ltd. . . . . . . . . 81355617254

EBV Switzerland . . . . . . . . . . . . (41) 1 7456161


Elbatex AG . . . . . . . . . . . . . . . . . (41) 56 4375111
Spoerle . . . . . . . . . . . . . . . . . . . . (41) 1 8746262

S. AFRICA
Advanced . . . . . . . . . . . . . . . . . (27) 11 4442333
Reuthec Components . . . . . . (27) 11 8233357

THAILAND
Shapiphat Ltd. . . (66)22210432 or 22215384

TAIWAN
AvnetMercuries Co., Ltd . . . (886)2 5167303
Solomon Technology Corp. . . . (886)2 7888989
Strong Electronics Co. Ltd. . . (886)2 9179917

UNITED KINGDOM

KOREA
Jung Kwang Sa . . . . . . . . . . . . . (82)22785333
LiteOn Korea Ltd. . . . . . . . . . . (82)28583853
Nasco Co. Ltd. . . . . . . . . . . . . . (82)237726800

NEW ZEALAND
AVNET VSI (NZ) Ltd . . . . . . . . . (64)9 6367801

Arrow Electronics (UK) Ltd . (44) 1 234 270027


Avnet/Access . . . . . . . . . . . . . (44) 1 462 488500
Future Electronics Ltd. . . . . . (44) 1 753 763000
Macro Marketing Ltd. . . . . . . . (44) 1 628 60600
Newark . . . . . . . . . . . . . . . . . . (44) 1 420 543333

Motorola TMOS Power MOSFET Transistor Device Data

5/1/96

MOTOROLA WORLDWIDE SALES OFFICES


Colmar . . . . . . . . . . . . . . . . . . . . . (215)9971020
Philadelphia/Horsham . . . . . . . (215)9574100

UNITED STATES
ALABAMA
Huntsville . . . . . . . . . . . . . . . . . . (205)4646800
ALASKA . . . . . . . . . . . . . . . . . . . (800)6358291

ARIZONA
Tempe . . . . . . . . . . . . . . . . . . . . . (602)3028056

CALIFORNIA
Calabasas . . . . . . . . . . . . . . . . . .
Irvine . . . . . . . . . . . . . . . . . . . . . .
Los Angeles . . . . . . . . . . . . . . . .
San Diego . . . . . . . . . . . . . . . . . .
Sunnyvale . . . . . . . . . . . . . . . . . .

(818)8786800
(714)7537360
(818)8786800
(619)5412163
(408)7490510

COLORADO
Denver . . . . . . . . . . . . . . . . . . . . (303)3373434

CONNECTICUT
Wallingford . . . . . . . . . . . . . . . . . (203)9494100

FLORIDA
Clearwater . . . . . . . . . . . . . . . . . (813)5244177
Maitland . . . . . . . . . . . . . . . . . . . (407)6282636
Pompano Beach/Ft. Lauderdale (305)3516040

GEORGIA
Atlanta . . . . . . . . . . . . . . . . . . . . (770)7297100

IDAHO
Boise . . . . . . . . . . . . . . . . . . . . . . (208)3239413

ILLINOIS
Chicago/Schaumburg . . . . . . . . (847)4132500

INDIANA
Indianapolis . . . . . . . . . . . . . . . . (317)5710400
Kokomo . . . . . . . . . . . . . . . . . . . (317)4555100

TENNESSEE
Knoxville . . . . . . . . . . . . . . . . . . . (423)5844841

TEXAS
Austin . . . . . . . . . . . . . . . . . . . . . (512)5022100
Houston . . . . . . . . . . . . . . . . . . . (713)2510006
Plano . . . . . . . . . . . . . . . . . . . . . . (214)5165100

VIRGINIA
Richmond . . . . . . . . . . . . . . . . . . (804)2852100

UTAH
CSI Inc. . . . . . . . . . . . . . . . . . . . . (801)5724010

WASHINGTON
Bellevue . . . . . . . . . . . . . . . . . . . (206)4544160
Seattle Access . . . . . . . . . . . . . (206)6229960

WISCONSIN
Milwaukee/Brookfield . . . . . . . . (414)7920122
Field Applications Engineering Available
Through All Sales Offices

CANADA
BRITISH COLUMBIA
Vancouver . . . . . . . . . . . . . . . . . . (604)2937650

ONTARIO
Ottawa . . . . . . . . . . . . . . . . . . . . (613)2263491
Toronto . . . . . . . . . . . . . . . . . . . . (416)4978181

QUEBEC
Montreal . . . . . . . . . . . . . . . . . . . (514)3333300

IOWA
Cedar Rapids . . . . . . . . . . . . . . . (319)3780383

KANSAS
Kansas City/Mission . . . . . . . . . (913)4518555

MARYLAND
Columbia . . . . . . . . . . . . . . . . . . (410)3811570

MASSACHUSETTS
Marlborough . . . . . . . . . . . . . . . . (508)3578200
Woburn . . . . . . . . . . . . . . . . . . . . (617)9329700

MICHIGAN
Detroit . . . . . . . . . . . . . . . . . . . . . (810)3476800
Literature . . . . . . . . . . . . . . . . . . (800)3922016

MINNESOTA
Minnetonka . . . . . . . . . . . . . . . . . (612)9321500

MISSOURI
St. Louis . . . . . . . . . . . . . . . . . . . (314)2757380

NEW JERSEY
Fairfield . . . . . . . . . . . . . . . . . . . . (201)8082400

NEW YORK
Fairport . . . . . . . . . . . . . . . . . . . . (716)4254000
Fishkill . . . . . . . . . . . . . . . . . . . . . . (914)8960511
Hauppauge . . . . . . . . . . . . . . . . (516)3617000

NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . (919)8704355

OHIO
Cleveland . . . . . . . . . . . . . . . . . . (216)3493100
Columbus/Worthington . . . . . . . (614)4318492
Dayton . . . . . . . . . . . . . . . . . . . . (513)4386800

OKLAHOMA
Tulsa . . . . . . . . . . . . . . . . . . . . . . (918)4594565

OREGON
Portland . . . . . . . . . . . . . . . . . . . (503)6413681

PENNSYLVANIA

INTERNATIONAL
AUSTRALIA
Melbourne . . . . . . . . . . . . . . . . (613)98870711
Sydney . . . . . . . . . . . . . . . . . . . (612)29661071

BRAZIL
Sao Paulo . . . . . . . . . . . . . . . . 55(11)8154200

CHINA
Beijing . . . . . . . . . . . . . . . . . . . . . 86108437222
Guangzhou . . . . . . . . . . . . . . . . 86207537888
Shanghai . . . . . . . . . . . . . . . . . . 86213747668
Tianjin . . . . . . . . . . . . . . . . . . . . . 86225325072

DENMARK
Denmark . . . . . . . . . . . . . . . . . . . . (45) 43488393

FINLAND
Helsinki . . . . . . . . . . . . . . . . . . 3580351 61191
car phone . . . . . . . . . . . . . . . . . . . 358(49)211501

FRANCE
Paris . . . . . . . . . . . . . . . . . . . . . . . 33134 635900

GERMANY
Langenhagen/Hanover . . . . . . . 49(511)786880
Munich . . . . . . . . . . . . . . . . . . . . . 49 89 921030
Nuremberg . . . . . . . . . . . . . . . . . 49 911 963190
Sindelfingen . . . . . . . . . . . . . . . . 49 7031 79 710
Wiesbaden . . . . . . . . . . . . . . . . . . 49 611 973050

HONG KONG
Kwai Fong . . . . . . . . . . . . . . . . 85226106888
Tai Po . . . . . . . . . . . . . . . . . . . 85226668333

INDIA
Bangalore . . . . . . . . . . . . . . . . . . 91805598615

ISRAEL
Herzlia . . . . . . . . . . . . . . . . . . . . . 9729590222

Motorola TMOS Power MOSFET Transistors Device Data

ITALY
Milan . . . . . . . . . . . . . . . . . . . . . . . . . . 39(2)82201

JAPAN
Kyusyu . . . . . . . . . . . . . . . . . . 81927257583
Gotanda . . . . . . . . . . . . . . . . . . 81354878311
Nagoya . . . . . . . . . . . . . . . . . . 81522323500
Osaka . . . . . . . . . . . . . . . . . . . . . 8163051801
Sendai . . . . . . . . . . . . . . . . . . 81222684333
Takamatsu . . . . . . . . . . . . . . . 81878379972
Tokyo . . . . . . . . . . . . . . . . . . . . 81334403311

KOREA
Pusan . . . . . . . . . . . . . . . . . . . . 82(51)4635035
Seoul . . . . . . . . . . . . . . . . . . . . . . . 82(2)5545118

MALAYSIA
Penang . . . . . . . . . . . . . . . . . . . . 60(4)2282514

MEXICO
Mexico City . . . . . . . . . . . . . . . . 52(5)2820230
Guadalajara . . . . . . . . . . . . . . . . 52(36)218977
Marketing . . . . . . . . . . . . . . . . . . 52(36)212023
Customer Service . . . . . . . . . . 52(36)6699160

NETHERLANDS
Best . . . . . . . . . . . . . . . . . . . . . . (31)4998 612 11

PHILIPPINES
Manila . . . . . . . . . . . . . . . . . . . . . (63)2 8220625

PUERTO RICO
San Juan . . . . . . . . . . . . . . . . . . . (809)2822300

SINGAPORE . . . . . . . . . . . . . . . . . . (65)4818188
SPAIN
Madrid . . . . . . . . . . . . . . . . . . . . . 34(1)4578204
or . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)4578254

SWEDEN
Solna . . . . . . . . . . . . . . . . . . . . . . 46(8)7348800

SWITZERLAND
Geneva . . . . . . . . . . . . . . . . . . . . 41(22)799 11 11
Zurich . . . . . . . . . . . . . . . . . . . . . 41(1)7304074

TAIWAN
Taipei . . . . . . . . . . . . . . . . . . . . 886(2)7177089

THAILAND
Bangkok . . . . . . . . . . . . . . . . . . . 66(2)2544910

UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . . . . 44 1 (296)395252

FULL LINE REPRESENTATIVES


CALIFORNIA, Loomis
Galena Technology Group . . . . . (916)6520268

NEVADA, Reno
Galena Tech. Group . . . . . . . . . (702)7460642

NEW MEXICO, Albuquerque


S&S Technologies, Inc. . . . . . . . (602)4141100

UTAH, Salt Lake City


Utah Comp. Sales, Inc. . . . . . . (801)5615099

WASHINGTON, Spokane
Doug Kenley . . . . . . . . . . . . . . . (509)9242322

HYBRID/MCM COMPONENT
SUPPLIERS
Chip Supply . . . . . . . . . . . . . . . .
Elmo Semiconductor . . . . . . . .
Minco Technology Labs Inc. . .
Semi Dice Inc. . . . . . . . . . . . . . .

(407)2987100
(818)7687400
(512)8342022
(310)5944631

Distributors and Sales Offices


75

Distributors and Sales Offices


76

Motorola TMOS Power MOSFET Transistor Device Data

TMOS Power MOSFET Transistor Device Data

1 Alphanumeric Index of Part Numbers

Selector Guide

Introduction to Power MOSFETs


Basic Characteristics of Power MOSFETs

Data Sheets

Surface Mount Package Information and


Tape and Reel Specifications

Package Outline Dimensions and Footprints

Distributors and Sales Offices

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