A 50 MHz Variable Gain Amplifier Cell in 2pm CMOS

R. Gomez and A. A. Abidi

Integrated Circuits & Systems Laboratory
Electrical Engineering Department
University of Califomia
Los Angeles, CA 90024-1594

ABSTRACT level shifted through a PMOS cascode device, with feed-

A CMOS Variable Gain Amplifier is described for possi-
ble use in disk drive read channels. The 0.9 sq mm cell
attains a 30 dB range of variable gain with 50 MHz
bandwidth, requires a single 5V supply, and dissipates 150
mW.
Introduction
The electronics for disk drive subsystems operating at data
r a t s approaching 20 to 40 Mb/s in large drives constitute
a very large market for video speed analog and digital
ICs. A recent trend in this application is to replace the
customary small scale integrated bipolar ICs with mixed
analogdigital CMOS ICs. in order to reduce total power
consumption and board space in applications such as lap-
top computers. We have previously described a high per-
formance CMOS head amplifier for disk drive heads’, and
here extend this work to the Variable Gain Amplifier
(VGA) which plays a critical role in signal conditioning
for pulse detection. We set as a target a bandwidth of 50
MHz. a variable gain range of 30 dB, and semi-
logarithmic gain control, so as to obtain similar charac-
teristics to those of high end standalone bipolar ICs avail-
able for this application2. The iniprtant difference is that
our macrocell, which may be readily included with digital
circuits on the same chip, requires only a single 5V sup-
ply, and dissipates 100 mW in the core and control cir-
cuits. and an additional 50 mW in buffers to drive off-chip
loads.
Circuit Description
Disk drive heads produced a balanced differential output;
it is natural for alI the subsequent analog signal condition-
ing to preserve this balance, and dicrcby obtain an immun-
ity to noise coupling into the signal path from the power
supplies and common mode pickup. Several altematives
for a CMOS VGA circuit were studied to obtain one that
best preserved wideband response over large variations in
gain. The core of the VGA circuit is a cascade of two
differential pairs, whose gain is varicd by changing the
bias currents (Fig.1). The input pair (Ml) opcrates at a
constant transconductance. but the resistance of its load
devices (M3) is varied by changing the bias current. The
transconductance of the differential pair in the second
stage (M2) is variable under control of tail current. The
amplified signal current emerging frorii the sccond stage is
forward capacitors to improve its high frequency perfor-
mance, into an NMOS 5:l current mirror. The large capa-
citance at the common gate node of the current mirror,
which includes a Miller multiplied Cgd,is partly cancelled
by a neutralization scheme implemented with controllcd
positive feedback. The amplified current at the mirror
output is converted to a voltage in a wideband shunt fecd-
back transresistance stage. A cascade of two tapcred vol-
tage followers follow this to drive a load of 5 pF up to a
frequency of 50 MHz.
AGC loops used in thii application require the logarilhm
of VGA gain to depend linearly on the control voltage
(VCOW). Assuming the FETs in the signal path obey a
square law, this requirement will be met if each control
current ( 1 ~IC*)
~ . in the VGA core individually varies
exponentially with VCON,. while the product I C , . 1 ~ 2
remains constant. These relationships could only be cap-
tured with the use of bipolar transistors in a circuit to gen-
erate the control currents, so we put to use the parmitic
lateral bipolar transistors available in CMOS’ for this pur-
pose (Fig.2).
Experimental Results
These circuits were fabricated in a 2 p CMOS single
poly, double metal process (Fig.3). and then extcnsively
characterized. An almost linear gain vs. control voltage
characteristic was obtained on a semi-log plot (Fig.4), vcr-
ifying the effectiveness of the circuit generating control
currents. The measured gain spanned the range from 10 to
40 dB. The -3 dB bandwidth was at least 50 MHz across
this range (Fig.5).
To minimize phase distortion, the pole positions for ttic
various amplifier stages were designed to cluster togcthcr
on the real axis of the s-plane; the observed group delay
was relatively constant over the passband (Fig.6). The
amplifier delivered a maximum differcntial signal of 2V at
the output, accompanied by 2mV r m s noise. Thc
differential noise voltage spectral density of 280 n V / G
remained almost constant with gain setting (Fig.7). and the
flicker noise comer frequency at 5 MHz was observed, as
expected4.

9.4.1
IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE CH2994-2/91/0000/0044 $1.00 ’1991 IEEE

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 Kcfcrcnccs

1. T-W. Pan and A. A. Abidi. "A 30 MHz Low-

Noise CMOS Preamplifier for Disk Drive Hcads."
Proc. oJ Custom IC Conference, pp. 7.1 .l-7.1.4,
San Diego. CA, May 1989.
2. "AD890 Precision Wideband Channel Processing
Element ." Preliminary Data Sheet. Analog Dev-
ices, 1988.
3. T.-W. Pan and A. A. Abidi. "A Variable Gain
Amplifier Using Parasitic Bipolar Transistors in
I
CMOS.'' IEEE J . of Solid Sfate Circuits, vol. 24. 1 H12"
pp. 951-961, August 1989.
4. A. A. Abidi. C. R. Viswanathan, J. J.-M. Wu and J.
A. Wikstrom. "Flickcr Noise in CMOS: A UniEed
Model," Symposium on VLSI Technology Digest of
Technical Papers. pp. 85-86. Karuizawa. Japan,
May 1987.
Fig.2. Circuit to generate VGA control currents. Feed-
back circuit maintains current in lateral collector of Q1
equal to la. FETs M R biased in triode region uscd as
resistors.

Ursi<

Fig3. Chip microphotograph. Active area is 900 pm on a

side, including control circuits and buffers.

hl2I
hl?2

hlR2

Fig.1. The Variable Gain AmpliGcr. Signal current flow

shown by arrows on the left half circuit. Current sources
implemented with FETs. CMFR indicates current source
driven by common-mode feedback loop (not shown).

9.4.2

. -

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 GROUP DELAY
22

20

18

16

14

12

10

0
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (MHz)

FIg.4. Measured characteristic of VGA Gain (in dB) vs. Fig.6. Measured Group Delay through VGA is relatively
Control Voltage. constant up to 50 MHz. (Spurious droop at low frquen-
cies introduced by measurement circuit).

FREQUENCY RESPONSE OUTPUT NOISE SPECTRUM

50

45

40

-
5
35

30
I-
0
4 25

20

15 0. I

10

5 0 01

0
0 10 20 30 40 50 (<I 70 E0 90 100 0 5 IO 15 20 ?S

FKEQUENCY ( M l l a ) FREQUENCY (MEW

FigS. Measured Frequency Response at several gain set- Fig.7. Measured Output Noise spcctra at maximum and
tings. Dots indicate location of -3 dB points. (Spurious minimum gain settings. Flicker noise extends to about 5
notches d low Gequencies introduced by measurement cir- MHz in thus low power circuit.
cuit.)

9.4.3

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