Proposal and Design of SALTran - A New Surface Accumulation Layer Transistor For Enhanced Current Gain

Proposal and Design of SALTran: A New Surface
Accumulation Layer Transistor for Enhanced Current Gain
A dissertation submitted in partial fulfillment of

the requirement for the degree of
Master of Science (Research)
By
Vinod Parihar
Under the Supervision of

Dr. M. Jagadesh Kumar
to the
Indian Institute of Technology, Delhi

April, 2004
ii
CERTIFICATE
This is to certify that the thesis entitled “Proposal and Design of SALTran: A New
Surface Accumulation Layer Transistor for Enhanced Current Gain” being
submitted by Vinod Parihar with entry no. 2001 EEM 002, to the Indian Institute of
Technology Delhi, for the award of the degree of Master of Science (Research) in
Electrical Engineering Department, is a bona fide work carried out by him under my
supervision and guidance. The research reports and the results presented in this thesis
have not been submitted in parts or in full to any other University or Institute for the
award of any other degree or diploma.
Date: April, 2004 Dr. M. Jagadesh Kumar

Associate Professor
Department of Electrical Engineering
Indian Institute of Technology
New Delhi - 110016
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ACKNOWLEDGEMENTS
I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar for his
invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to
him for his continuing encouragement and support without which, it would not have been
possible for me to complete this undertaking successfully. His insightful comments and
suggestions have continually helped me to improve my understanding.
I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory
facilities at all points of time. I would also like to express my heartfelt gratitude to Mr. K.C.
Sharma for his help. I would like to thank Sukhendu ,Venkateshwara Reddy, C. Linga Reddy
and Anurag for their help throughout the course. My special thanks to my friends, Atul,
Pankaj, Ashish, Alok and Ritesh for making my stay a very memorable one. My sincere
thanks and acknowledgements are due to all of my family members who have constantly
encouraged me for completing this project.
Vinod Parihar
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ABSTRACT
Whether for driving highly capacitive loads using BiCMOS technology or in high
voltage applications and in many mixed signal and precision analog applications, bipolar
transistors are inevitable. To combine the high-density integration of MOS logic with the
current-driving capabilities of BJT along with better device isolation of Silicon-on-Insulator
(SOI), BiCMOS technology has opened up new avenues for the lateral bipolar transistors
(LBT) on SOI. To meet the strict demand on device performance parameters such as β, gm
and fT, many structures like HBTs and polysilicon BJTs are already in use. But these require
complex process steps and also suffer from collector emitter offset voltage in the case of
HBTs and high emitter resistance in the case of polysilicon emitter transistors.
Surface Accumulation Layer Transistor (SALTran) is proposed for the first time to
offer an alternative way of meeting the stringent performance parameters requirements, by
just changing the emitter contact and emitter doping in conventional bipolar transistors. Using
process and device simulations, we have demonstrated the SALTran concept both on NPN
and PNP LBT on SOI structures to obtain high performance in terms of high current gain,
better thermal stability, and less hot carrier degradation without significantly affecting the
cut-off frequency. We have also implemented the SALTran concept on power SiC BJT and
showed through our simulations the superiority of the power SALTran. Our simulations show
that the SALTran concept is useful to both lateral and vertical bipolar transistors whether they
are high speed or high voltage structures.
In conclusion, we have demonstrated the superior attributes offered by the SALTran
structure, supported by extensive simulation studies. The proposed structures should be very
useful for VLSI and power applications. The results presented in this work are expected to
provide incentive for further experimental applications.
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TABLE OF CONTENTS
CERTIFICATE.……………………………………………………………………………...iii
ACKNOWLEDGEMENTS.………………………………………………………….………v
ABSTRACT.…………………………………………………………………………………vii
TABLE OF CONTENTS.…………………………………………………………………...ix
CHAPTER 1…………………………………………………………………………………1
Introduction…………………………………………………………………………………...1
1.1. The context…………………………………………………………………………..1
1.2. Preceding efforts…………………………………………………………………….2
1.3. Objective of the project…...…………………………………………………………3
1.4. Organization of thesis…………………………………………………….…………3
CHAPTER 2…………………………………………………………………………………5
Surface Accumulation Layer transistor(SALTran): A New Bipolar Transistor for
Enhanced Current Gain……………………………………………………………………...5
2.1. Introduction………………………………………………………………………….5
2.2. The SALTran concept…………………………………………………………….…6
2.3 Design methodology of SALTran…………………………………………………..9
2.4. Profile design using the process simulator ATHENA……………………………..10
2.5. Simulation results and discussion…………………………………………………14
2.5.1 Device characteristics……………………………………………………………………14
2.5.2 Emitter region optimization………………………………………………………………19
2.6 Hot carrier degradation…………………………………………………………….22
2.7 Temperature effects on current gain……………………………………………….24
2.8 Effect of interface traps on current gain…………………………………………...26
2.9 Conclusions………………………………………………………………………..28
CHAPTER 3………………………………………………………………………………..29
Realizing high current gain PNP transistors on SOI for complementary bipolar
technology……………………………………………………………………………………29
3.1. Introduction………………………………………………………………………...29
3.2. The SALTran concept on PNP transistor…………………………………………..30
3.3. Design methodology of PNP SALTran…………………………………………...31
3.4. Profile design using the process simulator ATHENA……………………………..33
3.5 Simulation results and discussions…………………………………………………36
3.5.1 Device characteristics……………………………………………………………………36
3.5.2 Emitter region optimization……………………………………………………………..41
3.5.3 Hot carrier injection problem…………………………………………………………...43
3.5.4 Temperature study on current gain …………………………………………………….45
3.5.5 Effect of interface traps on current gain……………………………………………….46
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3.6. Conclusions………………………………………………………………………...47
CHAPTER 4……………………………………………………………………………….49
Implementation of SALTran concept on power SiC BJT…………………………… …49
4.1. Introduction…………………………………………………………………………...49
4.2. Device structure and parameters……………………………………………………...49
4.3. Design methodology………………………………………………………………….52
4.4. Simulation results……………………………………………………………………..52
4.5 Conclusions…………………………………………………………………………...60
CHAPTER 5………………………………………………………………………………..63
Conclusions…….…………………………………………………………………………….63
APPENDICES……………………………………………………………………………….67
REFERENCES………………………………………………………………………………89
List of Publications…………………………………………………………………………..93
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CHAPTER 1
Introduction
1.1 The Context

Bipolar transistors find their use in many high speed mixed signal applications. The
problem with the conventional vertical BJTs is that they require complicated fabrication
process in the case of BiCMOS integration and the cost of manufacturing is high. This
process may be further complicated when CMOS on SOI substrate is integrated. Thus to
avoid the complexity, lateral bipolar transistors have been implemented on SOI technology
which makes SOI BiCMOS integration possible with a few additional masks and ion
implants resulting in only a few minor changes in the standard CMOS process[1-4]. SOI
BiCMOS technology offers many advantages as compared to its bulk counterpart such as
reduced analog to digital cross talk, less sensitivity to alpha particles, reduction of substrate
capacitance and better device isolation. However, bipolar transistors on SOI do suffer from
significant base widening at higher collector current, large base charge storage time, lower
cut-off frequency and lower current gain. In the case of PNP BJTs, the situation is much
worse due to low hole mobility, whereas often we require identical performance as that of
NPN BJT in many applications.
On the other hand, SiC based power BJT and related devices like IGBT and GTOs are
very attractive for high voltage applications because of high breakdown field and high band
gap of SiC [5,6]. But SiC BJTs also suffer from low current gain due to small minority
carrier lifetime of SiC.
1
1.2 Preceding efforts
In order to improve the performance of lateral Bipolar transistor on SOI several
techniques have been used. Both heterojunction bipolar transistors(HBTs) and polysilicon
emitter transistors have been used for realizing high current gains. However, this leads to Vce
off-set voltage and complex process control in the case of HBTs and high emitter resistance
and high 1/f noise current due to interfacial oxide in the case of polyemitter transistor [7-9].
Another method used to improve the current gain of bipolar transistors is the application of
high-low emitter junction in which a lightly doped n-region is introduced between the n+-
region and the p-base region [10]. However, it has been observed experimentally that in such
structures, although there is an improvement in current gain, the cut-off frequency of the
transistor decreases [10]. Also the fabrication process of the high-low emitter structure is
complex and is not suitable for VLSI transistors. It would be very beneficial if the current
gain of a BJT can be enhanced using a simple emitter contact concept while averting the
above difficulties.
The aim of this work is therefore to present for the first time a new technique of
increasing the current gain of a bipolar transistor using a structure called the Surface
Accumulation Layer Transistor(or SALTran). We have applied this concept to both NPN
and PNP transistors in this work. This concept is particularly important in the case of PNP
transistors due to the difficulty in realizing high current gains due to poor hole mobility. Even
the use of SiGe base [11] and polysilicon emitter [12] could not be of much help in realizing
large gain PNP transistors. However, the presence of PNP BJTs in the output stage is crucial
for improved driver performance. Also, active loads in many analog applications cannot be
implemented without PNP transistors. We demonstrate in this thesis that a significant current
2
gain enhancement in PNP transistors can be obtained using proposed Surface Accumulation
Layer Transistor(SALTran) concept.
We have also examined the possibility of applying the SALTran concept to SiC Bipolar
transistors [13] since they too suffer from poor current gain problems due to excessive base
recombination. We have presented detailed simulation results and followed by discussions
on the physical mechanisms responsible for the improved performance of SALTran.
1.3 Objective of the project
The main objective of this work is to propose novel high gain transistor structures
namely, (1) A New Surface Accumulation Layer Transistor(SALTran) concept for current
gain enhancement in bipolar transistor, (2) A Novel High Current Gain Lateral PNP
Transistor on SOI for Complimentary Bipolar Technology, (3) Implementation of the
SALTran concept on SiC power bipolar transistor to increase its current gain.
We have used two–dimensional process and device simulations to study the characteristics
of the above devices. Based on the simulated results, we have analyzed the reasons for the
improved performance of the proposed structures over the conventional devices. The results
presented in this work are expected to provide incentive for further experimental exploration
by other researchers.
1.4 Organization of the thesis
♦ Chapter one: Introduction

Brief overview of issues related to lateral BJTs on SOI and SiC power BJT. Objectives
of the report and outline of the thesis.
♦ Chapter Two: Surface Accumulation Layer Transistor (SALTran): A New Bipolar
Transistor for Enhanced Current Gain.
This chapter introduces a new concept (SALTran) for increasing the current gain of
the bipolar transistor without degrading the cut-off frequency. Also, its performance is
3
compared with standard LBT structure in terms of thermal stability and hot carrier
degradation.
♦ Chapter Three: Realizing high current gain PNP transistors on SOI for
complimentary Bipolar Technology.
This chapter demonstrates the application of the SALTran concept on lateral PNP
transistor on SOI to increase its gain significantly so that its performance can become
comparable to that of an NPN bipolar transistor.
♦ Chapter Four: Implementation of SALTran concept on SiC power BJTs.
This chapter implements the SALTran concept on SiC power BJT, to enhance its gain
and also simultaneously obviating the need for high emitter doping which is difficult
for SiC BJT.
♦ Chapter Five: Conclusions.
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CHAPTER 2
Surface Accumulation Layer Transistor (SALTran): A New

Bipolar Transistor for Enhanced Current Gain
2.1 Introduction
In many analog applications, such as accurate current mirrors, variable gain amplifiers
bandgap voltage references and other high speed mixed signal circuits, lateral bipolar
transistors on SOI have been found to be of great interest with the advent of BiCMOS
technologies [7,14]. The advantages of BJTs over MOSFETs and the inherent isolation
possible with the SOI devices led to the emergence of SOI based BiCMOS technologies
where both lateral BJTs and MOSFETs are fabricated on the same chip.
One of the crucial design parameters in a bipolar transistor is the current gain. A large
current gain can be traded off against increased base doping to alleviate the problems
associated with elevated base sheet resistance commonly observed in high performance BJTs
[15]. Current gain of a BJT can be increased using several techniques such as using a
polysilicon emitter [9], [16-22] or a SiGe base [8], [23-32]. While both the techniques are
widely used, they require complex process steps. Further, in a polysilicon emitter BJT, the
emitter as well as the base are heavily doped which may lead to excessive emitter-base
junction capacitance and emitter tunneling current. Also, the high emitter resistance due to
the interfacial oxide may result in high 1/f noise. Likewise, in the case of HBTs, a finite
collector offset voltage VCE(sat) [31] may result due to the dissimilarity in the emitter-base and
base-collector junctions. Another technique which has been reported to increase the current
gain of a bipolar transistor is the application of low-high emitter junction [10], [32-34].
Nonetheless, in these structures, the cut-off frequency deteriorates due to the increase of
5
minority carrier transit time caused by the presence of the high-low junction [34] and the need
to create an additional junction within the emitter region makes it unfit for VLSI applications
which use submicron transparent emitters. It would be of great practical importance, if the
current gain of a BJT can be enhanced using a simple emitter contact concept while obviating
the above difficulties.
The aim of this chapter is, therefore, to present for the first time a new technique of
increasing the current gain of a bipolar transistor using a structure called the Surface
Accumulation Layer Transistor(or SALTran). The process steps in SALTran are similar to
that of a conventional bipolar transistor except that in SALTran a lightly doped emitter with a
metal contact whose workfunction is less than that of silicon is employed. This results in a
Schottky-Ohmic emitter contact forming a reflecting boundary for the holes injected into the
emitter from the base region leading to a significant reduction in the base current. We
demonstrate using two-dimensional process and device simulation that the proposed
SALTran is superior in performance compared to an equivalent lateral npn BJT on SOI in
terms of high current gain and cut-off frequency. We further ascertain that unlike in the case
of high-low emitter bipolar transistors, the cut-off frequency of SALTran does not degrade by
the presence of the reflecting boundary in the emitter if pertinent emitter doping and length
are used. The dependence of current gain on temperature and the surface states at the metal-
semiconductor contact are analyzed and the reasons for the improved performance are
explained in detail.
2.2 The Surface Accumulation Layer Transistor (SALTran) Concept
The SALTran is based on a concept that when a metal of low work function is
brought in contact with a lightly doped n-type semiconductor having a workfunction higher
6
E0
φm φs
EC
EF
(a)
EV
EC
EF
EV
(b)
n(x)
(c)
x
E(x)
(d)
x
Fig. 2.1 (a) Energy band diagram of metal and semiconductor before contact, (b) Energy band
diagram after contact, (c) Electron accumulation near emitter contact and (d) Electric field
due to accumulation.
7
than that of the metal, an accumulation of electrons will come about in the semiconductor
near the metal-semiconductor interface [35] as shown in Fig. 2.1. This results in an electric
field due to the electron concentration gradient from the metal-semiconductor interface
towards the emitter-base junction. The direction of this field is such that it causes the
reflection of minority holes injected from the base into the emitter resulting in a reduced hole
concentration gradient in the emitter region. As a consequence, the application of such a
Schottky-Ohmic contact to the emitter region should result in a reduced base current leading
to a prodigious improvement in the current gain.
We will establish in the following sections that the above forecasting is indeed
genuine if a low emitter doping and an emitter metal contact of appropriate workfunction
(e.g. titanium) are chosen so that it results in a Schottky Ohmic contact at the emitter.
Knowing the electron affinity and the band gap of silicon to be χs =4.05 eV and EG=1.12 eV
respectively at room temperature and assuming that the metal work function φm is greater
thanχs, we can show that the emitter doping concentration ND below which the contact
becomes a reflecting boundary for minority carriers can be given as
ND=niexp[(χs+(EC-Ei)-φm)/kBT]=niexp[(4.61-φm)/kBT] (1.1)
where Ei is the intrinsic Fermi level, ni is the intrinsic carrier concentration, kB is the
Boltzmann constant and T is temperature in degrees Kelvin. For example, if aluminum is used
for the metal contact, the emitter doping should be approximately ≤ 3.56x1018/cm3 for
realizing the Schottky-Ohmic contact at the emitter.
In the following sections, we shall demonstrate using accurate two dimensional
process and device simulations that the application of surface accumulation layer emitter
contact does indeed enhance the bipolar transistor performance significantly.
8
Base
Emitter Collector
1µm
0.3 µm 0.4 µm 1.6 µm 2.4 µm
Metal contact Poly contact Metal contact
Field oxide
-
0.2µm n p n n+
0.38 µm
Buried oxide
Silicon substrate
Fig.2.2 Top layout and schematic cross-section of SALTran and LBT structures
2.3 Design Methodology of SALTran
To demonstrate the concept of SALTran on SOI and to calibrate our device
simulations, we have first chosen an experimental process for an SOI NPN lateral bipolar
transistor (LBT) reported in literature[7]. The top layout and the schematic cross-section of
the SALTran or LBT are shown in Fig 2.2. For both the structures, the epitaxial silicon film
thickness is chosen to be 0.2 µm, the oxide thickness is 0.38 µm, the p-base width is 0.4 µm
9
with a peak doping level of 5x1017/cm3 and the collector drift region width is 1.6 µm with a
doping level of 4.5x1014/cm3 and the n+ collector doping is 5x1019/cm3. In the case of LBT,
the emitter n-region has a doping of 5x1019/cm3 with 0.3 µm length while for the SALTran,
we have varied the emitter doping from 4.5x1014/cm3 to 1018/cm3 , keeping the emitter length
at 0.3 µm. We have implemented the fabrication steps of [7] in the process simulator
ATHENA [36] and imported the structure and doping profiles into the device simulator
ATLAS [37]. We have calibrated the default model parameters in ATLAS such that the
simulated current gain and the cut-off frequency of the lateral SOI BJT matches with the
experimentally reported values in [7]. We have then carried out the process simulation for
SALTran with different emitter dopings and emitter lengths keeping all the other process
steps and device data same as that of the reported lateral bipolar transistor (LBT) on SOI so
that our simulations are well validated.
2.4 Profile Design Using the Process Simulator ATHENA

We have used the following process steps in ATHENA to design the doping profiles
for both the LBT and the SALTran. First the n+ collector implant was done with a phosphorus
dose of 5x1014 cm-2 at 100 keV after patterning of the deposited silicon nitride. Then a 0.8
µm thick CVD-oxide is deposited, patterned and etched. Next, a screen oxide of 0.03 µm
thickness was deposited, followed by a 0.24 µm thick CVD-nitride deposition and etching to
form a spacer. Following this, the emitter is formed by implanting phosphorus with a dose of
2.5x1013 cm-2 and an energy of 50 keV while the base region is protected by the spacer. The
emitter is then driven in for 1hr at 965 0C in nitrogen followed by LOCOS for 1 hr in wet
oxygen at 900 0C to give a 0.18 µm thick oxide over emitter. After opening the base area by
a wet chemical etch and removal of the nitride spacer by phosphoric acid, three subsequent
10
Table 2.1: ATLAS input parameters used in the simulation of SALTran/LBT
Parameter Value
Silicon film thickness tsi 0.20 µm
Buried oxide thickness tbox 0.38 µm
Metal work function for emitter contact(Titanium) 3.9 eV
Emitter length 0.3 – 5.6 µm
Base length 0.40 µm

Collector length 1.6 µm
Emitter region doping for SALTran 4.5x1014 cm-3 to
1x1018 cm-3
Emitter region doping for LBT 5x1019 cm-3
Base region doping 5x1017 cm-3

Collector region doping 4.5x1014 cm-3
N+ collector region doping 5 x1019 cm-3
SRH electron minority carrier lifetime coefficient 6.5x10-6 s
(TAUN0)
SRH hole minority carrier lifetime coefficient (TAUP0) 1x10-6 s

SRH concentration parameter for electrons and holes
NSRHN and NSRHP 5x1016 cm-3
Surface recombination velocity at poly base contact
(VSURFN) 5.5 x104 cm/s
boron implants of 3x1012 cm-2 at 60 keV, 3x1012 cm-2 at 20 keV, 5x1012 cm-2 at 20 keV were
performed. Next annealing at 965 0C for 20 minutes and 800 0C for 60 minutes was done.
This is followed by the deposition of a polysilicon layer of 0.3 µm thickness and was doped
11
by boron implantation of dose 2.5x1015 cm-2 with 70 keV energy followed by annealing at
850 0C for 80 minutes. The oxide layer was etched followed by silicon etching on the side of
the emitter and the metal was deposited and patterned for providing the emitter contact. The
final structure looks as shown in Fig 2.2. The process for LBT is same as that of SALTran
except that the emitter implant dose and the nitride spacer width are 2.5x1015 cm-2 and 0.34
µm respectively in the case of LBT. As an example, the final doping profiles of the SALTran
and LBT obtained using the above process in ATHENA are shown in Fig. 2.3 for an emitter
doping of 1018 cm-3. We have adjusted the process parameters to obtain different emitter
doping values between 4.5x1014 and 1018 cm-3. This doping data is given as an input to the
device simulator ATLAS to evaluate the electrical characteristics of both the structures as
discussed in the following section. Fig. 2.4 shows the band diagram near the emitter contact .
1022
SALTran
Doping concentration (/cm3)
LBT
1020
1018
1016
1014
0 1 2 3 4
Distance from emitter contact (µm)
Fig. 2.3 Doping profile of SALTran and LBT structures.
12
14 3
1.0 SALTran (4.5x10 /cm )
LBT
0.5 Conduction band
Energy (eV)
(a)
0.0
fermi level
-0.5 Valence band
-1.0
Metal Silicon
-1.5
-0.04 0.00 0.04 0.08
1.0 14 3
SALTran (4.5 x 10 /cm )
LBT
0.5 Hole quassi fermi level
VBE= 0.7 V Conduction band
(b)
Energy (eV)
0.0
Electron quassi fermi level
-0.5
Valence band
-1.0
Metal Silicon
-1.5
-0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10
Fig 2.4 Band diagram of SALTran and LBT (a) Without bias and (b) With bias
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2.5 Simulation Results and Discussion
2.5.1 Device Characteristics
In the device simulator ATLAS, we have used suitable models for the bandgap narrowing,
SRH and Auger recombination and the concentration and field dependent mobility. The
simulation parameters are given in Table 2.1. The simulated output characteristics of the
SALTran and LBT are shown in Fig. 2.5. The emitter doping of SALTran is 4.5x1014 cm-3
and its length is 0.3 µm. It is clearly seen that SALTran has a higher current driving
capability than the LBT for a given base current. The gummel plot shown in Fig. 2.6 for two
emitter dopings of SALTran with an emitter length of 0.3 µm indicates that the base current in
SALTran is quite smaller than that of LBT resulting in an enhanced current gain as shown in
Fig. 2.7. We further notice that with the reduction in emitter doping from 1018 cm-3 to 4.5 x
1014 cm-3, the base current decreases significantly resulting in a drastic improvement in the
current gain. We notice that the ideality factor of base current for SALTran increases slightly
when compared to the LBT. While the peak current gain of LBT is only 20, the SALTtran
exhibits a peak current gain of 200 and 1500 when the emitter doping is 1018 cm-3 and 4.5 x
1014 cm-3, respectively. This significant enhancement in current gain can be understood from
the electron profile and the electric field profile in the emitter region shown in Fig. 2.8. As
pointed out in Section 2.2, since we have chosen the workfunction (3.9 eV) of the emitter
metal contact to be less than that of the silicon emitter region, there is an accumulation of
electrons under the metal contact as shown by the simulated electron profile in Fig.
2.8(a) for the SALTran structure with two different emitter dopings. No such
electron accumulation is observed in the case of LBT even though the same
metal is used for the emitter contact. The accumulated electron gradient in SALTran results
14
2.0
Ib=0.1 nA to 0.9 nA
1.5 Step 0.2 nA
Collector current (µA)
1.0
(a)
0.5
0.0
0 1 2 3 4 5
Collector emitter voltage (V)
0.025
Ib=0.1 nA to 0.9 nA
0.020 Step 0.2 nA
0.015 (b)
0.010
0.005
0.000
0 1 2 3 4 5
Fig. 2.5 Output characteristics of (a) SALTran, (b) LBT structures
15
-3
10
VCE=3 V
Collector and base current (A)

-5
10 SALTran(4.5x10 /cm )
14 3
18 3
-7 SALTran(1x10 /cm )
10 LBT
-9
10
IC
-11
10
10
-13 IB
-15
10
0.0 0.2 0.4 0.6 0.8 1.0
Base emitter voltage (V)
Fig. 2.6 Gummel plots of SALTran and LBT structures.
14 3
SALTran(4.5x10 /cm )
18 3
VCE=3 V
3 SALTran(1x10 /cm )
10 LBT
Current gain
2
10
1
10
-15 -13 -11 -9 -7 -5 -3

10 10 10 10 10 10 10
Collector current (A)
Fig. 2.7 Current gain versus collector current of SALTran and LBT structures.
16
3)
1020
Electron concentration (/cm

1015
(a)
1010 SALTran (4.5x10 /cm )

14 3
18 3
SALTran (1x10 /cm )
LBT
105
0.0 0.1 0.2 0.3
800
14 3
SALTran (4.5x10 /cm )
600 SALTran (1x10 /cm )
18 3
Electric field (kV/cm)
LBT
400 (b)
200
0
0.0 0.1 0.2 0.3
Fig. 2.8 (a) Electron concentration and (b) Electric field of SALTran and LBT structures in
the emitter.
17
14 14 3
Carrier Concentration (/cm )

SALTran(4.5x10 /cm )
3
LBT Emitter base junction
12
VBE=0
10
8
6
4
2
Metal
0
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
20
14 3
Carrier concentration (/cm )
3
LBT
VBE=0.7 V Emitter base junction
15
Metal
10
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fig.2.9 Minority carrier profile in emitter and base region (a) Without bias and (b) With bias
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in a large electric field under the emitter as shown in Fig. 2.8(b) and acts as a reflecting
boundary for the holes arriving from the emitter-base junction. The base current of SALTran
will, therefore, be significantly smaller than that of the LBT as demonstrated in the gummel
plots of Fig. 2.6. The minority carrier profile in the emitter and base region for both SALTran
and LBT structures is shown in Fig. 2.9
The simulated cut-off frequency fT of SALTran and LBT are compared in Fig. 2.10.
We notice that when the emitter doping of SALTran is 1018 cm-3, the fT of SALTran is
greater than that of the LBT. This is unlike the behaviour shown by the high-low junction
emitter bipolar transistors in which the presence of the high-low junction deteriorates the cut-
off frequency due to an increase in the emitter transit time because of charge storage
effects[34]. If the emitter doping is reduced to a low value (4.5x1014 cm-3), a slight reduction
in fT is observed in the case of SALTran because of increase in the emitter resistanc also
indicating that one has to optimize both the emitter length and the emitter doping of SALTran
to get the desired current gain enhancement without seriously affecting the cut-off frequency
as discussed below.
2.5.2 Emitter Region Optimization
An important aspect of the SALTran structure is that as the emitter length decreases
both the current gain and cutoff frequency begin to increase. A reduction in the emitter length
causes the rate of reflection of the holes from the emitter to be significant. Fig. 2.11 shows the
peak current gain variation for different emitter lengths and emitter dopings for both
SALTran and LBT structures. We notice that when the emitter doping is far smaller than the
peak base doping, the current gain enhancement is maximum. For example, when the emitter
doping is 4.5x1014 cm-3 , the current gain enhancement is largest for shallow emitter lengths
19
VCE=3 V
2.5 SALTran (4.5X10 /cm )
14 3
Cutoff frequency (GHz)

18 3
SALTran (1X10 /cm )
2.0 LBT
1.5
1.0
0.5
0.0
-10 -9 -8 -7 -6 -5 -4
10 10 10 10 10 10 10
Fig. 2.10 Cutoff frequency versus collector current for SALTran and LBT structures
which makes the SALTran structure very attractive for scaled down VLSI BJTs. We also
notice that for deeper emitter lengths too the current gain enhancement is still impressive
when
the emitter is lightly doped. This is an indication that the SALTran concept can be
conveniently applied to even high voltage power bipolar transistors in which low current gain
is often a problem. In the case of deeper emitter junctions, the current gain of SALTran is
smaller than that of shallower emitter due to the increased emitter region recombination for
deeper emitters.
The peak cutoff frequency variation with emitter length and emitter doping is shown
in Fig. 2.12. It is seen that when the emitter doping is 1018 cm-3, at an emitter length of 0.5
µm, the SALTran has almost the same peak cutoff frequency as that of LBT and at 0.3 µm
emitter length, it surpasses the LBT in terms of both the current gain and the cutoff frequency.
With proper optimization of emitter length and emitter doping we can get both high current
gain and high cutoff frequency.
20
1600 14 3 17 3
4.5x10 /cm 1x10 /cm
1400 1x10 /cm
15 3
1x10 /cm
18 3
1200 1x10 /cm

16 3
5x10 /cm
19
Peak current gain

1000
800
600
400
200
0
0 1 2 3 4 5 6
Emitter length (µm)
Fig. 2.11 Current gain versus emitter length of SALTran for different emitter dopings
(4.5x1014 /cm3to 1x1018 /cm3 ) and LBT structure for an emitter doping of 5x1019 /cm3.
14 3 17 3
3 4.5x10 /cm 1x10 /cm
15 3 18 3
1x10 /cm 1x10 /cm
Cut off frequency (GHz)
16 3 19 3
1x10 /cm 5x10 /cm
2
0
0 1 2 3 4 5 6
Fig. 2.12 Cutoff frequency versus emitter length of SALTran for different emitter dopings
(4.5x1014 /cm3 to 1x1018 /cm3 ) and LBT structure for an emitter doping of 5x1019 /cm3.
21
2.6 Hot Carrier Injection Problem
A major reliability concern for bipolar transistors is the current gain degradation due
to an increase in base current caused by the hot carrier injection when a reverse bias appears
across the emitter-base junction [38,39].
In bipolar transistors, the heavy doping in the emitter and base regions results in
sufficiently large electric field even at typical emitter-base reverse-bias voltages (<5 V) and
is the primary cause of the hot carrier injection problem. In order to investigate this, we have
compared the simulated reverse emitter-base characteristics of SALTran and LBT in Fig.
2.13 (a). It can be seen that because of low emitter doping (4.5x1014 cm-3) used in SALTran,
its reverse breakdown voltage is significantly larger than that of LBT which breaks down
approximately at a reverse bias of 5.5V. The electric field in the emitter region shown in Fig.
2.13(b) at the breakdown of LBT (5.5 V) clearly shows that in the case of LBT with its
heavily doped emitter, there is a larger peak electric field at the emitter-base junction
compared to that of SALTran whose emitter is completely depleted because of low doping. It
may be pointed out that although the electric field at the metal-semiconductor interface of the
SALTran is not negligible, carrier multiplication is very unlikely to take place here due to the
extremely narrow thickness of the high electric field region [40]. This clearly indicates the
less vulnerability of SALTran to the hot carrier injection phenomenon if the emitter is lightly
doped. In the case of SALTran, therefore, the lightly doped emitter not only helps in realizing
a large gain but it may also result in a reduced hot carrier injection.
22
-5
10
14 3
-7
10 LBT
-9
Reverse current (A)
10
-11
10 (a)
-13
10
-15
10
-17
10
-19
10
0 5 10 15 20
Reverse emitter base voltage (V)
800
14 3
VEB=5.5 V SALTran (4.5x10 /cm )
LBT
600
(b)
400
200
0
0.0 0.1 0.2 0.3
Fig. 2.13 (a) Reverse break down characteristics of the emitter-base junction of SALTran and
LBT structures and (b) Electric field in the emitter region of SALTran and LBT structures at
a reverse bias of 5.5 V
23
2.7 Temperature Effects on Current Gain
The current gain of a silicon bipolar transistor increases with ambient temperature and
this can cause problems in many applications. To understand the temperature effects, we have
compared the current gain dependence of SALTran with that of LBT in Fig. 2.14 (a) by
plotting the normalized current gain as a function of temperature. We notice that the
dependence of current gain on temperature is far less in the case of SALTran as compared to
the LBT.
It is well known[34] that the variation in peak current gain and the temperature can be
related by β=βoexp(- ∆Eg / kBT) where βo is the maximum current gain for activation energy
∆Eg =0, kB is the Boltzmann constant and T is the absolute temperature in degrees Kelvin. If
Ege and Egb are the effective bandgap narrowing in the emitter and base regions,
respectively, the activation energy ∆Eg can be obtained as ∆Eg = Ege - Egb. From the peak
current gain variation of SALTran and LBT as a function of temperature, one can obtain the
activation energy by plotting ln β versus 1/ (kBT) as shown in Fig. 2.14 (b). The activation
energy for SALTran comes out to be 30 meV and 34 meV for the emitter doping of 4.5x1014
cm-3 and 1018 cm-3 , respectively. The activation energy of LBT is found to be 53 meV. This
clearly shows that SALTran can be operated at higher temperatures compared to LBT while
keeping the current gain variations much smaller than that of LBT.
24
14 3
2.8 SALTran (4.5x10 /cm )β300=1500
18 3
SALTran (1x10 /cm )β300=198
2.4 LBTβ300=21
2.0 (a)
β(T)/β300
1.6
1.2
0.8
300 350 400 450 500

Temperature (K)
4
10
∆Eg=30 meV
Peak current gain
3
10 ∆Eg=34 meV
(b)
2 ∆Eg=53 meV
10
14 3
1 SALTran (4.5x10 /cm )
10 18 3
SALTran (1x10 /cm )
LBT
0
10
24 28 32 36 40
-1
1/KBT (eV )
Fig. 2.14 (a) Normalized peak current gain [β(T)/ β300] versus temperature,
(b) Peak current gain versus 1/kBT of SALTran and LBT structures.
25
2.8 Effect of Interface Traps on Current Gain
Since a Schottky-Ohmic contact is employed at the emitter of SALTran, it is obvious
that there could be interface traps at the metal-semiconductor interface depending on the
surface preparation and metal deposition method employed. Both acceptor and donor type
interface traps are known to be present which will affect the band bending [41]. Since band
bending is crucial to create an accumulation of electrons in SALTran, it is of practical interest
to examine the extent to which the presence of interface states will affect the current gain.
While it is difficult to predict the number and type of traps in the band gap which can vary
from process to process, we can at least introduce in the simulator the typical range of
interface traps to study their influence on the device characteristics. The effect of interface
traps, for example, have been carried out earlier using simulation in the case of Schottky
junctions on silicon [42]. In the device simulator ATLAS, we have introduced both donor and
acceptor type interface traps to see their effect on the current gain of SALTran. For
acceptor(or donor) type traps, we have set the trap energy level(E.level) at 0.49 eV from the
conduction(or valance) band. The degeneracy factor(degen) for the trap level is chosen to be
12 and the capture cross-sections for electrons(sign) and holes(sigp) are taken to be
2.84x10-15 cm2 and 2.84x10-14 cm2, respectively. at the interface. We observe that the
current gain decreases as the interface trap concentration increases and that the effect is more
pronounced if both acceptor and donor type traps are present. We have observed an increase
in the simulated base current when the trap concentration is increased and this, therefore, will
cause the current gain to decrease.
26
1600
1400
Peak current gain
1200 E.level=0.49 eV degen=12
2
sign=2.84e-15 cm
2
sigp=2.84e-14 cm
1000
Donor or acceptor states only
Both donor and acceptor states
800
7 8 9 10 11 12
10 10 10 10 10 10
2
Trap density (/cm )
Fig. 2.15 Peak current gain versus trap density for SALTran and LBT structures.
Fig. 2.15 shows the peak current gain of SALTran with an emitter doping of
4.5x1014/cm3 and emitter length of 0.3 µm as a function of both acceptor and donor type traps
However, even in the presence of a significant number of interface traps, the current gain
enhancement realized in SALTran over that of LBT is approximately 40 times larger which is
very impressive. Therefore, if the surface preparation is well controlled as is the practice in
most advanced fabrication procedures, it should be possible to preserve the current gain
enhancement of the proposed SALTran structure. On the other hand, growing a native oxide
of approximately 10 – 15 Å on the emitter surface using RCA cleaning, just as is commonly
done in the case of polysilicon emitter bipolar transistors [22] will minimize the effect of
surface traps and may further enhance the current gain. Therefore, the interface states should
not be a cause for concern.
27
2.9 Conclusions
For the first time, the concept of surface electron accumulation to increase the current gain
and also the cutoff frequency of bipolar transistors is successfully shown by using 2-D
process and device simulation. We have demonstrated that the presence of a Schottky-Ohmic
contact at the emitter results in a reflecting boundary for the minority carriers resulting in a
significant improvement in the current gain of the bipolar transistors. We have also showed
the less vulnerability of SALTran to hot carrier injection compared to LBT. Our simulations
show that activation energy of SALTran is significantly lower than that of LBT making its
current gain less dependent on temperature variations. Unlike in the case of the high-low
emitter bipolar transistors, the cut-off frequency of the SALTran does not deteriorate in the
presence of surface electron accumulation if optimized emitter design is used. Since the
SALTran structure obviates the need to create a high-low junction in the emitter region and
since its performance improves for both shallow and deep emitters, the proposed SALTran
concept should be useful to the designers to enhance the bipolar transistor performance in
VLSI as well as high voltage switching circuit applications .
28
CHAPTER 3
Realizing high current gain PNP transistors on SOI for

Complimentary Bipolar Technology
3.1 Introduction
Complementary bipolar technologies using NPN and PNP transistors play an important role in
many analog applications such as feedback amplifiers, current mirrors and push-pull circuits
[43]. The presence of PNP BJTs in the output stage is crucial for improved driver
performance. Also, active loads in analog applications can not be implemented without PNP
transistors. However, realizing compatible PNP and NPN transistors is difficult because PNP
transistors exhibit low current gains due to poor hole mobility. Even the use of SiGe base [11]
and polysilicon emitter [12] could not be of much help in realizing large gain PNP transistors.
While both the above techniques are widely used, they require complex process steps.
Further, in a polysilicon emitter BJT, the high emitter resistance due to the interfacial oxide
may result in high 1/f noise. Likewise, in the case of HBTs, a finite collector offset voltage
VCE(sat) [31] may result due to the dissimilarity in the emitter-base and base-collector
junctions. Another technique which has been reported to increase the current gain of a bipolar
transistor is the application of low-high emitter junction [10, 32-34]. Nonetheless, in this case,
the cut-off frequency deteriorates due to the increase of minority carrier transit time caused by
the presence of the high-low junction [34] and the need to create an additional junction within
the emitter region makes it unfit for VLSI applications which use submicron transparent
emitters. It would be of great practical importance, if we can get high current gain in PNP BJT
using a simple emitter contact concept with out above difficulties.
29
The main objective of this chapter is to therefore successfully implement the high
current gain PNP bipolar transistor using Surface Accumulation Layer Transistor(or
SALTran) concept. The process steps in SALTran are similar to that of a conventional
bipolar transistor except that in case of SALTran a lightly doped emitter with a metal contact
whose workfunction is higher than that of the silicon is employed. This results in a Schottky-
Ohmic emitter contact forming a reflecting boundary for the electrons injected into the emitter
from the base region leading to a significant reduction in the base current. The proposed
PNP SALTran is superior in performance compared to an equivalent lateral PNP BJT on SOI
[14] in terms of high current gain. We further ascertain that unlike in the case of low-high
emitter bipolar transistors, the cut-off frequency of SALTran does not degrade by the
presence of the reflecting boundary in the emitter if optimized emitter doping and length are
used.
3.2 The Surface Accumulation Layer Transistor(SALTran) Concept on

PNP transistor
For realizing the SALTran concept on PNP, a metal of high work function is brought in
contact with a lightly doped p-type semiconductor such that an accumulation of holes takes
place in the semiconductor near the metal-semiconductor interface [35]. This results in an
electric field due to the hole concentration gradient from the metal-semiconductor interface
towards the emitter-base junction. The direction of this field is such that it causes the
reflection of electrons injected from the base into the emitter resulting in a reduced electron
concentration gradient in the emitter region. Thus the application of such a Schottky-Ohmic
contact to the emitter region results in a reduced base current leading to a significant
improvement in the current gain.
30
In the following sections, we shall demonstrate using accurate two dimensional
process and device simulations that the application of surface accumulation layer emitter
contact does indeed enhance the PNP bipolar transistor performance significantly.
3.3 Design Methodology of PNP SALTran
To demonstrate the concept of SALTran on SOI and to calibrate our device
simulations, we have first chosen the typical experimental process steps for an SOI PNP
lateral bipolar transistor (LBT) reported in literature [7]. The top layout and the schematic
cross-section of the SALTran or LBT are shown in Fig 3.1. The simulation parameters are
given in Table 3.1. We have implemented the fabrication steps of [7] in the process simulator
Base
Emitter Collector
1µ m
0.3 µ m 0.4 µ m 3.8 µ m 3 µm
Field oxide
P N P P+
0.2 µ m
Buried oxide
0.38 µm
Silicon substrate
Fig. 3.1 Top layout and schematic cross-section of SALTran and LBT structures.
31
Table 3.1: ATLAS input parameters used in the simulation of PNP SALTran/LBT
Parameter Value
Silicon film thickness tsi

0.20 µm
Buried oxide thickness tbox
0.38 µm
Metal work function for emitter contact (Nickel)
5.4 eV
Emitter length
0.3 – 3.8 µm
Base length
0.40 µm
Collector length
3.8 µm
Emitter region doping level in LBT
5x1019 /cm3
Emitter region doping in SALTran
1x1014 cm-3 to 1x1018 cm-3
Base region doping 5x1017 cm-3
Collector region doping 1x1017 cm-3
P+ collector region doping 5 x1019 cm-3
SRH electron minority carrier life time coefficient 6.5x10-6 s

(TAUN0)
SRH hole minority carrier life time coefficient (TAUP0) 1x10-6 s
SRH concentration parameter for electrons and holes

NSRHN and NSRHP 5x1016 cm-3
Surface recombination velocity at poly base contact

(VSURFP) Atlas’ default
ATHENA [36] to obtain the PNP lateral SOI structure reported in [14] and imported this
structure and doping profiles into the device simulator ATLAS [37], to calibrate the model
parameters in ATLAS such that the simulated current gain of the PNP lateral SOI BJT
32
matches with the reported value in [14]. We have then carried out process simulation for to
obtain PNP SALTran structures of different emitter dopings and emitter lengths, which are
then given as an input to the device simulator ATLAS for further investigation regarding
cutoff frequency and current gain. variation of SALTran for different emitter doping and
emitter lengths.
3.4 Profile Design Using the Process Simulator ATHENA

We have used the following process steps in ATHENA to design the doping profiles for both
the LBT and the SALTran. For the LBT first the p+ collector implant was done with a boron
dose of 2x1015 cm-2 at 40 keV after patterning the deposited silicon nitride on 0.2 µm SOI of
doping 1x1017 cm-3. Then a thick CVD-oxide is deposited, patterned and etched. Next, a
screen oxide of 0.03 µm thickness was deposited, followed by a 0.31 µm thick CVD-nitride
deposition and etching to form a spacer. Following this, the emitter region is formed by
implanting boron with a dose of 3x1015 cm-2 and an energy of 50 keV at a tilt angle of 300
while the base region is protected by the nitride spacer. Then drive-in is done for 60 minutes
at 9650C in nitrogen. After opening the base diffusion window by a wet chemical etch and
removal of the nitride spacer by phosphoric acid, three subsequent phosphorus implants of
4x1012 cm-2 at 20 keV, 7x1012 cm-2 at 40 keV and 6x1012 cm-2 at 60 keV were performed.
Next annealing at 950 0C for 20 minutes was done. This is followed by the deposition of a 0.2
µm of n+ polysilicon layer of doping 5x1019 cm-3. Finally, the oxide layer was etched
followed by silicon etching on the side of the emitter and the metal was deposited and
patterned for providing the emitter contact.
The final structure looks as shown in Fig.3.1. The process steps for SALTran are same
as that of LBT except that in the case of SALTran, the emitter doping is chosen to form the
33
Schottky-Ohmic contact. For the SALTran with emitter doping of 1x1014 cm-3 the nitride
spacer width is 0.08 µm. The p- collector implant was done in two subsequent boron implants
of 4x1012 cm-2 at 50 keV with a tilt angle of 250and 2x1012 cm-2 at 20 keV with a tilt angle of
500 and it was followed by drive in for 20 minutes at 950 0C. The base was defined by three
subsequent boron implants of 9x1012 cm-2 at 20 keV, 1x1013 cm-2 at 40 keV and 6x1012 cm-2
at 60 keV. The final doping profiles of the SALTran and LBT obtained using the above
process in ATHENA are shown in Fig 3.2 for an emitter doping of 1014 cm-3. We have
adjusted the emitter implantation parameters to obtain different emitter doping values between
1x1014 cm-3 and 1x1018 cm-3. This device structure is given as an input to the device simulator
ATLAS to evaluate the electrical characteristics of both the structures as discussed in the
following section. Fig 3.3 shows the band diagram of both structures in emitter base region.
1020
Doping concentration (/cm3)
1019
1018
1017
1016
1015
1014 SALTran
1013 LBT
1012
0 1 2 3 4 5 6 7
Distance from emitter contact (µ m)
Fig. 3.2 Doping profile of SALTran and LBT structures.
34
1.5
Conduction band PNP SALTran
1.0 LBT
0.5
Energy (eV)
0.0
Fermi level
-0.5
Valence band
-1.0
Metal
Silicon
-1.5
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
1.5
VBE=-0.7 V Conduction band
1.0
0.5
Energy (eV)
Hole quassi fermi level
0.0
Electron quassi fermi level Valence band
Metal
-0.5
Silicon
-1.0 PNP SALTran
LBT
-1.5
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fig. 3.3 Band diagram in the Emitter-base region (a) without bias and (b) with bias
35
0.8
I = 0.5 nA to 2.5 nA Step 0.5 nA

B

0.6
0.4
0.2
0 1 2 3
Emitter-collector voltage (V)
Fig. 3.4 Output characteristics of the SALTran structure
3.5. Simulation Results and Discussion
3.5.1 Device Characteristics
In our simulations using device simulator ATLAS, we have used suitable models for the
bandgap narrowing, SRH and Auger recombination and the concentration and field dependent
mobility. The simulated output characteristics of the SALTran are shown in Fig. 3.4 for an
emitter doping of 1x1014 cm-3 and emitter length of 0.3 µm. The gummel plot shown in
Fig. 3.5 (a) of SALTran indicates that the base current in SALTran is quite smaller than that
of LBT resulting in an enhanced current gain as shown in Fig.3.5 (b). We further notice that
with the reduction in emitter doping from 1018 cm-3 to 1014 cm-3, the base current decreases
significantly resulting in a drastic improvement in the current gain. As we changed the emitter
length from 3.8 µm to 0.3 µm, the peak current gain of LBT decreased from 14 to 2 due to
reduction in the emitter gummel number, while that of SALTran increased from 120 to 235
36
-3
10
Collector and base current (A)

-5 VCE=-1.5 V
10
SALTran
-7
10 LBT
(a)
-9
10
IC
-11
10
IB
-13
10
-15
10
0.0 0.2 0.4 0.6 0.8 1.0
3
10 SALTran (3.8µm) LBT(3.8µm)
SALTran(0.3µm) LBT(0.3µm)
2 VCE=-1.5 V
10
Current gain
(b)
1
10
0
10
-14 -12 -10 -8 -6 -4
10 10 10 10 10 10
Fig. 3.5 (a) Gummel plots and (b) Current gain versus collector current of SALTran and LBT
structures.
37
because of increase in the reflection rate of the electrons. The significantly high current gain
in case of SALTran can be understood from the electron profile and the electric field profile
shown in Fig. 3.6. As pointed out earlier since we have chosen the workfunction (5.4 eV) of
22
20
Hole concentration (/cm )
3
18
16 (a)
14
12
SALTran
10 LBT
8
0.0 0.1 0.2 0.3
-400
SALTran
-300 LBT
(b)
-200
-100
0
0.0 0.1 0.2 0.3
Distance from emitter contact ( µm)
Fig. 3.6 (a) Electron concentration and (b) Electric field of SALTran and LBT structures in
the emitter.
38
Carrier concentration (/ cm3)
1012 PNP SALTran Emitter base junction
LBT
1010
108
106
104
102
100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Distance from emitter contact ( µm)
1018
Carrier concentration ( /cm3)
VBE =-0.7 V
1016
1014
1012 Emitter base junction
1010
108
106
104 PNP SALTran
102 LBT
100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fig. 3.7 Minority carrier profile in the emitter-base region (a) without bias (b) with bias
39
the emitter metal contact to be greater than that of the silicon emitter region, there is an
accumulation of holes under the metal contact as shown by the simulated hole profile in Fig.
3.6 (a) for the SALTran structure . No such hole accumulation is observed in the case of
LBT. The accumulated hole gradient in SALTran results in a large electric field under the
emitter as shown in Fig. 3.6 (b) and acts as a reflecting boundary for the electrons arriving
from the emitter-base junction. The base current of SALTran will, therefore, be significantly
smaller than that of the LBT as demonstrated in the Gummel plots of Fig. 3.5.
The simulated cut-off frequency fT of SALTran and LBT are compared in Fig. 3.8.
The cut-off frequency of SALTran is almost same as that of the LBT. This is unlike the
behavior shown by the high-low junction emitter bipolar transistors in which while a gain
enhancement is observed due to the presence of the high-low junction but the cut-off
frequency deteriorates because of charge storage effects [34]. Fig. 3.7 shows the minority
carrier profile in the emitter base region of both the structures.
1.0
SALTran
Cutoff frequency (GHz)
0.8
LBT
0.6
0.4
0.2
0.0
-9 -8 -7 -6 -5 -4
10 10 10 10 10 10
Fig. 3.8 Cutoff frequency versus collector current for SALTran and LBT structures.
40
14 -3 17 -3
10 cm 10 cm
240
15 -3 18 -3
10 cm 10 cm
200 16
10 cm
-3
5x10 cm
19 -3
Current gain
160
120
80
40
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Fig. 3.9 Current gain versus emitter length of SALTran for emitter dopings (1x1014 /cm3
to 1x1018 /cm3 ) and LBT structure for an emitter doping of 5x1019 /cm3.
3.5.2 Emitter Region Optimization
An important aspect of the SALTran structure is that as the emitter length decreases
both the current gain and cutoff frequency begin to increase. As pointed earlier, reduction in
the emitter length causes the rate of reflection of the electrons from the emitter to be
significant. Fig. 3.9 shows the peak current gain variation for different emitter lengths and
emitter dopings for both SALTran and LBT structures. We notice that when the doping is far
smaller than the peak base doping, the current gain enhancement is maximum. For example,
when the emitter doping is 1x1014 cm-3, the current gain enhancement is largest for shallow
emitter lengths which makes it very attractive for scaled down VLSI BJTs. Like NPN
SALTran here also we notice that for deeper emitter lengths too the current gain enhancement
41
900
14 -3 17 -3
10 cm 10 cm
800
15 -3 18 -3
10 cm 10 cm
Cutoff frequency (MHz)

700 16 -3 19 -3
10 cm 5x10 cm
600
500
400
300
200
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Fig. 3.10 Cutoff frequency versus emitter length of SALTran for different emitter dopings
(1x1014 /cm3 to 1x1018 /cm3 ) and LBT structure for an emitter doping of 5x1019 /cm3
is still impressive when the emitter is lightly doped. This is an indication that the SALTran
concept can be conveniently applied to even high voltage power bipolar transistors in which
low current gain is often a problem. In the case of deeper emitter junctions, the current gain
of SALTran is smaller than that of shallower emitter due to the increased emitter region
recombination for deeper emitters.
The peak cutoff frequency variation with emitter length and emitter doping is shown
in Fig. 3.11. It is seen that with proper optimization of emitter length and emitter doping we
can get both high current gain and high cutoff frequency.
42
3.5.3 Hot Carrier Injection Problem
Hot carrier injection being a major reliability concern for bipolar transistors, for PNP
SALTran also we have studied its susceptibility to reverse bias emitter base voltage which
degrades the transistors performance [38].
In bipolar transistors, the heavy doping in the emitter and base regions results in
sufficiently large electric field even at typical emitter-base reverse-bias voltages and is the
primary cause of the hot electron injection problem. In order to investigate this, we have
compared the simulated reverse emitter-base characteristics of SALTran and LBT in Fig.
3.11 (a). It can be seen that because of low emitter doping (1x1014 cm-3) used in SALTran, its
reverse breakdown voltage is significantly larger than that of LBT which breaks down
approximately at a reverse bias of 8 V. The electric field in the emitter region shown in Fig.
3.11 (b) at breakdown (8 V) clearly shows that in the case of LBT with its heavily doped
emitter, there is a larger peak electric field at the emitter-base junction compared to that of
SALTran whose emitter is completely depleted because of low doping. It may be pointed out
that although there is a large electric field at the metal-semiconductor interface of the
SALTran, carrier multiplication is very unlikely to take place here due to the extremely
narrow thickness of the high electric field region [40]. In the case of SALTran, therefore, the
lightly doped emitter not only helps in realizing a large gain but it also results in a reduced hot
carrier injection.
43
-12
10
-13
10 SALTran

LBT
-14
10
-15
10
-16
10
-17
10
0 5 10 15 20
Reverse base emitter voltage (V)
-800
-700
SALTran
-600 LBT
-500
-400
-300
-200
-100
0
0.0 0.1 0.2 0.3
Fig. 3.11(a) Reverse break down characteristics of the emitter-base junction of SALTran and
LBT structures and (b) Electric field in the emitter region of SALTran and LBT structures at
a reverse bias of 8 V.
44
3.5.4 Temperature study on current gain
Fig. 3.12 shows the effect of temperature on normalized current gain i.e β(Τ)/β300 where
β(Τ) is the current gain at a given temperature, while β300 is the current gain at room
temperature . LBT shows an increase in current gain with temperature while SALTran shows
a decrease of current gain till 350 K and then an increase. The percentage increase in case of
SALTran is less as compared to the LBT. This lower or negative temperature co-efficient for
PNP SALTran makes it very attractive for high temperature applications.
1.6
1.5 SALTran
LBT
1.4
1.3
β(T)/β300
1.2
1.1
1.0
0.9
300 350 400 450
Temperature(K)
Fig. 3.12 Normalized peak current gain versus temperature for SALTran and LBT
45
3.5.5 Effect of Interface Traps on Current Gain
Since a Schottky-Ohmic contact is employed at the emitter of SALTran, it is obvious
that there could be interface traps at the metal-semiconductor interface depending on the
surface preparation and metal deposition method employed. Both acceptor and donor type
interface traps are known to be present which will affect the band bending. Since band
bending is crucial to create an accumulation of holes in SALTran, it is of practical interest to
examine the extent to which the presence of interface states will affect the current gain.
We have introduced the typical range of interface traps in the simulator to study their
influence on the device characteristics. The effect of interface traps, for example, have been
carried out earlier using simulation in the case of Schottky junctions on silicon [42]. In the
device simulator ATLAS, we have introduced both donor and acceptor type interface traps to
see their effect on the current gain of SALTran. For acceptor(or donor) type traps, we have set
the trap energy level(E.level) at 0.49 eV from the conduction(or valance) band. The
degeneracy factor(degen) for the trap level is chosen to be 12 and the capture cross-sections
for electrons(sign) and holes(sigp) are taken to be 2.84x10-15 cm2 and 2.84x10-14 cm2
respectively.
Fig. 3.13 shows the peak current gain of SALTran with an emitter doping of
1x1014/cm3 and emitter length of 0.3 µm as a function of both acceptor and donor type traps
at the interface. We observe that the current gain decreases as the interface trap concentration
increases and that the effect is more pronounced if both acceptor and donor type traps are
present. We have observed an increase in the simulated base current when the trap
concentration is increased and this, therefore, will cause the current gain to decrease.
However, even in the presence of a significant number of interface traps, the reduction in the
46
240
235
Peak current gain 230

E.Level=0.49 eV
225 Degen=12
2
220 Sign=2.84e-15 cm
2
Sigp=2.84e-14 cm
215 Donor or acceptor states only
Both donor and acceptor states
210
8 9 10 11 12
10 10 10 10 10
-2
Density of states (cm )
Fig. 3.13 Peak current gain versus trap density for SALTran and LBT structures.
current gain is very small. Therefore, if the surface preparation is well controlled as is the
practice in most advanced fabrication procedures, it should be possible to preserve the current
gain enhancement of the proposed SALTran structure. Therefore, the interface states should
not be a cause for concern.
3.6 Conclusions
The concept of surface electron accumulation to increase the current gain almost without
affecting the cutoff frequency of PNP bipolar transistors is successfully shown by using 2-D
process and device simulation. We have demonstrated that for the PNP transistor also the
presence of a Schottky-Ohmic contact at the emitter results in a reflecting boundary for the
minority carriers resulting in a significant improvement in the current gain of the bipolar
transistors. We have demonstrated the less susceptibility of SALTran to hot carrier injection
47
compared to LBT. Since the SALTran structure obviates the need to create a high-low
junction in the emitter region and since its performance improves for both shallow and deep
emitters, the proposed PNP SALTran concept should be useful to the designers to enhance the
bipolar transistor performance in analog VLSI applications where high performance PNP
transistors are often required.
48
CHAPTER 4
Implementation of SALTran concept on power SiC BJT

4.1 Introduction
Silicon Carbide (SiC) has been recognized as the choice for high voltage, high temperature,
high power applications because of its large bandgap and high critical electric field [44, 45].
Power MOSFETs [46, 47] are yet to be developed due to poor MOS channel mobility and
reliability, especially in 4H-SiC. On the other hand, bipolar devices such as GTOs[48-50]
have demonstrated high blocking voltage and high on currents, taking full advantage of the
material properties of SiC. Current gain is a key parameter for power BJT as it decides the
driving loss of the transistor. But the power SiC BJTs reported in literature exhibit low current
gain usually in the range of 10-15. This is mainly because of the poor carrier lifetimes in SiC
material. The main objective of this chapter is to therefore, implement the SALTran concept
on power SiC BJT using a two dimensional device simulator ATLAS [37] and examine if the
current gain of the SiC BJT can be improved. Based on our simulation results we demonstrate
that the performance of power SiC SALTran is better than conventional power SiC BJT in
terms of high current gain. Also we observe that due to low emitter doping required in the
case of SALTran, the complexity involved in high doping epitaxial growth can be avoided
for the SiC BJT.
4.2 Device structure and parameters
In order to validate our simulation results we have first implemented the power SiC
BJT already reported in literature [13] in ATLAS with the following parameters. The
collector drift-region thickness is 20 µm with a uniform doping of 2.5x1015/cm3 and the n+
49
Emitter
N, 0.3 µm
Base
P+ P+
P, 2.5x1017 cm-3, 0.4 µm
P, JTE P, JTE
N-, 2.5 x 1015 cm-3, 20 µm
N+ 4H-SiC Substrate
Collector
Fig. 4.1 Schematic cross section of the Power SiC SALTran and Power SiC BJT
collector doping is 1x1019/cm3, the p-base thickness is taken as 1 µm with a uniform doping
of 2.5x1017/cm3 while the emitter doping is 1x1019/cm3 with thickness 0.75 µm. The JTE
doping is taken as 2.5x1017/cm3. The cell pitch for the structure is taken to be 14 µm. For the
above dimensions, we have adjusted the recombination parameters in our simulation so that
our simulated peak current gain matches with the reported experimental current gain of the
published structure[13] which is approximately 10. Fig. 4.2 shows the band diagram in the
emitter-base region for both power SiC SALTran and power SiC BJT structures.
50
3 Power SiC SALTran
Power SiC BJT
2
Conduction band
Energy (eV) 1
0
Fermi level
-1
Metal
Valence band
-2
-3
-4 Emitter Base
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

5
Power SALTran V =2.96 V
4 Power SiC BJT
BE
Hole quassi fermi level
3
2
Conduction band
Energy (eV)
1
0
Electron quassi fermi level
-1
-2 Valence band
Metal
-3
-4 Emitter Base
-5
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fig. 4.2 Band diagram of emitter-base region (a) without bias and (b) with bias
51
4.3 Design methodology
Fig. 4.1 shows the cross-sectional view of the optimized power SiC BJT and power
SiC SALTran. To apply the SALTran concept to the power SiC BJT reported in [13], we have
optimized the thickness of the emitter and base thickness to 0.3 µm and 0.4 µm respectively.
It may be noted that the base thickness is reduced compared to the original structure in [13]
to make sure that the base region recombination does not overshadow the gain enhancement
provided by the SALTran concept. Also for the power SALTran we have changed the emitter
doping to 1x1014 /cm3. Moreover for the emitter contact in power SALTran, we have chosen a
metal with very low workfunction (3.35eV) e.g magnesium, to obtain surface accumulation
near the emitter contact. In the following sections we show the comparison of the power SiC
SALTran with the power SiC BJT which differ only in their emitter doping and emitter
contact.
4.4 Simulation results
We have taken the value of electron affinity and band gap for the 4H-SiC to be 3.9 eV and 3.2
eV respectively. We have used the two-dimensional simulator ATLAS to understand the DC
characteristics of the proposed structure. Drift-diffusion calculations are carried out using
appropriate physical models given in ATLAS for 4H SiC. The field dependent mobility [51]
and the Arora mobility [52] models are used and the bandgap narrowing effect is taken
into account. For recombination we have incorporated SRH and Auger recombination
mechanism. SRH minority carrier lifetime coefficient for electrons and holes are tuned to be
30 nS and 6 nS respectively, while the SRH equilibrium concentration is 5x1016 cm-3 for both
electrons and holes. The incomplete ionization is also taken into account.
52
Fig. 4.3 shows the output characteristics of power SiC SALTran and power SiC BJT.
The comparison shows that the current driving capability of power SiC SALTran is higher as
compared to the power SiC BJT. Our simulations indicate the power SiC SALTran device
shows a high BVceo of around 1700 V. The current gain comparison in Fig. 4.4 shows that
the power SiC SALTran exhibits almost double the current gain of the power SiC BJT. The
gummel plots in Fig. 4.5 clearly shows that the high current gain of the power SALTran is due
to reduced base current. The reduced base current in the case of power SiC SALTran can be
attributed to the reduction in number of holes reaching the emitter because of the SALTran
effect.
0.5
Power SiC SALTran
Power SiC BJT
0.4 IB=0.5 µA to 2 µA
Collector current (mA)
Step 0.5 µA
0.3
0.2
0.1
0.0
0 20 40 60 80 100
Fig. 4.3 Output characteristics of the power SiC SALTran and power SiC BJT
53
140 VCE= 10 V
120
Power SiC SALTran
100 Power SiC BJT
Current gain
80
60
40
20
0
-9 -8 -7 -6 -5 -4 -3
10 10 10 10 10 10 10
Fig. 4.4 Current gain of power SiC SALTran and power SiC BJT
-3
10
Collector and base currents (A)
VCE=10 V
-5
10 Power SiC SALTran
-7 Power SiC BJT
10
IC
-9 IB
10
-11
10
-13
10
-15
10
1.5 2.0 2.5 3.0 3.5
Fig. 4.5 Gummel plots of power SiC SALTran and power SiC BJT
54
The Schottky-Ohmic emitter contact in the case of power SiC SALTran causes an
accumulation of electrons near the emitter contact as shown in Fig. 4.6, also the minority
carrier profile is shown in Fig. 4.7. This results in a high electric field near the emitter contact
as shown in Fig. 4.8 which causes the reflection of holes coming from the base. Because of
the presence of this reflecting boundary in the emitter to holes coming from the base, the hole
gradient in the emitter decreases reducing the base current. This is clearly indication that the
SALTran effect works not only for lateral high speed bipolar transistors but is also effective
for vertical power bipolar transistors. However, when applying the SALTran concept to the
power transistors, care should be taken to see that the base width is of some reasonable value
so that the base recombination does not overshadow the potential benefits of the reflecting
boundary in the emitter.
1022
Electron concentration (cm-3)
1018

Power SiC BJT
1010
0.0 0.1 0.2 0.3
Distance from emitter contact (µ m)
Fig. 4.6 Electron concentration in the emitter region of power SiC SALTran and power SiC
BJT
55
1020
Carrier concentration (/cm3)
Power SALTran
1010 Emitter base junction
Power SiC BJT
100
10-10
10-20
10-30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Distance from emitter contact ( µ m)
1018
Carrier concentration (/cm3)
VBE=2.96 V Emitter base junction
1016
1014
1012 Power SALTran

Power SiC BJT
1010
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Distance from emitter contact ( µ m)
Fig. 4.7 Minority carrier profile in the emitter-base region (a) without bias (b) with bias
56
500

Electric field (kV/cm) Power SiC BJT
300
200
100
0.0 0.1 0.2 0.3

Fig. 4.8 Electric field in the emitter region in power SiC SALTran and power SiC BJT
Fig 4.9 (a) and 4.9 (b) show the current gain for different temperatures for the power
SiC SALTran and the power SiC BJT. We observe that in both the cases the current gain
decreases with increasing temperature. Further the effect of temperature on normalized
current gain i.e β(Τ)/β300 is also plotted in Fig. 4.10, where β(Τ) is the peak current gain at a
particular temperature and β300 is the peak current gain at room temperature. Power SiC
SALTran shows a higher negative temperature coefficient for the current gain due to low
emitter doping. The negative temperature coefficient for current gain is due to deep level
acceptors in the base region [53]. At elevated temperatures, the minority carrier lifetime
increases, this causes a significant increase in the current gain
57
140
T= 300 K to 450 K 300 K
120 Step 50 K
100
Current gain
(a)
80
60 450 K
40
20
0
-8 -7 -6 -5 -4 -3
10 10 10 10 10 10
80
T=300 K to 450 K 300 K
70
Step 50 K
60
50
Current gain
(b)
40 450 K
30
20
10
0
-8 -7 -6 -5 -4 -3
10 10 10 10 10 10
Fig. 4.9 Current gain versus collector current for different temperature for (a) power
SiC SALTran and (b) power SiC BJT
58
Power SiC SALTran
1.0
(β300=140)
Power SiC BJT
β(T)/β300 0.9 (β300=70)
0.8
0.7
0.6
250 300 350 400 450 500
Temperature (K)
Fig. 4.10 Normalized peak current gain of power SiC SALTran and power SiC BJT
of the conventional silicon bipolar devices. However, in SiC npn BJTs, due to deep level of
acceptors, holes that were frozen out at room temperature ionize at elevated temperatures,
resulting in higher hole concentrations in the base at high temperatures. This effect reduces
the emitter injection efficiency of the device at elevated temperatures, which cancels out the
increasing minority carrier lifetime in the base region and keeps the current of the SiC npn
BJTs almost stable. This negative temperature coefficient makes this device attractive for
paralleling and for preventing thermal runaways [54]. In Fig. 4.11 we have plotted peak
current gain for different temperatures against 1/KBT of power SALTran and power SiC
structure. The slope of the natural logarithm of peak current gain curve for different
temperatures gives the activation energy which is nothing but the difference of the effective
bandgap narrowing of the emitter and the base[34].
59
∆Eg=-44.5 meV
Peak current gain 100 ∆Eg=-37.5 meV
Power SiC SALTran

Power SiC BJT
10
24 28 32 36 40
1/KBT(eV-1)
Fig. 4.11 Peak current gain versus 1/KBT for power SiC SALTran and and power SiC BJT.
Since the slope for the line is not constant, as evident from the curve, we have taken the slope
which is followed by maximum number of points, as the activation energy. Thus we see that
the activation energy comes out to be -44.5 meV and -37.5 meV for power SiC SALTran and
power SiC BJT respectively. This shows that in the case power SiC SALTran, the current gain
decreases at a higher rate than the power SiC BJT making the SALTran structure more
suitable for high temperature applications.
4.5 Conclusions
In this chapter we have successfully implemented the SALTran concept on the power
SiC BJT. The high current gain obtained for the proposed structure results in the low driving
loss, so the device should be effective for high voltage applications. Further the high current
60
gain can be traded off to obtain better output characteristics in terms of increased early
voltage, by increasing the base doping. The power SiC SALTran is also shown to be more
suitable in situations where thermal runaway due to an increase in temperature is a problem.
61
62
CHAPTER 5
Conclusions
In this thesis work, we have proposed a new bipolar transistor concept called Surface
Accumulation Layer Transistor (SALTran) and we have successfully implemented the
concept on (i) NPN lateral structure on SOI, (ii) Lateral PNP structure on SOI and (iii)
vertical SiC power BJT. The SALTran and conventional lateral Bipolar transistor on SOI or
the conventional vertical SiC power BJT were implemented using process simulator
ATHENA and DC and AC characteristics of the SALTran NPN and PNP were compared with
normal NPN and PNP lateral bipolar structure using two dimensional device simulator
ATLAS. We have explored the characteristics for various emitter doping and emitter length.
Based on our simulation results we have demonstrated that the proposed SALTran lateral
bipolar structure exhibits a significantly enhanced current gain, thermal stability, less hot
carrier degradation along with almost same cut-off frequency, when compared with the
conventional PNP and NPN LBT structures. Further there is no complexity involved in the
fabrication steps and the structure can be obtained just by changing the type of emitter
contact. Therefore the proposed SALTran lateral structure can find importance in large
number of VLSI applications, especially in mixed signal applications, not only due to their
high performance but also because of smaller size and compatibility with the existing CMOS
process. Further if we take the emitter doping and the collector drift doping to be same then
apart from the high performance which we obtain, the need for emitter implantation is
avoided thus it reduces one process step.
We have also implemented the SALTran concept on SiC power BJT to enhance its
current gain as the drive loss can be reduced considerably by increasing the current gain of a
63
power BJT. The SALTran concept is very general which can be successfully implemented on
different structures to enhance performance just by choosing a metal of proper workfunction
for the emitter contact so that surface accumulation near the emitter contact is ascertained.
It is worthwhile to point out a few limitations of the SALTran concept. These are as
follows:
• Since the SALTran concept is based on the principle of reducing the base current by
reflecting the majority carriers from the base thus reducing the minority carrier
gradient in the emitter region, it is not so effective for the power devices with very
high base width where the base current is dominated by the recombination in the base
region and so reducing the emitter recombination component of the base current is not
of much help in realizing high current gain.
• SALTran concept relies on metal semiconductor contact. Therefore, due to the
surface states near the emitter contact, Fermi level pinning may occur due to which the
gain is expected to reduce. One should take extra precautions for making the contact
for the device to meet the expected performance.
Scope of Future work
Some specific extension of the present work are
1. The study can be extended to silicon power BJTs which are known to have less base
recombination compared to the SiC power BJTs.
2. The SALTran concept can be further applied to the SiGe HBTs so that these can be
further optimized to get very high cutoff frequency.
3. Fabrication of these devices could be carried out to study the effect of temperature
variation and the emitter contact properties.
64
4. Although the SALTran concept has been demonstrated in this thesis on lateral BJTs
with a base width of approximately 0.4 µm, this study can be extended to transistors
with very narrow base widths to realize high cut-off frequencies.
65
66
Appendix A
TITLE Input file for NPN SALTran process simulation for emitter doping of 4.5x1014
cm-3 and emitter length 0.3 µm
Go ATHENA
line x loc=0 spacing=0.1
line x loc=6.4 spacing=0.1
line x loc=6.41 spacing=.02
line x loc=11 spacing=.2
#
line y loc=0 spacing =.0475
line y loc=.38 spacing=.0475
#
init oxide
## INITIALIZING SOI
deposit silicon thick=0.20 c.phosp=4.5e14 dy=0.01 ydy=0.00
deposit nitride thick=0.50 dy=0.10 ydy=0.00
etch nitride right p1.x=8.6
## N+ COLLECTOR IMPLANT
implant phosp dose=5e14 energy=100 s.oxide =.03 tilt=0
diffus time=30 temp=950
struct outf=/home/data/vinod/lateral/14ntap.str
etch nitride all
deposit oxide thick=.8 dy=.1 ydy=0.0
etch oxide left p1.x=7.05
deposit nitride thick=.12 dy=.01 ydy=0.0
etch nitride thick=.12
etch oxide above p1.y=-0.8
etch nitride all
struct outf=/home/data/vinod/lateral/14ntap2.str
etch oxide start x=6.425 y=-0.7
67
etch cont x=6.425 y=-0.8
etch done x=6.93 y=-0.7
## BASE IMPLANT
implant boron dose=3.5e12 energy=20 s.oxide=.03 tilt=0
implant boron dose=3e12 energy=30 s.oxide=.03 tilt=0
struct outf=/home/data/vinod/lateral/14nide_org2.str
diffuse time=40 temp=800 nitro press=1.00
#
deposit poly thick=.07 dy=.01 ydy=0 c.boron=5e19
## CONTACT
etch poly thick =.07
struct outf=/home/data/vinod/lateral/nide_org4.str
struct outf=/home/data/vinod/lateral/14incase_comp.str
etch silicon left p1.x=6.5
etch oxide right p1.x=9
deposit alu thick=1 dy=.02 ydy=0
etch alu above p1.y=-0.8
etch alu start x=0 y=-1
etch cont x=6.6 y=-1
etch cont x=6.6 y=-.228
etch done x=0 y=-.228
#
electrode x=7 name=base
electrode x=.5 name=emitter
electrode x=10 name=collector
#
struct outf=/home/data/vinod/lateral/14remnide65.str
68
TITLE Input file for NPN SALTran process simulation for emitter doping of 1x1018 cm-3
and emitter length 0.3 µm
Go ATHENA
line x loc=0 spacing=0.1
line x loc=6.4 spacing=0.1
#
#
init oxide
## INITIALIZING SOI
struct outf=/home/data/vinod/lateral/ntap1.str
etch nitride all
etch oxide left p1.x=7
save outf=/home/data/vinod/lateral/ntap2.str
struct outf=/home/data/vinod/lateral/ntap3.str
## EMITTER IMPLANT
implant phosp dose=2.5e13 energy=50 s.oxide=.03 tilt=0
#
diffus time=60 temp=965 nitro press=1.00
#
diffus time=60 temp=900 weto2 press=1.00 hcl.pc=0
69
etch nitride all
## BASE IMPLANT
deposit poly thick=.3 dy=.02 ydy=0
#
implant boron dose=2.5e15 energy=70 s.oxide =.03
## CONTACT
etch poly thick =.3
#
diffuse temp=850 time=80
etch alu above p1.y=-1
#
electrode x=6.7 name=base
#
struct outf=/home/data/vinod/lateral/internide65.str
quit
70
TITLE Input file for NPN SALTran process simulation for emitter doping of 5x1019 cm-3
Go ATHENA
#
#
init oxide
## INITIALIZING SOI
##
struct outf=/home/data/vinod/nlateral/testtemp_org1.str
etch nitride all
etch oxide left p1.x=7
## EMITTER IMPLANT
implant phosp dose=2e15 energy=50 s.oxide=.03 tilt=10 rotation=180
diffus time=60 temp=805 weto2 press=1.00 hcl.pc=0
etch nitride all

## BASE IMPLANT
71
diffuse time=20 temp=950
deposit poly thick=.3 dy=.02 ydy=0
implant boron dose=2.5e15 energy=70 s.oxide =.03
##CONTACT
etch poly thick =.3
diffuse temp=850 time=80
struct outf=/home/data/vinod/nlateral/incase60.str
#
#
electrode x=1 name=emitter
#
struct outf=/home/data/vinod/nlateral/closenfinal65.str
etch alu start x=0 y=-0.178
struct outf=/home/data/vinod/nlateral/closenfinal65_rev.str
quit
72
TITLE Input file of NPN SALTran of emitter doping of 4.5x1014 cm-3 and emitter
length 0.3 µm for gummel and frequency plots
Go ATLAS
mesh infile=/home/data/vinod/lateral/14remnide65.str
models bipolar kla fermi print temp=300
output qfn qfp con.band val.band flowlines e.field
#
contact name=emitter alu workfun=3.9
contact name=base p.poly surf.rec vsurfn=5.5e4
contact name=collector
material taun0=6.5e-6 taup0=1e-6 nsrhn=5e16 nsrhp=5e16
method autonr trap maxtrap=5
#
solve init
save outf=/home/data/vinod/lateral/init_14udense65.str
solve prev
solve vcollector=.01
solve vcollector=.1
solve vcollector=1
solve vcollector=3
log outf=/home/data/vinod/nlateral/14remnide65.log
solve vbase=.1 vstep=.05 vfinal=.6 name=base
solve vbase=.6 vstep=.02 vfinal=1 name=base
extract name ="ft" max(curve(i."collector",g."collector""base"/(2*3.14*c."base""base")))
outf="/home/data/vinod/nlateral/14reminde65.dat"
tonyplot /home/data/vinod/nlateral/14remnide65.log
quit
73
TITLE Input file for NPN SALTran of emitter doping of 4.5x1014 cm-3 and emitter
length 0.3 µm for output characteristics
Go ATLAS
mesh infile=/home/data/vinod/nlateral/14remnide65.str
models bipolar kla fermi
impact selb
contact name =emitter alu workfun=3.9
method newton autonr maxtrap=5
solve init
solve prev
solve vbase=0 vstep =.05 vfinal= 1 name=base
contact name= base current
solve ibase=1e-10
save outf= /home/data/vinod/nlateral/14oup_iclow5.str master
solve ibase=3e-10
save outf=/home/data/vinod/nlateral/14oup_iclow6.str master
solve ibase=5e-10
solve ibase=7e-10
solve ibase=9e-10
##
load infile=/home/data/vinod/nlateral/14oup_iclow5.str master
log outf=/home/data/vinod/nlateral/14oup_iclow5.log
solve vcollector=.1 vstep=.1 vfinal=5 name=collector
solve vcollector=5.5 vstep=.5 vfinal=25 name=collector compliance=1e-5 cname=collector
##
##
solve vcollector=.1 vstep=.1 vfinal=5 name=collector master
##
74

quit
75
TITLE Input file of NPN SALTran of emitter doping of 4.5x1014 cm-3 and emitter
length 0.3 µm for reverse emitter base breakdown
Go ATLAS
mesh infile=/home/data/vinod/lateral/14remnide65.str
models bipolar kla fermi print
impact selb
output qfn qfp con.band val.band flowlines e.field
#
method autonr trap maxtrap=5
#
solve init
log outf=/home/data/vinod/nlateral/14rev_breakide65.log
solve vemitter=0.1
solve vemitter=0.1 vstep=.1 vfinal=5.5 name=emitter
save outf= /home/data/vinod/nlateral/prof_14revudense65.str
solve vemitter=5.5 vstep=.5 vfinal=10 name=emitter
solve vemitter=10 vstep=1 vfinal=40 name=emitter
quit
76
Appendix B
TITLE Input file for PNP SALTran process simulation for emitter doping of 1x1014 cm-3
Go ATHENA
line x loc=5.38 spacing =.02
#
#
init oxide
## INITIALIZING SOI
deposit silicon thick=0.20 c.boron=1e14 dy=0.01 ydy=0.00
#
etch oxide right p1.x=9.4
## P+ COLLECTOR IMPLANT
etch oxide all
# COLLECTOR IMPLANT
implant boron dose=4e12 energy=50 s.oxide=.03 tilt=25 rotation=180
struct outf=/home/data/vinod/pnp/14ath_pnptemp.str
struct outf=/home/data/vinod/pnp/14ath_pnptemp.str
etch nitride all
77
struct outf=/home/data/vinod/pnp/14ath_pnp1.str
## BASE IMPLANT
implant phosp dose=9e12 energy=20 s.oxide=.03 tilt=0
implant phosp dose=1.2e13 energy=40 s.oxide=.03 tilt=0
deposit poly thick=.2 dy=.02 ydy=0 c.phosph=5e19
## CONTACT
etch poly thick =.2
#
#
etch cont x=12 y=-0.8
etch cont x=12 y=-0.9
etch done x=6 y=-0.9
struct outf=/home/data/vinod/pnp/14ath_pnpfinal45.str
quit
78
TITLE Input file for PNP SALTran process simulation for emitter doping of 5x1019 cm-3
Go ATHENA
#
#
init oxide
## INITIALIZING SOI
deposit silicon thick=0.20 c.boron=1e17 dy=0.01 ydy=0.00
##P+ COLLECTOR IMPLANT
etch oxide all
struct outf=/home/data/vinod/pnp/ath_pnptemp.str
## EMITTER IMPLANT
diffus time=60 temp=900 press=1.00 hcl.pc=0
struct outf=/home/data/vinod/pnp/ath_pnp1.str
etch nitride all
79
struct outf=/home/data/vinod/pnp/ath_pnptemp.str
etch oxide thick=0.1
## BASE IMPLANT
deposit poly thick=.3 dy=.02 ydy=0 c.phosph=5e19
# # CONTACT
etch poly thick =.3
etch done x=0 y=-0.7
struct outf=/home/data/vinod/npm/ath_pnpfinal.str
80
TITLE Input file for PNP SALTran of emitter doping of 1x1014 cm-3 and emitter length
0.3 µm for gummel and frequency plots
Go ATLAS
mesh infile=/home/data/vinod/npm/14ath_pnpfinal45.str
models bipolar kla fermi print temp=300
output con.band val.band flowlines e.field
#
contact name=base n.poly surf.rec
method newton autonr trap maxtrap=5
#
solve init
save outf =/home/data/vinod/nlateral/ath_pnp45_init.str
solve vcollector=-.01
solve vcollector=-1.5
log outf=/home/data/vinod/nlateral/14ath_pnpfinal45.log
solve vbase=-.1 vstep=-.02 vfinal=-.5 name=base ac freq=1e6 aname=base
solve vbase=-.5 vstep=-.01 vfinal=-1 name=base ac freq=1e6 aname=base
tonyplot /home/data/vinod/nlateral/14ath_pnpfinal45.log
extract name ="ft" max(curve(i."collector",g."collector""base"/(2*3.14*c."base""base")))
outf="/home/data/vinod/nlateral/test.dat"
quit
81
APPENDIX C
TITLE Input file for Power SALTran for obtaining gummel plots
Go ATLAS
mesh
x.mesh loc=0 spacing=.5
#
y.mesh loc=-.2 spacing=.1
y.mesh loc=.3 spacing=.02
y.mesh loc=1 spacing=.16
y.mesh loc=1.2 spacing=.05
y.mesh loc=2 spacing=2
#
region num=1 material=oxide
region num=2 material=b-sic x.min=0 x.max=23 y.min=20.7 y.max=24
region num=3 material=b-sic x.min=0 x.max=23 y.min=0.7 y.max=20.7
region num=6 material=b-sic x.min=3 x.max=20 y.min=.3 y.max=0.7
region num=7 material=b-sic x.min=3.5 x.max=5.5 y.min=.3 y.max=.4
region num=8 material=b-sic x.min=17.5 x.max=19.5 y.min=.3 y.max=0.4
region num=9 material=b-sic x.min=6.5 x.max=16.5 y.min=0 y.max=0.3
82
electrode name=emitter x.min=6.5 x.max=16.5 y.min=-.2 y.max=0
electrode name=base x.min=3.5 x.max=5.5 y.min=-.2 y.max=0.3
electrode name=collector bottom
doping region=2 uniform n.type conc=1e19
doping region=3 uniform n.type conc=2.5e15
doping region=4 uniform p.type conc=2.5e17
doping region=7 uniform p.type conc=1e19
#
material material=b-sic egalpha=3.3e-4 nc300=7.68e18 nv300=4.76e18 permittivity=9.66
eg300=3.2 affinity=3.9 edb=0.065 eab=0.191 arichn=140 arichp=32
material material=b-sic taun0=3e-8 taup0=6e-9 nsrhn=5e16 nsrhp=5e16
models material=b-sic fldmob arora analytic consrh auger bgn fermi incomplete ionize print
temperature=300
output con.band val.band e.field
solve init
save outf=/home/data/vinod/sic/test_sic14_ref.str
solve prev
solve vcollector=.1
solve vcollector=.5
solve vcollector=1
solve vcollector=1 vstep=2 vfinal=10 name=collector
log outf=/home/data/vinod/sic/test_sic14_ref.log
solve vbase=.01
solve vbase=.05
solve vbase=.1
solve vbase=2 vstep=.02 vfinal=3 name=base
solve vbase=3 vstep=.1 vfinal=3.2 name=base
tonyplot /home/data/vinod/sic/test_sic14_ref.log
quit
83
TITLE Input file of Power SiC BJT for obtaining gummel plots
Go ATLAS
mesh
#
#
region num=8 material=b-sic x.min=17.5 x.max=19.5 y.min=.3 y.max=0
#
#
84
electrode name=base x.min=3.5 x.max=5.5 y.min=-.2 y.max=.3
electrode name=base x.min=17.5 x.max=19.5 y.min=-.2 y.max=.3
#
#
temperature=300
contact name=emitter
solve init
save outf=/home/data/vinod/sic/test_sic19_ref.str
solve prev
solve vcollector=.1
solve vcollector=.5
solve vcollector=1
log outf=/home/data/vinod/sic/test_sic19_ref.log
solve vbase=.01
solve vbase=.05
solve vbase=.1
solve vbase=2 vstep=.02 vfinal=3 name=base
solve vbase=3 vstep=.1 vfinal=3.2 name=base
tonyplot /home/data/vinod/sic/test_sic19_ref.log
quit
85
TITLE Input file for Power SALTran for obtaining output characteristics
Go ATLAS
mesh
#
#
region num=8 material=b-sic x.min=17.5 x.max=19.5 y.min=.3 y.max=0.4
#
86
#
#
temperature=300
impact material=b-sic selb egran=0.0 current gainn= 1.0 current gainp=1.0 an1=1.66e6
an2=1.66e6 bn1=1.273e7 bn2=1.273e7 ap1=5.18e6 ap2=5.18e6 bp1=1.4e7 bp2=1.4e7
solve init
solve prev
solve vbase=0.01
solve vbase=.1
contact name=base current
solve ibase=5e-7
save outf= /home/data/vinod/nlateral/withimp_14_sic_ic1.str master
solve ibase=1e-6
save outf=/home/data/vinod/nlateral/withimp_14_sic_ic2.str master
solve ibase=1.5e-6
solve ibase=2e-6
#
load infile=/home/data/vinod/nlateral/withimp_14_sic_ic1.str master
log outf=/home/data/vinod/nlateral/withimp_14_sic_ic1.log
solve vcollector=.1 vstep=-.1 vfinal=1 name=collector
solve vcollector=100 vstep=50 vfinal=2200 name=collector compliance =1e-3
cname=collector
87
cname=collector
#
cname=collector

solve vcollector=100 vstep=50 vfinal=2200 name=collector compliance=1e-3
cname=collector
quit
88
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92
Publications from this work
1. “A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain
Enhancement in Bipolar Transistors ,” Proceedings of 17th International Conference on
VLSI Design, January 5-9, 2004.
2. “A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar
Technology,” Proceedings of International Semiconductor Device Research Symposium
(ISDRS), Dec 10-12, 2003, Washington DC, USA.
3. “Surface Accumulation Layer Transistor (SALTran): A New Bipolar Transistor for

Enhanced Current Gain and Reduced Hot-carrier Degradation,” To appear in IEEE
Transactions on Device and Materials Reliability, 2004.
4. “Realizing high current gain PNP transistors using a novel Surface Accumulation Layer
Transistor (SALTran) concept”, Under review with IEE Proc. On Circuits,
Devices and Systems.
5. “High current gain power SiC bipolar transistors using SALTran concept,” Under review
with Journal of Solid State Electronics.
6. “A method for increasing current gain in bipolar

transistors” Patent application filed, Jan 2004.
93

Proposal and Design of SALTran - A New Surface Accumulation Layer Transistor For Enhanced Current Gain

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Proposal and Design of SALTran - A New Surface Accumulation Layer Transistor For Enhanced Current Gain

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Proposal and Design of SALTran: A New Surface

Accumulation Layer Transistor for Enhanced Current Gain

A dissertation submitted in partial fulfillment of

Under the Supervision of

Indian Institute of Technology, Delhi

Surface Accumulation Layer Transistor for Enhanced Current Gain” being

award of any other degree or diploma.

Date: April, 2004 Dr. M. Jagadesh Kumar

suggestions have continually helped me to improve my understanding.

I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory

encouraged me for completing this project.

current-driving capabilities of BJT along with better device isolation of Silicon-on-Insulator

offer an alternative way of meeting the stringent performance parameters requirements, by

are high speed or high voltage structures.

In conclusion, we have demonstrated the superior attributes offered by the SALTran

provide incentive for further experimental applications.

1.1 The Context

NPN BJT in many applications.

carrier lifetime of SiC.

In order to improve the performance of lateral Bipolar transistor on SOI several

Layer Transistor(SALTran) concept.

recombination. We have presented detailed simulation results and followed by discussions

on the physical mechanisms responsible for the improved performance of SALTran.

1.3 Objective of the project

Transistor on SOI for Complimentary Bipolar Technology, (3) Implementation of the

1.4 Organization of the thesis

♦ Chapter one: Introduction

Surface Accumulation Layer Transistor (SALTran): A New

the above difficulties.

SALTran is superior in performance compared to an equivalent lateral npn BJT on SOI in

2.2 The Surface Accumulation Layer Transistor (SALTran) Concept

concentration gradient in the emitter region. As a consequence, the application of such a

to a prodigious improvement in the current gain.

becomes a reflecting boundary for minority carriers can be given as

realizing the Schottky-Ohmic contact at the emitter.

In the following sections, we shall demonstrate using accurate two dimensional

contact does indeed enhance the bipolar transistor performance significantly.

0.3 µm 0.4 µm 1.6 µm 2.4 µm

Metal contact Poly contact Metal contact

2.3 Design Methodology of SALTran

To demonstrate the concept of SALTran on SOI and to calibrate our device

that our simulations are well validated.

2.4 Profile Design Using the Process Simulator ATHENA

Silicon film thickness tsi 0.20 µm

Buried oxide thickness tbox 0.38 µm

Metal work function for emitter contact(Titanium) 3.9 eV

Emitter length 0.3 – 5.6 µm

Base length 0.40 µm

Base region doping 5x1017 cm-3

SRH hole minority carrier lifetime coefficient (TAUP0) 1x10-6 s

Fig. 2.3 Doping profile of SALTran and LBT structures.

2.5.1 Device Characteristics

Fig. 2.5 Output characteristics of (a) SALTran, (b) LBT structures

Collector and base current (A)

Fig. 2.6 Gummel plots of SALTran and LBT structures.

-15 -13 -11 -9 -7 -5 -3

Electron concentration (/cm

1010 SALTran (4.5x10 /cm )

Carrier Concentration (/cm )

and LBT structures is shown in Fig. 2.9

2.5.2 Emitter Region Optimization

Cutoff frequency (GHz)