678 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 59, NO.

10, OCTOBER 2012

New Decomposition Theorems on Majority Logic for
Low-Delay Adder Designs in Quantum Dot
Cellular Automata
Vikramkumar Pudi and K. Sridharan, Senior Member, IEEE
AbstractThe design of low-delay multibit adders in quantum
dot cellular automata is considered in this brief. We present a
general approach for delay reduction based on two new theorems
called decomposition theorems. We consider the carry-lookahead
adder (CLA) and the carry-ow adder (CFA) as specic appli-
cations of the theorems. For 16-bit CLA and 16-bit CFA, the
decomposition theorems yield reductions in delay for the leading
carry of approximately 60% and 25%, respectively, when com-
pared to the best existing designs. In addition, the decomposition
theorems lead to designs with low areadelay product. Simulations
in QCADesigner are also presented.
Index TermsCarry-ow adder (CFA), carry-lookahead adder
(CLA), decomposition theorems, delay, majority logic, quantum
dot cellular automata (QCA).
I. INTRODUCTION
D
ESIGN OF arithmetic circuits in quantum dot cellular au-
tomata (QCA) has been of interest during the last decade.
Single-bit adder designs are reported in [1][3]. Multibit adders
have also been investigated. In particular, the ripple-carry adder
and carry-lookahead adder (CLA) have been studied in [4],
while an interesting variation on the ripple-carry adder named
as the carry-ow adder (CFA) has been explored in [5]. Designs
for specic adders based on majority logic reduction have been
presented in [6] and [7]. The motivation for the works in [6] and
[7] is the research on minimal realizations for three-variable
functions described in [8]. Recently, a variant of the ripple-
carry adder with the goal of obtaining a low-area design (in
comparison to the CFA) has been reported in [9].
The major contributions of this brief are as follows. First,
this brief develops a general approach for delay reduction of
various types of adders. This is accomplished via the devel-
opment of two new theorems (called decomposition theorems)
that examine the relationship between the initial carry and the
leading carry in a multibit adder. In particular, the theorems are
based on the observation that the nth carry in any n-bit adder
can be related to the initial carry via a purely recursive rela-
tionship that uses the 3-bit majority function. The second major
contribution of this brief is the application of the new theorems
to well-established QCA adders, namely, the CLA and the CFA.
Manuscript received January 10, 2012; revised April 12, 2012 and June 29,
2012; accepted August 4, 2012. Date of publication September 14, 2012; date of
current version October 12, 2012. This paper was recommended by Associate
Editor Y. Ha.
The authors are with the Department of Electrical Engineering,
Indian Institute of Technology Madras, Chennai 600036, India (e-mail:
sridhara@iitm.ac.in).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TCSII.2012.2213356
Fig. 1. Primitives in the QCA model.
For 16-bit CLA and 16-bit CFA, the decomposition theorems
yield reductions in delay for the leading carry of approximately
60% and 25%, respectively, when compared to the best existing
designs [4], [5]. We also give detailed results of simulations
of various adders in QCADesigner [10]. In the next section,
we review essential QCA terminology to enable presentation of
the new theorems. In the subsequent sections, we present the
applications, simulation results, and comparisons.
II. PRELIMINARIES
The QCA paradigm is based on a cell with four quantum dots
[1], [11], [12]. Each QCA cell is occupied by two electrons.
Fundamental QCA logic devices are the three-input majority
gate and inverter shown in Fig. 1. These, along with the
interconnect, complete the list of primitives.
A clocking mechanism is used to cause electrons to tunnel
through to the appropriate locations. A four-phase clocking
scheme [12] is commonly used.
A QCA design permits two options for crossover, termed
coplanar and multilayer crossover. Multilayer crossover is used
here for wire crossings since we can effectively cross signals
over on another layer and the extra layers of QCA can be used
as active components of the circuit [13].
III. NEW DECOMPOSITION THEOREMS
Theorem 1: Let x
0
, x
1
, . . . , x
n2
, x
n1
, y
0
, y
1
, . . . , y
n2
,
y
n1
, and c
0
be 2n + 1 binary inputs. Furthermore, let p
i
=
M(x
i
, y
i
, 1) and g
i
= M(x
i
, y
i
, 0). Then, carry c
n
is given by
the equation shown at the bottom of the next page.
Proof: c
n
is shown at the bottom of the next page. By
regrouping terms from i + 3 to n 1 and from 2 to
i 1 using Property 1, we get L.H.S., shown at the bottom
of the next page.
1549-7747/$31.00 2012 IEEE
PUDI AND SRIDHARAN: NEW DECOMPOSITION THEOREMS ON MAJORITY LOGIC FOR ADDER DESIGNS IN QCA 679
The new theorems are intended to obtain low-delay QCA
adder designs. Two direct formulations for the leading carry,
one in terms of majority logic and the other in terms of
ANDOR logic, are presented to motivate the need for the new
decomposition theorems (denoted by Theorems 1 and 2). Both
the direct formulations result in high delay.
The rst is a recursive majority gate formulation. Let x
0
, y
0
,
and c
0
be the inputs to a full-adder. The computation of c
n
is
given in (1) and incurs n-gates of delay.
c
n
= M (x
n1
, y
n1
, M (x
n2
, y
n2
, . . . ,
M (x
1
, y
1
, M(x
0
, y
0
, c
0
)))) . (1)
The second direct formulation is based on an approach that
uses only ANDOR logic. The computation of c
n
in this case is
shown in
c
n
= g
n1
+
0

i=n2

i+1

j=n1
p
j

g
i
+

j=n1
p
j

c
0
(2)
where p
i
= x
i
+y
i
and g
i
= x
i
y
i
. This is appropriate (for
delay reduction), however, only when AND and OR happen to
be the basic gates (for example, in CMOS technology). If one
were to use this approach in QCA, the AND and OR terms have
to be realized by majority logic, leading to poor performance
(with respect to area and delay). This is exemplied by
c
8
=(g
7
+p
7
g
6
+p
7
p
6
g
5
+p
7
p
6
p
5
g
4
)
+ [(p
7
p
6
p
5
p
4
)(g
3
+p
3
g
2
+p
3
p
2
g
1
+p
3
p
2
p
1
g
0
)]
+ (p
7
p
6
p
5
p
4
)(p
3
p
2
p
1
p
0
)c
0
. (3)
The c
8
computation requires a delay of (at least) seven ma-
jority gates (since g
i
and p
i
require one majority gate each)
assuming two-input AND and OR gates. Furthermore, the logic
requirement is high. The proposed formulation which forms
the basis of the new decomposition theorems facilitates the
computation of c
n
with less delay (by reducing the major-
ity gates in the critical path) in comparison to direct real-
ization of (2). It relies on two properties of majority logic
(named Properties 1 and 2). The proofs are direct and hence
omitted.
Property 1: If f
1
, f
2
, and f
3
are three binary inputs, then
M(f
1
, f
2
, f
3
) = M(f
1
, f
2
, 0) +M(f
1
, f
2
, 1) f
3
.
An immediate consequence of Property 1 is M(x
2
, y
2
,
M(x
1
, y
1
, M(x
0
, y
0
, z
0
))) = g
2
+p
2
g
1
+p
2
p
1
g
0
+p
2
p
1
p
0
z
0
,
where all the quantities are binary inputs.
Property 2: If f
1
, f
2
, and f
3
are three binary inputs such
that f
1
and f
2
satisfy f
1
f
2
= f
1
and f
1
+f
2
= f
2
, then
M(f
1
, f
2
, f
3
) = f
1
+f
2
f
3
.
Let g
i
=x
i
y
i
=M(x
i
, y
i
, 0) and p
i
=x
i
+y
i
=M(x
i
, y
i
, 1).
The direct calculation of g
i
+p
i
c
i
requires two majority
gates. However, in viewof Property 2, we can obtain g
i
+p
i
c
i
using only one majority gate as M(g
i
, p
i
, c
i
).
Theorem 1 describes the overall delay calculation using the
leading carry (c
n
) since other carries incur less or equal delay.
For a compact description of Theorem 1, we introduce some
additional notation. In particular, we dene two quantities,
denoted by K(i, j) and L(i, j), as shown in (4) and (5), shown
at the bottom of the page. These quantities will also be used to
present Theorem 2.
M (x
n1
, y
n1
, M (x
n2
, y
n2
, . . . , M (x
1
, y
1
, M(x
0
, y
0
, c
0
)) ))
= M (x
n1
, y
n1
, M(x
n2
, y
n2
, . . . , M(x
i
, y
i
, 0)) )
+p
n1
p
n2
p
i+1
p
i
M (x
i1
, y
i1
, M (x
i2
, y
i2
, . . . , M (x
1
, y
1
, M(x
0
, y
0
, c
0
)) )) , where 0<i <n
c
n
=M (x
n1
, y
n1
, M (x
n2
, y
n2
, . . . , M(x
1
, y
1
, M(x
0
, y
0
, c
0
)) ))
=g
n1
+p
n1
g
n2
+p
n1
p
n2
g
n3
+ +p
n1
p
n2
p
i+2
(g
i+1
+p
i+1
g
i
)
+p
n1
p
n2
p
i+1
p
i
[g
i1
+p
i1
g
i2
+ +p
i1
p
i2
p
1
(g
0
+p
0
c
0
)] [from (2)]
=g
n1
+p
n1
g
n2
+p
n1
p
n2
g
n3
+ +p
n1
p
n2
p
i+3
(g
i+2
+p
i+2
M(x
i+1
, y
i+1
, g
i
))
+p
n1
p
n2
p
i+1
p
i
[g
i1
+p
i1
g
i2
+ +p
i1
p
i2
p
2
(g
1
+p
1
M(x
0
, y
0
, c
0
))] (from Property 1)
=g
n1
+p
n1
g
n2
+p
n1
p
n2
g
n3
+ +p
n1
p
n2
p
i+4
(g
i+3
+p
i+3
M (x
i+2
, y
i+2
, M(x
i+1
, y
i+1
, g
i
)))
+p
n1
p
n2
p
i+1
p
i
[g
i1
+p
i1
g
i2
+ +p
i1
p
i2
p
3
(g
2
+p
2
M (x
1
, y
1
, M(x
0
, y
0
, c
0
)))]
L.H.S. =M (x
n1
, y
n1
, M (x
n2
, y
n2
, . . . , M (x
i+1
, y
i+1
, M(x
i
, y
i
, 0)) ))
+p
n1
p
n2
p
i+1
p
i
M (x
i1
, y
i1
, M (x
i2
, y
i2
, . . . , M (x
1
, y
1
, M(x
0
, y
0
, c
0
)) ))
K(i, j) =

M (x
i
, y
i
, M (x
i1
, y
i1
, . . . , M(x
j
, y
j
, 0)) )) , for 0 j < i
g
i
= M(x
i
, y
i
, 0), for i = j
(4)
L(i, j) =

M(x
i
, y
i
, 1)M(x
i1
, y
i1
, 1) M(x
j
, y
j
, 1), for 0 j < i
p
i
= M(x
i
, y
i
, 1), for i = j
(5)
680 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 59, NO. 10, OCTOBER 2012
The statement of Theorem 1 can be rewritten using (4) and
(5). In particular, c
n
is given by
c
n
=K(n 1, i) +L(n 1, i)c
i
[since c
i
=M(x
i1
, y
i1
,
M(x
i2
, y
i2
, . . . , M(x
0
, y
0
, c
0
)) ))]
K(n1, i)=K(n1, j)+L(n1, j)K(j1, i),
for i < j < n. (6)
We now use (6) to state Theorem 2.
Theorem 2: Let x
0
, x
1
, . . . , x
n2
, x
n1
, y
0
, y
1
, . . . , y
n2
,
y
n1
, and c
0
be 2n + 1 binary inputs. Furthermore, let c
i
be as
dened in Theorem 1. Then, K(n 1, i) +L(n 1, i) c
i
=
M(K(n 1, i), p
n1
, L(n 2, i) c
i
).
Proof:
K(n 1, i) =M (x
n1
, y
n1
,
M(x
n2
, y
n2
, . . . ,
M (x
i+1
, y
i+1
, M(x
i
, y
i
, 0)) ))
=M(x
n1
, y
n1
, 0) +M(x
n1
, y
n1
, 1)
M (x
n2
, y
n2
, . . . ,
M (x
i+1
, y
i+1
, M(x
i
, y
i
, 0)) )
=g
n1
+p
n1
K(n 2, i)
p
n1
=M(x
n1
, y
n1
, 1).
Hence,
K(n 1, i) p
n1
= [g
n1
+p
n1
K(n 2, i)] p
n1
=g
n1
p
n1
+p
n1
p
n1
K(n 2, i)
=g
n1
+p
n1
K(n 2, i)
=K(n 1, i)
K(n 1, i) +p
n1
=g
n1
+p
n1
K(n 2, i) +p
n1
=p
n1
+p
n1
K(n 2, i) = p
n1
.
K(n 1, i) and p
n1
satisfy the two conditions of Property 2.
Therefore, from Property 2, we have
M (K(n 1, i), p
n1
, L(n 2, i) c
i
)
= K(n 1, i) +p
n1
L(n 2, i)c
i
= K(n 1, i) +L(n 1, i) c
i
[since L(n 1, i) = p
n1
L(n 2, i)] .

IV. APPLICATIONS OF DECOMPOSITION THEOREMS TO

ADDER DESIGN
A. Application to CLA
Consider n = 8 and i = 4 in Theorem 1. It turns out that
i = 4 yields the best possible decomposition (leading to the
least delay). The decomposition is expressed via
c
8
= K(7, 4) +L(7, 4)c
4
. (7)
The delay incurred for generating c
8
corresponds to six majority
gates (savings of 14%). This is shown in Fig. 2.
The delay of six majority gates (via Theorem 1) for an
8-bit CLA can be reduced (to ve majority gates) by applying
Theorem 2 to c
8
. We obtain
c
8
= M (K(7, 3), p
7
, L(6, 3) c
3
) . (8)
Fig. 2. Illustration for six-majority-gate delay for the leading carry in 8-bit
CLA applying Theorem 1.
Fig. 3. Illustration for ve-majority-gate delay for the leading carry in 8-bit
CLA applying Theorems 1 and 2.
Furthermore, K(7, 3) can be expressed as given by
K(7, 3) = M (K(7, 5), p
7
, L(6, 5) K(4, 3)) . (9)
Fig. 3 shows the maximum delay for carries in an 8-bit CLA
upon application of Theorem 2. Note the reduction in delay in
comparison to Fig. 2. The realization of carries c
5
to c
7
for 8-bit
CLA is given by
c
5
=K(4, 3) +L(4, 3)c
3
(10)
c
6
=M (K(5, 3), p
5
, L(4, 3)c
3
) (11)
c
7
=K(6, 3) +L(6, 3) c
3
. (12)
Carries c
1
to c
4
are calculated as c
i+1
= M(x
i
, y
i
, c
i
). The
calculation of the sum (s
i
) is described in [7]. For larger size
CLAs (more than 8 bits), generation of the carry bits directly is
difcult, so the general approach is to use group generate (G
i
)
and group propagate(P
i
) terms. The G
i
and P
i
themselves can
be expressed as shown in
G
i
=M (x
8i+7
, y
8i+7
,
M (x
8i+6
, y
8i+6
, . . . ,
M (x
8i+1
, y
8i+1
, M(x
8i
, y
8i
, 0)) ))
=K(8i + 7, 8i) (13)
P
i
=p
8i+7
p
8i+6
p
8i+5
p
8i+4
p
8i+3
p
8i+2
p
8i+1
p
8i
=L(8i + 7, 8i). (14)
PUDI AND SRIDHARAN: NEW DECOMPOSITION THEOREMS ON MAJORITY LOGIC FOR ADDER DESIGNS IN QCA 681
Fig. 4. Thirty-two-bit CLA block diagram.
The carries c
16
and c
24
are calculated using G
1
, P
1
, G
2
, P
2
,
and initial carry c
8
as shown in
c
16
=G
1
+P
1
c
8
(15)
c
24
=G
2
+P
2
G
1
+P
2
P
1
c
8
. (16)
c
8
is used in (15) instead of the pair (G
0
, P
0
) since the latter will
result in additional logic. Furthermore, c
8
generation requires
the same resources (majority logic) as G
0
. For a 32-bit CLA,
c
24
is obtained using G
1
and P
1
with initial carry c
8
as in
(16). (Consider Fig. 4; the generation of c
16
and c
24
using c
8
facilitates the generation of c
17
, c
25
, etc., in parallel.) c
32
is
obtained from 8-bit CLA using c
24
as initial carry.
Remark 1: For a 64-bit CLA, in addition to c
16
and c
24
, we
can obtain c
32
and c
40
as shown in
c
32
=G
3
+P
3
G
2
+P
3
P
2
G
1
+P
3
P
2
P
1
c
8
(17)
c
40
=G
4
+P
4
G
3
+P
4
P
3
G
2
+P
4
P
3
P
2
G
1
+P
4
P
3
P
2
P
1
c
8
.
(18)
Similarly, c
48
and c
52
can be calculated.
The expression for G
i
is similar to that of c
n
(where n = 8)
shown in (1). In other words, we can realize G
i
with ve
majority gates in the critical path as shown in
G
i
=M (K(8i + 7, 8i + 3), p
8i+7
,
L(8i + 6, 8i + 3)K(8i + 2, 8i)) . (19)
P
i
is given by
K(8i + 7, 8i + 3) =M (K(8i + 7, 8i + 5), p
8i+7
,
L(8i + 6, 8i + 5)K(8i + 4, 8i + 3))
P
i
=M (p
8i+7
(p
8i+6
p
8i+5
)(p
8i+4
p
8i+3
),
p
8i+2
(p
8i+1
p
8i
), 0) . (20)
Fig. 5 shows the layout in QCADesigner [10] for 8-bit CLA.
The results of the simulation of the 8-bit layout are shown
in Fig. 6. In Fig. 6, we can note that the sum of X and
Y is obtained after a 5/2-clock-cycle delay, so the rst two
outputs of the sum (shown in Fig. 6) correspond to dummy
values.
Fig. 5. QCA layout for 8-bit CLA.
Fig. 6. Simulation of the proposed QCA design for 8-bit CLA.
Remark 2: The approach in [6] can be applied to the CLA.
The results shown in Table I.
B. Application to CFA
The CFA [5] is an interesting variation on the ripple-carry
adder structure. The carry and sum in a CFA are given by
(21) and (22). The QCA design of a CFA involves a careful
rearrangement of clock zones for the calculation of sum and
carry with lower delay than CLA and ripple-carry (as reported
in [4]). However, the recursive formulation for the carry does
not permit a substantial reduction in the overall delay (even with
appropriate clock zone rearrangements at the implementation
level). The proposed decomposition theorems can be applied
to the CFA to obtain enhanced performance (especially with
respect to delay).
c
i+1
=M(x
i
, y
i
, c
i
) (21)
s
i
=M (c
i+1
, M(x
i
, y
i
, c
i
), c
i
) . (22)
The expressions for carries c
7
, c
8
, c
15
and c
16
are provided in
(23)(26). c
7
and c
15
are calculated using Theorem 1, whereas
c
8
and c
16
are calculated using Theorem 2. The logic for c
7
and
c
15
can be reused to get c
8
and c
16
.
c
7
=M (K(6, 4), L(6, 4)c
4
, 1) (23)
c
8
=M (K(7, 4), p
7
, L(6, 4)c
4
) (24)
c
15
=M (K(14, 8), L(14, 8)c
8
, 1) (25)
c
16
=M (K(15, 8), p
15
, L(14, 8)c
8
) . (26)
Remark 3: There exists deep pipelining in QCA circuits
[13]. Hence, ideas in [14][16] may be appropriate for QCA
adder design. However, even interconnect in QCA exhibits de-
lay and this is independent of the gates involved. With specic
reference to the proposed CFA, calculation of c
16
requires c
8
682 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 59, NO. 10, OCTOBER 2012
TABLE I
DELAY AND AREA FOR THE PROPOSED DESIGN (INDICATED BY Prop)
AND PRIOR DESIGNS.
$
DATA FOR 16, 32, AND 64 BITS NOT AVAILABLE
FOR THE DESIGN IN [9]. THE CLA RESULTS USING THE APPROACH FOR
THE BRENTKUNG ADDER IN [6] APPEAR AT THE BOTTOM OF THE TABLE
Fig. 7. QCA layout for modied 16-bit CFA (carry only).
but propagation of c
8
incurs some delay and K(15, 8) (Fig. 7)
can be calculated in the meantime.
The advantages in using the decomposition theorems are best
seen via the layout for a 16-bit CFA shown in Fig. 7. The calcu-
lation of c
16
using CFA directly requires seventeen clock zones
while the proposed theorems facilitate c16 calculation in just
eleven clock zones. For clarity, Fig. 7 shows only the leading
carry c
16
but the remaining carries can be computed with less
or equal delay (as c
16
). Similarly, c
32
and c
64
are calculated
using the decomposition theorems as shown in (27) and (28).
To reduce area in proposed CFA, K(31, 16) and K(63, 32) are
calculated in recursive style. Further, select carries (c
9
, c
10
,
c
11
, and c
12
in the case of 16-bit) are calculated in recursive
fashion ensuring that delay is not more than that of the leading
carry while the remaining carries are computed by applying the
decomposition theorems.
c
32
=M (K(31, 16), p
31
, L(30, 16)c
16
) (27)
c
64
=M (K(63, 32), p
63
, L(62, 32)c
32
) . (28)
V. COMPARISONS WITH PRIOR WORKS
Table I gives the details of the cell count, area, and delay of
two adders (CLAand CFA) on application of the decomposition
theorems (indicated by Prop in parentheses). The table also
presents a comparison with the best existing multibit adder
designs in QCA [4], [9]. The decomposition theorems enable
substantial delay reductions (up to 60% for CLA and roughly
25% for CFA for a 16-bit adder). With respect to the adder
in [9], the proposed CFA offers a lower areadelay product
for 8 bits. Data for 16 bits and higher are not available in
[9], but the 4-bit layout in [9] suggests high delay for exten-
sions to 16 bits and higher. The proposed CFA also offers
advantages with respect to areadelay product in comparison
to the BrentKung adder in [6] and the hybrid adder [7].
Moreover, the decomposition theorems provide a very general
methodology for delay reduction applicable to a large class of
adders.
VI. CONCLUSION
In this brief, we have developed a general methodology to
obtain low-delay adders in QCA. The methodology has been
applied to obtain the following: 1) low-delay CLA and 2) low-
delay CFA.
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