7, JULY 2005
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KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1415
(1)
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1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005
TABLE II
GAIN AND NOISE BUDGET (L1 BAND)
(5)
where is a raw data rate of 50 b/s for L1 C/A and 25 b/s for
L2 C/S.
Once the minimum required or is given by a
digital correlator to maintain the wanted tracking or acquisition
performance, the receiver sensitivity is uniquely determined by
(6) without any confusion caused by the bandwidth ambiguity.
Fig. 3. Effect of image rejection ratio on C=N performance.
Sensitivity in dBm
dBm C. Image Rejection
dB Hz dB
Hz With a finite image rejection ratio (IMRR), image band noise
dB dB Hz can contribute a substantial portion at the receiver output. Fortu-
nately, in GPS RF bands, even wider bandwidth than necessary
dBm for the C/A code was reserved for P code, and hence we can ex-
dB (6) ploit the low-IF architecture. This choice of low IF causes the
Hz
image signal to lie within the same GPS band; thus the receiver
where is the thermal noise power density at the antenna port need only to reject thermal noise of the unwanted side band. The
which equal to 174 dBm/Hz at typical room temperature and effective is related to the IMRR in the following equation:
NF is the noise figure of the receiver. For example, if a dig-
ital correlator requires of 25 dB Hz, in other words,
of 8 dB, and a radio has an NF of 4 dB, then the re-
ceiver sensitivity can go down to 145 dBm. In our work, an (7)
active antenna system composed of an antenna, prefilter, and a
low-noise amplifier (LNA) followed by an image rejection filter The loss due to a finite image rejection ratio is plotted in
was assumed as depicted in Fig. 2. Table II summarizes the gain Fig. 3. The result shows that an IMRR of 16 dB yields just a
and noise distribution in this work. 0.1-dB loss, which is negligible for most cases.
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KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1417
Fig. 4. Reciprocal mixing of the in-band thermal noise and phase noise.
TABLE III
GPS RECEIVER REQUIREMENTS
D. Phase Noise
The phase noise of a local oscillator also corrupts the spec-
trum and degrades the . The phase-noise requirement orig-
inates from the reciprocal mixing of the phase-noise spectrum
by the in-band thermal noise itself, as seen in Fig. 4. Multipli- or
cation in the time domain corresponds to convolution in the fre-
quency domain, and hence the added noise density due to the
phase noise is calculated by
(11)
To obtain less than 0.1-dB loss, the averaged phase noise should
be lower than 80 dBc/Hz, as seen in Fig. 5. This number is
(8) quite loose. From this fact, it can be inferred that a small-sized
ring voltage-controlled oscillator (VCO) is a promising solution
for a low cost, as presented in [7]. However, in the viewpoint of
where is the phase noise of an LO. Interestingly, the last power consumption, an LC resonator-based VCO is still advan-
integral term is equivalent to the absolute rms jitter of the local tageous.
oscillator, normalized to its period, thus,
E. Filter Bandwidth and ADC Bit Resolution
(9) Determining the filter bandwidth and the attenuation require-
ment is very straightforward. From the anti-aliasing and the
Similar to (7), the effective at the mixer output can be image rejection requirement, illustrated in Fig. 6, a simple sixth-
written by order (third-order in baseband-equivalent) band-pass filter with
2-MHz bandwidth fulfills both requirements. The degradation
of due to the ADC is dependent on three factors: the
number of quantization levels, the IF filter bandwidth, and the
(10) ratio of the maximum A/D threshold to the rms noise level [15].
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1418 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005
Fig. 8. Dual-band GPS application. (a) L1/L2 selectable receiver. (b) Full dual-band receiver.
The effective at the output of a quantizer can be expressed where denotes the quantization noise power, and is the
as bandwidth of the IF filter. The typical degradation intro-
duced by a limiter is approximately 2 dB. For a 2-bit ADC with
an optimal AGC, the minimum loss of 0.7 dB can be reachable
(12) [17]. The loss is marginally worse. The receiver requirements
discussed in this section are summarized in Table III.
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1420 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005
V. CIRCUIT IMPLEMENTATION
A. RF Section
The low-noise preamplifier depicted in Fig. 9 uses a single-to-
differential architecture based on the following two reasons.
First, because we adopted a dual conversion architecture, the
first mixer should be a double-balanced mixer in order to mini-
mize the LO feed-through that will cause an unacceptably large
dc offset at the second mixer output. Second, alternatively, we
can exploit a fully differential amplifier with an external balun.
However, the external balun causes an extra gain loss and NF
increase of about 1 dB. By adopting a single-to-differential am-
plifier, we can eliminate the need of an external balun and its
performance loss.
In Fig. 9, the input stage M1 is an inductively degenerated
common source stage. M3 forms a common gate amplifier while
M2 forms a common source amplifier. If the transconductance
of M3 is equal to that of M2, then the drain current of M3 is
equal in magnitude and different in polarity to the drain current
of M2. A high-voltage gain is necessary to sufficiently reduce
the noise contribution of the following mixers. The voltage gain Fig. 13. Complex filter unit cell. (a) Gm-C implementation. (b) Pole location.
(c) Frequency response.
is
provide a gain control function. A - based complex filter
(13)
as shown in Fig. 13 was adopted. The transfer function of the
unit filter cell is
The gain of the low-noise preamplifier was specified as 21 dB,
while the requirements for both the noise figure and IIP3 were
quite moderate, with values of 6 dB and 10 dBm, respectively.
Fig. 10 shows the RF mixer. A conventional Gilbert-type (14)
mixer, with a source-grounded input stage and a current where is the midband voltage gain,
bleeding technique at the load, is used to support a high gain is the real part of the complex pole, and
as well as a low-voltage operation. The IF mixer, shown in is the image part of the complex pole. It can
Fig. 11, is almost identical to the RF mixer except that it pro- be inferred from (14) that, by controlling , we can adjust
vides quadrature outputs. Due to the high gain in the preceding the filter gain without affecting the pole location. To reduce
circuits of about 32 dB, the second mixer limits the receiver the current consumption and the number of cascaded stages,
linearity. The RF section provides total gain of 44 dB, cascaded we proposed a unit filter cell as depicted in Fig. 14. In this
noise figure of 7 dB, and IIP3 of 30 dBm. circuit, , built by nMOS transistors, and and ,
built by pMOS transistors, are sharing the dc bias current. One
B. IF Section important design consideration in a fully differential complex
Fig. 12 shows a block diagram of the IF strip. The IF strip filter is the common mode stability. In common-mode opera-
consists of four cascaded stages. The first three stages make tion, the polarity of is changed to positive. This leads
three complex poles and the two variable-transconductor stages to an unwanted positive feedback loop. Applying a negative
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KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1421
common mode feedback or reducing the common mode gain Fig. 16 shows a linear cell used in the first stage. A replica
[18], can help to avoid this problem. In our work, we adopt circuit technique is used. The transconductance of the slave cell
the later method. Fig. 15 shows the final complex load circuit, is a copy of the very linear master circuit and is equal to .
including the extra transistors for common-mode gain reduc- The final stage in the receiver signal path is a 2-bit ADC
tion. The common-mode rejection ratio is given by the ratio as illustrated in Fig. 17. Using a 2-bit converter results in a
of the common-mode conductance to the differential-mode slightly improved performance compared to that of a 1-bit con-
conductance verter. The quantizer has a nominal input range of 500 mV
and provides a 2-bit output coded as Sign (SIGN) and Magni-
(15) tude (MAG) bits. The AGC feedback loop, used in our work, is
(16) similar to that used in [3].
CMRR C. Synthesizer
The synthesizer provides two LO frequencies for mixers and
a master clock signal for a digital correlator. The frequencies
(17)
are generated by an on-chip PLL including an LC VCO, a di-
vider chain, a phase-frequency detector, and a charge pump. As
Equation (17) ensures that the CMRR is far greater than 1 for seen in Figs. 7 and 18, by choosing a PLL reference frequency
the frequency band of interest. of (10.9493 MHz), the whole divider chain could
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1422 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005
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KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1423
Fig. 22. Die microphotograph of the complete CMOS receiver front-end chip
occupying 2.6 mm die area.
TABLE IV
RADIO PERFORMANCE SUMMARY
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1424 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005
to 90 C. It drains 10.5 mA from a 1.8-V supply at room tem- [15] A. A. Abidi et al., “Power-conscious design of wireless circuits and sys-
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ACKNOWLEDGMENT
The authors would like to thank M. Son for her circuit layout. Jinho Ko received the B.S. degree and the M.S.
degree in electrical engineering from the Korea
They would also like to thank W. Oh for test as well as layout Advanced Institute of Science and Technology
assistance. (KAIST), Daejeon, Korea, in 1994 and 1996, re-
spectively, where he is currently working toward the
Ph.D. degree.
From 1996 to 1998, he was with the R&D Center,
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