A CMOS Automatic Gain Control for Hearing Aid Devices

Jos6 Silva-Martinez and Jorge Salcedo-Sutber

Instituto Nacional de Astrofisica Optica y Electr61nica
Integrated Circuits Design Group
P.O. Box 51 and 216,72000
Puebla, MCxico

Abstract: In this paper a CMOS Automatic Gain amplifier's gain is controlled by adjusting the bias
Control (AGC) for Hearing aid devices is current of OTA2. If the envelope detector output is
proposed. Montecarlo analyses have shown total lower than the reference voltage, ih3 become zero
harmonic distortions below 0.5% and 0.6% for and the OTA2 bias current equals 1 ~ 2 .Hence the
uncompressed and hard compressed operations, voltage gain remains constant.
respectively. Dynamic Range is 69 dB while the
THD is around 0.5%. Power consumption for the
complete AGC is 54 pWatts under normal
conditions and 162 pWatts for maximum OlTA 2
compression operation. Attack and release times 0 I 1
vout2
/
are below than 5 ms. The AGC is operated with Vin2
ENVELOPE
+1.5 supply voltages.
- I L DETECTOR
IB 1 VgR
I. Introduction

Automatic Gain Controls play a very important -

role in modern hearing aid devices [ 1-31. An AGC
or compressor is a closed loop regulating system
that automatically adjust the voltage gain such that
the output voltage stays within a desired range.
The design of the AGC is not trivial because it is
required that the harmonic distortion components Fig. 1 .- AGC Block Diagram.
be below to 1% under all conditions of operation,
On the other hand, if Vel is larger than VER,
and its response must be fast enough [l-31.
Several AGCs have been proposed in the
CONTROL increases according to the voltage
difference, then the OTA2 small signal
literature, most of them based on rectifiers and
transconductance increases. As a result the voltage
lowpass filters. The architecture proposed in this
gain is reduced.
paper is shown in figure 1. In this topology the
The paper is organized as follows. The voltage
voltage amplifier is composed by two linearized
amplifier is discussed in section 11. In order to
fully-differential operational transconductance
reduce both attack and release times, an envelope
amplifiers. The voltage gain is very well controlled
detector is used; this circuit and the voltage
because depends on the ratio of transistor
comparator are presented in section 111. The AGC
dimensions and the ratio of bias currents; both
has been simulated using a CMOS 1.2 ym process;
parameters are precisely controlled in current
simulated results are discussed in section IV.Also,
CMOS technologies. Under compression the
breadboard results are presented in the same

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 section. In the last section some conclusions are The linear range of the OTA can be increased if
addressed. two structures are connected in series [ 5 ] ,as shown
in figure 2.
11. OTA Based Voltage Amplifier. In order to avoid of common-mode feedback
system, OTA2 is divided in two grounded
The voltage amplifier is based on two linearized structures instead of a floating one. In figure 2, the
OTAs. In the typical differential pair, the third structures are grounded by transistor Ml'.
harmonic distortion is given by HD3=(1/32) If OTAl [4] and OTA2 are used in the voltage
(Vin/VDSAT)2, where VDSAT is the saturation amplifier, the overall voltage gain is given by the
voltage of the transistors. For Vin = 100 mV and following expression.
harmonic distortion components below to -50 dB
the saturation voltage must be larger than 300 mV.
For low-voltage applications, such as hearing aid
devices, this saturation voltage is too large. The
linearized topology proposed in [4] allows to
reduce the harmonic distortion components,
making a similar effect of a saturation voltage as
large as 3.5"VDSAT. In principle, the voltage Where subscripts 1 and 2 corresponds to OTAl
amplifier can be implemented by using two similar and OTA2, respectively. icONTKOL is the current
OTA's, nevertheless some practical design generated by the amplitude controller.
considerations must be taken into account for the
implementation of OTA2. IV. Envelope Detector.
When the structure is further compressing, the bias
current for OTA2 can be as large as IB~+~CONTROL: The common sources of the differential pair shown
91B2.This represents an increment of 3 times the in Figure 3a, senses and rectifies the amplitude of
original VDSAT; this effect could cause that some the output voltages. In order to reduce the ripple
transistors become out of saturation. For this large capacitors (10 pF) and very low current
reason the saturation voltage for OTA2 must be sources (0.2 nA) are employed. The resulting
lower than 50 mV but the linearity should be good voltage V,, is compared with the reference voltage
enough in order to maintain the harmonic VER, and the result is converted to current by a
distortion components below to -50 dB for input voltage to current transducer. The current is
signals as large as 100 mV. fedback to OTA2, as shown in figure 1.

vouh

-
VER
Ve 1

vss vss

M4
I
M4
' Vb2
Fig. 3.- a) Envelope detector b) Voltage reference
vss
The current source is implemented by using current
Fig. 2.- Schematic of OTA2. cancellation techniques [6]. The implementation of
the 0.2 nA dc current source is shown in figure 4.
In this structure it is assumed that M, N, 0 and X

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 are the W/L ratios of the transistors MM, MN,
MO, and MX, respectively. In this current source,
IBIAs is divided in 4 branches; for large division
factors MM is designed much wider than the other
1
transistors, therefore most of the current flows
throughout this transistor. The output current
results from the subtraction between the drain
VDD
I[B 'p
currents of MN and MO. By using typical circuit
analysis techniques it can be demonstrated that the
output current is given by

- N-0
IREFl.2 - IB,.4S
M+N+20

If M is much larger than N and 0 then further . -.,

current division factors are obtained. For example
M=97.2, N=l, and 0=0.9 leads to a current
division factor of 1000. Therefore, for IBIAs=200
nA the output currents are IREFI,:! = 0.2 nA.
Although the sensitivity of the current source is
proportional to the factor (l-N/O)-', variations of
the output current are not relevant for this
application, nevertheless additional design
considerations must be taken into account in other
applications.
IBIAS
0 the voltage amplifier 'outputs become lower than
Fig. 5.- Implementation of OTA3.
V. Simulated Results.
In this section both simulated, obtained from the
extracted circuit, and breadboard results are
presented. For the simulations, VREF= 80 mV and
Vpulsed= (1 50 mV, 50 mV) are employed. In figure
6 the AGC response for pulsed inputs is shown;
note that both attack arid release times are less than
5 msec.
During compression operation, the error voltage
Vel-VER is small due to the high loop gain. When
the reference voltage, the capacitor of the envelope
detector is discharged by IREF.Because the high-
loop gain, small discharges in C1 rapidly reduces
I'CONTROL, hence reducing the release time.

vss
Fig. 4.- Realization of the 0.2 nA dc current
source. IBIAS=200 nA.

The implementation of OTA3 is presented in

figure 5 ; it is composed by a differential pair that 020 &, I I
is acting as a voltage comparator. Drain current of 0 00 0 01 0.02 0.03

M5 is given by IM1-1~2(M3=M4). Therefore, if Vel Time (Seconds)

is smaller than VER, iM5 = 0; on the other hand if Fig 6.- AGC Response for pulsed inputs.
Vel is higher than VERthen the OTA2 bias current

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 hp Slopped

Similar results have been obtained for an

amplitude modulated sinusoidal signal with VPEAK
= (150 mV, 50 mV), see figure 7. Montecarlo
simulations have shown harmonic distortion
components below to O S % , for 1% transistor
mismatches; these results are shown in figure 8.
For the same analyses, the inband gain varies only I I I
+0.5 dB under uncompressed operation.
- 9 8 . 2 0 0 m5
500
100.700 ms
us/div
103.200 m8
r e e l !,ma
2 50.0 m Y I 3 50.0 mV/ 4 50 0 m V I
0.00000 v 0.00000 v 0.00000 v

Fig. 9.- Experimental response for an AM input

signal.

Conclusions

A CMOS AGC system intended for Hearing Aid

Devices has been presented. The AGC shows THD
below than 0.5% and 0.6% for compressed and
L - - zn +
0 00
uncompressed operations, respectively.
TIME The power consumption for the complete AGC is
Fig. 7.- AGC response €or an AM sinusoidal input. 54 pWatts under uncompressed operation and 162
pWatts for the worst case. The input referred noise,
integrated from 100 Hz up to 10 KHz, is below
than 19 pVrms. The dynamic Range, THD - O S % ,
is 69 dB.

References
[ I ] Mead C. Killion "The K-Amp Hearing Aid: An Attempt to
Present High Fidelity for Persons With Impaired Hearing",
American Journal of Audiology, Vol. 2, No. 2, pp 51-74, July
1993.
[2] J. Francisco Duque-Carrillo, Piero Malcovati, Franco
Maloberti, Raquel PCrez-Aloe, Alexander H. Reyes, Edgar
SBnchez-Sinencio, Guido Torelli, and JosC M. Valverde,
0 10 020 030 0 40 0 50 060 "VERDI: An Acoustically Programmable and CMOS Mixed-
W o r s t case THD in% Mode Signal Processor For Hearing Aid Applications", IEEE
Journal of Solid-State Circuits, Vol. 31, No. 5,pp 634-645,
Fig 8.-Histogram of THD with transistor May 1996.
mistmatches of 1%. [3] Wouter Serdjin "The Design of Low-Power Analog
Integrated Circuits and Their Applications in Hearing
Instruments", Ph. D. Thesis, Delft University Press, 1994.
The operation of the proposed architecture has [4] F. Krummenacher and N. Johel "A 4 MHz CMOS
been experimentally verified by employing a Continuous time Filter with on chip Automatic Tuning" IEEE
single-ended breadboard prototype. For the J. of Solid-state Circuits, Vol. SC-23, pp 750-757, June 1988.
prototype, bipolar based OTAs (LM 13600) and [ 5 ] JosC Silva-Martinez, M. Steyaert and W. Sansen, "Design
Techniques for High Performance Full CMOS OTA-R-C
discrete bipolar transistors were used. Continuous-Time Filters", IEEE Journal of Solid State
Experimental results are depicted in figure 9. For Circuits, pp. 993-1001, July 1992.
compressed signal, Vi, = 180 mVp, the voltage [6] JosC Silva-Martinez and Jorge Salcedo-Sufier, "IC Voltage
gain is Av = -1 1.ldB. For uncompressed operation to Current Traducers with Very Small Transconductance",
V,, = 40 mVp and the voltage gain is -2.7dB, in Analog Integrated Circuits and Signal Processing, Vol. 13, pp.
285-293, July 1997.
both cases VREF = 50 mV.

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