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SERVICE MANUAL

Model: L2 MST1

1. Safety Precaution...1~2
2. Production Specification .3~4
3. Remote Control View

.5~

. Circuit Diagram and Component Position .~


. Basic Operations & Circuit Description .~2
. Main IC Information.2~
. Panel Information.~
. .
. List.
1.Software Upgrade .~

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

5. When replacing a MAIN PCB in the cabinet,

PRODUCT SAFETY NOTICE

always be certain that all protective are


installed properly such as control knobs,

Many electrical and mechanical parts in this

adjustment covers or shields, barriers, isolation


resistor networks etc.

apparatus have special safety-related


characteristics.

6. When servicing is required, observe the original


lead dressing. Extra precaution should be given
to assure correct lead dressing in the high
voltage area.

These characteristics are offer passed


unnoticed by visual spection and the protection
afforded by them cannot necessarily be obtained
by using replacement components rates for a

7. Keep wires away from high voltage or high


tempera ture components.

higher voltage, wattage, etc.


The replacement parts which have these

8. Before returning the set to the customer,


always perform an AC leakage current check

special safety characteristics are identified by


marks on the schematic diagram and on the parts

on the exposed metallic parts of the cabinet,


such as antennas, terminals, screwheads,metal

list.

overlay, control shafts, etc., to be sure the set


is safe to operate without danger of electrical

read the parts list in this manual carefully. The


use of substitute replacement parts which do not

shock. Plug the AC line cord directly to the


AC outlet (do not use a line isolation

have the same safety characteristics as specified


in the parts list may create shock, fire, or other

transformer during this check). Use an AC


voltmeter having 5K ohms volt sensitivity or

hazards.
9. Must be sure that the ground wire of the AC

more in the following manner.


Connect a 1.5K ohm 10 watt resistor paralleled

inlet is connected with the ground of the


apparatus properly.

Before replacing any of these components,

by a 0.15F AC type capacitor, between a


good earth ground (water pipe, conductor etc.,)
and the exposed metallic parts, one at a time.
Measure the AC voltage across the combination
of the 1.5K ohm resistor and 0.15 uF
capacitor. Reverse the AC plug at the AC
outlet and repeat the AC voltage measurements
for each exposed metallic part.
The measured voltage must not exceed 0.3V
RMS.
This corresponds to 0.5mA AC. Any value
exceeding this limit constitutes a potential
shock hazard and must be corrected
immediately.
The resistance measurement should be done
between accessible exposed metal parts and
power cord plug prongs with the power switch
"ON". The resistance should be more than
6M ohms.
AC VOLTMETER

Good earth ground


such as the water
pipe, conductor,
etc.

Place this probe


on each exposed
metallic part

AC Leakage Current Check

2113
2108

Product Specification
General Description
1. Main features

Production Description
Panel Supplier and Model
Main Chip
Market

CX LCD TV 22 PAL/SECAM System AC100V-240V


LPL:V216B1-P01
Mstar106
Europe

1.1 VIDEO SECTION

Display size
Display Resolution
Pixel Pitch
Peak Brightness
Contract Ratio
View Angle
Color Deeps
PC Resolution Supporting
HDTV Compatible
Picture Size
Picture Mode
Advanced 3D Noise Reduction
Color Temperature Control
Comb Filter
Second De-interlace for Sub picture
Picture Freeze Function
ATV RF System
DTV System MODULATION
DTV VIDEO SYSTEM
DTV SOUND SYSTEM

21.6 inch 16:9


1366X768
0.1165(H)mm0.3495(V)mm
400 cd/m2
800:1
Hor. : =170 And Vert. =160 degree
16.7M Color
VGA ,SVGA,XGA
480p, 576p, 720p, 1080i,1080p 50/60Hz
Yes
Yes
Yes
Yes
Yes (3D)
No
Yes
PAL BG/DK/I, SECAM BG/DK/L/L'
COFDM,2k/8k QPSK,16/64QAM
MPEG-2 MP@ML
MPEG-1 Layer1,2 / MPEG-2 Layer 2

1.2 AUDIO SECTION


Audio Output Power (10%THD)
Sound Mode (Preset)
SRS
Surround
Tone Control
1.3 Input Terminals

2W2
Yes
No
Yes

Yes
Antenna Input (Din Type) 1
Video (RCA) Input 1
S-Video Input 1
VGA Input 1
SCART 1
Stereo Audio Input2

1.4 Output Terminals


1.5 Others

No

Closed Caption / V-Chip


Teletext
Teletext Language
OSD Language

No
Yes
WEST/EAST/RUSSIAN/FARSI
English/French//Spanish/Portuguese/Italian/German

3113

Stereo Decode

Yes

Power Rating
Power Consumption

AC 100-240V, 50/60Hz
<60W

1.6 Support the Signal Mode


This machine can support the different from VGA signal mode in 4 kinds
No
Resolution
Horizontal
Vertical
Frequency(Hz)
Frequency(KHz)
1)
2)
3)
4)

640480
800x600
800x600
1024x768

31.50
35.16
37.90
48.4

60.00
56.25
60.00
60.00

1.7 SDTV / HDTV /HDMI(YCbCr / YPbPr)


No

Resolution

Horizontal
Frequency(KHz)

Vertical
Frequency(Hz)

1)
2)
3)
4)
5)
6)
7)

480i
480p(720480)
576i(720576)
576p(720X576)
720p(1280720)
720p(1280720)
1080i(19201080)

15.734
31.468
15.625
31.250
37.50
45.00
28.13

60.00
60.00
50.00
50.00
50.00
60.00
50.00

8)

1080i(19201080)

33.750

60.00

4113

previouse

Enter

CLOCK Teletex clock on and off

AUDIO OP

TDA1517P
12VA
U31
TDA1517

6VA

R127

NC

10K

47K

C234 100p

100nF
C245

6 CA62

R283
2.2M

470uF/16V
470uF/16V

SP_L

SP_L

SP_R

M/SS
SVRR

1
2
3
4

SP_R
H47
TPAD

VP

R280
10K

DD32
BAV99

OUT2

INV2

CA50

4 CA61

GND
GND
GND
GND
GND
GND
GND
GND
GND

1n

22K

C239

12VA

470uF/16V
+

R296

12VA

CN20

OUT1

2
5
10
11
12
13
14
15
16

C236
R288

R179

22K

1n
AMP-PLout
100uF/16V

CA464

2 -

R285

9
7

R352

AMP_LIN1

C233

10K

U32A
TL062
1

2.2u

L25 10uH

8
3 +

C257

INV1

12VA

R333
1.2K

C244

R332

R1

1.2K

1.2K

R374 3.3K

PWD_MT

R286
1K

1
5
6
4
7
3
2
8

R292
10k

Q22
3906

R298

R144

NC

10K

47K

C240 100p
C

H50
TPAD
CN21
1

R183

47U/16V

R331
NC-1K

1
2
3
4

R330

1,3 PWR-ON/OFF

NC-470R
1

Q25
NC-3904

10K

C243
Q23
NC-3904

R295

6 -

R289
22K

+ CA55
470uF/16V

3.3VU

Near MST.IC

3
R293

MUTE_AMP

1K 1

Q24
3904

H51
TPAD

R309
10K

Ground in the middle of the L/R

1
2
3
4

CON4_2.54/NC

C235 2.2u

AMP-PRout
100uF/16V

HP1

1
5
6
4
7
3
2
8
HP-JACK

100R

CA465

R294

18n
13K

AUOUTR0

C237
R299

R290
2.2M
AMP_RIN1

NC-EZJZ1V270RA/NC
DD64

U32B TL062

5 +

2.2u
C238

VCC-OP2
R281
47K

2009-9-29

R4
1.2K

470U/10V

6VA

1
2
3
4

CON4_2.54/NC
H49
TPAD

R284
10R

100R

VCC-OP2
+ CA52
100uF/16V

R278

AUOUTL0

C229
2.2u R291

R279
47K

18n
13K

R276
4.7K

C310

+
CA51
100uF/16V

DD56
NC-EZJZ1V270RA/NC

R275

0.1u

4.7K

H48
TPAD

2.2u

AMP-PRout

R325
470R

C256

R322
470R

GND
GND
GND
GND

AMP-PLout

20
19
18
17

R274
100R

R11

NC

R12

NC

R13

NC

6VA
VCC-OP2
C242
2.2u

R287
47K

3 +

R355

0R

R376

4.7K

LINEOUTL

9
B

R57
10K

Q36
NC

LINEOUTR

9
4

H6
PAD

DD53
NC-EZJZ1V270RA/NC

H13
TPAD

H12
TPAD

H5
TPAD

H7
TPAD

H11
TPAD

H10
TPAD

H4
PAD

1
2
3

5
A

H3
PAD

1
2
3

7
6

H2
PAD

Near MST.IC
Ground in the middle of the L/R

H1
PAD

1
2
3

47K

C252 100p

Q37
NC

4.7K

NC

C268
nc

C260
R304

R373

R64
10K
MUTE_AMPR315

R314

0R

R371

C312
10uF/6.3V

6 -

1
2
3

10K

C247 2.2u R307

100R

R311

18n
13K

AUOUTR1

U33B TL062

5 +
3

1
2
3

VCC-OP2
R301
47K

HOLE

6VA

NC

47K

C246 100p

MUTE_AMPR303
R308

DD51
NC-EZJZ1V270RA/NC

C259
R302

C311
10uF/6.3V

2 -

10K

R306

C241
2.2u

100R

R305

AUOUTL1

C264
nc

18n
13K

U33A
TL062
1

H8
TPAD

H9
TPAD

F3
SMD1206P100TF
1
2

5VA

R328
51K

USB_OCD_N

USB_OCD_N

R272
100K
CON42
+5V_USBO

+5V_USBO
USB_DMO
USB_DPO

C143
0.1U

1
2
3
4

CON4_2.0

3
3

USB_DP
USB_DM

R297 0R

USB_DPO
USB_DMO

R282 0R

DD58

DD44

EZJZ1V80010

EZJZ1V80010
B

H24
TPAD

L1

CON6_2.0mm

U19

VGA-B

C85

10U

VGAT_G

CA10

10U

R409

47K
C79

R196

DD43

10U

R103

100R

VGA_HSYNC1

VGA-VS

R105

100R

VGA_VSYNC1

VGAT_R

DD42

DVD_ON/OFF

R211
47K

VGA-R

R192
47K
EZJZ1V270RA
EZJZ1V270RA

R174

NC/4.7K

R111

100R DDC-SDA

DDC-SCLIN

R114

100R DDC-SCL

R101

C63

CON8

DD48
BAT54C

R106
12K

2.2u

VGA-Lin

0R

IR_in

DVDIR_EN

8
7
6
5

R112

VGA-VS

10K

C66

DD11
ADUC10S033R3/NC

PHONEJACK

EZJZ1V270RA/NC
DD17

CA5

R5
10K

D8

NC-1N4148
3

4
3
5

EZJZ1V270RA/NC
DD16

DDC-SCL
DDC-SDA

3.3VU

D9

DVD_ON/OFF

R115
12K

HD-VSW0

VGAT_G
VGAT_B
VGAT_R

2
5
11
14

S1A
S1B
S1C
S1D

DA
DB
DC
DD

4
7
9
12

DVD_YIN
DVD_PBIN
DVD_PRIN

3
6
10
13

S2A
S2B
S2C
S2D

VCC

16

GND
EN

8
15

R76

100

C97

8.2n

RGB1_SOG

1K

RGB1_Gi
RGB1_Bi
RGB1_Ri

R131

47R C46

47n

RGB1_G+

R130

47R C96

47n

RGB1_B+

R132

47R C51

47n

RGB1_R+

C155
0.1uF

IN

PI5V330

CON4
R70

1
2
3
4
5

DVD_ON/OFF
H37
TPAD

VGA-HS

10K

VCC
VCLK
SCL
SDA

R122

R121

R119
10K

24C21

10K

VGA-5V

5VU

C65
560p

EZJZ1V270RA/NC
DD14

H38
TPAD

R69
10K

2
1

VGA-5V

470R

U17

10K

DD10
EZJZ1V270RA/NC

FB

Q13
3904

5VPI

DVD CONTROL

VGA-VS
DDC-SDAIN

NC
NC
NC
GND

5VA

R138

R210
47K

5VA

U6

5VA
0.1uF

CON13

C283
C14
0.1u 10uF

VGA-HS

1
2
3
4

C186

H23
TPAD

VGA-G

C87
DD41

VGA-HS
R108

VGA-R
R88

VGA-B

VGAT_B

R109

3
3

EZJZ1V270RA

C280
10uF/6.3V

22K

ISP-TXD
ISP-RXD

22K

0R

17

16

11

0R

R156

R87

12

NC/FB 600(4.5X3.2)

L45
R113

R86

13

VGA
5
10
4
9
3
8
2
7
1
6

1
2
3
4

L55

8
7
6
5

75R

14

75R

CON7

15

75R

D1
D2
D3
D4

9435
SOIC08

470uF/16V/NC

4.7K

R145
47K

R195
47K
VGA-G

S1
S2
S3
G1

470uF/16V

1
2
3
4

5VPI

VGA INPUT

NC/FB 600(4.5X3.2)
12VU

VGA-G
VGA-B
VGA-R

R93
R94
R95

0/NC
0/NC
0/NC

RGB1_Gi
RGB1_Bi
RGB1_Ri

CON5-2.0/NC

2.2u

VGA-Rin

C68
560p

DDC-SDAIN
EZJZ1V270RA/NC

DD18
If U6=24C01/24C02,you should
solder R125 and left R119 float

DDC-SCLIN

R125
NC

P16
Y

1
2

AV1-V
Pb

AV1-V
AVOUT-V

EZJZ1V270RA/NC

0R

C18
NC

R28
C19
330p

47R
C16

47n

AV1-Vin+

SV2-Y

3
CON34

R30
75R

H45
TPAD
H44
TPAD
H43
TPAD

2
Y
P18

Pr

EZJZ1V270RA/NC

Pr

Y
SC1_FSO

8.2K
R229

SC1_FS

R231

HD-Pb

AV1-L

R32

10K

HD-Pr
1
HD-Y
1

CON6-2.0

2.2u

AV1-Lin

11

LINEOUTR

11

CON35
AV2-L

1
2
3
4

SV2-Y
H42
TPAD

CON4-2.0

R48
C40
330p

47R C42

47n

SV2-Yin

47R C77

47n

SV2-Cin

R50
75R

EZJZ1V270RA

1
2
3

AV2-R

SV2-C

L29

CON3-2.0

0R

C76
NC

H40 TPAD

R51
C74
330p

R53
75R
5VPI
R216
47K

R226
47K
R40

10K

C35

2.2u

AV2-Lin

C26
560p
DD23
NC-EZJZ1V270RA

EZJZ1V270RA/NC

1.5K

DD19

CON12

SV2-C

0R

C73
NC

3
AV2-L

LINEOUTL

H41
TPAD

L24

H39
TPAD

DD20
EZJZ1V270RA
C22

DD2
R34
NC-EZJZ1V270RA/NC 12K

DD12

LINEOUTL
AV1-R
LINEOUTR

DVD CONNECTOR

1
2
3
4
5
6

Keep AGND trace with signal


Keep spacing for L/R

Y
SC1_FSO
Pb
AV1-L

L11
DD6

75

R41
12K

3
HD-Y

C89

10U

HD-Pb

C90

10U

HD-Pr

C91

10U

C34
560p

DVD_YIN
R227
47K
DVD_PBIN

SCART
AV1-Rin

3
AV2-R

R79

470RC43

1n

RGB0-SOG

R81

47R C45

47n

RGB0_GIN+

Pb

R83

47R C48

47n

RGB0_BIN+

RGB0_RIN+

R42

10K

C37

2.2u

AV2-Rin

DD22
NC-EZJZ1V270RA

R43
12K

C38
560p

R236

2.2u

C33
560p

R246

C28

R235

10K

75R

R36

DD3
R38
NC-EZJZ1V270RA/NC 12K

75R

AV1-R

75R

24

P17

DD13

21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

SC1_FB

R232

P14

25

10
R230

SCART

DVD_PRIN

DD59 DD60 DD61

R234
47K
R225
47K

EZJZ1V270RA
EZJZ1V270RA
EZJZ1V270RA

5VA

R228
47K

Pr

R84

47R C49

47n

R129

R128

75R

75R

DD45

L68
FB220/100mA

DD62
C265

10uF/6.3V

C41

0.1u

R58
33k

VIDEO_OUT

R56
470R

3906
Q32

EZJZ1V270RA/NC
EZJZ1V270RA/NCEZJZ1V270RA/NC
3

CVBS_OUT

R54

10R

C269

10uF/6.3V

1
R60
15k

Q14
3904

R110
75R

DD63

R59
R63
120R

390R

R62

75R

AVOUT-V
B

DD35
NC-EZJZ1V270RA/NC

SPDIF Output

CON2-2.0

CON10

1
2
R71
NC

5VA
U46
3

CON40 RCA1

DVD_ON/OFF
R77
NC

1
SV1-Y
CON16 S-Vdieo
SV1-C

SV1-Y

L12

0R

C20
NC
DD4
NC-EZJZ1V270RA

SV1-Y

R29
C21
330p

47R C17

47n

SV1-Yin

R55
5VA

SPDIFOUT

2
3

C59
NC_0.1u

NC

IN

S2

VDD

GND

S1

NC_ADG779

DD31

R31
75R

SPDIF Switc

SPDIFOUT

R154
0R

AV

CON23

AV3-V

AV3-L

AV3-R

AV3-L

10

L13

DD5

C25
NC

HD-Y

R33

12

47R C23

47n

SV1-Cin

HD-Pb

HD-Pr

AV3-R

C27
330p

R45
C64
330p

47R C100

47n

AV3-Vin+

R46
75R

10K Comp_L
R82
12K

C50

2.2u

HD-Lin

C55

2.2u

HD-Rin

C47
560p

10K Comp_R
R89
12K

C254
560p

Keep AGND trace with signal


Keep spacing for L/R
Keep trace width(12mil+)

RCA_3_1
3

R35
75R

R85
DD52
EZJZ1V270RA

CLOSED TO MSD109

0R

C101
NC

11

13

0R

R80
DD29
EZJZ1V270RA

16

NC-EZJZ1V270RA

SV1-C

L28
DD28
EZJZ1V270RA

15

14
SV1-C

AV3-V

SPDIFO
R78
330R

NC-EZJZ1V270RA

D62

5VU

5VU

5VU

BAV99DW
1

5VU

DB0+

3
5

5VU

2
2

5VU

DB0-

BAV99DW
1

5
5

2
2

5VU

DB1+

DD24

BAV99DW
1

BAV99DW

DB1-

DD25

DB2+

DD26

DB2-

CLKB+
6

CLKB-

5VU

CON9
R133
R135
R137
R136
R139
R140
R141
R142
R143
R146

DB2DB1+
DB1DB0+
DB0CLKB+

RXB2P
RXB2N
RXB1P
RXB1N
RXB0P
RXB0N
RXBCLKP
RXBCLKN
DDCBSDA
DDCBSCL

10R
10R
10R
10R
10R
10R
10R
10R
10R
10R

cec

HOTPLUG

DD39
BAT54C
1
5VA

R152

22K

SDA

GND

3 R153

22K

SCL

A2

WP

A1

VCC

A0

DD55

DD50

DD54

C129
Q12
3904

5VU

U12

Q56

R324
27K

HDMI-CEC
B

2N7002
R377
NC/0R

24C02

R159
NC

0.1u

3.3VU

cec

R157
1K

10K

HOTPLUG

R388
100R

R161

RXB0N
RXB0P
RXB1N
RXB1P
RXB2N
RXB2P
RXBCLKN
RXBCLKP
DDCBSCL
DDCBSDA

RXB0N
RXB0P
RXB1N
RXB1P
RXB2N
RXB2P
RXBCLKN
RXBCLKP
DDCBSCL
DDCBSDA

CLKB-

HDMI

HOTPLUG

3
3
3
3
3
3
3
3
3
3

20

DB2+

NC-EZJZ1V270RA

22
23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

NC-EZJZ1V270RA

21
DATA2+
DATA2 SHIELD
DATA2DATA1+
DATA1 SHIELD
DAT1ADATA0+
DATA0 SHIELD
DATA0CLK+
CLK SHIELD
CLK22
CEC
23
NC
SCL
SDA
DDC/CEC GND
+5V POWER
20
HOT PLUG

NC-EZJZ1V270RA

21

R158
10K

TS_D[7:0]
8 6 4 2 8 6 4 2

RP44

7 5 3 1 7 5 3 1

TS_MDO0
TS_MDO1
TS_MDO2
TS_MDO3
TS_MDO4
TS_MDO5
TS_MDO6
TS_MDO7

RP43

100X4

TS_D[7:0]

PCM_CD_N
PCM_RESET
PCM_WAIT_N
PCM_REG_N
PCM_OE_N
PCM_WE_N
PCM_IORD_N
PCM_IOWR_N
PCM_CE_N
PCM_IRQA_N

TS_D0
TS_D1
TS_D2
TS_D3
TS_D4
TS_D5
TS_D6
TS_D7

100X4

TS_MDO[7:0]
TS_MOCLK
R167
TS_MOSTART R165
TS_MOVAL
R166

100R
100R
100R

PCM_A[14:0]

TS_CLK
3
TS_MOSTART0 3
TS_MOVAL0
3

PCM_D[7:0]

PCM_CD_N 3
PCM_RESET 3
PCM_WAIT_N 3
PCM_REG_N 3
PCM_OE_N 3
PCM_WE_N 3
PCM_IORD_N 3
PCM_IOWR_N 3
PCM_CE_N 3
PCM_IRQA_N 3

3.3VU
3.3VU
D

R397
4.7K

C459
100nF

R421
NC

U27
PCM_CD1_N
PCM_CD2_N

PCM_A[14:0] 3
PCM_D[7:0]

R393
4.7K

1
2
3

VCC

GND

5
4

3
NC7SZ32

PCM_CD_N
C460
2.2u

5VU

3.3VU

VCC-PCMCIA
R709
10K R657

VCC-PCMCIA
R708
4.7K

U7
CEM4953

C852 0.1uF
5VU

4.7K
+3.3VPCM

VCC-PCMCIA

TSSTART

VCC-PCMCIA

TS_MDI0
TS_MDI1
TS_MDI2
TS_MDI3

TS_MDI4
TS_MDI5
R391
TS_MDI6
TS_MDI7
4.7K
TS_MOCLK
PCM_RESET
PCM_WAIT_N
C209
nc

PCM_REG_N
TS_MOVAL
TS_MOSTART
TS_MDO0
TS_MDO1
TS_MDO2
PCM_CD2_N
TS_MDI[7:0]

R717

NC
C854
0.1uF

+3.3VPCM

3.3VU
R392
4.7K

R711
10K

R713
4.7K R718
4.7K

R658
R714

TS_MICLK
PCM_A12
PCM_A7
PCM_A6
PCM_A5
PCM_A4
PCM_A3
PCM_A2
PCM_A1
PCM_A0
PCM_D0
PCM_D1
PCM_D2

TSVALID
C461 +
TSCLK
10uF

5
5

C456
0.1u

4.7K
100uF

Q55
MMBT3904

PCM_PWR_CTL1

C458 +

R420
1K

D6
SS14

Q57
MMBT3904

VCC-PCMCIA

D4
D5
1N4001 1N4001

8
7
6
5

5VU

PCM_VS1

Q54
MMBT3904

R710 4.7K1

D1
D1
D2
D2

C853
B

0.1uF
1K
LOW: ON
HIGH: OFF

70
69

100

PCM_VS1
PCM_IORD_N
PCM_IOWR_N

PCM_VS1

R715

S1
G1
S2
G2

PCM_D3
PCM_D4
PCM_D5
PCM_D6
PCM_D7
PCM_CE_N
PCM_A10
PCM_OE_N
PCM_A11
PCM_A9
PCM_A8
PCM_A13
PCM_A14
PCM_WE_N
PCM_IRQA_N

PCM_PWR_CTL

R712
4.7K

GND
GND
CD1#
D3
MDO3
D4
MDO4
D5
MDO5
D6
MDO6
D7
MDO7
CE1#
CE2#
A10
VS1#
OE#
IORD#
A11
IOWR#
A9
MISTRT
A8
MDI0
A13
MDI1
A14
MDI2
WE#
MDI3
READY
VCC
VCC
VPP2
VPP1
MDI4
MIVAL
MDI5
MICLK
MDI6
A12
MDI7
A7
MOCLK
A6
RESET
A5
WAIT#
A4
INPACK
A3
REG#
A2
MOVAL
A1
MOSTART
A0
MDO0
D0
MDO1
D1
MDO2
D2
CD2#
WP
GND
GND
GND
GND

PCM_CD1_N
TS_MDO3
TS_MDO4
TS_MDO5
TS_MDO6
TS_MDO7

3.3VU

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

CONN1
PCMCIA_CONN
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

1
2
3
4

5V

RFAGC

SCL

SDA

AS

5V

XTAL OUT

AIF OUT

IF AGC

11

IF OUT1

GND
GND
GND
GND
15
14
13
12

T_RF-AGC

IF_TV
C469 10u/NC

IF_OUT_tuner

220

TDAG2-D02A-TUNER/NC

C398 33pf

ANT POW

RF AGC

AS

SCL

SDA

XTAL OUT
6

MB

T_RF-AGC

closed to tuner

AIF OUT
8

IF AGC
9

IF OUT2

C463

IF_TV

C404 0.22uf

1u

C465

10

0.1u

T_SCL
T_SDA

5V-OUT

T_SCL
T_SDA

5
5

#IF_OUT_tuner

R434

47 C118 0.1u

SIFP

R459

47 C119 0.1u

SIFM

IF_OUT_tuner

5V_TUNER

IF_AGC 5
R182
NC

C165
22nF

CA2

0.1u

closed to demod

C138

100uF/16V

10u

C284

0.1u

100uF/16V

20080506

C199

TV-Video

1K

10nF
C177

5V_TUNER

R178
TIF_AGC

R147 33R/2W

CA9

2
R457 390

R496 39k

150/NC

0.1u C348

R495 33k

R497

LM7805

OUT

GND

2009-9-29
R148 33R/2W
12VA

R426 100

R175
1K

R177
4.7K

10u

Q44
3904

R425 1001

U18

L83 FB/220_500MA

IN

47uF/16V
CA73

C313

TUNER POWER

5V_B2

5V-OUT

20080506

IF_OUT

U20

C448

5V_B2
L47

#IF_OUT

1u/NC

C446

closed to tuner
5V_TUNER
FB

220R 2009-9-29

TIF_AGC

IF OUT1

VCO/IF

220

R436

11

VCO FB

0.1u/NC

U26
R2S10407

R424 30K

R422 39K

0.22uf

10n
C347

R435

GND
GND
GND
GND

C414 0.22uf

13

FB/220_500MA/NC

#IF_OUT_tuner

5V_B1

L40

12

11

10

RE AGC

SIF OUT

RF AGC

REF IN

14

15

16
IF AGC
GND
9

17

18
SCL

SDA
EQ F/B
8

VCC
AUDIO-FB

VOUT

19

20
APC FIL

21
AFT OUT
C344 0.1uf

C346

GND

2009-9-29

T_SCL
T_SDA

5V_B1

R428
100

T_SCL
T_SDA

5V_TUNER

OUT1

47uF/16V

5V_B2

ING

0.1u
R482
100K

C317 10n

CA72
+

C464

2
1

C275

Y4
4MHz

C267

10u

C345
0.01UF

R502
150

PORT

DE-EMS

VIF2

SAW OUT2

1 IN

VIF1

U29
K3953D

VCO F/B

GND

3904

23

22
AFC FIL

24

GND

C277 10n

R503
100K

SIF IN

OUT1

ING
D9650H

Q29

R491

C258
220n

C266
0.1u

0.01UF

C318 10n

SDA 3,5

5V-OUT

2.7K

SAWOUT2

IN

SCL 3,5

100n C343

C301 1uf R507 6.8K

10K
R400

R488 1.2K

2.7K
R415

C262
1NF

5V_B1

BA277

U23

RF-AGC

5V_B2

C230 10n D66

22K

BLH-702

5V-OUT

IF_TV

R423

100K

15
14
13
12

R2S10401:PAL NTSC
R2A10407:PAL SECAM

R262

GND
GND
GND
GND
GND
GND

10

21
20
19
18
17
16

5V-OUT

IF OUT2

U22

5V_TUNER
5V_TUNER

VCC
NC
S

6
5
4

R452

1k CONTROL-AGC#

C281
0.1u

R454
0/NC
T_RF-AGC 3

FSA1156

2009-9-29

R456

L66

R453
4.7K

Q46
3906

TV-Video

R505

47

C78

47n

ATV-Vin+ 3

47

C82

47n

ATV-Vin- 3

0
C226

100K

RF-AGC

A
GND
B

Q45
3904

1
2
3

CONTROL-AGC#

T_RF-AGC

2 RF-AGC

From R2S10407 RF AGC


U34

C285

R455

CONTROL_AGC
10K

GPIO Control

NC/330p

R506
75
NC/330p
R504

To tuner RF AGC

2009-9-22

VDD_T

Vcore

VCC3.3_T
TS1_CK
TS1_DO
TS1_VALID
TS1_START

C192
22pF/NC

56PF/NC
C168

VDD_T
C

PLLVDD

21
26
22

PLLVDD
PLL1TEST
PLLGND

43

GPP3

35
36

CLK2/GPP0
DATA2/GPP1

44

3
3
3
3

12
15
16
17
18
SADD4
SADD3
SADD2
SADD1
SADD0

AGC1
AGC2/GPP2
AVDD
AGND
AGND
VDD
RFLEV

SMTEST

7
19
37
39
59
64
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD

42
41
28
29
32
33
34

CE6353

XTO

33
33
R215
R188

VIN

24

R201
R170
4.7K
4.7K

31

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AGC1
AVDD

T_SCL
T_SCL
T_SDA
T_SDA
VCC3.3_T

TS1_CK1
TS1_DO1
TS1_VALID1
TS1_START1

MICLK
MOCLK
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

63
61
49
50
51
52
53
56
57
58

MOVAL
MOSTRT

48
47

BKERR

62

STATUS
SLEEP

11
10

IRQ

DATA1
CLK1
RESET

5
4
9

C53
10uF
C1206
TS1_CK
TS1_DO

R203

RP12

33

33X4

RP13
TS1_VALID R205
TS1_STARTR181

33X4

TS_MDI0
TS_MDI1
TS_MDI2
TS_MDI3
TS_MDI4
TS_MDI5
TS_MDI6
TS_MDI7

33
33

VCC1.8_T
U11
AP1117-18
3 VIN VOUT 2
Vout 4

TSCLK

TS_MDI[7:0]
TSVALID
TSSTART

7
7
7

C441

+ C52
C44

0.1uF

10uF
C1206

0.1uF

R204

8.2K

VDD_T
SDA
SCL

SDA
SCL

3,6
3,6

VCC3.3_T

1
3
8
14
20
25
38
40
46
55
60

100

VIN

XTI

R176

30

OSCMODE

U14

27

6
IF_AGC

6
6

33
33
33
33

#IFind
0.1uF

23

#IF_OUT

2
13
45
54

#IF_OUT

VDD
VDD
VDD
VDD

R217
R219
R220
R223

2 4 6 8 2 4 6 8

330NH/NC

C178

1 3 5 7 1 3 5 7

L35

RP14
47X4

C166
22pF/NC

GND

IFind
0.1uF

1 3 5 7

IF_OUT

2 4 6 8

IF_OUT

VDD_T

C169
6
D

R180
0/NC

R207
C167 33pF

R260

10K
X1

SYS-RESET

R214

1K
2.2M

C92
0.1uF

20.48MHZ
C171 33pF

5VA

VCC3.3_T

C80
10uF
C1206

C67
0.1uF

GND

U16
GM11733
3 VIN VOUT 2
Vout 4

C70
C443

+
10uF
C1206

0.1uF

VCC3.3_T
L30

VDD_T

VCC1.8_T
L31

PLLVDD

VCC1.8_T
L38

VCC1.8_T
L32

Vcore

AVDD

FB/220_500MA
FB/220_500MA

C184

FB/220_500MA
+ C117

C131 C174 C175 C183 C187 C164

FB/220_500MA
+ C116

C185 C191 C125 C126 C128


+ C115

+ C193
10uF

2.2uF
10uF

C127
0.1uF

10uF

0.1uF

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

22.
22.
22.
56.
56.

Close to MStar IC
R118
R72
R104

56R
56R
56R

WEZM0
CASZM0
RASZM0

21
22
23

WE
CAS
RAS

DQS1
DQS0

R97
R74

22R
22R

LDQS0
UDQS0

16
51

LDQS
UDQS

LDM0
UDM0

20
47

LDM
UDM

MBA0
MBA1

26
27

BA0
BA1

24

CS

DQM1
DQM0

A8
A9
A10/AP
A11

WEZ
CASZ
RASZ

Close to DDR-SDRAM

22.
22.

U9
HY5DU561622ETP-4 256Mb_TSOP66
A0
DQ0 2
A1
DQ1 4
A2
DQ2 5
A3
DQ3 7
A4
DQ4 8
A5
DQ5 10
A6
DQ6 11
A7
DQ7 13

R73
R117

56R
56R

Close to MStar IC
BA0
BA1

R395
R396

56R
56R

14
17

NC
NC

34
48
66
6
12
52
58
64

VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

54
56
57
59
60
62
63
65

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

VREF

49

MVREF-1

CLK
CLK
CKE

46
45
44

CLKN0
CLK0
MCKE

NC
NC
NC
NC
NC
NC

19
25
42
43
50
53

MVDD
MVDD
MVDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1
18
33
3
9
15
55
61

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

2 4 6 8 2 4 6 8

29
30
31
32
35
36
37
38
39
40
28
41

2 4 6 8 2 4 6 8

MADR0
MADR1
MADR2
MADR3
MADR4
MADR5
MADR6
MADR7
MADR8
MADR9
MADR10
MADR11

1 3 5 7 1 3 5 7

MADR[12:0]

RP10/RP3456.
RP10 RP22X4
RP34 RP22X4
RP38 RP22X4
RP17 RP22X4
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
1 3 5 7 1 3 5 7

DDR-SDRAM DATA[15:0]

Close to DDR-SDRAM

R394

VCC2.5V

DMQC0

L19
FB/220_500MA

390mA

MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7

Close to DRAM
R120

DDR-SDRAM DATA[15:0] Power

MDATA[15:0]
MDATA8
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
MDATA14
MDATA15

C426
10uF

C425
10uF

R102

22R

MCLK-

R75

22R

MCLK+

150R_1%

22R CKE

Close to Mstar IC
Close to MStar IC

MCLK+
MCLK-

MCLK+
MCLK-

3
3

CKE
WEZ
CASZ
RASZ
BA0
BA1

CKE
WEZ
CASZ
RASZ
BA0
BA1

3
3
3
3
3
3

DQS[1:0]

DQM[1:0]

MADR[12:0]

MDATA[15:0]

DQS[1:0]

VCC2.5V
MADR12

DQM[1:0]
DMQC0

MADR[12:0]

R107
1K

MDATA[15:0]
MVREF-1

R116
1K

C428
100nF

C54
1nF

2M X 16bit X 8BK
DMQC0

C433
100NF

C434
100nF

C435
100nF

C436
100nF

C437
100nF

C438
100nF

C439
100nF

C440
100nF

CLOSED TO MEMORY

RP35/RP36/RP3722.
CLOSED TO MSD109

RGB0_GIN-

47n

RGB0_RIN-

9
9
9
9
9
9
9
9
R123
47R

3.3VU

C72
47nF
6

10K

10K

10K

CVBS_OUT

R404

ATV-Vin+
ATV-Vin-

R389

R353

3.3VU

6
6

HOTPLUG
DVDIR_EN

HOTPLUG
DVDIR_EN

SC1_FS
SC1_FB
SV1-Cin
SV1-Yin
SV2-Cin
SV2-Yin
AV1-Vin+
AV3-Vin+

CIN_1+
YIN_1+
CIN_2+
YIN_2+
C88
VCOM147nF
ATV-Vin+
ATV-VinAVDD_ADC
CVBS_OUT
AVDD_SIF
SIFP
SIFM
VDDC

AVDD_SIF
SIFP
SIFM

8
9
9
9
9
9
9
9
9
9

HD-VSW0

AV1-Lin
AV1-Rin
HD-Lin
HD-Rin
VGA-Lin
VGA-Rin
AV2-Lin
AV2-Rin
AUCOM

AV1-Lin
AV1-Rin
HD-Lin
HD-Rin
VGA-Lin
VGA-Rin
AV2-Lin
AV2-Rin

3.3VU
C421
100nF

11
11

11
11

AUOUTL0
AUOUTR0

AVDD_AU

AUOUTL1
AUOUTR1

VDDC
VDDP

TS_MOVAL0
TS_MOSTART0
TS_CLK

VDDC
TS_D0
TS_D1
TS_D2
TS_D3
TS_D4
TS_D5
TS_D6
TS_D7
TS_MOVAL0
TS_MOSTART0
TS_CLK

Close to IC
with width trace

VDDP

L73
FB/220_100MA

C30
10uF
AUVRM
AUVRP
AUVAG
AVDD_AU

C24
1uF

VDDC
PCM_D7100X4 RP41
PCM_D6
PCM_D5
PCM_D4
PCM_D3100X4
RP42
PCM_D2
PCM_D1
PCM_D0
PCM_A14
100X4
RP46
PCM_A13
PCM_A12
PCM_A11
PCM_A10 100
R401
PCM_A9 100
R402
PCM_A8 100
R403
VDDP
PCM_A7100X4
RP47
PCM_A6
PCM_A5
PCM_A4
PCM_A3100X4
RP48
PCM_A2
PCM_A1
PCM_A0
LED
SYS-RESET
UART-TX
UART-RX
KEY0
KEY1

AUVRP
AUVAG
C36
100nF

4
4
4
4
4
4

DQS[1:0]

33
33

R239
R240

DQM[1:0]

I2C_SCL
I2C_SDA

MADR[12:0]
MDATA[15:0]

DQM[1:0]

MADR[12:0]

MDATA[15:0]

A0
A1
A2
GND

VCC
WP
SCL
SDA

10K

8
7
6
5

R316
R312

24C512
3.3VU
R473

R476
100
100

100 EPM_WP
SCL
SDA

I2C address
at A0.

4.7K
R484

A0
A1
A2
GND

5VU
C316
0.1uF

U21

1
2
3
4

VCC
WP
SCL
SDA

8
7
6
5

10K
R358
R359
R360

CON33

1
2
3
4
5

100 SCL
100 SDA
NC

24C04

DQS1
AVDD_DDR
MDATA8
MDATA9
DQM1

I2C address
at A4

MDATA10
MDATA11
AVDD_DDR
MDATA12
MDATA13
MDATA14
MDATA15
POWER_KEY
IR_SYNC

R387
R382

U43

1
2
3
4

POWER_KEY C342
5
IR_SYNC
5
nc

AVDD_DDR

TS1_CK1
5
TS1_START1
5
TS1_VALID1
5
TS1_DO1
5
PCM_CD_N 7
PCM_RESET 7
1
PWR-ON/OFF
PWR-ON/OFF 1,11
ON_PBACK
ON_PBACK
1

R8
1K_1%

0R PCM_CD_N
0R PCM_RESET

ON_PANEL
EPM_WP

NC

MDDR_VREF
R9
1K_1%

C416
100nF

C39
1nF

VDDC
AVDD_LPLL

LVDS CONNECTOR

AVDD_LPLL
RXO0RXO0+
RXO1RXO1+
RXO2RXO2+
RXOCRXOC+

VDDP

RP50

RP49

100X4

100X4

FOR CEC

RXOCRXO3RXE0RXE1RXE2RXECRXE3-

HDMI-CEC
33X4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

RXO0RXO1RXO2-

RXO3RXO3+
RXE0RXE0+
RXE1RXE1+
RXE2RXE2+
RXECRXEC+
RXE3RXE3+
PCM_WAIT_N
PCM_IRQA_N
PCM_CE_N
PCM_REG_N
PCM_WE_N
PCM_OE_N
PCM_IOWR_N
PCM_IORD_N

VDDP
RP16

SPI-CSNI
SPI-SDOI
SPI-SDII
SPI-SCKI

VCC-Panel

CON11

PCM_WAIT_N 7
PCM_IRQA_N 7
PCM_CE_N 7
PCM_REG_N 7
PCM_WE_N 7
PCM_OE_N 7
PCM_IOWR_N 7
PCM_IORD_N 7

C75
2.2u

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

RXO0+
RXO1+
RXO2+
RXOC+
RXO3+
RXE0+
RXE1+
RXE2+
RXEC+
RXE3+

2x17x2mm

SPI-CSN
SPI-SDO
SPI-SDI
SPI-SCK

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

AUVRM

ON_PANEL
C422
10uF

CKE
WEZ
CASZ
RASZ
BA0
BA1

DQS[1:0]

SCL
SDA
4.7K

257

AUCOM

R335
10K

U2
MSD106CL

SCL
SDA

7 5 3 1

47n

47R C58

RGB1_B+
RGB1_SOG
RGB1_G+
RGB1_R+
RGB0_BINRGB0_BIN+
RGB0_GINRGB0_GIN+
RGB0-SOG
RGB0_RINRGB0_RIN+
AVDD_ADC

CKE
WEZ
CASZ
RASZ
BA0
BA1

0.1uF

PCM_A[14:0]

PCM_A[14:0] 7

PCM_D[7:0]

TS_D[7:0]

TS_D[7:0]

PCM_D[7:0]

47R C57

R92

9
9
9
9
9
9
9
9
9
9
9

192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129

4
4

FLASH_WP
Jupiter-PWM0
Jupiter-PWM1
DVDIR_EN
ADJ-PWM
Jupiter-RST

R91

REFP
C419
NC/100nF
REFM

C420
100nF

ADJ-PWM

11
KEY0
11
KEY1
PCM_PWR_CTL

RGB0_BIN-

5 SYS-RESET

47n

VCLP
REFP
REFM
RGB1_B+
RGB1_SOG
RGB1_G+
RGB1_R+
RGB0_BINRGB0_BIN+
RGB0_GINRGB0_GIN+
RGB0-SOG
RGB0_RINRGB0_RIN+
AVDD_ADC

7
7
7

47R C56

RXB2N
RXB2P
HOTPLUG
HDMI-REXT
DDCBSDA
DDCBSCL

GND
AVDD_MPLL
XTALI
XTALO
AVSS_OTG
USB_DP
USB_DM
AVDD_OTG
OTG_REXT
AVDDL_DVI
DDR_DQS0
AVDD_DDR
SDR_DQ0
SDR_DQ1
SDR_DQM0
GNDM
SDR_DQ2
SDR_DQ3
AVDD_DDR
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ7
VDDC
SDR_CAS_N
SDR_RAS_N
SDR_WE_N
SDR_BA0
SDR_BA1
SDR_AD12
SDR_AD11
SDR_AD10
SDR_AD9
SDR_AD8
SDR_AD7
AVDD_DDR
SDR_AD6
SDR_AD5
SDR_AD4
SDR_AD3
SDR_AD2
SDR_AD1
SDR_AD0
AVDD_MEMPLL
SDR_CKE
DDR_CKO
DDR_CKO_N
MVREF
GPIO14/UART_TX1/CEC
I2S_OUT_MUTE
I2C_SCL(DDCR_CK2)
I2C_SDA(DDCR_DA2)
SPDIF_OUT
I2S_OUT_SD
I2S_OUT_BCK
VDDC
GNDC
VDDP
I2S_OUT_WS
I2S_OUT_MCK
SPDIF_IN
I2S_IN_SD
I2S_IN_BCK/GPIO45
I2S_IN_WS/GPIO44

GND

C418
100nF
R90

DDCBSDA
DDCBSCL
VGA_HSYNC1
VGA_VSYNC1

3.3VU

AVSS_AU
AUVRM
AUVRP
AUVAG
AVDD_AUSDM
LINE_OUT_2L
LINE_OUT_2R
LINE_OUT_1L
LINE_OUT_1R(DACO_S)
LINE_OUT_0L(DACO_L)
LINE_OUT_0R(DACO_R)
VDDP
GNDP
VDDC
TS_D0/BT656_D0/FDSP_IMS
TS_D1/BT656_D1/DSP_ICLK
TS_D2/BT656_D2/FDSP_IDI
TS_D3/BT656_D3/FDSP_IDO
TS_D4/BT656_D4
TS_D5/BT656_D5
TS_D6/BT656_D6
TS_D7/BT656_D7
TS_VLD
TS_SYNC
TS_CLK/BT656_CLK
GNDC
VDDC
PCM_D7/CI_D7
PCM_D6/CI_D6
PCM_D5/CI_D5
PCM_D4/CI_D4
PCM_D3/CI_D3
PCM_D2/CI_D2
PCM_D1/CI_D1
PCM_D0/CI_D0
PCM_A14/CI_A14
PCM_A13/CI_A13
PCM_A12/CI_A12
PCM_A11/CI_A11
PCM_A10/CI_A10
PCM_A9/CI_A9
PCM_A8/CI_A8
VDDP
PCM_A7/CI_A7
PCM_A6/CI_A6
PCM_A5/CI_A5
PCM_A4/CI_A4
PCM_A3/CI_A3
PCM_A2/CI_A2
PCM_A1/CI_A1
PCM_A0/CI_A0
GPIO3
GPIO4
UART_TX(DDCA_DAT)
UART_RX(DDCA_CLK)
SAR0
SAR1
SAR2
SAR3
PWM0
PWM1
PWM2
PWM3
HWRESET

VCLP

8
8
9
9

CONTROL_AGC

MCLK+
MCLK-

SPI-CS1N

5,6
5,6
PCM_PWR_CTL1
PCM_VS1
5

33
33

DDR_DQS1
AVDD_DDR
SDR_DQ8
SDR_DQ9
SDR_DQM1
GNDM
SDR_DQ10
SDR_DQ11
AVDD_DDR
SDR_DQ12
SDR_DQ13
SDR_DQ14
SDR_DQ15
INT2
IRIN2
TS1_CLK/FDSP_IDO
TS1_SYNC/FDSP_IDI
TS1_VLD/FDSP_ICLK
TS1_D0/FDSP_IMS
CI_CD
CI_RESET
LVSYNC/GPIO97
LHSYNC/GPIO98
LDE/GPIO99
LCK/GPIO100
VDDC
GNDC
AVSS_LPLL
AVDD_LPLL
R7_RXO0R6_RXO0+
R5_RXO1R4_RXO1+
R3_RXO2R2_RXO2+
R1_RXOCR0_RXOC+
G7_RXO3G6_RXO3+
VDDP
G3_RXE0G2_RXE0+
G1_RXE1G0_RXE1+
B7_RXE2B6_RXE2+
B5_RXECB4_RXEC+
B3_RXE3B2_RXE3+
PCM_WAIT_N/CI_WACK
PCM_IRQA_N/CI_INT
PCM_CE_N/CI_CS
PCM_REG_N/CI_CLK
PCM_WE_N
PCM_OE_N
PCM_IOWR_N/CI_WR
PCM_IORD_N/CI_RD
GPIO15/CEC
VDDP
SPI_CZ
SPI_DO
SPI_DI
SPI_CK

7 5 3 1 7 5 3 1 7 5 3 1

C417
100nF

8
RXB2N
8
RXB2P
8
HOTPLUG
390R_1%

R10

UART1
GPIO0/CEC
GPIO1/TX1
GPIO2
RXCN
RXCP
RX0N
RX0P
AVDD_DVI
RX1N
RX1P
AVSS_DVI
RX2N
RX2P
HOTPLUGA
REXT
DDCDA_DA
DDCDA_CK
HSYNC1
VSYNC1
VCLP
REFP
REFM
BIN1P
SOGIN1
GIN1P
RIN1P
BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
AVDD_ADC2
AVSS_ADC2
HSYNC0
VSYNC0
C1(CVBS7P)
Y1(CVBS5P)
C0(CVBS6P)
Y0(CVBS4P)
CVBS3P
CVBS2P
CVBS1P
VCOM1
CVBS0P
VCOM0
AVDD_ADC
CVBS_OUT
AVSS_CVBSO
AVDD_SIF
SIF_IN1P
SIF_IN1M
VDDC
GNDC
LINE_IN_0L
LINE_IN_0R
LINE_IN_1L
LINE_IN_1R
LINE_IN_2L
LINE_IN_2R
LINE_IN_3L
LINE_IN_3R
VIM0

8 6 4 2 8 6 4 2 8 6 4 2

8
8

Close to IC
as close
AVDD_DVI
as possible
with width trace

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

7 5 3 1 7 5 3 1

USB_OCD_N
MUTE_AMP
10
11
HD-VSW0
HD-VSW0
RXBCLKN
RXBCLKN
RXBCLKP
RXBCLKP
RXB0N
RXB0N
RXB0P
RXB0P
AVDD_DVI
RXB1N
RXB1N
RXB1P
RXB1P

9
8
8
8
8

8 6 4 2 8 6 4 2

10
10

256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193

R160
R155
USB_DP
USB_DM

33

4.7K

R150

EEPROM

R475 C306

MCLK+
MCLK-

R237

SPI-CS1NI

8 6 4 2

SPDIFO

R248

VDDC

8 6 4 2 8 6 4 2

2.2M
JUPITER-XTALO

Y5
12MHZ

3.3VU

VDDP

3.3VU

+3.3VD

L22 10uH

SERIAL FLASH

2.2u
C248

R212

3
C172
20p

9
9

3.3VU

DDR-SDRAM Block

I2C_SCL
I2C_SDA

ISP-TXD
ISP-RXD

MDATA2
MDATA3
AVDD_DDR
MDATA4
MDATA5
MDATA6
MDATA7
VDDC
CASZ
RASZ
WEZ
BA0
BA1
M_ADR12
M_ADR11
M_ADR10
M_ADR9
M_ADR8
M_ADR7
AVDD_DDR
M_ADR6
M_ADR5
M_ADR4
M_ADR3
M_ADR2
M_ADR1
M_ADR0
AVDD_MEMPLL
CKE
MCLK+
MCLKMDDR_VREF

33R UART-RX
33R UART-TX

100p100p

5VU

AVDD_OTG
AVDDL_DVI

AVDD_MEMPLL

R3
0R

USB_DP
USB_DM
AVDD_OTG
OTG_REXT
AVDDL_DVI
DQS0
AVDD_DDR
MDATA0
MDATA1
DQM0

R126
R124

C314C315

CON4-2.0
Debug Port

AVDD_MPLL

JUPITER-XTALI

TESTPIN
AVDD_MPLL
JUPITER-XTALI
JUPITER-XTALO

C173
20p

1
2
3
4

R221
4.7K
R222
4.7K
ISP-RXD
ISP-TXD

CON31

RP56X4

4.7K

DEBUG PORT

RP56X4

R241

RP36

MADR12
MADR11
MADR10
MADR9
MADR8
MADR7
MADR6
MADR5
MADR4
MADR3
MADR2
MADR1
MADR0

7 5 3 1 7 5 3 1

R2
909R_1%

8 6 4 2 8 6 4 2 8 6 4 2

RP35
5VU
D

56R
RP56X4

7 5 3 1 7 5 3 1 7 5 3 1

R390
RP37

+3.3VD

U25
NC/EON-b32-32MBit

8
7
6
5

C176
0.1u
SPI-SCK
SPI-SDI
SPI-SDO
SPI-CS1N

VDD
HOLD#
SCK
SI

CE#
SO
WP#
VSS

1
2
3
4

CLOSED TO msd109

3.3VU

3906
Q41
C308
10uF/6.3V

R249
R252
47K

100R Jupiter-RST
C307
1n

10K

10K

10K

10K

10K

10K

R418

R419

R410

R411

1K

10K

R416

OFF3.25V 1.76V
R367 1K
LED

PCM_IORD_N
PCM_IOWR_N
PCM_OE_N
PCM_WE_N
PCM_REG_N
PCM_CE_N
PCM_IRQA_N
PCM_WAIT_N
PCM_RESET

ON0V

2009-9-29

R321

10K

R414

6K8

10K

R413

10uF/6.3V

R412

C331

R369

10K

R259

R399

3.3VU

3.3VU

DD30
BAV99

RESET

R253
10K

LED_R

LED_G
4.7K

0.44V

Q27
3904

+3.3VD

U24
EON-b32-32MBit

3.3VU
LED_R

R26

1K

Jupiter-PWM1

R47

1K

Jupiter-PWM0

Jupiter-PWM1

SERIAL FLASH

Mode Selection

1.88V

R347

R149

LED_G

10K

C170
C231 NC-22p 0.1u

DVD_ON/OFF

SPI-SCK
SPI-SDI
SPI-SDO
SPI-CSN

8
7
6
5

VDD
HOLD#
SCK
SI

CE#
SO
WP#
VSS

R218
NC

1
2
3
4

FLASH_WP
33K

R224

C336
0.1u

CLOSED TO msd109

L33
15uH/3A

4
2

AMS1084-3.3
5VDC-DC

5
1

U30
R14
6.2K_1%

C110
0.1u

4A

5VDC-DC
0.1u

R349
4.7K

1 PW-ON/OFF-INV

0.1u

4.7K

S1
G1
S2
G2

Q31
3904

3,11 PWR-ON/OFF

5VA

8
7
6
5

D1
D1
D2
D2

H:ON
L:OFF

1
2
3
4
5
6
7
8
9
10
11
12
13

Q42
3904

470uF/16V

CA8

C69
0.1u

12
Q11
3904

R27
3

C95
1n

1
2
3
4
5
6
7
8
9
10
11
12
13

8
7
6
5

D1
D1
D2
D2

R22
10K

PW-ON/OFF-INV

ON_PANEL

1K

C215
0.1u
C98
0.1U

VCC-Panel

S1
G1
S2
G2

R44
10K

NC-1x13x2.54mm

C99
0.1U

C13
0.1u

NC

Q26
3904

1K

L:ON
H:OFF

R356
18K

R340
4.7K

R320

12VA

C106

C109
R348
18K

R334

C108

R339

0.1u

4.7K

3
2

H46
TPAD

H:ON
L:OFF

U13
IRF7314

1
2
3
4

1
2
3
4

Q9
3904

C103

F2

NC

R398
C197
0.1u

5VU

R329

R25
12VUE

C455
+
100uF/16V
+

4.7K

3.3VU

12VU
CON5

VCC-PL

3.3VU

4.7K

L33,U47,D12,U13

U5
IRF7314

VCC-PL
0R

3.3VU
C454
10uF

Low ESR

PANEL POWER

NC

R386

5VU

R18
2K_1%

FB

R7
5VU

4.7K

CA15
470uF/16V

R319

C9
0.1u/NC
4 GND

C261

C196
0.1u

SS

12VU

IN

D12
SK34

BST

R23
100K/NC

C3
10n

OUT

C10
3.9n/NC

EN
COMP

ADJ

7
6

C111
0.1u

10uF/6.3V

5VU

L23 FB/220_3A

R384

OUT

CA47
100uF/16V

VCC

0.1u

U47
EC9483

5V DC-DC
12VU

1
5VA

R338

100R
5VU

5VA
1
PW-ON/OFF-INV 1
5VU

H17
TPAD
H18
TPAD

H19
TPAD

H20
TPAD

C93
1n
12VU

CON21

Note: C8,C9,C11 close to CON15 for EMI


C

3.3VU

5VU

AVDD_MPLL

C182
0.1u

+ C396
10uF

VDDP

CA3

470uF/16V

R256
470
+ C378
1u

AVDD_AU

100R PB-ON/OFF

R21
Q7
3904

12VU

3.3VU
C181

+ C379
10uF

C334
0.1u

6
5
4
3
2
1

2009-9-29

0.1u
R336
10K

5VA

AVDD_SIF

PB-ON/OFF
PB-ADJUST

3.3VU 5VU
R15
10K

R39

H21

10K/NC

H22
TPAD

CON6_2.0mm

510

C431
2.2u/NC

VDDP

1K 1

L:ON
H:OFF

VCC2.5V
R255

R24

ON_PBACK

L15
FB/NC
C430
2.2u/NC

AMS1117-3.3/NC

R20
10K

R37
10K/NC

IN

OUT

ADJ

IN

OUT

ADJ

5VU

L14
FB/NC

R19
10K

U28

AMS1117-adj

3.3VU
2009-9-29
U37

1
TPAD

CON2

L20 FB/220_1000MA
VDDP
L34
FB/220_500MA

C373
100nF

C374
100nF

C375
100nF

C376
100nF

+ C377
10uF

C393
100nF

C394
100nF

10uF

ADJ-PWM

R17

4.7K

R16

1K

Q6
3904

PB-ADJUST
C255
2.2u

+ C370
10uF

C371
100nF

C384
+

3.3VU

Note: Left C255 NC if want to output PWM puls

AVDD_AU
L2
FB/220_500MA

AVDD_DDR
L7
FB/220_500MA

AVDD_SIF
L4
FB/220_500MA

VCC2.5V

+ C391
10uF
3.3VU

AVDD_DVI
L10
FB/220_500MA

AVDD_LPLL
L17
FB/220_500MA

DVD Power Interface

H16
TPAD

AVDD_LPLL
AVDD_ADC

C429
2.2u

C372C383
100nF
+

AVDD_MPLL

C386
100nF

C387
100nF

10uF

AVDD_MPLL
L9
FB/220_500MA

AVDD_MEMPLL

AVDD_DVI

Using power plane


AVDD_MEMPLL
L6
FB/220_500MA

AVDD_OTG
L18
FB/220_500MA

C395
100nF

+ C388

C380 C381
100nF
100nF

CON6_2.0mm/NC

5VA

AVDD_OTG
C389
2.2u

AVDD_ADC
L5
FB/220_500MA

C385
100nF

AVDD_DDR

C390
100nF

C263
10uF/6.3V/NC

0.1u/NC

10uF
C399
100nF

C400
100nF

C401
100nF

C402
100nF

C403
100nF

1
2
3
4
5
6

H15

C251

TPAD

CON6

C263 & C251 close to CON6

12VA
CA75

10uF/16V/NC

C250
0.1u/NC

H14
TPAD

CA75 & C250 close to CON6

+1.2V FOR MST CORE

SS

GND

BST

FB

VCC1.2V
VCC1.2V

5
1

C86
10n/NC

L16
FB/1A

VDDC

+ C405
10uF

D3
SS14

C406
0.1u

VDDC

+
R245

220_1%

R244
10K_1%

C407
100nF
0.1u

4
2

C200

EN
COMP

C249

7
6

OUT

10uF/6.3V

10K/NC

VCC

CA6

R257

C272

0.1u

C327

C198

CA39

0.1u/NC

3.9n/NC

R251 100K
A

100uF/16V

L8
15uH/1A

U15
EC9410

470uF/16V

L3
FB/220_1000MA

5VU

C408
100nF

C409
100nF

C410
100nF

C411
100nF

C412
100nF

L74 AVDDL_DVI
FB/220_500MA
C413

C415
100nF

2.2U

H33
TPAD
5VU

470R

R406

680R

R408

H26
TPAD

1.2K/NC

R317

470R

H30
TPAD

1
H28
TPAD

H27
TPAD

H36
TPAD
E_KEY0

H29
TPAD

R407

680R

H31
TPAD

H34 H35
TPAD TPAD

R323

LED_G
LED_R
IR_in

CN31

E_KEY1

10R

R417

LED_G
LED_R
IR_in

5
4
3
2
1

CON5_2.0

R405

1.2K/NC

CON9-2.0

1
2
3
4
5
6
7
8
9
CON37

P_KEY

H25
TPAD

H32
TPAD

2K R258

2K R243

KEY PAD

10K R254

3.3VU

P_KEY
E_KEY1
E_KEY0

R380
R429
R427

22K POWER_KEY POWER_KEY


1K KEY1
KEY1
1K KEY0
KEY0

LED_G

0.1uF
C270
0.1uF
C212
0.1uF
C213

C349
0.1uF
LED_R
C341
0.1uF
IR_in

IR_SYNC
4.7K

IR_SYNC

100PF
C211

C210
10PF

R379

close to IC side

Basic Operations & Circuit Description


Main Electric Components
(1). MODULE:

There are 1 pc. panel and 1 pcs. PCB including


T-CONTROL board,

(2).SIGNAL PROCESS

There are 3 pcs. PCBs including


1 pc. Main digital board,
1 pc. Keypad board,
1 pc. Remote Control Receiver board

(3).POWER
There are 1 pc. PCB for power.

13113

PCB function
1. Power:
(1). Input voltage: AC 100V~240V, 50~60Hz.
(2). To provide power for PCBs.
a). +5Vsb for standby,
b). +5VCC for signal power,
c). +12V for AMPLIFIER power.
d). Converter the low DC voltage +12V to high AC voltage to drive the backlight.

2. Main (Video InterFace) board:

(1).Convert TV RF signal to video and audio signal to Main board.


(2).Decoder the video signal (TV,CVBS,S-VIDEO) from analog to digital
signal.
(3).Converter the Video signals( TV,CVBS,S-VIDEO ) and graphics signal
(VGA,YPbPr) from internace to progressive,
(4).Converter the Digital to fit the panel display mode and output the LVDS
signal to Panel.

3. KEY board
To get the main button control on LCD_TV as SOURCE,MENU,
CHANEL +,CHANEL -, VOL +,VOL-, STANDBY functions.
4. Remote Control board
Receive the remote signal and active for the control.

5. T-CONTROL board
Converter the LVDS signal to the digital signal for fitting the PANEL.

14113

PCB failure analysis


1. CONTROL:
a. Abnormal noise on screen.
b. No picture.

2. MAIN (VIDEO):
a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.

3. POWER:
No picture, no power output.

Basic operation of LCD-TV


1. After turning on power switch, power board sends 5Vst-by Volt to Micro
Processor IC waiting for ON signals from Key Switch or Remote Receiver.
2. When the ON signal from Key Switch or Remote Receiver is detected, Micro
Processor will send ON Control signals to Power. Then Power sends (5Vsc,
12Vsc, ) to PCBs working. This time VIF will send signals to display back light,
OSD on the panel and start to search available signal sources. If the audio signals
input, them will be amplified by Audio AMP and transmitted to Speakers.
3. If some abnormal signals are detected (for example: over volts, over current,
over temperature and under volts), the system will be shut down by Power off.

15113

LCD basic display theory.


When an electrical field is applied to the LC planes, the LC molecules re-align
themselves so that they are parallel to the electrical field. This electrical process
is known as twisted nematic field effect or TNFE. In this alignment, polarized
light is not twisted as it passes through the LC material (see Diagram 3A and
3B). If the front polarizer is oriented perpendicular to the rear polarizer, light will
pass through the energized display but will be blocked by the rear polarizer. An
LCD in this form is acting as a light shutter.
Displays with variable characters are created by selectively etching away the
conductive surface that was originally deposited on the glass. Etched areas
become the displays background; unetched areas become the displays
characters.

Diagram 3A. The off state of a TN LCD-the LC molecules form a twist and therefore
cause polarized light to twist as it passes through.

Diagram 3B. The on state-the electrical field re-aligns the LC molecules so they do
not twist the polarized light.

16113

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1
Attention Please: Under the technology license agreement between MStar and Dolby/SRS/BBE, MStar is obliged not to
provide samples that incorporate Dolby/SRS/BBE technology to any third party who is not a qualified licensee of
Dolby/SRS/BBE.

FEATURES
n

Twin-turbo 8051 Micro-controller


Twin-turbo 8051 MCU
Interrupt controller
Supports ISP
One full duplex UART
Transport Stream De-multiplexer
One external TS input and one internal TS
data path
Supports both parallel and serial TS interface,
with or without sync signal
Maximum TS data rate is 104 Mbps for serial
or 13 MB/sec for parallel
32 general purpose PID filters and section
filters for each transport stream de-multiplexer
One video PES and one audio PES channel
Supports DVB subtitle and digital teletext
Optionally supports MHEG5 Note 1
MPEG-2 A/V Decoder
ISO/IEC 13818-2 MPEG-2 video MP@ML
Automatic frame rate conversion
Supports resolution in SDTV
MPEG-1, MPEG-2 (Layer I/II) audio decoder
Optionally supports Dolby1 Digital (AC-3) audio
decoding Note 2
MPEG-4 Decoder
Supports ISO/IEC 14496-2 MPEG-4 ASP video
decoding
Supports resolution up to D1
NTSC/PAL/SECAM Video Decoder
Supports NTSC-M, NTSC-J, NTSC-4.43, PAL
(B,D,G,H,M,N,I,Nc), and SECAM
Automatic TV standard detection
Motion adaptive 3-D comb filter for NTSC/PAL
8 configurable CVBS & Y/C S-video inputs

2
1

Dolby is a Trademark of Dolby Laboratories.

Supports Teletext level-1.5, Closed Caption


(analog CC 608/analog CC 708/digital CC
608/digital CC 708), V-chip and SCTE
Macrovision detection
CVBS video output
Multi-Standard TV Sound Processor
Supports BTSC/A2/EIA-J demodulation in NTSC
and A2/NICAM/FM/AM demodulation in PAL
Supports MTS Mode MONO/STEREO/SAP in
BTSC/EIA-J and MONO/STEREO/DUAL in
A2/NICAM
L/Rx4 and SIF audio input
L/R speaker and 2 additional L/R audio line-out
Built-in audio output DACs
Audio processing for loudspeaker channel,
including volume, balance, mute, tone, EQ,
virtual stereo/surround, and treble/bass
Optional advanced surround available (Dolby,
SRS2, BBE3 etc) Note 3
Digital Audio Interface
HDMI audio channel processing capability
Programmable delay for audio/video
synchronization
Analog RGB Compliant Input Ports
Two analog ports support up to 1080P
Supports PC RGB input up to SXGA@75Hz
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG
(Sync-on-Green) separator
Automatic color calibration
High-Performance Scaling Engine
Fully Programmable shrink/zoom capabilities
Nonlinear video scaling supports various
modes including Panorama
DVI/HDCP/HDMI Compliant Input Port
Supports up to 225MHz @ 1080P 60Hz with
12-bit deep-color resolution
Single link on-chip DVI 1.0 compliant receiver

Trademark of SRS Labs, Inc.


Registered trademark of BBE Sound, Inc.

-1Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

High-bandwidth Digital Content Protection


(HDCP) 1.1 compliant receiver
High Definition Multimedia Interface (HDMI)
1.3 compliant receiver with CEC (Consumer
Electronics Control) support
Long-cable tolerant robust receiving
Auto-Configuration/Auto-Detection
Auto input signal format and mode detection
Auto-tuning function including phasing,
positioning, offset, gain, and jitter detection
Sync Detection for H/V Sync
Video Processing & Conversion
3-D motion adaptive video de-interlacers with
edge-oriented adaptive algorithm for smooth
low-angle edges
Automatic 3:2 pull-down & 2:2 pull-down
detection and recovery
MStar 3rd Generation Advanced Color Engine
(MStarACE-3) automatic picture enhancement
gives:
Brilliant and fresh color
Intensified contrast and details
Vivid skin tone
Sharp edge
Enhanced depth of field perception
Accurate and independent color control
sRGB compliance allows end-user to
experience the same colors as viewed on CRTs
and other displays
3-channel gamma curve adjustment
Programmable 10-bit RGB gamma CLUT
3-D video noise reduction
Frame rate conversion

Output Interface
Supports up to 8-bit dual LVDS
UXGA/WSXGA+ panel interface
Supports 2 data output formats: Thine & TI
data mappings
Compatible with TIA/EIA
With 6/8 bits options
Spread spectrum output frequency for EMI
suppression
CVBS Video Output
Supports CVBS/S-video bypass output
Built-in video encoder for encoding digital
video into CVBS output
2D Graphics Engine
Point draw, line draw, rectangle draw/fill and
text draw
BitBlt and stretch BitBlt
Raster Operation (ROP)
Miscellaneous
DRAM controller to support up to 16-bit DDR
interface
Supports Common Interface for conditional
access
SPI bus for external flash
USB 2.0 host controller with the flexibility for
connecting external storage devices
256-LQFP package
Operating at 1.2V (core), 2.5V (DDR), and
3.3V (I/O and analog)

Note:
1. The optional MHEG5 function is available with
MSD106CHL.
2. The optional Dolby Digital function is available with
all MSD106CL models except those with suffixes Z1.
3. Please see Ordering Guide for details on advanced
surround.

-2Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

GENERAL DESCRIPTION
The MSD106CL is a highly integrated controller IC for LCD/PDP DTV applications with resolutions up to
UXGA/WSXGA+. It is configured with an integrated triple-ADC/PLL, a multi-standard TV video and audio
decoder, a motion adaptive video de-interlacer, a scaling engine, the MStarACE-3 color engine, an advanced 2D
graphics engine, a transport processor, a standard-definition (SD) MPEG video decoder, a 24-bit DSP for MPEG
audio decoding, a DVI/HDCP/HDMI receiver, and a peripheral control unit providing a variety of HDTV control
functions.
The MSD106CL comprises an MPEG-2 transport processor with advanced section filtering capability, an MPEG-2
(MP@ML profile) video decoder, an MPEG layer I and II digital audio decoder with analog audio outputs that
are designed to support DVB SDTV programs while handling conditional access. Furthermore, it is also
possible to decode MPEG-4, JPEG, MP3 formats from external sources such as USB interfaces.
For analog TV, the MSD106CL includes NTSC/PAL/SECAM multi-standard video decoder comprising a 3-D
motion adaptive comb filter and time-based correction, and a NICAM/A2 audio decoder to support worldwide
television standards. The MSD106CL is also configured with a VBI processor to decode digital information such
as Close Caption/V-chip/teletext/WSS/CGMS-A/VPS. In addition, the MStar advanced LCD TV processor
enhances video quality, motion adaptive de-interlacer, picture quality adjustment units, and MStarACE-3 color
engine.
By integrating peripherals including USB 2.0 host controller, UART, IR, SPI, I2C, and PWM, the MSD106CL
fulfills all requirements in advanced DTV sets. To further reduce system costs, the MSD106CL also integrates
intelligent power management control capability for green-mode requirements and spread-spectrum support for
EMI management.

-3Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

-4Copyright 2007 MStar Semiconductor, Inc. All rights reserved.


128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

40

105

39

104

38

103

37

102

36

101

35

100

34

99

33

98

32

97

31

96

30

95

29

94

28

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

188

6
187

7
186

8
185

9
184

10
183

11
182

12
181

13
180

14
179

15
178

16
177

17
176

18
175

19
174

20
173

21
172

22
171

23
170

24
169

25
168

26
167

27
166

MSD106CL

66

XXXXXXXX
XXXXX

65

GPIO0/UART_RX1/CEC
GPIO1/UART_TX1
GPIO2
RXCKN
RXCKP
RX0N
RX0P
AVDD_33
RX1N
RX1P
GND
RX2N
RX2P
GPIO125
REXT
DDCD_DA
DDCD_CK
HSYNC1
VSYNC1
VCLAMP
REFP
REFM
BIN1P
SOGIN1
GIN1P
RIN1P
BINM
BIN0P
GINM
GIN0P
SOGIN0
RINM
RIN0P
AVDD_33
GND
HSYNC0
VSYNC0
CVBS7
CVBS5
CVBS6
CVBS4
CVBS3
CVBS2
CVBS1
VCOM1
CVBS0
VCOM0
AVDD_33
CVBSOUT
GND
AVDD_SIF
SIF1P
SIF1M
VDDC
GND
AUL0
AUR0
AUL1
AUR1
AUL2
AUR2
AUL3
AUR3
AUCOM

GND
AUVRM
AUVRP
AUVAG
AVDD_AU
AUOUTL2
AUOUTR2
AUOUTL1
AUOUTR1
AUOUTL0
AUOUTR0
VDDP
GND
VDDC
TS0DATA[0]
TS0DATA[1]
TS0DATA[2]
TS0DATA[3]
TS0DATA[4]
TS0DATA[5]
TS0DATA[6]
TS0DATA[7]
TS0VALID
TS0SYNC
TS0CLK
GND
VDDC
PCMDATA[7]/CI_DATA[7]
PCMDATA[6]/CI_DATA[6]
PCMDATA[5]/CI_DATA[5]
PCMDATA[4]/CI_DATA[4]
PCMDATA[3]/CI_DATA[3]
PCMDATA[2]/CI_DATA[2]
PCMDATA[1]/CI_DATA[1]
PCMDATA[0]/CI_DATA[0]
PCMADR[14]/CI_A[14]
PCMADR[13]/CI_A[13]
PCMADR[12]/CI_A[12]
PCMADR[11]/CI_A[11]
PCMADR[10]/CI_A[10]
PCMADR[9]/CI_A[9]
PCMADR[8]/CI_A[8]
VDDP
PCMADR[7]/CI_A[7]
PCMADR[6]/CI_A[6]
PCMADR[5]/CI_A[5]
PCMADR[4]/CI_A[4]
PCMADR[3]/CI_A[3]
PCMADR[2]/CI_A[2]
PCMADR[1]/CI_A[1]
PCMADR[0]/CI_A[0]
GPIO3
GPIO4
DDCA_DA
DDCA_CK
SAR0
SAR1
SAR2
SAR3
PWM0
PWM1
PWM2
PWM3
HWRESET
193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

GND
AVDD_MPLL
XIN
XOUT
GND
USB_DP
USB_DM
AVDD_USB
USB_REXT
AVDDL_DVI
DQS[0]
AVDD_DDR
MDATA[0]
MDATA[1]
DQM[0]
GND
MDATA[2]
MDATA[3]
AVDD_DDR
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
VDDC
CASZ
RASZ
WEZ
BADR[0]
BADR[1]
MADR[12]
MADR[11]
MADR[10]
MADR[9]
MADR[8]
MADR[7]
AVDD_DDR
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]
AVDD_MEMPLL
MCLKE
MCLK
MCLKZ
MVREF
GPIO14/UART_TX1
I2S_OUT_MUTE/CEC
DDCR_CK
DDCR_DA
SPDIFO
I2S_OUT_SD
I2S_OUT_BCK
VDDC
GND
VDDP
I2S_OUT_WS
I2S_OUT_MCK
SPDIFI
I2S_IN_SD
I2S_IN_BCK
I2S_IN_WS

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

PIN DIAGRAM (MSD106CL)

1
192

2
191

3
190

Pin 1
189

165

164

163

162

161

160

159

158

157

156

155

41
154

152

42
153

151

43
150

44
149

45
148

46
147

47
146

48
145

49
144

50
143

51
142

52
141

53
140

54
139

55
138

56
137

57
136

58
135

59
134

60
133

61
132

62
131

63
130

64
129

DQS[1]
AVDD_DDR
MDATA[8]
MDATA[9]
DQM[1]
GND
MDATA[10]
MDATA[11]
AVDD_DDR
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
INT
IRIN
TS1CLK
TS1SYNC
TS1VALID
TS1DATA
CI_CD
CI_RST
GPIO97
GPIO98
GPIO99
GPIO100
VDDC
GND
GND
AVDD_LPLL
LVB0M
LVB0P
LVB1M
LVB1P
LVB2M
LVB2P
LVBCKM
LVBCKP
LVB3M
LVB3P
VDDP
LVA0M
LVA0P
LVA1M
LVA1P
LVA2M
LVA2P
LVACKM
LVACKP
LVA3M
LVA3P
PCMWAIT/CI_WACK
PCMIRQ/CI_INT
PCMCEN/CI_CS
PCMREG/CI_CLK
PCMWEN
PCMOEN
PCMIOW/CI_WR
PCMIOR/CI_RD
GPIO15/CEC
VDDP
SCZ
SDO
SDI
SCK

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

PIN DESCRIPTION
Analog Interface
Pin Name

Pin Type

Function

Pin

VCLAMP

CVBS/YC Mode Clamp Voltage Bypass

20

REFP

Internal ADC Top De-coupling Pin

21

REFM

Internal ADC Bottom De-coupling Pin

22

REXT

Analog Input

External Resister 390 ohm to AVDD_33

15

BIN1P

Analog Input

Analog Blue Input from Channel 1

23

SOGIN1

Analog Input

Sync-On-Green input from Channel 1

24

GIN1P

Analog Input

Analog Green Input from Channel 1

25

RIN1P

Analog Input

Analog Red Input from Channel 1

26

BINM

Analog Input

Reference Ground for Analog Blue Input

27

BIN0P

Analog Input

Analog Blue Input from Channel 0

28

GINM

Analog Input

Reference Ground for Analog Green Input

29

GIN0P

Analog Input

Analog Green Input from Channel 0

30

SOGIN0

Analog Input

Sync-On-Green Input from Channel 0

31

RINM

Analog Input

Reference Ground for Analog Red Input

32

RIN0P

Analog Input

Analog Red Input from Channel 0

33

HSYNC1

Schmitt Trigger Input HSYNC/Composite Sync for VGA Input from channel 1
w/ 5V-tolerant

18

VSYNC1

Schmitt Trigger Input VSYNC for VGA Input from channel 1


w/ 5V-tolerant

19

HSYNC0

Schmitt Trigger Input HSYNC/Composite Sync for VGA Input from channel 0
w/ 5V-tolerant

36

VSYNC0

Schmitt Trigger Input VSYNC for VGA Input from channel 0


w/ 5V-tolerant

37

Analog Video Input/Output Interface


Pin Name

Pin Type

Function

Pin

VCOM1

Analog Input

CVBS Video Input Reference Ground

45

VCOM0

Analog Input

CVBS Video Input Reference Ground

47

CVBS7

Analog Input

CVBS (Composite) Video Input Channel 7

38

CVBS5

Analog Input

CVBS (Composite) Video Input Channel 5

39

CVBS6

Analog Input

CVBS (Composite) Video Input Channel 6

40

CVBS4

Analog Input

CVBS (Composite) Video Input Channel 4

41

CVBS3

Analog Input

CVBS (Composite) Video Input Channel 3

42

-5Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Pin Name

Pin Type

Function

Pin

CVBS2

Analog Input

CVBS (Composite) Video Input Channel 2

43

CVBS1

Analog Input

CVBS (Composite) Video Input Channel 1

44

CVBS0

Analog Input

CVBS (Composite) Video Input Channel 0

46

CVBSOUT

Analog Output

CVBS (Composite) Video Output

49

Analog Audio Input/Output Interface


Pin Name

Pin Type

Function

Pin

SIF1P

Analog Input

SIF Audio Input Channel 1

52

SIF1M

Analog Input

Reference Ground for SIF Audio Input Channel 1

53

I2S_OUT_MCK

Output

Audio Master Clock Output

197

I2S_OUT_BCK

Output

Audio Bit Clock Output

202

I2S_OUT_WS

Output

Word Select Output; 4mA driving strength

198

I2S_OUT_SD

Output

Audio Serial Data Output; 4mA driving strength

203

I2S_OUT_MUTE/
CEC

Output w/5V-tolerant Audio Output Mute Control /


Consumer Electronics Control

207

SPDIFO

Output

S/PDIF Audio Output; 4mA driving strength

204

I2S_IN_BCK

Input

Audio Bit Clock Input

194

I2S_IN_WS

Input

Word Select Input

193

I2S_IN_SD

Input

Audio Serial Data Input

195

SPDIFI

Input

S/PDIF Audio Input

196

AUVRM

Analog Output

Negative Reference Voltage for Audio ADC

66

AUVRP

Analog Output

Positive Reference Voltage for Audio ADC

67

AUVAG

Analog Output

Reference Voltage for Audio Common Mode

68

AUL0

Analog Input

Audio Line Input Left Channel 0

56

AUR0

Analog Input

Audio Line Input Right Channel 0

57

AUL1

Analog Input

Audio Line Input Left Channel 1

58

AUR1

Analog Input

Audio Line Input Right Channel 1

59

AUL2

Analog Input

Audio Line Input Left Channel 2

60

AUR2

Analog Input

Audio Line Input Right Channel 2

61

AUL3

Analog Input

Audio Line Input Left Channel 3

62

AUR3

Analog Input

Audio Line Input Right Channel 3

63

AUOUTL2

Analog Output

Main Audio Output Left Channel 2

70

AUOUTR2

Analog Output

Main Audio Output Right Channel 2

71

AUOUTL1

Analog Output

Main Audio Output Left Channel 1

72

AUOUTR1

Analog Output

Main Audio Output Right Channel 1

73

-6Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Pin Name

Pin Type

Function

Pin

AUOUTL0

Analog Output

Main Audio Output Left Channel 0

74

AUOUTR0

Analog Output

Main Audio Output Right Channel 0

75

AUCOM

Analog Input

Reference Ground for Audio Line Input

64

Common Interface
Pin Name

Pin Type

Function

Pin

PCMDATA[7:0]/
CI_DATA[7:0]

I/O

PCMCIA Data[7:0] /
Common Interface Data[7:0]

92-99

PCMADR[14:0]/
CI_A[14:0]

Output

PCMCIA Address[14:0] /
Common Interface Address[14:0]

100-106,
108-115

PCMIOR/
CI_RD

Output

PCMCIA Input/Output Read /


Common Interface Read

135

PCMIOW/
CI_WR

Output

PCMCIA Input/Output Write /


Common Interface Write

136

PCMOEN

Output

PCMCIA Output Enable

137

PCMWEN

Output

PCMCIA Write Enable

138

PCMREG/
CI_CLK

Output

PCMCIA Register /
Common Interface Clock

139

PCMCEN/
CI_CS

Output

PCMCIA Card Enable /


Common Interface Chip Select

140

PCMIRQ/
CI_INT

Input

PCMCIA Interrupt Request /


Common Interface Interrupt

141

PCMWAIT/
CI_WACK

Input

PCMCIA Extend Bus Wait Cycle /


Common Interface Wait Acknowledge

142

CI_RST

Output

Common Interface Reset

172

CI_CD

Input

Common Interface Card Detect

173

Function

Pin

TS Input Interface
Pin Name

Pin Type

TS0CLK

Input w/ 5V-tolerant TS Clock

89

TS0DATA[7:0]

Input w/ 5V-tolerant TS Data in Parallel; LSB (bit 0) is for serial TS data

86-79

TS0VALID

Input w/ 5V-tolerant TS Data Valid

87

TS0SYNC

Input w/ 5V-tolerant TS Sync-Byte Indicator

88

nd

TS1CLK

Input w/ 5V-tolerant 2

TS1DATA

Input w/ 5V-tolerant 2nd TS Data in Parallel


nd

TS Clock

TS1VALID

Input w/ 5V-tolerant 2

TS Data Valid

TS1SYNC

Input w/ 5V-tolerant 2nd TS Sync-Byte Indicator


-7Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

177
174
175
176
10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

DVI/HDMI Interface
Pin Name

Pin Type

Function

Pin

RX0N

Input

DVI/HDMI Channel 0 Negative Data Input

RX0P

Input

DVI/HDMI Channel 0 Positive Data Input

RX1N

Input

DVI/HDMI Channel 1 Negative Data Input

RX1P

Input

DVI/HDMI Channel 1 Positive Data Input

10

RX2N

Input

DVI/HDMI Channel 2 Negative Data Input

12

RX2P

Input

DVI/HDMI Channel 2 Positive Data Input

13

RXCKN

Input

DVI/HDMI Negative Clock Input

RXCKP

Input

DVI/HDMI Positive Clock Input

Pin Name

Pin Type

Function

Pin

LVA0M

Output

LVDS A-Link Channel 0 Negative Data Output

152

LVA0P

Output

LVDS A-Link Channel 0 Positive Data Output

151

LVA1M

Output

LVDS A-Link Channel 1 Negative Data Output

150

LVA1P

Output

LVDS A-Link Channel 1 Positive Data Output

149

LVA2M

Output

LVDS A-Link Channel 2 Negative Data Output

148

LVA2P

Output

LVDS A-Link Channel 2 Positive Data Output

147

LVACKM

Output

LVDS A-Link Negative Clock Output

146

LVACKP

Output

LVDS A-Link Positive Clock Output

145

LVA3M

Output

LVDS A-Link Channel 3 Negative Data Output

144

LVA3P

Output

LVDS A-Link Channel 3 Positive Data Output

143

LVB0M

Output

LVDS B-Link Channel 0 Negative Data Output

163

LVB0P

Output

LVDS B-Link Channel 0 Positive Data Output

162

LVB1M

Output

LVDS B-Link Channel 1 Negative Data Output

161

LVB1P

Output

LVDS B-Link Channel 1 Positive Data Output

160

LVB2M

Output

LVDS B-Link Channel 2 Negative Data Output

159

LVB2P

Output

LVDS B-Link Channel 2 Positive Data Output

158

LVBCKM

Output

LVDS B-Link Negative Clock Output

157

LVBCKP

Output

LVDS B-Link Positive Clock Output

156

LVB3M

Output

LVDS B-Link Channel 3 Negative Data Output

155

LVB3P

Output

LVDS B-Link Channel 3 Positive Data Output

154

LVDS Interface

-8Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Serial Flash Interface


Pin Name

Pin Type

Function

Pin

SCK

Output

SPI Flash Serial Clock

129

SDI

Output

SPI Flash Serial Data Input

130

SDO

Input w/ 5V-tolerant

SPI Flash Serial Data Output

131

SCZ

Output

SPI Flash Chip Select

132

IRIN

Input w/5V-tolerant

IR Receiver Input

178

INT

Input w/5V-tolerant

MCU Bus Interrupt; 4mA driving strength

179

Pin Name

Pin Type

Function

Pin

GPIO125

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength

14

GPIO100

I/O

General Purpose Input/Output; 4mA driving strength

168

GPIO99

I/O

General Purpose Input/Output; 4mA driving strength

169

GPIO98

I/O

General Purpose Input/Output; 4mA driving strength

170

GPIO97

I/O

General Purpose Input/Output; 4mA driving strength

171

GPIO15/CEC

I/O

General Purpose Input/Output; 4mA driving strength

134

GPIO14/
UART_TX1

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength /


Universal Asynchronous Transmitter

208

GPIO4

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength

117

GPIO3

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength

116

GPIO2

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength

GPIO1/
UART_TX1

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength /


Universal Asynchronous Transmitter

GPIO0/
UART_RX1/
CEC

I/O w/ 5V-tolerant

General Purpose Input/Output; 4mA driving strength /


Universal Asynchronous Receiver /
Consumer Electronics Control

PWM3

Output

Pulse Width Modulation Output; 4mA driving strength

127

PWM2

Output

Pulse Width Modulation Output; 4mA driving strength

126

PWM1

Output

Pulse Width Modulation Output; 4mA driving strength

125

PWM0

Output

Pulse Width Modulation Output; 4mA driving strength

124

SAR3

Analog Input

SAR Low Speed ADC Input 3;


General Purpose Input/Output

123

SAR2

Analog Input

SAR Low Speed ADC Input 2;


General Purpose Input/Output

122

SAR1

Analog Input

SAR Low Speed ADC Input 1;


General Purpose Input/Output

121

GPIO Interface

-9Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Pin Name

Pin Type

Function

Pin

SAR0

Analog Input

SAR Low Speed ADC Input 0;


General Purpose Input/Output

120

DRAM Interface
Pin Name

Pin Type

Function

Pin

DQM[1:0]

Output

Data Mask for Low Byte; active high

188, 242

DQS[1:0]

I/O

Data Strobe

192, 246

MVREF

Input

Reference Voltage for DDR SDRAM Interface 209

MCLKZ

Output

DRAM Memory Negative Differential Clock

210

MCLK

Output

DRAM Memory Positive Differential Clock

211

MCLKE

Output

DRAM Memory Clock Enable

212

BADR[1:0]

Output

DRAM Memory Bank Address

228, 229

WEZ

Output

Write Enable; active low

230

RASZ

Output

Row Address Strobe; active low

231

CASZ

Output

Column Address Strobe; active low

232

MDATA[15:0]

I/O

DRAM Memory Data Bus

180-183, 185, 186,


189, 190, 234-237,
239, 240, 243, 244

MADR[12:0]

Output

DRAM Memory Address

227-222, 220-214

Pin Type

Function

Pin

USB External Resistor Pin;


Connected through 910 ohm (1%) Resistor to GND (Pin

248

USB Interface
Pin Name
USB_REXT

#252)
USB_DM

Analog I/O

USB Inverting Data Input/Output

250

USB_DP

Analog I/O

USB Non Inverting Data Input/Output

251

Pin Name

Pin Type

Function

Pin

DDCD_DA

I/O w/ 5V-tolerant

HDCP Serial Bus Data/DDC Data of DVI/HDMI Port

16

DDCD_CK

Input w/ 5V-tolerant HDCP Serial Bus Clock/DDC Clock of DVI/HDMI Port

17

DDCA_DA

I/O w/ 5V-tolerant

DDC Data for Analog Port

118

DDCA_CK

I/O w/ 5V-tolerant

DDC Clock for Analog Port

119

HWRESET

Schmitt Trigger
Hardware Reset; active high
Input w/ 5V-tolerant

Misc. Interface

- 10 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

128

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Pin Name

Pin Type

Function

Pin

DDCR_DA

I/O w/ 5V-tolerant

DDC Data for ROM

205

DDCR_CK

I/O w/ 5V-tolerant

DDC Clock for ROM

206

XIN

Analog Input

Crystal Oscillator Input

254

XOUT

Analog Output

Crystal Oscillator Output

253

Pin Name

Pin Type

Function

Pin

AVDD_SIF

3.3V Power

SIF Power

51

AVDD_AU

3.3V Power

Audio Power

69

AVDD_DDR

2.5V Power

DDR Power

184, 191, 221, 238, 245

AVDD_LPLL

3.3V Power

LPLL Power

164

AVDD_MPLL

3.3V Power

MPLL Power

255

AVDD_MEMPLL

3.3V Power

PLL Power

213

AVDD_33

3.3V Power

ADC Power

8, 34, 48

AVDDL_DVI

1.2V Power

DVI Power

247

AVDD_USB

3.3V Power

USB Power

249

VDDC

1.2V Power

Digital Core Power

54, 78, 91, 167, 201, 233

VDDP

3.3V Power

Digital Input/Output Power

76, 107, 133, 153, 199

GND

Ground

Ground

11, 35, 50, 55, 65, 77, 90, 165,


166, 187, 200, 241, 252, 256

Power Pins

- 11 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

ELECTRICAL SPECIFICATIONS
Analog Interface Characteristics
Parameter

Min

VIDEO ADC Resolution

Typ

Max

10

Unit
Bits

DC ACCURACY
Differential Nonlinearity

TBD

Integral Nonlinearity

TBD

TBD

LSB
LSB

VIDEO ANALOG INPUT


Input Voltage Range
Minimum

0.5

Maximum

1.0

V p-p
V p-p

Input Bias Current

uA

Input Full-Scale Matching

1.5

%FS

Brightness Level Adjustment

62

%FS

SWITCHING PERFORMANCE
Maximum Conversion Rate

150

MSPS

Minimum Conversion Rate

12

MSPS

HSYNC Input Frequency

15

200

kHz

PLL Clock Rate

12

150

MHz

PLL Jitter

500

ps p-p

Sampling Phase Tempco

15

ps/C

250

MHz

DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
DIGITAL INPUTS
Input Voltage, High (VIH)

2.5

Input Voltage, Low (VIL)

0.8

Input Current, High (IIH)

-1.0

uA

Input Current, Low (IIL)

1.0

uA

Input Capacitance

pF

DIGITAL OUTPUTS
Output Voltage, High (VOH)

VDDP-0.1

Output Voltage, Low (VOL)

0.1

VIDEO ANALOG OUTPUT


CVBS Buffer Output
Output Low
Output High

1.5

2.0

- 12 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

Parameter

Min

Typ

Max

Unit

AUDIO
ADC Input

2.0

V p-p

DAC Output

2.0

V p-p

SIF Input Range


Minimum
Maximum
FSSW Input1
SAR ADC Input
FB ADC Input

0.1

V p-p
V p-p

1.8

3.3

1.25

1.0

Specifications subject to change without notice.


Notes:
1. Input full scale is typically 1.8V, but input range is 0 ~ 3.3V.
2. Input full scale is 1.25V, but input range is 0 ~ 3.3V.

Absolute Maximum Ratings


Parameter

Symbol

Min

3.3V Supply Voltages

VVDD_33

2.5V Supply Voltages

Typ

Max

Units

-0.3

3.6

VVDD 25

-0.3

2.75

1.2V Supply Voltages

VVDD_12

-0.3

1.32

Input Voltage (5V tolerant inputs)

VIN5Vtol

-0.3

5.0

Input Voltage (non 5V tolerant inputs)

VIN

-0.3

VVDD_33

Ambient Operating Temperature

TA

70

Storage Temperature

TSTG

-40

150

Junction Temperature

TJ

150

Thermal Resistance (Junction to Air) Natural

JA

TBD

C/W

JC

TBD

C/W

Conversion
Thermal Resistance (Junction to Case) Natural
Conversion

Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and does not imply functional operation of the device. Exposure to absolute maximum ratings for
extended periods may affect device reliability.

- 13 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

ORDERING GUIDE
Model

Temperature

Package

Package

Range

Description Option

MSD106CL

0C to +70C

LQFP

256

MSD106CL-LF

0C to +70C

LQFP

MSD106CL-S1

0C to +70C

MSD106CL-LF-S1

Model

Temperature

Package

Package

Range

Description Option

MSD106CHL

0C to +70C

LQFP

256

256

MSD106CHL-LF

0C to +70C

LQFP

256

LQFP

256

MSD106CHL-S1

0C to +70C

LQFP

256

0C to +70C

LQFP

256

MSD106CHL-LF-S1

0C to +70C

LQFP

256

MSD106CL-S2

0C to +70C

LQFP

256

MSD106CHL-S2

0C to +70C

LQFP

256

MSD106CL-LF-S2

0C to +70C

LQFP

256

MSD106CHL-LF-S2

0C to +70C

LQFP

256

MSD106CL-S3

0C to +70C

LQFP

256

MSD106CHL-S3

0C to +70C

LQFP

256

MSD106CL-LF-S3

0C to +70C

LQFP

256

MSD106CHL-LF-S3

0C to +70C

LQFP

256

MSD106CL-S4

0C to +70C

LQFP

256

MSD106CHL-S4

0C to +70C

LQFP

256

MSD106CL-LF-S4

0C to +70C

LQFP

256

MSD106CHL-LF-S4

0C to +70C

LQFP

256

MSD106CL-S5

0C to +70C

LQFP

256

MSD106CHL-S5

0C to +70C

LQFP

256

MSD106CL-LF-S5

0C to +70C

LQFP

256

MSD106CHL-LF-S5

0C to +70C

LQFP

256

MSD106CL-Z1

0C to +70C

LQFP

256

MSD106CHL-Z1

0C to +70C

LQFP

256

MSD106CL-LF-Z1

0C to +70C

LQFP

256

MSD106CHL-LF-Z1

0C to +70C

LQFP

256

MSD106CL-Z1-S1

0C to +70C

LQFP

256

MSD106CHL-Z1-S1

0C to +70C

LQFP

256

MSD106CL-LF-Z1-S1

0C to +70C

LQFP

256

MSD106CHL-LF-Z1-S1 0C to +70C

LQFP

256

MSD106CL-Z1-S2

0C to +70C

LQFP

256

MSD106CHL-Z1-S2

0C to +70C

LQFP

256

MSD106CL-LF-Z1-S2

0C to +70C

LQFP

256

MSD106CHL-LF-Z1-S2 0C to +70C

LQFP

256

MSD106CL-Z1-S3

0C to +70C

LQFP

256

MSD106CHL-Z1-S3

0C to +70C

LQFP

256

MSD106CL-LF-Z1-S3

0C to +70C

LQFP

256

MSD106CHL-LF-Z1-S3 0C to +70C

LQFP

256

MSD106CL-Z1-S4

0C to +70C

LQFP

256

MSD106CHL-Z1-S4

0C to +70C

LQFP

256

MSD106CL-LF-Z1-S4

0C to +70C

LQFP

256

MSD106CHL-LF-Z1-S4 0C to +70C

LQFP

256

MSD106CL-Z1-S5

0C to +70C

LQFP

256

MSD106CHL-Z1-S5

0C to +70C

LQFP

256

MSD106CL-LF-Z1-S5

0C to +70C

LQFP

256

MSD106CHL-LF-Z1-S5 0C to +70C

LQFP

256

Note on product suffix:


1. LF: Lead-free version.
2. S1 ~ S5: Advanced surround features.
3. Z1: Dolby Digital function not provided.
Code
S1

Description
SRS TruSurround XTTM

S2

Dolby ProLogic II + Dolby Virtual Speaker

S3

Dolby ProLogic II + Virtual Dolby Surround

S4

BBE Digital

S5

BBE ViVATM

- 14 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

The SRS TruSurround XTTM technology rights incorporated in the

MARKING INFORMATION

MSD106CL are owned by SRS Labs, a U.S. Corporation and

MSD106CL

licensed to MStar. Purchaser of MSD106CL must sign a license for

Part Number

use of the chip and display of the SRS Labs trademarks. Any

Lot Number
Operation Code A

products incorporating the MSD106CL must be sent to SRS Labs


for review. SRS TruSurround XT is protected under US and foreign

Operation Code B
Date Code (YYWW)

patents issued and/or pending. SRS TruSurround XT, SRS and (O)
symbol are trademarks of SRS Labs, Inc. in the United States and

DISCLAIMER

selected foreign countries. Neither the purchase of the MSD106CL,

MSTAR SEMICONDUCTOR RESERVES THE


RIGHT
TO
MAKE
CHANGES
WITHOUT
FURTHER NOTICE TO ANY PRODUCTS HEREIN
TO IMPROVE RELIABILITY, FUNCTION OR
DESIGN. NO RESPONSIBILITY IS ASSUMED
BY MSTAR SEMICONDUCTOR ARISING OUT OF
THE APPLICATION OR USER OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.

nor the corresponding sale of audio enhancement equipment


conveys the right to sell commercialized recordings made with any
SRS technology. SRS Labs requires all set makers to comply with
all rules and regulations as outlined in the SRS Trademark Usage
Manual separately provided.

Electrostatic charges accumulate on both test equipment and human body and can discharge
without detection. MSD106CL comes with ESD protection circuitry; however, the device may be
permanently damaged when subjected to high energy discharges. The device should be handled
with proper ESD precautions to prevent malfunction and performance degradation.

REVISION HISTORY
Document

Description

Date

MSD106CL_pb_v01

Initial release

Oct 2007

- 15 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

10/1/2007

MSD106CL
DVB LCD/PDP DTV Processor
Preliminary Product Brief Version 0.1

MECHANICAL DIMENSIONS
D
D1
A
A2

E2

A1

E-Pad
(at back of IC)

q1

q2

R1
R2
q

Gauge Plane

0.25mm

Seating Plane
b

Symbol

L1

E1

D2

Millimeter

Inch

Min. Nom. Max. Min. Nom. Max.

Symbol

Millimeter

Inch

Min. Nom. Max. Min. Nom. Max.

1.6

0.063

A1

0.05

0.002

q1

A2

1.35

1.40

1.45 0.053 0.055 0.057

q2

12 Ref

30.00

1.181

0.11

0.16

D1

28.00

1.102

0.12

D2

10.0

0.394

30.00

1.181

E1

28.00

1.102

L1

E2

10.0

0.394

12 Ref
0.21 0.004 0.006 0.008
0.20 0.005

0.40 TYP.
0.45

0.60

0.008

0.0157 TYP.

0.75 0.018 0.024 0.030

1.00 Ref
0.20

- 16 Copyright 2007 MStar Semiconductor, Inc. All rights reserved.

0.039 Ref
-

0.008

10/1/2007

CE6353

Nordig Unified DVB-T COFDM Terrestrial


Demodulator for
PC-TV and Hand-held Digital TV (DTV)
Data Sheet
Features

February 2006

Compliant with ETSI 300 744 DVB-T, Unified


Nordig and DTG performance specifications

High performance with fast fully blind acquisition


and tracking capability

Low power consumption: less than 0.32 W, and


eco-friendly standby and sleep modes

Digital filtering of adjacent channels

Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM

Ordering Information
DJCE6353 882077
WJCE6353 882206
DJCE6353 S L9EN 882128
WJCE6353 S L9G5 882170

Superior single frequency network performance

Fast AGC to track out signal fades

Good Doppler tracking capability

Enhanced frequency capture range to include


triple offsets

External 4 MHz clock or single low-cost


20.48 MHz crystal, tolerance up to +/-200 ppm

Automatic mode (2 K/8 K), guard and spectral


inversion detection

Very low driver software overhead due to on-chip


state-machine control

Novel RF level detect facility via a separate ADC

Pin
Pin
Pin
Pin

LQFP
LQFP*
LQFP
LQFP*

Pre and post Viterbi-decoder bit error rates, and


uncorrectable block count

Figure 1 - Block Diagram

1
Intel Corporation

Trays
Trays
Tape and Reel
Tape and Reel

*Pb Free Matte Tin

64
64
64
64

D55752-001

Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright 2006 Intel Corporation. All rights reserved.

CE6353

Data Sheet

Applications

Digital terrestrial set-top boxes

Integrated digital televisions

Personal video recorders

PC-TV receivers

Portable applications

Description
The CE6353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds,
with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including
Unified Nordig and DTG.
A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz IF analog signal. Advanced digital
filtering of the upper and lower channel enables a single 8 MHz channel SAW filter to be used for 6, 7 and 8 MHz
OFDM signal reception. All sampling and other internal clocks are derived from a single 20.48 MHz crystal or a 4
MHz clock input, the tolerance of which may be relaxed as much as 200 ppm.
The CE6353 has a wide frequency capture range able to automatically compensate for the combined offset
introduced by the tuner xtal and broadcaster triple frequency offsets.
An on-chip state machine controls all acquisition and tracking operations of the CE6353 as well as controlling the
tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism
ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead.
Also included in the design is a 7-bit ADC to detect the RF signal strength and thereby efficiently control the tuner
RF AGC.
Users have access to all the relevant signal quality information, including input signal power level, signal-to-noise
ratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods are
programmable over a wide range.
The device is packaged in a 10 x 10 mm 64-pin LQFP and is very low power.

2
Intel Corporation

CE6353

Data Sheet

Table of Contents
1.0 Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 IF to Baseband Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Interpolation and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Carrier Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Symbol Timing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Channel Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.14 Symbol and Bit De-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.19 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 Examples of 2-Wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.4 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 MPEG Data Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4.1 Selection of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1.1 Loop Gain Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1.2 List of Equation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1.3 Calculating Crystal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.1.4 Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.1.5 Oscillator/Clock Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3
Intel Corporation

CE6353

Data Sheet

List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4
Intel Corporation

CE6353

Data Sheet

List of Tables
Table 1 - Pin Names - numeric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2 - Pin Names - alphabetical order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5
Intel Corporation

CE6353
1.0

Pin & Package Details

1.1

Pin Outline

Figure 2 - Pin Outline

6
Intel Corporation

Data Sheet

CE6353
1.2

Data Sheet

Pin Allocation

Pin

Function

Pin

Function

Pin

Function

Pin

Function

Vss

17

SADD1

33

Vdd

49

MDO0

Vdd

18

SADD0

34

RFLEV

50

MDO1

Vss

19

CVdd

35

CLK2/GPP0

51

MDO2

CLK1

20

Vss

36

DATA2/GPP1

52

MDO3

DATA1

21

PLLVdd

37

CVdd

53

MDO4

IRQ

22

PLLGND

38

Vss

54

Vdd

CVdd

23

XTI

39

CVdd

55

Vss

Vss

24

XTO

40

Vss

56

MDO5

RESET

25

Vss

41

AGC2/GPP2

57

MDO6

10

SLEEP

26

PLLTEST

42

AGC1

58

MDO7

11

STATUS

27

OSCMODE

43

GPP3

59

CVdd

28

AVdd

44

SMTEST

60

Vss

12
13

Vdd

29

AGnd

45

Vdd

61

MOCLK

14

Vss

30

VIN

46

Vss

62

BKERR

15

31

VIN

47

MOSTRT

63

MICLK

16

32

AGnd

48

MOVAL

64

CVdd

Table 1 - Pin Names - numeric

Function

Pin

Function

Pin

Function

Pin

Function

Pin

AGC1

42

GPP3

43

PLLTEST

26

Vdd

54

AGC2/GPP2

41

IRQ

PLLVdd

21

VIN

30

AGnd

29

MDO0

49

RESET

VIN

31

AGnd

32

MDO1

50

RFLEV

34

Vss

AVdd

28

MDO2

51

SADD0

18

Vss

BKERR

62

MDO3

52

SADD1

17

Vss

CLK1

MDO4

53

N/C

16

Vss

14

CLK2/GPP0

35

MDO5

56

N/C

15

Vss

20

CVdd

MDO6

57

N/C

12

Vss

25

CVdd

19

MDO7

58

SLEEP

10

Vss

38

CVdd

37

MICLK

63

SMTEST

44

Vss

40

CVdd

39

MOCLK

61

STATUS

11

Vss

46

Table 2 - Pin Names - alphabetical order

7
Intel Corporation

CE6353

Data Sheet

CVdd

59

MOSTRT

47

Vdd

Vss

55

CVdd

64

MOVAL

48

Vdd

13

Vss

60

DATA1

OSCMODE

27

Vdd

33

XTI

23

DATA2/GPP1

36

PLLGND

22

Vdd

45

XTO

24

Table 2 - Pin Names - alphabetical order (continued)

1.3

Pin Description

Pin Description Table


Pin No

Name

Pin Description

I/O

Type

mA

MPEG pins
47

MOSTRT

MPEG packet start

3.3

48

MOVAL

MPEG data valid

3.3

49-53, 56-58

MDO(0:4)/MDO(5:7)

MPEG data bus

3.3

61

MOCLK

MPEG clock out

3.3

62

BKERR

Block error

3.3

63

MICLK

MPEG clock in

11

STATUS

Status output

IRQ

Interrupt output

CLK1

Serial clock

DATA1

23

XTI

24

XTO

10

SLEEP

Device power down

12, 15-18

SADD(4:0)

Serial address set

CMOS Tristate

3.3
CMOS
3.3

Open drain

CMOS

Serial data

I/O

Open drain

Low phase noise oscillator

Control pins

O
3.3
CMOS

3.3

44

SMTEST

Production test (only set low)

3.3

35

CLK2/GPP0

Serial clock tuner

I/O

36

DATA2/GPP1

Serial data tuner

I/O

42

AGC1

Primary AGC

41

AGC2/GPP2

Secondary AGC

I/O

43

GPP(3)

General purpose I/O

I/O

RESET

Device reset

CMOS

27

OSCMODE

Crystal oscillator mode

CMOS

3.3

26

PLLTEST

PLL analog test

(tristated)

8
Intel Corporation

Open drain

CE6353

Data Sheet

Pin Description Table (continued)


Pin No

Name

Pin Description

I/O

Type

Analog inputs
30

VIN

positive input

31

VIN

negative input

34

RFLEV

RF level

21

PLLVdd

PLL supply

1.8

22

PLLGnd

7, 19, 37, 39, 59, 64

CVdd

Core logic power

1.8

2, 13, 45, 54,

Vdd

I/O ring power

3.3

1, 3, 8, 14, 20, 25,


38, 40, 46, 55, 60

Vss

Core and I/O ground

28

AVdd

ADC analog supply

1.8

29, 32

AGnd

33

Vdd

3.3

Supply pins

2nd ADC supply

9
Intel Corporation

mA

CE6353
2.0

Data Sheet

Functional Description

A functional block diagram of the CE6353 OFDM demodulator is shown in Figure 3. This accepts an IF analog
signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and
frequency synchronization operations are all digital and there are no analog control loops except the AGC. The
frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to
combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,
the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC
can be switched from one stream to another with minimal interruption to the transport stream.

Figure 3 - OFDM Demodulator Diagram


The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to
provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures
minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi
and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at
the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting
intervals of these are programmable over a very wide range.

10
Intel Corporation

CE6353

Data Sheet

Figure 4 - FEC Block Diagram


The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus to
the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the
received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.

2.1

Analog-to-Digital Converter

The CE6353 has a high performance 10-bit analog-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:

36.17 MHz IF

43.75 MHz IF

5 - 10 MHz near-zero IF

An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly
programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.

2.2

Automatic Gain Control

An AGC module compares the absolute value of the digitized signal with a programmable reference. The error
signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which
has to be RC low-pass filtered to obtain the voltage to control the amplifier.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC
clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined
assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit
theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This
reference or target value may have to be lowered slightly for some applications. Slope control bits have been
provided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gain
control amplifiers.

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Intel Corporation

CE6353

Data Sheet

The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being
established. This is one of the features of CE6353 used to minimize acquisition time. A robust AGC lock
mechanism is provided and the other parts of the CE6353 begin to acquire only after the AGC has locked.

2.3

IF to Baseband Conversion

Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at
approximately 8.9 MHz. The first step of the demodulation process is to convert this signal to a complex (in-phase
and quadrature) signal in baseband. A correction for spectral inversion is implemented during this conversion
process. Note also that the CE6353 has control mechanisms to search automatically for an unknown spectral
inversion status.

2.4

Adjacent Channel Filtering

Adjacent channels, in particular the Nicam digital sound signal associated with analog channels, are filtered prior to
the FFT.

2.5

Interpolation and Clock Synchronization

CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the
signal at a fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate is
achieved using the time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by
factors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is
programmed in a CE6353 register (defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase
locked loop in the CE6353 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the
sampling clock.

2.6

Carrier Frequency Synchronization

There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to
broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes,
without the need for an analog frequency control (AFC) loop.
The default frequency capture range has been set to 286 kHz in the 2 K and 8 K mode. However, these values
can be increased, if necessary, by programming an on-chip register (see 7.4.1). It is recommended that a larger
capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to
adjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequency
offset can be read from an on-chip register.

2.7

Symbol Timing Synchronization

This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize intersymbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated
to dynamically adapt to time-variations in the transmission channel.

2.8

Fast Fourier Transform

The FFT module uses the trigger information from the timing synchronization module to set the start point for an
FFT. It then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. An
extremely hardware-efficient and highly accurate algorithm has been used for this purpose.

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Intel Corporation

CE6353
2.9

Data Sheet

Common Phase Error Correction

This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of
the tuner phase noise on system performance.

2.10

Channel Equalization

This consists of two parts. The first part involves estimating the channel frequency response from pilot information.
Efficient algorithms have been used to track time-varying channels with a minimum of hardware.
The second part involves applying a correction to the data carriers based on the estimated frequency response of
the channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.

2.11

Impulse Filtering

CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.

2.12

Transmission Parameter Signalling (TPS)

An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS
carriers in every symbol and all these carry one bit of TPS. These bits, when combined, include information about
the transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition,
the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are
in odd frames. The TPS module extracts all the TPS data, and presents these to the host processor in a structured
manner.

2.13

De-Mapper

This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature
components of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm
depends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy ( = 0, 1, 2 or 4). Soft decisions for both
low- and high-priority data streams are generated.

2.14

Symbol and Bit De-Interleaving

The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The deinterleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions
to the FEC in the original order.

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Intel Corporation

CE6353
2.15

Data Sheet

Viterbi Decoder

The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream.
The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch
metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor
memory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back
depth of 128 is used to minimize any loss in performance, especially at high code rates.
The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors
at its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.

2.16

MPEG Frame Aligner

The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to
ensure correct lock and to prevent loss of lock due to noise impulses.

2.17

De-interleaver

Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a
number of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The deinterleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced by
the transmitter.

2.18

Reed-Solomon Decoder

Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a
systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of
correcting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.
In addition to efficiently performing this decoding function, the Reed-Solomon decoder in CE6353 keeps a count of
the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This
information can be used to compute the post-Viterbi BER.

2.19

De-scrambler

The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a
pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packet
header may be set if required to indicate uncorrectable packets.

2.20

MPEG Transport Interface

MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present
the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard
ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the CE6353
with a clock provided by the user.

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Intel Corporation

CE6353
3.0

Interfaces

3.1

2-Wire Bus

3.1.1

Data Sheet

Host

The primary 2-wire bus serial interface uses pins:

DATA1 (pin 5) serial data, the most significant bit is sent first.

CLK1 (pin 4) serial clock.

The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
In TNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:
ADDR[7]

ADDR[6]

ADDR[5]

ADDR[4]

ADDR[3]

Not programmable
VSS

VSS

VSS

VDD

VDD

ADDR[2]

ADDR[1]

SADD[1]

SADD[0]

VDD

VDD

When the CE6353 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive
mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD
register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.

3.1.2

Tuner

The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See register
GPP_CTL address 0x8C.
Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.

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Intel Corporation

CE6353
3.1.3

Data Sheet

Examples of 2-Wire Bus Messages

KEY:

Start condition

Write (= 0)

Stop condition

Read (= 1)

Acknowledge

NA

NOT Acknowledge

Italics

CE6353 output

RADD

Register Address

Write operation - as a slave receiver:


S

DEVICE

RADD

ADDRESS

DATA

(n)

(reg n)

DATA

(reg n+1)

Read operation - CE6353 as a slave transmitter:


S

DEVICE

ADDRESS

DATA

DATA

(reg 0)

(reg 1)

DATA

NA

(reg 2)

Write/read operation with repeated start - CE6353 as a slave transmitter:


S

DEVICE

RADD

ADDRESS

3.1.4

(n)

DEVICE

DATA

ADDRESS

(reg n)

DATA

NA

(reg n+1)

Primary 2-Wire Bus Timing

t BUFF

Sr

DATA1

t LOW

tR

tF

CLK1
P

t HD;STA

t HD;DAT

tHIGH

t SU;DAT t SU;STA

Figure 5 - Primary 2-Wire Bus Timing


Where:

S = Start
Sr = Restart, i.e., start without stopping first.
P = Stop.

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Intel Corporation

t SU;STO

CE6353

Data Sheet
Value

Parameter

Symbol

Unit
Min.

Max.
400 1

CLK clock frequency (Primary)

fCLK

Bus free time between a STOP and START condition.

tBUFF

200

ns

Hold time (repeated) START condition.

tHD;STA

200

ns

LOW period of CLK clock.

tLOW

1300

ns

HIGH period of CLK clock.

tHIGH

600

ns

Set-up time for a repeated START condition.

tSU;STA

200

ns

Data hold time (when input).

tHD;DAT

100

ns

Data set-up time

tSU;DAT

100

ns

Rise time of both CLK and DATA signals.

tR

Fall time of both CLK and DATA signals, (100 pF to ground).

tF

20

ns

Set-up time for a STOP condition.

tSU;STO

200

ns

note 2

Table 3 - Timing of 2-Wire Bus


1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.

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Intel Corporation

kHz

ns

CE6353
3.2
3.2.1

Data Sheet

MPEG
Data Output Header Format

188 byte packet output


184 Transport packet bytes

Transport
Packet
Header
4 bytes
0

1st byte
2nd byte

TEI

MDO[7]

MDO[0]

Figure 6 - DVB Transport Packet Header Byte


After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any
uncorrectable packet will automatically be set to 1. If TEI_En bit is low then TEI bit will not be changed (but note
that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at
output).

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Intel Corporation

CE6353
3.2.2

Data Sheet

MPEG Data Output Signals

The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in
the packet synchronization byte position is limited to 1 output clock period. MOCLK will be a continuously running
clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with
MOCLKINV = 1, the default state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.

188 byte packet n

1st byte packet n

1st byte packet n+1

MOCLKINV=1
MOCLK

MDO7:0

MOSTRT

MOVAL

BKERR

Tp

Ti

Figure 7 - MPEG Output Data Waveforms

3.2.3

MPEG Output Timing

Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80oC, Output load = 10pF.
Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10oC, Output load = 10pF.
MOCLK frequency = 45.06 MHz.

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Intel Corporation

CE6353
3.2.4

Data Sheet

MOCLKINV = 1
Delay conditions
Parameter

Units
Maximum

Minimum

Data output delay tD

3.0

1.0

Setup Time tSU

7.0

10.0

Hold Time tH

7.0

10.0

ns

MOCLK
MDO
MOSTRT
MOVAL
BKERRB
BKERR

tD

tSU
tH
Figure 8 - MPEG Timing - MOCLKINV = 1

3.2.5

MOCLKINV = 0

MDOSWAP = 0
Delay conditions
Parameter

Units
Maximum

Minimum

3.0

1.0

18.0

20.0

1.0

0.2

Data output delay tD


Setup Time tSU
Hold Time tH

ns

The hold time is better when MOCLKINV = 1, therefore this should be used if possible.

MOCLK
MDO
MOSTRT
MOVAL
BKERRB
BKERR

tD

tSU
tH
Figure 9 - MPEG Timing - MOCLKINV = 0

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Intel Corporation

CE6353
4.0

Electrical Characteristics

4.1

Recommended Operating Conditions


Parameter

Power supply voltage:

Power supply current:

Data Sheet

Symbol

Min.

Typ.

Max.

Units

VDD

3.0

3.3

3.6

core

CVDD

1.62

1.8

1.98

periphery 1

IDDP

mA

core

IDDC

170

mA 2

periphery

Input clock frequency 3

XTI

CLK1 primary serial clock frequency 4

16.00

20.48

fCLK
-10

Ambient operating temperature

25.00

MHz

400

kHz

80

1. Current from the 3.3 V supply will be mainly dependent on the external loads.
2. Current given is for optimum performance, lower current is possible with reduced performance.
3. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as defined in the design
manual. Frequencies outside these limits are acceptable with an external clock signal.
4. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

4.2

Absolute Maximum Ratings

Maximum Operating Conditions


Parameter

Symbol

Min.

Max.

Unit

VDD

-0.3

+3.6

CVDD

-0.3

+2.0

Voltage on input pins (5 V rated)

VI

-0.3

5.5

Voltage on input pins (3.3 V rated)

VI

-0.3

VDD + 0.3

Voltage on output pins (5 V rated)

VO

-0.3

5.5

Voltage on output pins (3.3 V rated)

VO

-0.3

VDD + 0.3

Storage temperature

TSTG

-55

150

Operating ambient temperature

TOP

-10

80

Junction temperature

TJ

125

Power supply

Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for
extended periods may reduce reliability. Functionality at or above these conditions is not implied.

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Intel Corporation

CE6353
4.3

Data Sheet

DC Electrical Characteristics

DC Electrical Characteristics
Parameter
Operating
voltage

Conditions

Pins

periphery
core

Supply current 1

1.62>CVDD>1.98

Symbol

Min.

Typ.

Max.

Unit

VDD

3.0

3.3

3.6

CVDD

1.62

1.8

1.98

IDDCORE

Supply current sleep mode

170

mA

300

Outputs
Output levels

IOH 2mA
3.0>VDD>3.6
IOL 2mA
3.0>VDD>3.6
IOL 6mA
3.0>VDD>3.6

Output capacitance

MDO(7:0), MOVAL,
MOSTRT, MOCLK,
STATUS, BKERR
GPP(3:0), DATA1,
AGC1, AGC2, IRQ

VOH

2.4

VOL

0.4

VOL

0.4

Not including track MDO(7:0), MOVAL,


MOSTRT, MOCLK,
STATUS, BKERR
GPP(3:0), DATA1,
AGC1, AGC2,IRQ

3.0

pF

3.6

pF

Output leakage (tri-state)

Inputs
Input levels

3.0>VDD>3.6
-0.5 Vin
VDD+0.5V

Input levels
Input levels
Input leakage Current
Input capacitance
Input capacitance

MICLK, SADD(4:0)
SLEEP, OSCMODE

VIH

2.0

GPP(3:0), CLK1,
3.0>VDD>3.6
-0.5 Vin +5.5V DATA1, RESET

VIH

2.0

3.0>VDD>3.6

All inputs

VIL

Capacitances do
not include track

SLEEP, SMTEST,
MICLK, CLK1,
OSCMODE
SADD(4:0), DATA1,
GPP(3:0)

1. Current given is for optimum performance, lower current is possible with reduced performance.

4.4

Crystal Specification and External Clocking

Parallel resonant fundamental frequency (preferred)


Tolerance over operating temperature range
Tolerance overall
Typical load capacitance
Drive level
Equivalent series resistance

20.4800 MHz
150 ppm
200 ppm
27 pF
0.4 mW max
<25

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Intel Corporation

0.8

1.8

pF

3.6

pF

CE6353
XTI

Data Sheet

XT0

OSCMODE

XTI

C1

C2

Figure 10 - Crystal Oscillator Circuit

4.4.1

Selection of External Components

The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is
greater than unity. Correct selection of the two capacitors is very important and the following method is
recommended to obtain values for C1 and C2.

4.4.1.1

Loop Gain Equation

Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to
ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the
circuit will exhibit good start-up characteristics.
Equation 1 -

-A=

Equation 2 -

- Zin =

4.4.1.2

Cout.gm

Cout + Cin

Cin

Rf.Cin

1
Zin

-1

Zo

1
(2..f.Cout)2.ESR

List of Equation Parameters

total loop gain (between 5 and 25)

Cin

C1 + Cpar

Cout

C2 + Cpar

Cpar

parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track
capacitances, package capacitance and cell input capacitance. Normally Cpar 4pF.

Zo

9.143 k - output impedance of amplifier at 1.8 V operation - typical

gm

8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical

Rf

2.3 M - internal feedback resistor

ESR

maximum equivalent series resistance of crystal - given by crystal manufacturer ()

fundamental frequency of crystal (Hz)

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Intel Corporation

CE6353
4.4.1.3

Data Sheet

Calculating Crystal Power Dissipation

To calculate the power dissipated in a crystal the following equation can be used.
Equation 3 -

Pc =

Vpp2
8.Zin

Pc = power dissipated in crystal at resonant frequency (W)


Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVDD
Zin = crystal network impedance (see Equation 2)

4.4.1.4

Capacitor Values

Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with
Equation 4 below.
Equation 4 -

Cin = Cout =

gm
2 1 .
1
2.ESR when: C = C = C
(2..f)
1
2
out - Cpar
A
R f Zo

Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the
resulting crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL
(standard values for CL are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.
Equation 5 -

- CL =

Cout . Cin
Cout + Cin

+ Cpar12

Cpar12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC packages pin-to-pin
capacitance (including any socket used) and the printed circuit boards track-to-track capacitance.
Cpar12 2pF.
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturers
recommended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations and
tolerances on frequency stability. Smaller values of CL tend to reduce startup time and crystal power dissipation.
Care must however be taken that CL does not fall outside the crystal pulling range or the circuit may fail to start up
altogether. It is also possible to quote CL to the crystal manufacturer who can then cut a crystal to order which will
resonate, under the specified load conditions, at the desired frequency.
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is
not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain
condition is still satisfied. This must be done using Equation 1.
C2
Note: 2 >
> 0.5
C1

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Intel Corporation

CE6353
4.4.1.5

Data Sheet

Oscillator/Clock Application Notes

On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible.
Other signal tracks must not be allowed to cross through this area. The component tracks should preferably
be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal
pins. It is also advisable to provide a ground plane for the circuit to reduce noise.

External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVDD)
and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cells
amplitude clamping circuit.

An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To
limit the current taken from the signal source a resistor should be placed between the clock source and XTI.
The recommended value for this series resistor is 470 for a clock signal switching between 0 V and
CVDD. The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left
unconnected in this configuration.

AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty
cycle of the OSCOUT signal cannot be guaranteed in such a configuration.

AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that
the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM
for XTI and XTO, (set by the 36 k and 22 k resistors) must be 800 mV < VCM < CVDD and the amplitude
Vpp of the clock signal must be >100 mV.

XTO

XTI

Vdd

OSCMODE

36k
10nF

100k

External clock

10nF

22k

Figure 11 - External Clocking via AC Coupling

External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode
voltage VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal
amplitude Vpp must be >100 mV. It is recommended that differential clock signals have VCM = 1.0V. For
Vpp > 400 mV a resistor of >390 in series with XTI or XTO may be required to limit the current taken from
or supplied to the clock sources.

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Intel Corporation

CE6353
5.0

Application Circuit

Figure 12 - Typical Application Circuit

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Intel Corporation

Data Sheet

Preliminary

PLL-SPLIT VIF/SIF

R2A10407SP
PLL VIF/SIF TV Tuner
Rev2.0.3
Aug.08.2006

DESCRIPTION
R2S10407SP is a semiconductor integrated circuit consisting of PLL split-carrier VIF/SIF
signal processing system compliant with PAL. Multi.

Features
*VIF frequency corresponds to 38.9MHz.
*SIF frequency corresponds to M/N,B/G,I,D/K and SECAM L,L'.
*Reference frequency is recommended 4.0MHz, and 4.433619MHz to Pin 15
*Built-in SIF Trap and SIF band-pass Filter.
*I2CBUS control.

Pin Arrangement

24

GND

VIF IN2

23

SIF IN

PORT

22

SIF MIX F/B

21

AFC FILTER
AFT OUT

DE-EMPHASIS

20

APC FILTER

AUDIO F/B

19

Vcc

VIDEO OUT

18

SCL

EQ F/B

17

SDA

GND
Audio / SIF Output
RF AGC DELAY

16

IF AGC FILTER2

10

15

11

14

REF.INPUT
RF AGC OUT

IF AGC FILTER1

12

13

VCO F/B

Rev.2.0.3 Aug.08.2006

R2A10407SP

VIF IN1

QIF
AMP

AFT

SDA

IF AGC FILTER2

REF.INPUT

RF AGC OUT

VCO F/B

21

SCL

22

Vcc

AFC FILTER

23

APC FILTER

SIF IN

24

AFT OUT

GND

Block Diagram

20

19

18

17

16

15

14

13

INV

RF
AGC

SECAM-L

BUS Receiv er

QIF AGC
Sy nc
SEP

AFC

VCO

APC
SIF
Conv erter

TRAP

HOR
CD

BPF

QIF DET

LIM

VCO2

SECAM-L

VIDEO
DET

VIF
AGC

FM
DET

Others

AF AMP

VIF
AMP

Audio

SIF

10

VIFIN2

PORT

SIF MIX F/B

DE-EMPHASIS

AUDIO F/B

VIDEO OUT

EQ F/B

GND

Audio / SIF Output

Rev.2.0.3 Aug.08.2006

11

12

IF AGC FILTER1

RF AGC DELAY

VIF IN1

EQAMP

Absolute Maximum Ratings


Parameter
Supply Voltage

Symbol
Vcc

Total Power
Dissipation

PORT Output Voltage


PORT Input Current
Operating Temperature
Storage Temperature

Ratings
6

Pd

TBD

Vpmax
Ipmax
Topr1
Tstg

6
2.5
-20~75
-40~125

(25 C, unless otherwise noted)


Note

Unit
V

Conditions of this ratings.


(1)70x70mm2 1.6mmt (1layer board)
(2)Board material = Glass epoxy (FR-4)
mW (3)Cupper share of board = 50%
(4)Wind velocity = 0m/sec
It changes with the material of mounting
board, the Cupper share, etc.
Pin3
V
Pin3
mA
o
C
o
C

Thermal Derating (Maximum rating)

800

Power Dissipation Pd (mW)

700

TBD

600
500

-20
0
25
75
75
150

728
728
728
437
0

437 Mounting in standard circuit board


437
437
437
437
0

400
300

TBD
200
100
0
-25

25

50

75

100

125

150

Ambient Temperature Ta ( C)

Recommended Operating Condition


Parameter
Supply Voltage
Functional Supply Voltage
Reference Frequency

Rev.2.0.3 Aug.08.2006

Pin No.
19
19
15

(25 oC, unless otherwise noted)


Recommended voltage
Unit
4.6~5.25
V
5.00
V
4.00 or 4.433619
MHz

23

22

QIF
AMP

21
AFT

2.7K
SDA

20

19

INV

SECAM-L

18

17

0.1uF

0.01uF

SCL

Vcc1

0.22uF 56

1000pF

24

47uF

AFT out
0.1uF

1u 6.8K

0.01u

Anal og GND

SIF
SAW

0.01uF

4MHz

RF AGC OUT

Application Circuit example

16

15

14

13

RF
AGC

BUS Receiv er

QIF AGC
Sy nc
SEP

AFC

VCO

APC
TRAP

HOR
CD

SIF
Conv erter

BPF

QIF DET

LIM

VCO2

SECAM-L

VIDEO
DET

VIF
AGC

FM
DET

Others

AF AMP

VIF
AMP

Audio

SIF

EQAMP

Video out

Rev.2.0.3 Aug.08.2006

10

11

12
0.22uF

30K

39K

0.01u

PORT1

VIF SAW

Digital GND

0.47uF

0.01uF

0.1uF

Audio/SIF out

Pin Function
Pin
No.

Pin Name

Equivalent Circuit

Function
19

1
2

VIF Input1 VIF input terminal.


IF signal after SAW filter is input.
VIF Input2 It is a balance-type input.

1.2K
1.2K

2
24

Port

Port output terminal.


The pull-up resistor is connected from
the terminal with the power supply.
Hi/Low of the output can be selected
by the I2C bus data. set the pull-up
resistor value to the maximum inflow
current to become 2mA or less.

19

9
19

SIF mix
F/B

Converter VCO Feedback terminal.


The feedback control is to keep the
internal VCO of the uniform freerunning frequency.

15K

24

It is consist LPF with internal resistance


and attaching 0.01uF..
That time constant is set by SIF
frequency.
DeM/N ---75usec
emphasis
Others ---50usec
At Secam L mode, it is activate SIF
AGC
filter.

19
MOS SW
MOS SW

24

19

AF Bypass terminal. It is connected to


one of the input of a differential
amplifier, external capacitor provides
Audio F/B
AC filtering. When resistor is connected
in series with capacitor, it is possible to
lower the amplitude of the audio output.

53. 7K

10. 5K
MOS
SW

10. 5K

53. 7K

7p

24

Rev.2.0.3 Aug.08.2006

Pin
No.

Pin Name

Equivalent Circuit

Function
19

100

Video Output Video out terminal.

7
1mA

24
19

EQ F/B

Equalizer feedback terminal.


It is possible to change the AC
response of the video signal by
attaching L,C,R to this terminal.

24

Ground terminal for Logic, Ref,

Digital GND Amplifier

and input circuit.


19
200

10

Audio/SIF
Output

Audio output and SIF output terminal.


Select by I2C bus data.

10

24
19

11

RF AGC delay terminal.


The RF AGC Delay point is possible
RF AGC to change by the voltage of this pin.
Delay point Internal voltageare selected by I2C
bus data. Refer to I2C BUS setting
data..

MOS SW

11

24

12

IF AGC
Filter1

IF AGC filter terminal 1.


External capacitor affects AGC speed.

19

12

16

IF AGC
Filter2

IF AGC filter terminal 2.


Built-in 2.5K ohm, it is possible to doble
time constant.

Rev.2.0.3 Aug.08.2006

16

2.5K

10K

MOS SW

24

Pin
No.

Pin Name

Equivalent Circuit

Function
19

13

VIF VCO Feedback terminal.


The feedback control is to keep the
VCO F/B
internal VCO of the uniform freerunning frequency.

8K

8K

13

24
19
MOS SW

14

RF AGC
Output

RF AGC output terminal


It is current drive type.

350uA

100

14

350uA

24

15

It is possible to select external input or


X'tal oscilator by the bus data. When
the
Ref Signal external input mode, Slave address
Input
is select by the pull-down resistance of
(ADS)
2.7K ohm.
Resistor
none: 42(1000010)
pulldown:43

19

15

1K

300

1K

300

3p

9
19

17

SDA

SDA input terminal.


Bus data protocol is conformed to I2C
BUS. (400Kbps.)

17

5K

5K

ACK

19

18

SCL

SCL input terminal.


18

5K

5K

Rev.2.0.3 Aug.08.2006

Pin
No.

Pin Name

19

Vcc

Equivalent Circuit

Function

Power supply terminal

19

19
18K

20

APC Filter

APC filter terminal.

18K

20

24
19

21

AFT output terminal.


Because of pulse-like signal output,
Smoothing capacitor is connected
AFT Output
externally. Output is muting at weak
input or un-lock status. Mute function
is selected by bus data.

350K

21

350K

24
19

6K

22

AFC Filter

AFC filter terminal.

6K

48K

22

24

19

23

SIF Input

SIF input terminal.


SIF signal after SAW filter is input.

23

2K
2K

24

24

Analog GND GND terminal.

Rev.2.0.3 Aug.08.2006

24

I2C BUS Setting Data


Bidirectional bus communication control can be performed. It consists of WRITE mode which receives
various data,and READ mode which transmits data. Recognition in WRITE mode and READ mode is
performed by specification of the last bit on Address Byte (R/W bit). When the setup of a R/W bit is "0",
it is set as WRITE mode and, in the case of "1", is set as READ mode. Furthermore, it has the address
in which two programs are possible. It enables this to use two devices on the same I2 C bus.
Moreover, two programmable addresses are possible. Therefore, two devices become usable on I2 C bus.
A setup of an address is chosen by the voltage impressed to an address setting terminal (ADS:15 pin).
If the address Byte in agreement is received, a data line will be set to "L" between knowledge, and at the
time of WRITE mode, if Data Byte is received, SDA line between knowledge will be set to "L."
(1) WRITE mode
The information of 3 bytes for circuit operation required for slave address, sub address and data byte.
Three kind of data byte is selected by sub address.

After the third byte is input, the setting of the bus data becomes effective.
When the stop condition is input, before 3 byte input data on the way becomes invalid.
Timing Chart

SDA

sub-address

address

DATA

SCL

Read into latch

Slave address
14pin
DC-open
pull-down at 2.7Kohm

S6
S5
S4
S3
S2
S1
S0
Address 1
1
0
0
0
0
1
0
Address 2
1
0
0
0
0
1
1
*When using the X'tal oscillator of built-in, the slave address is only "Adress1".
Write mode data format
Address Byte
Start
slave address R/W
S6~S0
0
MSB
Address Byte
Sub address Byte
Data Byte
Sub address
Mode1
Mode2
Mode3
Mode4

Rev.2.0.3 Aug.08.2006

S6
A7
B7
MSB
A7

S5
A6
B6

A6

Sub address Byte


Sub address
A7~A0

S4
A5
B5

A5

S3
A4
B4

A4

S2
A3
B3

A3

S1
A2
B2

A2
0
0
0
0

Data Byte
Data
B7~B0
LSB
S0
A1
B1

R/W=0
A0
B0

A1
0
0
1
1

LSB
A0
0
1
0
1

Stop

Data Byte

Mode1
Mode2
Mode3
Mode4

B7

B6

XTAL
OSC

REF
443

AFT MUTE
FUNCTION

B5

B4

SIF FM GAIN
OUT24 DOWN

B3
POS
MOD

AFT
RF AGC
MUTE_H BUS

B2

B1

B0

PORT1

OVER
MOD

41H
CCH

INITIAL

RF AGC DELAY SET UP

SIF MODE SELECT

AUDIO
OUT

DEEMPHASIS

AUDIO
MUTE

AGC
SPD

3DH
00H

< Mode1 >


Ref Signal Oscilator
B7
External
0
X'tal OSC
1
Ref Signal Frequency
B6
4.433619MHz
0
4.00MHz
1
Pin10 Audio/SIF select
B5
0
1

Audio
SIF

Audio OUT Gain


B4
0
1

0dB
-14dB

Video Moduration
B3
0
1

Negative
Positive

PIN3 Port Output(Low Active)


B2
OFF
0
ON
1
Not Used
B1
0

"1" is not allowed

Over Modulation Function


B0
OFF
0
ON
1

Rev.2.0.3 Aug.08.2006

10

< Mode2 >


AFT Mute Function Select
AFT Mute Function
B7
B6
Mute OFF
0
0
Mute ON Only Un-Lock status
0
1
Mute ON Only week signal input
1
0
When Un-lock status or Dynamic AGC operation status,Mute ON.
1
1
AFT Mute Voltage
AFT Mute Voltage
B5
Center (about 0.5*Vcc)
0
High(about Vcc)
1
RF AGC Delay Control Select
RF AGC Delay Control
B4
Input
Voltage
of RF AGC Delay Pin11 Control
0
Bus Data Control
1
RF AGC Delay Adj
Delay Point
B3
B2
B1
B0
-12
0
0
0
0
-11
0
0
0
1
-10
0
0
1
0
-9
0
0
1
1
-8
0
1
0
0
-7
0
1
0
1
-6
0
1
1
0
-5
0
1
1
1
-4
1
0
0
0
-3
1
0
0
1
-2
1
0
1
0
-1
1
0
1
1
0
1
1
0
0
+1
1
1
0
1
+2
1
1
1
0
+3
1
1
1
1
When B4 of mode2 is "1" , RF AGC Delay point is possible to adjust by B3~B0 of mode2.
< Mode3 >
SIF Mode Select
B7
B6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Not Used
B4
1

B5
0
1
0
1
0
1
0
1

Sound Carrier Freq.


4.5MHz
5.5MHz
6.0MHz
6.5MHz
5.74MHz
SECAM L
SECAM L'(reverse AFT)
SECAM L'(not reverse AFT)

"0" is not allowed

Rev.2.0.3 Aug.08.2006

11

Audio OUT
B3
0
1

OFF
ON

De-emphasis
B2
OFF
0
ON
1
*Time constant is connected with SIF. (75usec@4.5MHz,50usec@5.5&6.0&6.5MHz,OFF@SECAM)
Audio Mute Function
B1
0
1

OFF
ON

IFAGC Speed Control Function


B0
slow
0
fast
1
< Mode4 >
Always input the following data
B7
B6
B5
B4
0
0
0
0

B3
0

B2
0

B1
0

B0
0

(2)READ Mode
At the time of READ mode, AFT output state is outputted to a master device.
( READ mode data format )
Address Byte
Start
slave address
S6~S0
MSB
Address Byte
Data Byte

S6
C7

Data Byte
data
C7~C0

A
R/W
1

S5
C6

S4
C5

S3
C4

S2
C3

S1
C2

Stop

LSB
S0
C1

R/W=1
C0

Data Byte
AFT
C7
0
0
0
0
1

C6
0
0
1
1
0

C5
0
1
0
1
0

Not used
C4~C0
X

Rev.2.0.3 Aug.08.2006

AFT output
0 to 0.2*Vcc
0.2*Vcc to 0.4*Vcc
0.4*Vcc to 0.6*Vcc
0.6*Vcc to 0.8*Vcc
0.8*Vcc to 1.0*Vcc

not used
-

12

Electrical Characteristics
General
No

Parameter

1 Vcc Current
2

Ref. Signal
Input Level

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Symbol

Test
Point

Input
Point

Input
Signal

Mode

Icc

Pin19

B/G

Fref

Pin15

Pin14

4MHz
sine
wave

VIF Section <NTSC/PAL>

Test
Point

Input
Point

Input
Signal

Mode

Vodet

TP7

Pin1,2

4 Sync Tip level1

Vsync1

TP7

Pin1,2

5 Video S/N1

VoS/N1

TP7

6 Input sensitivity1

VinMIN1

7 Max.IF Input1

Parameter

Condition

Min

Typ

Max

SW19=2

TBD

60

TBD

50

200

400

Unit

Note#

1
mVpp

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Symbol

No

Limits

SW

Limits

SW

Unit

Note#

Min

Typ

Max

B/G

1.68

2.10

2.52

Vpp

B/G

1.0

1.35

1.7

Pin1,2

B/G

45

50

dB

TP7

Pin1,2

B/G

35

45

dBuV

VinMAX1

TP7

Pin1,2

B/G

100

105

dBuV

8 Capture range U1

CR-U1

TP7

Pin1,2

B/G

TBD

TBD

MHz

9 Capture range L1

CR-L1

TP7

Pin1,2

B/G

TBD

TBD

MHz

10 D/G

DG

TP7

Pin1,2

B/G

11 D/P

DP

TP7

Pin1,2

B/G

deg

12 Inter modulation

IM

TP7

Pin1,2

B/G

27

35

dB

RFagcH

TP14

Pin1,2

10

B/G

Vcc
-0.5

Vcc
-0.2

RFagcL

TP14

Pin1,2

11

B/G

0.2

0.5

RFDP

TP14

Pin1,2

12

B/G

85

90

95

dBuV

TP21

Pin1,2

13

B/G

10

26

40

mV
/KHz

10

17 AFT High voltage

AFTH

TP21

Pin1,2

14

B/G

Vcc
-0.5

Vcc
-0.2

10

18 AFT Low voltage

AFTL

TP21

Pin1,2

15

B/G

0.2

0.5

10

19 AFT Mute voltage

AFTM

TP21

B/G

AFT High-Mute
voltage

AFTHM

TP21

B/G

21 AFT Center voltage

Vaft

TP21

Pin1,2

B/G

VF40

TP7

Pin1,2

16

M/N

-10

-5

-2

dB

11

VF45

TP7

Pin1,2

16

M/N

-30

-25

dB

11

VF443

TP7

Pin1,2

16

B/G

-5

dB

12

3 Video out1

RF AGC
High voltage
RF AGC
14
Low voltage
13

15

RF AGC delay
point

16 AFT Sensitivity

20

Video out Freq.


22 Response
@4.0MHz (M/N)
Video out Freq.
23 Response
@4.5MHz (M/N)
Video out Freq.
24 Response
@4.43MHz(B/G)

Rev.2.0.3 Aug.08.2006

Condition

Vcc/2
Vcc/2
Vcc/2
-0.4
+0.4
Vcc
Vcc
-0.5
-0.2
Vcc/2
Vcc/2
Vcc/2
-0.45
+0.45

V
V
V

13

No

Parameter

Video out Freq.


25 Response
@5.5MHz(B/G)
Video out Freq.
26 Response
@5.74MHz(B/G)
Video out Freq.
27 Response
@6.0MHz(I)
Video out Freq.
28 Response
@6.5MHz(D/K)
29

VIF VCO free run


frequency

Min

Limits
Typ

Max

B/G

-25

16

B/G

Pin1,2

16

TP7

Pin1,2

16

D/K

TP21

B/G

Symbol

Test
Point

Input
Point

Input
Signal

Mode

VF55

TP7

Pin1,2

16

VF574

TP7

Pin1,2

VF60

TP7

VF65
Fvcof

VIF Section <SECAM-L>

-20

-15

dB

14

-500

+500

KHz

15

Pin1,2

35

45

dBuV

TP7

Pin1,2

TBD

TBD

MHz

TP7

Pin1,2

TBD

TBD

MHz

VinMIN2

TP7

33 Capture range U2

CR-U

34 Capture range L2

CR-L

Rev.2.0.3 Aug.08.2006

32 Input sensitivity2

45

13

1.7

Pin1,2

44

dB

1.35

TP7

43

-15

1.0

Vsync2

42

-20

31 Sync Tip level2

41

Audio S/N
(B/G,I,D/K)
Limiting
sensitivity (M/N)
Limiting
sensitivity
(B/G,I,D/K)
SIF output level
(M/N)
SIF output level
(B/G,I,D/K)
BPF frequency
@+/- 300KHz

12

Vpp

Pin1,2

40

dB

2.52

TP7

39 Audio S/N (M/N)

-13

2.10

Vodet2

AF output level
(M/N)
AF output level
36
(B/G,I,D/K)
AF output THD
37
(M/N)
AF output THD
38
(B/G,I,D/K)

-18

1.68

30 Video out2

35

12

Mode

Parameter

dB

Max

Input
Signal

No

-20

Min

Input
Point

SIF Section <NTSC/PAL>

Note#

Limits
Typ

Test
Point

Parameter

SW21=
2

Unit

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Symbol

No

SW
Condition

SW
Condition

Unit

Note#

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Symbol

Test
Point

VoAF1

TP10

VoAF2

TP10

THDAF1

TP10

THDAF2

TP10

AF S/N1

TP10

AF S/N2

TP10

LIM1

TP10

LIM2

TP10

SIFG1

TP10

SIFG2

TP10

BWBPF

TBD

Input
Point
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23

Min

Limits
Typ

Max

M/N

0.6

1.0

1.4

Vpp

18,3

B/G, I,
D/K

0.6

1.0

1.4

Vpp

17,3

M/N

0.5

1.0

18,3

B/G, I,
D/K

0.5

1.0

19,3

M/N

54

60

dB

16

20,3

B/G, I,
D/K

54

60

dB

16

21,22,3

M/N

20

30

dBuV

17

23,24,3

B/G, I,
D/K

20

30

dBuV

17

19,3

M/N

100

105

110

dBuV

18

20,3

B/G, I,
D/K

100

105

110

dBuV

18

29,3

B/G

-20

-15

dB

19

Input
Signal

Mode

17,3

SW
Condition

SW14=
2

Unit

14

Note#

SIF Section <SECAM-L>

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1) SW=1)

Min

Limits
Typ

Max

TBD

TBD

25,3

0.6

27,28

L'

25,3

Test
Point

AFDC

TP10

VoAF3

TP10

VoAF4

TP10

THDAF3

TP10

THDAF4

TP10

AFS/N3

TP10

SIF Input
sensitivity (L)

LIM3

TP10

53 SIF Max.IF Input

SinMAX

TP10

Symbol

Test
Point

Input
Point

SW Condition

V PORTL

TP3

SW3=2
Io2=2mA

I PORTL

TP3

46
47
48
49
50

Parameter
AF output DC
voltage
AF output level
(L)
AF output level
(L')
AF output THD
(L)
AF output THD
(L')

51 Video S/N (L)


52

Others
No

Parameter

PORT Output Low


Voltage
PORT Output
55
Leak Current

54

Rev.2.0.3 Aug.08.2006

Input
Point
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23
Pin1,2,
Pin23

Input
Signal

Mode

20,3

SW

Symbol

No

Unit

Note#

TBD

20

1.0

1.4

Vpp

0.6

1.0

1.4

Vpp

0.5

1.0

27,28

L'

0.5

1.0

20,3

TBD

TBD

dB

21

26,3

TBD

TBD

dBuV

22

26,3

TBD

TBD

dBuV

23

Condition

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Min

Limits
Typ

Max

-10

Unit

Note#

0.4

24

10

25

15

Data Entry Section


No
56
57
58
59

(Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1) SW=1)

Parameter

Symbol

High Level Input


Voltage
Low Level Input
Voltage
High Level Input
Current
Low Level Input
Current
Low Level Output
Voltage
SCL Clock
Frequency

ViH
ViL
IiH
IiL

Test
Point

TP17
TP18
TP17
TP18
TP17
TP18
TP17
TP18

SW Condition

SW17=2 or SW18=2
Vo=5.0V
SW17=2 or SW18=2
Vo=0V
SW17=2 , SW17a=2
Io3=3mA (Sync Current)

Min

Limits
Typ

Max

2.3

Vcc

0.7

-10

10

-10

10

0.4

Unit

VoSL

TP17

fSCL

TP18

440

KHz

62 Bus Free Time

tBUF

TP17

1300

nsec

63 Start Hold Time

tHD STA

TP17

600

nsec

t LOW

TP18

1300

nsec

t HIGH

TP18

600

nsec

600

nsec

nsec

100

nsec

300

nsec

300

nsec

600

nsec

60
61

SCL Low Hold


Time
SCL High Hold
65
Time

64

66 Start Setup Time

tSU STA

67 Data Hold Time

tHD DAT

68 Data Setup Time

tSU DAT

69 Rise Time

tR

70 Fall Time

tF

71 Setup Time

t SUSTO

TP17
TP18
TP17
TP18
TP17
TP18
TP17
TP18
TP17
TP18
TP17
TP18

Data Timing Chart

SDA
tLOW

tBUF

tR

tF

tHDSTA

SCL
tHDSTA
[STOP]
condition

[START]
condition

Rev.2.0.3 Aug.08.2006

tHDDAT

tHIGH

tSUDAT

tSUSTA

tSUSTO
[START]
condition

[STOP]
condition

16

Note#

Test circuit
Vcc

A
A

2.7K

TP18

19

SDA

18

SW15

SW17

TP14

TP17

17

16

15

14

13

RF
AGC

SECAM-L

INV

0.1u

0.22u 56

SCL

20

AFT

SW18

0.01u

21

QIF
AMP

47u

0.1u

6.8K

1
SW20
TP21

22

SW17a

1u

23

1
1

I2C BUS

0.01u

51

SW19

0.01u

0.01u

24

Ref
Signal

Vo

51

Io3=3mA

BUS Receiv er

QIF AGC

VCO

APC

Sy nc
SEP

AFC

TRAP

HOR
CD

SIF
Conv erter

BPF

QIF DET

LIM

VCO2

SECAM-L

VIDEO
DET

VIF
AGC

FM
DET

Others

AF AMP

VIF
AMP

Audio

SIF

EQAMP

10

11

12

TP12

TP7

TP10

2
V12

0.01u

0.47u

0.01u

0.1u
4.7K 1

2
Io2=2mA

51

0.01u

TP3

SW3

Vcc

Vcc

VIF
Signal

Rev.2.0.3 Aug.08.2006

17

Input Signal
Termination with 50 ohm

SG
1
2
3
4
5
6
7
8

fo=38.9MHz

Sync Tip Level=90dBuV


Negative 90% TV modulation 10 step waveform

B/G system

fo=38.9MHz

L system

White Peak Level=90dBuV

Positive 95% TV modulation 10 step waveform


fo=38.9MHz

Vi=Variable

fo=38.9MHz

Sync Tip Level=Variable


Negative 90% TV modulation 10 step waveform
fo=38.9MHz

CW
B/G system

White Peak Level=Variable L system

Positive 95% TV modulation 10 step waveform


fo=38.9MHz

Vi=Variable

fo=Freq. Variable

fm=20KHz

Sync Tip Level=90dBuV


Negative 90% TV modulation 10 step waveform

B/G system

fo=Freq. Variable

L system

White Peak Level=90dBuV

AM=16.0%

Positive 95% TV modulation 10 step waveform


Vi=90dBuV
Vi=80dBuV
Vi=80dBuV

CW
CW
CW

10 fo=38.9MHz

Vi=70dBuV

CW

11 fo=38.9MHz

Vi=110dBuV

CW

12 fo=38.9MHz

Vi=Variable

CW

13 fo=Freq. Variable

Vi=90dBuV

CW

14 fo=38.9MHz-0.5MHz

Vi=90dBuV

CW

15 fo=38.9MHz+0.5MHz

Vi=90dBuV

CW

f1=38.9MHz

Vi=90dBuV

CW

f2=Freq. Variable

Vi=80dBuV

CW

17
18
19
20
21

fo=34.4MHz
fo=33.4(32.9, 32.4)MHz
fo=34.4MHz
fo=33.4(32.9, 32.4)MHz
fo=34.4MHz

Vi=80dBuV
Vi=80dBuV
Vi=80dBuV
Vi=80dBuV
Vi=Variable

fm=1KHz
fm=1KHz
CW
CW
fm=1KHz

22
23
24
25

fo=34.4MHz
fo=33.4(32.9, 32.4)MHz
fo=33.4(32.9, 32.4)MHz
fo=32.4MHz

Vi=Variable
Vi=Variable
Vi=Variable
Vi=80dBuV

CW
fm=1KHz
CW
fm=1KHz

26 fo=32.4MHz

Vi=Variable

fm=1KHz

AM=54%

27 fo=33.9MHz
28 fo=40.4MHz

Vi=90dBuV
Vi=80dBuV
Vi=80dBuV

CW
fm=1KHz
CW

AM=54%

16

f1=38.9MHz
f2=34.47MHz
fo=33.4MHz

29 f0=33.40.3MHz

Rev.2.0.3 Aug.08.2006

Mixed signal

Mixed signal
+/- 25KHz dev
+/- 50KHz dev

+/- 25KHz dev


+/- 50KHz dev
AM=54%

18

Note
*VIF,SIF Input frequency
MODE
VIF IN
M/N (4.5MHz)
38.9MHz
B/G (5.5MHz)
38.9MHz
I (6.0MHz)
38.9MHz
D/K (6.5MHz)
38.9MHz
SECAM L
38.9MHz
SECAM L'
38.9MHz

SIF IN
34.4MHz
33.4MHz
32.9MHz
32.4MHz
32.4MHz
40.4MHz

*Out put SIF frequency, Note It isn't limiting in the band inside the IC.
frequency
Audio system
Note
4.5MHz
M/N
It isn't limiting in
5.5MHz
B/G
the band inside
I
6.0MHz
the IC.
D/K
6.5MHz

Rev.2.0.3 Aug.08.2006

19

Note
Note1 Vcc Current:Icc
1. Set SIF mode to B/G(5.5MHz).
2. Measure the current that flow into Vcc(Pin19).
This current is named Vcc Current.

Note2 Sync Tip Voltage : Vsync1, Vsync2


1 Input SG1@B/G or SG2@SECAM-L to VIF IN(Pin1,Pin2).
2 The Vsync1 and Vsync2 are the minimum DC level of the output waveform
defined Video output(TP7).
TP7

0V

Vsync1(Vsync2)

Note3 Video S/N:VoS/N1


1. Input SG3 to VIF IN (Pin1,Pin2) and measure the Video Output (TP7) noise in r.m.s.
through a 5MHz (-3dB) L.P.F.
2. The Video S/N is calculated by following.

Vo S/N=20xlog

0.7 X Vodet (Vpp)


NOISE
(rms)

(dB)

Note4 Input sensitivity : Vin MIN1,VinMIN2


1. Input SG4@B/G or SG5@SECAM-L to VIF IN(Pin1,Pin2), and then gradually
reduce Vi and measure the input level when the 20KHz component
of Video Output (TP7), reaches -3dBuV from Vodet level.
2. This input level is named Input sensitibity.

Note5 Maximum allowable input : VinMAX1


1. Input SG6 (Vi=90dBu) to VIF IN(Pin1,Pin2) , and measure the level of the 20KHz
component of Video Output(TP7).
2. Gradually increase the Vi of SG6 and measure the input level
when the output reaches -3dB.
3. This input level is named Maximum allowable input.

Rev.2.0.3 Aug.08.2006

20

Note6 Capture range U : CR-U1, CR-U2


1. Input SG7@B/G or SG8@SECAM-L to VIF IN(Pin1,Pin2),and then
Increase the frequency of SG7 or SG8 until the VCO is out of locked-oscillation.
2. And decrease the frequency of SG7(SG8) and measure the frequency fU
when the VCO is locked.
3. The Capture range U is calculated by following.
CR-U1 = fU-38.9
CR-U2 = fU-38.9

(MHz)

Note7 Capture range L : CR-L1, CR-L2


1. Input SG7@B/G or SG8@SECAM-L to VIF IN(Pin1,Pin2),and then
decrease the frequency of SG7 or SG8 until the VCO is out of locked-oscillation.
2. And increase the frequency of SG7(SG8) and measure the frequency fL
when the VCO is locked.
3. The Capture range L is calculated by following.
CR-L1 = 38.9-fL
CR-L2 = 38.9-fL

(MHz)

Note8 Inter modulation : IM


1. Set SIF IN(Pin23) to 5.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=1)
2. Input SG9 to VIF IN(Pin1,Pin2),and measure Video Output (TP7) with an oscilloscope.
3. Set SW12 to 2,and then adjust V12 so that the minimum DC level of the output
waveform is Vsync1.
4. Measure TP7 with a spectrum analyzer. The inter modulation is defined as a difference
between 1.07MHz and 4.43MHz frequency components.

Note9 RF AGC delay point : RFDP


1. Input SG12 to VIF IN(Pin1,Pin2) and gradually reduce level and then measure
2. the input level when RF AGC Output(TP14) reaches 1/2Vcc, as shown below.
This level is named RF AGC delay point.
3. AT that time, the set point of RE AGC (I2C BUS) is initial state.
TP14
Volt.
RFagcH
RFagcL

1/2Vcc

RFDP

Rev.2.0.3 Aug.08.2006

SG12 Level
(dBuV)

21

Note10 AFT sensitivity : , Maximum AFT voltage:AFTH, Minimum AFT voltage:AFTL


1. Input SG13 to VIF IN(Pin1,Pin2), and set the frequency of SG13 so that the voltage of
AFT Output (TP21) is 3 volt. This frequency is named f(3).
2. Set the frequency of SG13 so that the AFT Output voltage is 2 volt.
This frequency is named f(2).
3. The AFT sensitivity is calculated by following.
=

1000
f(2) - f(3)

(mV)
(KHz)

(mV/KHz)

4. IN the graph shown below, maximum and minimum DC voltage are


AFTH and AFTL, respectively.
TP21
Volt.
3V

AFTH

2V

AFTL

f(3)

f(MHz)

f(2)

Note11 Video out Freq. Respons M/N (4.0MHz,4.5MHz) : VF40,VF45


1. Set SIF mode select to 4.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=0)
2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer
when SG16 (f2=37.9MHz) is input to VIF IN(Pin1,Pin2). This level is named F(1.0M).
At that time, measure the voltage at TP11, and then fix V11 at that voltage.(SW12=2)
3. SG16(f2=34.9MHz),measure the level t of 4.0MHz of Video Output (TP7).
This level is named F(4.0M).
4. SG16(f2=34.4MHz),measure the level of 4.5MHz of Video Output (TP7).
This level is named F(4.5M).
5. The Video out Freq. Respons @4.0MHz(M/N),and Video out Freq. Respons
@4.5MHz(M/N) is calculated by following.
VF40 = F(4.0M) - F(1.0M)
(dB)
VF45 = F(4.5M) - F(1.0M)
(dB)
TP7

VF40

F(1.0M)
F(4.0M)

VF45

F(4.5M)
1.0

Rev.2.0.3 Aug.08.2006

4.0

4.5

(MHz)

22

Note12 Video out Freq. Respons B/G (4.43MHz,5.5MHz,5.74MHz) : VF443,VF55,VF574


1. Set SIF mode select to 5.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=1)
2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer
when SG16 (f2=37.9MHz) is input to VIF IN(Pin1,Pin2). This level is named F(1.0M).
At that time, measure the voltage at TP11, and then fix V11 at that voltage.(SW12=2)
3. SG16(f2=34.47MHz),measure the level of 4.43MHz of Video Output (TP7).
This level is named F(4.43M).
4. SG16(f2=33.4MHz),measure the level of 5.5MHz of Video Output (TP7).
This level is named F(5.5M).
5. SG16(f2=33.16MHz),measure the level of 5.74MHz of Video Output (TP7).
This level is named F(5.74M).
6. The Video out Freq. Respons @4.43MHz (B/G), Video out Freq. Respons
@5.5MHz (B/G) and Video out Freq. Respons @5.74 (B/G) is calculated by following.
VF443 = F(4.43M) - F(1.0M)
VF55 = F(5.5M) - F(1.0M)
VF574 = F(5.74M) - F(1.0M)
TP7

(dB)
(dB)
(dB)
VF443

VF55 VF574

4.43

5.5 5.74

F(1.0M)
F(4.43M)

F(5.74M)
F(5.5M)
1.0

(MHz)

Note13 Video out Freq. Respons I (6.0MHz) : VF60


1. Set SIF mode select to 6.0MHz.(I2C BUS : Mode3 B7=0,B6=1,B5=0)
2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer
when SG16 (f2=37.9MHz) is input to VIF IN(Pin1,Pin2). This level is named F(1.0M).
At that time, measure the voltage at TP11, and then fix V11 at that voltage.(SW12=2)
3. Adjust SG16(f2=32.9MHz),measure the level of 6.0MHz of Video Output (TP7).
This level is named F(6.0M).
4. The Video out Freq. Respons @6.0MHz (I) is calculated by following.
VF60 = F(6.0M) - F(1.0M)

(dB)

TP7
VF60

F(1.0M)

F(6.0M)
1.0

Rev.2.0.3 Aug.08.2006

6.0

(MHz)

23

Note14 Video out Freq. Respons D/K (6.5MHz) : VF65


1. Set SIF mode to 6.5MHz.
2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer
when SG16 (f2=37.9MHz) is input to VIF IN(Pin1,Pin2). This level is named F(1.0M).
At that time, measure the voltage at TP11, and then fix V11 at that voltage.(SW12=2)
3. SG16(f2=32.4MHz),measure the level of 6.5MHz of Video Output (TP7).
This level is named F(6.5M).
4. The Video out Freq. Respons @6.5MHz (D/K) is calculated by following.
VF65 = F(6.5M) - F(1.0M)

(dB)

TP7
VF65

F(1.0M)

F(6.5M)
1.0

(MHz)

6.5

Note15 VIF VCO freerun freq. : Fvcof


1. Input the following the bus data, and makes the free run measurement mode.
Address Byte
Sub address Byte
Data Byte

1
X
0

0
X
0

0
X
1

0
X
0

0
X
0

1
0
0

X
1
0

0
1
0

2. Set SW21 to 2, measure the freq. Output to TP21. This freq is named Faft.
3. VCO free run freq is calculated by following.
In the case of standard signal frequency = 4.00MHz
Fvcof = { Faft (MHz) - 4.00 (MHz) * 2 } * 1000

[KHz]

In the case of standard signal frequency = 4.433619MHz


Fvcof = { Faft (MHz) - 4.433619 (MHz) * 2 } * 1000
[KHz]
4. Do apower once in off the free run measurement comletes.
or input the following the bus data, and cancels the free run measurement mode.
Address Byte
Sub address Byte
Data Byte

Rev.2.0.3 Aug.08.2006

1
X
0

0
X
0

0
X
0

0
X
0

0
X
0

1
0
0

X
1
0

0
1
0

24

Note16 Audio S/N: AF S/N1, AF S/N2


1. Set De-emphasis to 75us@M/N or 50us@B/G(SUB),I,D/K.
2. Input SG3 to VIF IN(Pin1,Pin2), SG19@M/N or SG20`B/G(SUB),I,D/K
to SIF IN(Pin23), and measure the output noise level of Audio Output (TP10)
with FLAT-r.m.s. This level is named Vn1(Vn2).
3. The Audio S/N(AF S/N1,AF S/N2) is calculated by following.

AF S/N1=20xlog

VoAF1 (mVrms)
Vn1 (mVrms)

(dB)

AF S/N1=20xlog

VoAF1 (mVrms)
Vn1 (mVrms)

(dB)

Note17 Limiting sensitivity : LIM1, LIN2


1. Set De-emphasis to 75use@M/N or 50us@B/G(SUB),I,D/K.
2. Input SG3 to VIF IN(Pin1,Pin2).
3. Input SG21@M/N or SG23@B/G(SUB),I,D/K to SIF IN(Pin23),
and measure the 1KHz component level of Audio Output(TP10) with FLAT-r.m.s.
4. Input SG22@M/N or SG24@B/G(SUB),I,D/K to SIF IN(Pin23),
and measure the 1KHz component level of Audio Output(TP10) with FLAT-r.m.s.
5. The Limiting sensitivity(LIM1,LIM2) is defined as the input level when the difference
between each 1KHz components of Audio Output (TP10) is 30dB,respectively,
as shown below.
TP10
(rms)

TP10 while SG21 (SG23) is input.

30dB
TP10 while SG22(SG24) is input.

LIM1(LIM2)

(dBuV)

SIF IN

Note18 SIF output level : SIFG1, SIFG2


1. Input SG3 to VIF IN(Pin1,Pin2), and SG19@M/N or SG20@B/G(SUB),I,D/K
to SIF IN(Pin23), and measure the 4.5~ 6.5MHz component level of TP10.
2. Attention, at this time, the SIF signal must not pass internal BPF.

Rev.2.0.3 Aug.08.2006

25

Note19 BPF Freq. Respons @ +/-300KHz : BWBPF


1. Set SIF mode to B/G.
2. Input the BUS of follwing, so that set to the mode measures BPF Freq.
X
0
Address Byte
1
0
0
0
0
1
Sub address Byte
X
X
X
X
X
1
0
0
Data Byte
0
1
0
0
1
0
0
0
3. Input SG3 to VIF IN(Pin1,Pin2), SG29 to SIF IN(Pin23) ,
and then measure the 600(+/-300)KHz component of TP14 .
TP14
VF0
BWBPF
V300

300

600

900

f0 (KHz)

4. Do apower once in off the BPF frequency response measurement comletes.


or input the following the bus data, and cancels the BPF frequency response
measurement mode.
Address Byte
Sub address Byte
Data Byte

1
X
0

0
X
0

0
X
0

0
X
0

0
X
1

1
1
0

X
0
0

0
0
0

Note 20 Audio output DC voltage : AFDC


1. Set SIF mode to SECAM-L.
2. Input SG3 to VIF IN(Pin1,Pin2), SG20(f0=32.4MHz) to SIF IN(Pin23) .
3. Measure the DC voltage of Audio output(TP10) .

Note 21 Audio S/N (L) : AFS/N3


1. Set SIF mode to SECAM-L.
2. Input SG3 to VIF IN(Pin1,Pin2), SG20(f0=32.4) to SIF IN(Pin23).
3. Measure the output noise level of Audio Output (TP10) with FLAT-r.m.s.
This level is named Vn3.
4. The Audio S/N(L) is calculated by following.
AF S/N3 = 20log

Rev.2.0.3 Aug.08.2006

VoAF3
Vn3

(mVrms)
(mVrms)

(dB)

26

Note22 SIF Input sensitivity (L) : LIM3


1. Set SIF mode to SECAM-L.
2. Input SG3 to VIF IN(Pin1,Pin2) , SG26(Vi=80dBuV) to SIF IN(Pin23) ,
and then gradually reduce Vi and measure the input level when the 1KHz component
of Audio Output (TP10), reaches -3dBuV from VoAF3 level.
3. This input level is named SIF input sensitibity(L).

Note23 SIF Maximum allowable input : SinMAX


1. Set SIF mode SECAM-L.
2. Input SG3 to VIF IN(Pin1,Pin2) , SG26(Vi=80dBuV) to SIF IN(Pin23) ,
and then gradually increase Vi and measure the input level when the 1KHz component
of Audio Output (TP10), reaches -3dBuV from VoAF3 level.
3. This input level is named SIF maximum allowable input.

Note24 Port output low voltage : VPROTL


1. Set PORT Out be on. (I2C BUS : Model1 B2=1)
2. Set SW3 to 2 so that Io1=2mA, and measure the output level of TP3.
This is named PORT Output Low Voltage

Rev.2.0.3 Aug.08.2006

27

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter

General Description

Features

The EC9410 is a 380 KHz fixed frequency


monolithic step down switch mode regulator with a
built in internal Power MOSFET. It achieves 2A
continuous output current over a wide input supply
range with excellent load and line regulation.

z
z
z
z
z

The device includes a voltage reference, oscillation


circuit, error amplifier, internal PMOS and etc.

z
z
z

The PWM control circuit is able to adjust the duty


ratio linearly from 0 to 100%. An enable function,
an over current protection function and a short
c ircu i t protection function are built inside. An
internal compensation block is built in to minimize
external component count.
The EC9410 serves as ideal power supply units
for portable devices.

z
z
z

2A Constant Output Current


140m RDSON Internal Power PMOSFET
Switch
Up to 95% Efficiency
Fixed 380KHz Frequency
Wide 3.6V to 20V Input Voltage Range
Output Adjustable from 1.222V to 18V
Built in Frequency Compensation
Built in Thermal Shutdown Function
Built in Current Limit Function
SOP8 Package is Available
The minimum dropout up to 0.3V

Applications
z

Portable DVD

LCD Monitor / TV

Battery Charger

ADSL Modem

Telecom / Networking Equipment

Function Block

E-CMOS Corp. (www.ecmos.com.tw)

Page 1 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Pin Description

Pin Assignments

Pin Number

Pin Name

1,6,8

Description

NC

Not Connect

Vin

Supply Voltage Input Pin. EC9410


operates from a 3.6V to 20VDC voltage.
Bypass Vin to GND with a suitably large
capacitor to eliminate noise on the input.

SW

Power Switch Output Pin. SW is the


switch node that supplies power to
the output.

GND

Ground Pin. Care must be taken in layout.


This pin should be placed outside of the
Schottky Diode to output capacitor ground
path to prevent switching current spikes
from inducing voltage noise into EC9410.

FB

Feedback Pin. Through an external


resistor divider network, FB senses the
output voltage and regulates it. The
feedback threshold voltage is 1.222V.

EN

Enable Pin. EN is a digital input that turns


the regulator on or off .Drive EN pin high
to turn on the regulator, drive it low to turn
it off.

Ordering/ Marking Information


EC9410 N - F
F: Lead-Free

Circuit Type

Package: N = SOP8

Package type

Part Number

Marking

EC9410-F
SOP8

EC9410N-F

YYWW
XXXXXXXX

E-CMOS Corp. (www.ecmos.com.tw)

Page 2 of 10

Marking Information
F is Lead free package
YY is the year of production. 06 means the
product is manufactured in year of 2006.
WW is the week of production. 25 means the
th
product is manufactured in the 25 week.
XXXXXXXX is Lot number.

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter

Absolute Maximum Ratings


Parameter

Symbol

Value

Unit

Input Voltage

VIN

-0.3 to 20

Feedback Pin Voltage

VFB

-0.3 to Vin

Enable Pin Voltage

VEN

-0.3 to 12

Switch Pin Voltage

VSW

-0.3 to Vin

Power Dissipation

PD

Operating Junction Temperature

TJ

Internally limited
150

TSTG

Storage Temperature
Lead Temperature (Soldering, 10 sec)
ESD (HBM)

mW
C

-65 to 150

TLead

260

VESD

2000

Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

Recommended Operating Conditions


Parameter

Symbol

Min.

Max.

Unit

VIN

3.6

20

Operating Junction temperature

TJ

-40

125

Operating Ambient Temperature

TA

-40

85

Input Voltage

E-CMOS Corp. (www.ecmos.com.tw)

Page 3 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Electrical Characteristics
VCC = 12V, Ta = 25 unless otherwise specified.

Parameters
Input voltage
Shutdown Supply Current

Symbol

Test Condition

Min.

Typ.

Max.

Unit

VIN

3.6

20

ISTBY

VEN=0V

30

90

uA

Supply Current

ICC

VEN=2V, VFB=1.3V

3.6

mA

Feedback Voltage

VFB

VIN = 3.6V to 23V

1.21

1.222

1.26

Feedback Bias Current

IFB

0.1

0.5

uA

Switch Current Limit

ILIM

Oscillator Frequency

FOSC

320

380

440

KHz

Frequency of Current Limit or


Short Circuit Protection

FOSC1

VFB=0V

42

KHz

VEN

0.7

1.2

1.7

EN Pin Threshold

VFB=1.3V

IH

VEN=2.5V

-0.1

-1

uA

IL

VEN=0.5V

-3

-10

uA

EN Pin Input Leakage Current

Internal PMOS RDSON

RDSON

VIN=12V,VFB=0V
VEN=12V, Iout=2A

140

Max. Duty Cycle

DMAX

VFB=0V, ISW=0.1A

100

VIN=12V,Vout=5V
Iout=2A

92

165

Efficiency
Thermal Shutdown

E-CMOS Corp. (www.ecmos.com.tw)

TOTSD

Page 4 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter

Typical Performance Characteristics

Switching Frequency vs. Temperature

Efficiency vs. Load (Vin=10V)

Icc vs. Temperature

E-CMOS Corp. (www.ecmos.com.tw)

VFB vs. Temperature

Page 5 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Typical Application Circuit
Typical Application Circuit @ 5V/2A

EC9410

Typical Application Circuit @ 3.3V/2A

EC9410

E-CMOS Corp. (www.ecmos.com.tw)

Page 6 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Typical Application Circuit (Continued)
Typical Application Circuit (with ceramic output capacitor) @ 5V/2A

EC9410

Typical Application Circuit (with ceramic output capacitor) @ 3.3V/2A

EC9410

E-CMOS Corp. (www.ecmos.com.tw)

Page 7 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Schottky Rectifier Selection Guide
EC9410 Lists some rectifier manufacturers.
Vin (Max)

2A Load Current

20V

Part Number

Vendor

B220

Diodes, Inc.

SK23

Pan Jit International

SR22

Pan Jit International

Output Voltage VS R1, R2 Resistor Selection Guide (Vout = (1+R1/R2)*1.222V)


EC9410 Vout VS. R1, R2 Select Table
R1

R2

1.8V

3.9K

8.2K

2.5V

3.2K

3K

3.3V

6.2K

3.6K

5V

6.2K

2K

9V

13K

2K

12V

16K

1.8K

Vout

E-CMOS Corp. (www.ecmos.com.tw)

Page 8 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter
Function Description
VIN
This is the positive input supply for the IC switching regulator. A suitable input bypass capacitor must be present
at this pin to minimize voltage transients and to supply the switching currents needed by the regulator

Gnd
Circuit ground.

SW
Internal switch. The voltage at this pin switches between (VIN VGS) and approximately 0.5V, with a duty
cycle of approximately VOUT / VIN. To minimize coupling to sensitive circuitry, the PC board copper area
connected to this pin should be kept a minimum.

FB
Senses the regulated output voltage to complete the feedback loop.

EN
Allows the switching regulator circuit to be shutdown using logic level signals thus dropping the total input supply
current to approximately 30uA. Pulling this pin below a threshold voltage of approximately 0.7 V turns the
regulator down, and pulling this pin above 1.3V (up to a maximum of 12V) shuts the regulator on. For automatic
starup condition, can be implemented by the addition of a resistive voltage divider from VIN to GND.

Thermal Considerations
The SOP8 package needs a heat sink under most conditions. The size of the heat sink depends on the input
voltage, the output voltage, the load current and the ambient temperature. The EC9410 junction temperature
rises above ambient temperature for a 2A load and different input and output voltages. The data for these curves
was taken with the EC9410 (SOP8 package) operating as a buck-switching regulator in an ambient temperature
of 25 C (still air). These temperature rise numbers are all approximate and there are many factors that can affect
these temperatures. Higher ambient temperatures require more heat sinking.
For the best thermal performance, wide copper traces and generous amounts of printed circuit board copper
should be used in the board layout.(Once exception to this is the output (switch) pin, which should not have large
areas of copper.) Large areas of copper provide the best transfer of heat (lower thermal resistance) to the
surrounding air, and moving air lowers the thermal resistance even further.
Package thermal resistance and junction temperature rise numbers are all approximate, and there are many
factors that will affect these numbers. Some of these factors include board size, shape, thickness, position,
location, andeven board temperature. Other factors are, trace width, total printed circuit copper area, copper
thickness, single or double-sided, multi-layer board and the amount of solder on the board.
The effectiveness of the PC board to dissipate heat also depends on the size, quantity and spacing of other
components on the board, as well as whether the surrounding air is still or moving. Furthermore, some of these
components such as the catch diode will add heat to the PC board and the heat can vary as the input voltage
changes. For the inductor, depending on the physical size, type of core material and the DC resistance, it could
either act as a heat sink taking heat away from the board, or it could add heat to the board.

E-CMOS Corp. (www.ecmos.com.tw)

Page 9 of 10

2007/04/10

EC9410
2A 380KHZ 20V PWM Buck DC/DC Converter

OUTLINE DRAWING FOR SOP-8

E-CMOS Corp. (www.ecmos.com.tw)

Page 10 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
General Description
The EC9483 is a 380 KHz fixed frequency
monolithic step down switch mode regulator with a
built in internal Power MOSFET. It achieves 3A
continuous output current over a wide input supply
range with excellent load and line regulation.
The device includes a voltage reference,
oscillation circuit, error amplifier, internal PMOS
and etc.
The PWM control circuit is able to adjust the duty
ratio linearly from 0 to 100%. An enable function,
an over current protection function and a short
c ircu i t protection function are built inside. An
internal compensation block is built in to minimize
external component count.
The EC9483 serves as ideal power supply units
for portable devices.

Features
z
z
z
z
z
z
z
z
z
z
z

3A Constant Output Current


140m RDSON Internal Power PMOSFET
Switch
Up to 95% Efficiency
Fixed 380KHz Frequency
Wide 3.6V to 28V Input Voltage Range
Output Adjustable from 1.222V to 26V
Built in Frequency Compensation
Built in Thermal Shutdown Function
Built in Current Limit Function
SOP8 Package is Available
The minimum dropout up to 0.3V

Applications
z
Portable DVD
z
LCD Monitor / TV
z
Battery Charger
z
ADSL Modem
z
Telecom / Networking Equipment

Function Block

E-CMOS Corp. (www.ecmos.com.tw)

Page 1 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
Pin Description

Pin Assignments

Pin Number

Pin Name

1,6,8

Description

NC

Not Connect

Vin

Supply Voltage Input Pin. EC9483


operates from a 3.6V to 28V DC voltage.
Bypass Vin to GND with a suitably large
capacitor to eliminate noise on the input.

SW

Power Switch Output Pin. SW is the


switch node that supplies power to
the output.

GND

Ground Pin. Care must be taken in layout.


This pin should be placed outside of the
Schottky Diode to output capacitor ground
path to prevent switching current spikes
from inducing voltage noise into EC9483.

FB

Feedback Pin. Through an external


resistor divider network, FB senses the
output voltage and regulates it. The
feedback threshold voltage is 1.222V.

EN

Enable Pin. EN is a digital input that turns


the regulator on or off. Drive EN pin high
to turn on the device, drive it low to turn it
off.

Ordering/ Marking Information

E C 9483 N - F
C ircuit T ype

F: Lead-Free
P ackage: N = S O P 8

Package type

Part Number

Marking

EC9483-F
SOP8

EC9483N-F

E-CMOS Corp. (www.ecmos.com.tw)

YYWW
XXXXXXXX

Page 2 of 10

Marking Information
F is Lead free package.
YY is the year of production. 06 means the
product is manufactured in year of 2006.
WW is the week of production. 25 means the
th
product is manufactured in the 25 week.
XXXXXXXX is Lot number.

2007/04/10

EC9483

EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter

Absolute Maximum Ratings


Parameter

Symbol

Value

Unit

Input Voltage

VIN

-0.3 to 28

Feedback Pin Voltage

VFB

-0.3 to Vin

Enable Pin Voltage

VEN

-0.3 to 12

Switch Pin Voltage

VSW

-0.3 to Vin

Power Dissipation

PD

Operating Junction Temperature

TJ

Internally limited
150

TSTG

Storage Temperature
Lead Temperature (Soldering, 10 sec)
ESD (HBM)

mW
C
C

-65 to 150

TLEAD

260

VESD

2000

Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended Operating Conditions


Parameter

Symbol

Min.

Max.

Unit

VIN

3.6

28

Operating Junction temperature

TJ

-40

125

Operating Ambient Temperature

TA

-40

85

Input Voltage

E-CMOS Corp. (www.ecmos.com.tw)

Page 3 of 10

2007/04/10

EC9483

EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter

Electrical Characteristics
VCC = 12V, Ta = 25 unless otherwise specified.

Parameters
Input voltage
Shutdown Supply Current

Symbol
VIN
ISTBY

Test Condition
VEN=0V

Min.

Typ.

Max.

Unit

3.6

28

30

90

Ua

Supply Current

ICC

VEN=2V, VFB=1.3V

3.6

mA

Feedback Voltage

VFB

VIN = 3.6V to 23V

1.21

1.222

1.26

Feedback Bias Current

IFB

0.1

0.5

uA

Switch Current Limit

ILIM

Oscillator Frequency

FOSC

320

380

440

KHz

Frequency of Current Limit or


Short Circuit Protection

FOSC1

42

KHz

0.7

1.2

1.7

EN Pin Threshold

EN Pin Input Leakage


Current

VEN

VFB=1.3V

VFB=0V

IH

VEN=2.5V

-0.1

-1

uA

IL

VEN=0.5V

-3

-10

uA

80

VIN=12V,VFB=0V

Internal PMOS RDSON

RDSON

VEN=12V, Iout=3A

Max. Duty Cycle

DMAX

VFB=0V, ISW=0.1A

100

VIN=12V,Vout=5V
Iout=3A

92

165

Efficiency
Thermal Shutdown

E-CMOS Corp. (www.ecmos.com.tw)

TOTSD

Page 4 of 10

2007/04/10

EC9483

EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter

Typical Performance Characteristics

Switching Frequency vs. Temperature

Efficiency vs. Load (Vin=10V)

Icc vs. Temperature

E-CMOS Corp. (www.ecmos.com.tw)

VFB vs. Temperature

Page 5 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
Typical Application Circuit
Typical Application Circuit @ 5V/3A

EC9483

Typical Application Circuit @ 3.3V/3A

EC9483

E-CMOS Corp. (www.ecmos.com.tw)

Page 6 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
Typical Application Circuit (Continued)
Typical Application Circuit (with ceramic output capacitor) @ 5V/3A

EC9483

Typical Application Circuit (with ceramic output capacitor) @ 3.3V/3A

EC9483

E-CMOS Corp. (www.ecmos.com.tw)

Page 7 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
Schottky Rectifier Selection Guide
EC9483 Lists some rectifier manufacturers.
3A Load Current

Vin (Max)

20V

30V

Part Number

Vendor

B320

Diodes, Inc.

SK33

Diodes, Inc.

SS32

General Semiconductor

B330

Diodes, Inc.

B340L

Diodes, Inc.

MBRD330

On Semiconductor

SK33

Diodes, Inc.

SS33

General Semiconductor

Output Voltage VS R1, R2 Resistor Selection Guide (Vout = (1+R1/R2)*1.222V)


EC9483 Vout VS. R1, R2 Select Table
Vout

R1

R2

1.8V

3.9K

8.2K

2.5V

3.2K

3K

3.3V

6.2K

3.6K

5V

6.2K

2K

9V

13K

2K

12V

16K

1.8K

E-CMOS Corp. (www.ecmos.com.tw)

Page 8 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
Function Description
VIN
This is the positive input supply for the IC switching regulator. A suitable input bypass capacitor must be present
at this pin to minimize voltage transients and to supply the switching currents needed by the regulator

GND
Circuit ground.

SW
Internal switch. The voltage at this pin switches between (VIN VGS) and approximately 0.5V, with a duty
cycle of approximately VOUT / VIN. To minimize coupling to sensitive circuitry, the PC board copper area
connected to this pin should be kept a minimum.

FB
Senses the regulated output voltage to complete the feedback loop.

EN
Allows the switching regulator circuit to be shutdown using logic level signals thus dropping the total input supply
current to approximately 30uA. Pulling this pin below a threshold voltage of approximately 1.3 V turns the
regulator down, and pulling this pin above 1.3V (up to a maximum of 12V) shuts the regulator on. Forautomatic
starup condition can be implemented by the addition of a resistive voltage divider from VIN to GND.

Thermal Considerations
The SOP8 package needs a heat sink under most conditions. The size of the heat sink depends on the input
voltage, the output voltage, the load current and the ambient temperature. The EC9483 junction temperature
rises above ambient temperature for a 3A load and different input and output voltages. The data for these curves
was taken with the EC9483 (SOP8 package) operating as a buck-switching regulator in an ambient temperature
of 25 C (still air). These temperature rise numbers are all approximate and there are many factors that can affect
these temperatures. Higher ambient temperatures require more heat sinking.
For the best thermal performance, wide copper traces and generous amounts of printed circuit board copper
should be used in the board layout.(Once exception to this is the output (switch) pin, which should not have large
areas of copper.) Large areas of copper provide the best transfer of heat (lower thermal resistance) to the
surrounding air, and moving air lowers the thermal resistance even further.
Package thermal resistance and junction temperature rise numbers are all approximate, and there are many
factors that will affect these numbers. Some of these factors include board size, shape, thickness, position,
location, and even board temperature. Other factors are, trace width, total printed circuit copper area, copper
thickness, single or double-sided, multi-layer board and the amount of solder on the board.
The effectiveness of the PC board to dissipate heat also depends on the size, quantity and spacing of other
components on the board, as well as whether the surrounding air is still or moving. Furthermore, some of these
components such as the catch diode will add heat to the PC board and the heat can vary as the input voltage
changes. For the inductor, depending on the physical size, type of core material and the DC resistance, it could
either act as a heat sink taking heat away from the board, or it could add heat to the board.

E-CMOS Corp. (www.ecmos.com.tw)

Page 9 of 10

2007/04/10

EC9483
EC9483
3A 380KHZ 28V PWM Buck DC/DC Converter
OUTLINE DRAWING FOR SOP8

E-CMOS Corp. (www.ecmos.com.tw)

Page 10 of 10

2007/04/10

INTEGRATED CIRCUITS

DATA SHEET

TDA1517; TDA1517P
2 6 W stereo power amplifier
Product specification
Supersedes data of 1995 Dec 15
File under Integrated Circuits, IC01

1998 Apr 28

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

FEATURES

GENERAL DESCRIPTION

Requires very few external components

The TDA1517 is an integrated class-B dual output


amplifier in a plastic single in-line medium power package
with fin (SIL9MPF) and a plastic heat-dissipating dual
in-line package (HDIP18). The device is primarily
developed for multi-media applications.

High output power


Fixed gain
Good ripple rejection
Mute/standby switch
AC and DC short-circuit safe to ground and VP
Thermally protected
Reverse polarity safe
Capability to handle high energy on outputs (VP = 0 V)
No switch-on/switch-off plop
Electrostatic discharge protection.
QUICK REFERENCE DATA
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VP

supply voltage

6.0

14.4

18.0

IORM

repetitive peak output current

2.5

Iq(tot)

total quiescent current

40

80

mA

Isb

standby current

0.1

100

Isw

switch-on current

40

|ZI|

input impedance

Po

output power

50

RL = 4 ; THD = 0.5%

RL = 4 ; THD = 10%

fi = 100 Hz to 10 kHz

SVRR

supply voltage ripple rejection

48

dB

cs

channel separation

40

dB

Gv

closed loop voltage gain

19

20

21

dB

Vno(rms)

noise output voltage (RMS value)

50

Tc

crystal temperature

150

ORDERING INFORMATION
TYPE
NUMBER
TDA1517
TDA1517P

1998 Apr 28

PACKAGE
NAME
SIL9MPF
HDIP18

DESCRIPTION

VERSION

plastic single in-line medium power package with fin; 9 leads

SOT110-1

plastic heat-dissipating dual in-line package; 18 leads

SOT398-1

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

BLOCK DIAGRAM

handbook, full pagewidth

non-inverting
input 1

mute switch

Cm

60
k
4
VA

output 1

2
k
power stage

18 k

VP
8
stand-by
switch

mute/stand-by
switch input

stand-by
reference
voltage

VA
15 k
x1
supply voltage
ripple rejection
output

mute
switch

3
15 k
mute
reference
voltage

TDA1517

18 k

2
k
non-inverting
input 2

VA
9
60
k
input
reference
voltage

mute switch

Cm
power stage

signal
ground
2

power
ground
5 (substrate)

MLC351

VP

SGND

PGND

Fig.1 Block diagram.

1998 Apr 28

output 2

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

PINNING
SYMBOL

PIN

DESCRIPTION

INV1

non-inverting input 1

SGND

signal ground

SVRR

supply voltage ripple rejection output

OUT1

output 1

PGND

power ground

OUT2

output 2

VP

supply voltage

M/SS

mute/standby switch input

INV2

non-inverting input 2

ndbook, halfpage

INV1

SGND

ndbook, halfpage

INV1

18

SGND

17

SVRR

SVRR

16

OUT1

OUT1

15

PGND

PGND

OUT2

OUT2

13

VP

VP

12

M/SS

M/SS

11

INV2

INV2

10

TDA1517

MLC352

TDA1517P

14

MLC353

Pins 10 to 18 should be connected to GND or floating.

Fig.2 Pin configuration for SOT110-1.

Fig.3 Pin configuration for SOT398-1.

FUNCTIONAL DESCRIPTION
The TDA1517 contains two identical amplifiers with
differential input stages. The gain of each amplifier is fixed
at 20 dB. A special feature of the device is the
mute/standby switch which has the following features:
Low standby current (<100 A)
Low mute/standby switching current
(low cost supply switch)
Mute condition.
1998 Apr 28

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VP

supply voltage

18

VP(sc)

AC and DC short-circuit safe voltage

18

VP(r)

reverse polarity

ERGO

energy handling capability at outputs

200

mJ

IOSM

non-repetitive peak output current

IORM

repetitive peak output current

2.5

Ptot

total power dissipation

15

Tstg

storage temperature

55

+150

Tamb

operating ambient temperature

40

+85

Tc

crystal temperature

150

VP = 0 V

see Fig.4

THERMAL RESISTANCE
SYMBOL

TYPE NUMBER

PARAMETER

VALUE

UNIT

Rth j-c

TDA1517

thermal resistance from junction to case

K/W

Rth j-p

TDA1517P

thermal resistance from junction to pins

15

K/W

Rth j-a

TDA1517; TDA1517P thermal resistance from junction to ambient 50

K/W

MLC354

18

handbook, halfpage

P
(W)
12
(1)

(2)
6

0
25

50

100
150
o
T amb ( C)

(1) Rth j-c = 8 K/W.


(2) Rth j-p = 15 K/W.

Fig.4 Power derating curve.

1998 Apr 28

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

DC CHARACTERISTICS
VP = 14.4 V; Tamb = 25 C; measured in Fig.6; unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply
VP

supply voltage

6.0

14.4

18.0

Iq(tot)

total quiescent current

note 1

40

80

mA

VO

DC output voltage

6.95

see Fig.5

8.5

VI(max) = 1 V; fi = 20 Hz to 15 kHz

mV

Mute/standby switch
V8

switch-on voltage level

Mute condition
VO

output signal in mute position

Standby condition
Isb

DC current in standby condition

100

Vsw

switch-on current

12

40

Note
1. The circuit is DC adjusted at VP = 6 to 18 V and AC operating at VP = 8.5 to 18 V.

1998 Apr 28

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

AC CHARACTERISTICS
VP = 14.4 V; RL = 4 ; f = 1 kHz; Tamb = 25 C; measured in Fig.6; unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Po

output power

THD = 10%; note 1

5.5

6.0

THD

total harmonic distortion

Po = 1 W

0.1

flr

low frequency roll-off

at 3 dB; note 2

45

Hz

at 1 dB

20

kHz

19

20

21

dB

on

48

dB

mute

48

dB

standby

80

dB

50

60

75

fhr

high frequency roll-off

Gv

closed loop voltage gain

SVRR

supply voltage ripple rejection

|Zi|

input impedance

Vno

noise output voltage

THD = 0.5%; note 1

note 3

on

Rs = 0 ; note 4

50

on

Rs = 10 ; note 4

70

100

note 5

50

Rs = 10

40

dB

0.1

dB

mute
cs

channel separation

|Gv|

channel unbalance

Notes
1. Output power is measured directly at the output pins of the IC.
2. Frequency response externally fixed.
3. Ripple rejection measured at the output with a source impedance of 0 , maximum ripple amplitude of 2 V (p-p) and
a frequency between 100 Hz and 10 kHz.
4. Noise voltage measured in a bandwidth of 20 Hz to 20 kHz.
5. Noise output voltage independent of Rs (VI = 0 V).

1998 Apr 28

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
MLC355

handbook, halfpage

18
V11
(V)

TDA1517; TDA1517P

ON (IP = 40 mA)

8.5
6.4

mute (IP = 40 mA)

3.3
2

standby (I P

100 A)

Fig.5 Standby, mute and on conditions.

APPLICATION INFORMATION

standby switch

handbook, full pagewidth

VP

100
F

100 nF

3
input
reference
voltage

2200
F

internal
1/2 V P

TDA1517
220 nF
input 1

20 dB

60 k

20 dB

60 k
9

MLC356

signal
ground

power
ground

1000 F

1000 F

Fig.6 Application circuit diagram.

1998 Apr 28

220 nF
input 2

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

PACKAGE OUTLINES
SIL9MPF: plastic single in-line medium power package with fin; 9 leads

SOT110-1

D1
q
P

A2

P1

A3
q1

q2

A
A4
seating plane

E
pin 1 index

L
1

9
b

b2

w M

b1

10 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A2
max.

A3

A4

b1

b2

D (1)

D1

E (1)

P1

q1

q2

Z (1)
max.

mm

18.5
17.8

3.7

8.7
8.0

15.8
15.4

1.40
1.14

0.67
0.50

1.40
1.14

0.48
0.38

21.8
21.4

21.4
20.7

6.48
6.20

2.54

3.9
3.4

2.75
2.50

3.4
3.2

1.75
1.55

15.1
14.9

4.4
4.2

5.9
5.7

0.25

1.0

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION

REFERENCES
IEC

JEDEC

EIAJ

ISSUE DATE
92-11-17
95-02-25

SOT110-1

1998 Apr 28

EUROPEAN
PROJECTION

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P

HDIP18: plastic heat-dissipating dual in-line package; 18 leads

SOT398-1

D
seating plane

ME

A2

A1
L

w M

b1

(e 1)

b2

b
10

18

MH

pin 1 index
E

10 mm

scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT

A
max.

A1
min.

A2
max.

b1

b2

D (1)

E (1)

e1

ME

MH

Z (1)
max.

mm

4.7

0.51

3.7

1.40
1.14

0.67
0.50

1.05
0.75

0.47
0.38

21.85
21.35

6.5
6.2

2.54

7.62

3.9
3.1

8.32
8.02

8.7
7.7

0.25

1.0

inches

0.19

0.02

0.15

0.06
0.04

0.03
0.02

0.04
0.03

0.02
0.01

0.87
0.84

0.26
0.24

0.10

0.30

0.15
0.12

0.33
0.32

0.34
0.30

0.01

0.04

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION

REFERENCES
IEC

JEDEC

EIAJ

ISSUE DATE
94-04-13
95-01-25

SOT398-1

1998 Apr 28

EUROPEAN
PROJECTION

10

Philips Semiconductors

Product specification

2 6 W stereo power amplifier

TDA1517; TDA1517P
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

The device may be mounted up to the seating plane, but


the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints

This text gives a very brief insight to a complex technology.


A more in-depth account of soldering ICs can be found in
our Data Handbook IC26; Integrated Circuit Packages
(order code 9398 652 90011).

Apply a low voltage soldering iron (less than 24 V) to the


lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 C, contact may be up to 5 seconds.

Soldering by dipping or by wave


The maximum permissible temperature of the solder is
260 C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Apr 28

11

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


LOW DROP FIXED AND
ADJUSTABLE POSITIVE VOLTAGE
REGULATORS

2 1

SOT-223

DESCRIPTION
The UTC LD1117/A is a LOW DROP Voltage Regulator
able to provide up to 0.8/1.0A of Output Current, available
even in adjustable version (Vref=1.25V). Concerning fixed
versions, are offered the following Output Voltages: 1.8V,
2.5V, 2.85V, 3.0V, 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is supplied in:
SOT-223, TO-252, TO-263, TO-263-3, SOP-8 and TO-220.
The SOT-223, TO-263, TO-263-3 and TO-252 surface mount
packages optimize the thermal characteristics even offering a
relevant space saving effect. High efficiency is assured by
NPN pass transistor. In fact in the case, unlike than PNP one,
the Quiescent Current flows mostly into the load. Only a very
common 10F minimum capacitor is needed for stability. On
chip trimming allows the regulator to reach a very tight output
voltage tolerance, within 1% at 25C. The ADJUSTABLE
LD1117/A is pin to pin compatible with the other standard
Adjustable voltage regulators maintaining the better
performances in terms of Drop and Tolerance.

SOP-8

1
1

TO-220

TO-252

TO-263
SOP-8

1: GND;
4: Vin;

TO-263-3

2,3,6,7: Vout;
5,8: NC

FEATURES
*Low dropout voltage (1V Typ.)
*2.85V device performances are suitable for SCSI-2 active
termination
*Output current up to 0.8/1.0A
*Fixed output voltage of: 1.8V,2.5V, 2,85V, 3.0V, 3.3V, 5.0V
*Adjustable version availability (Vref=1.25V)
*Internal current and thermal limit
*Available in 1%(at 25C) and 2% in all temperature range
*Supply voltage rejection: 75dB (TYP)
*Temperature range: 0C to 125C

UTC

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


MARKING INFORMATION
PACKAGE

VOLTAGE PIN CODE PIN 1

PIN 2

PIN 3

MARKING

CODE
18:1.8V

GND

OUT

IN

OUT

GND

IN

CURRENT
CODE
VOLTAGE
CODE

25:2.5V
SOT-223

28:2.85V
30:3.0V

GND

IN

OUT

IN

GND

OUT

GND

OUT

IN

OUT

GND

IN

GND

IN

OUT

IN

GND

OUT

33:3.3V
50:5.0V
AD:ADJ

TO-263
TO-263-3

PIN CODE
DATE
CODE

UTC
LD1117

TO-220
TO-252

LD1117

CURRENT
CODE
PIN CODE

VOLTAGE
CODE

DATE
CODE

Note: The current code A means output current up to 1.0A, while without A means output current up to 0.8A.

UTC

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS


PARAMETER

SYMBOL

VALUE

UNIT

DC Input Voltage
VIN
15
V
Power Dissipation
Ptot
12
W
Storage temperature
Tstg
-65 ~ +150
C
Operating Junction
Top
0 ~ +125
C
Temperature
Note: Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional
operation under there condition is not implied. Over the above suggested Max Power Dissipation a Short Circuit
could definitively damage the device.

THERMAL DATA
PARAMETER

SYMBOL

Thermal Resistance Junction-case


SOT-223
SOP-8
TO-252
TO-220
TO-263
Thermal Resistance Junction-ambient
TO-220

Rth-case

UTC

VALUE

UNIT

15
20
8
3
3

C/W
C/W
C/W
C/W
C/W

50

C/W

Rthj-amb

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


APPLICATION CIRCUIT

LD1117/A

UTC LD1117/A-1.8 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

Output Voltage
Output Voltage
Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current
Output Noise Voltage
Supply Voltage
Rejection
Dropout Voltage

Vo
Vo
Vo
Vo
Vo
Vo
Vin
Id
Io
eN
SVR
Vd

Thermal Regulation

TEST CONDITIONS
Vin=3.8V, Io=10mA, Tj=25C
Io=0 to 800/1000mA, Vin=3.3 to 8V
Vin=3.3 to 8V, Io=0mA
Vin=3.3V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin8V
Vin=6.8V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=5.5V,
Vripple=1Vpp
Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

MIN.

TYP.

MAX.

UNIT

1.780
1.760

1.800

1.820
1.840
6
10

V
V
mV
mV
%
%
V
mA
mA
V
dB

1
1
0.5
0.3

800
60

5
950
100
75

10
10
1200

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

MIN.

TYP.

MAX.

UNIT

2.475
2.450
2.450
2.400

2.500
2.500

2.525
2.550
2.550
2.600
6
10

V
V
V
V
mV
mV
%
%
V
mA
mA

UTC LD1117/A-2.5 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

TEST CONDITIONS

Output Voltage

Vo

Vin=4.5V, Io=10mA, Tj=25C

Output Voltage

Vo

Io=0 to 800/1000mA,
Vin=3.9 to 10V

Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current

UTC

Vo
Vo
Vo
Vo
Vin
Id
Io

1%
2%
2%
4%

Vin=3.9 to 10V, Io=0mA


Vin=3.9V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin10V
Vin=7.5V, Tj=25C

1
1
0.5
0.3

800

5
950

15
10
1200

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


PARAMETER

SYMBOL

Output Noise Voltage


Supply Voltage
Rejection
Dropout Voltage

eN
SVR
Vd

Thermal Regulation

TEST CONDITIONS
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=5.5V,
Vripple=1Vpp
Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

MIN.

TYP.

60

100
75

MAX.

UNIT
V
dB

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

MIN.

TYP.

MAX.

UNIT

2.82
2.79

2.85

2.88
2.91
6
10

V
V
mV
mV
%
%
V
mA
mA
V
DB

UTC LD1117/A-2.85 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

Output Voltage
Output Voltage
Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current
Output Noise Voltage
Supply Voltage
Rejection
Dropout Voltage

Vo
Vo
Vo
Vo
Vo
Vo
Vin
Id
Io
eN
SVR
Vd

Thermal Regulation

TEST CONDITIONS
Vin=4.85V, Io=10mA, Tj=25C
Io=0 to 800/1000mA,Vin=4.25 to 10V
Vin=4.25 to 10V, Io=0mA
Vin=4.25V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin10V
Vin=7.85V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=5.85V,
Vripple=1Vpp
Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

1
1
0.5
0.3

800
60

5
950
100
75

15
10
1200

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

MIN.

TYP.

MAX.

UNIT

2.97
2.94
2.94
2.88

3.00
3.00

3.03
3.06
3.06
3.12
6
10

V
V
V
V
mV
mV
%
%
V
mA
mA
V
dB

UTC LD1117/A-3.0 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

TEST CONDITIONS

Output Voltage

Vo

Vin=5V, Io=10mA, Tj=25C

Output Voltage

Vo

Io=0 to 800/1000mA,
Vin=4.5 to 10V

Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current
Output Noise Voltage
Supply Voltage
Rejection

UTC

Vo
Vo
Vo
Vo
Vin
Id
Io
eN
SVR

1%
2%
2%
4%

Vin=4.5 to 12V, Io=0mA


Vin=4.5V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin12V
Vin=8V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=6V,
Vripple=1Vpp

1
1
0.5
0.3

800
60

5
950
100
75

15
10
1200

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


PARAMETER

SYMBOL

Dropout Voltage

Vd

Thermal Regulation

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

MIN.

TYP.

MAX.

UNIT

3.267
3.235
3.235
3.160

3.300
3.300

3.333
3.365
3.365
3.440
6
10

V
V
V
V
mV
mV
%
%
V
mA
mA
V
DB

Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

UTC LD1117/A-3.3 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

TEST CONDITIONS

Output Voltage

Vo

Vin=5.3V, Io=10mA, Tj=25C

Output Voltage

Vo

Io=0 to 800/1000mA,
Vin=4.75 to 10V

Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current
Output Noise Voltage
Supply Voltage
Rejection
Dropout Voltage

Vo
Vo
Vo
Vo
Vin
Id
Io
eN
SVR
Vd

Thermal Regulation

1%
2%
2%
4%

Vin=4.75 to 15V, Io=0mA


Vin=4.75V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin15V
Vin=8.3V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=6.3V,
Vripple=1Vpp
Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

1
1
0.5
0.3

800
60

5
950
100
75

15
10
1200

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

MIN.

TYP.

MAX.

UNIT

4.95
4.90
4.90
4.80

5.00
5.00

5.05
5.10
5.10
5.20
10
15

V
V
V
V
mV
mV
%
%
V
mA
mA
V
dB

UTC LD1117/A-5.0 ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

TEST CONDITIONS

Output Voltage

Vo

Vin=7V, Io=10mA, Tj=25C

Output Voltage

Vo

Io=0 to 800/1000mA,
Vin=6.5 to 15V

Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Quiescent Current
Output Current
Output Noise Voltage
Supply Voltage
Rejection

UTC

Vo
Vo
Vo
Vo
Vin
Id
Io
eN
SVR

1%
2%
2%
4%

Vin=6.5 to 15V, Io=0mA


Vin=6.5V, Io=0 to 800/1000mA
1000 hrs, Tj=125C
Io=100mA
Vin15V
Vin=10V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C, Vin=8V,
Vripple=1Vpp

1
1
0.5
0.3

800
60

5
950
100
75

15
10
1200

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


PARAMETER

SYMBOL

Dropout Voltage

Vd

Thermal Regulation

TEST CONDITIONS

MIN.

Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

TYP.

MAX.

UNIT

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

UTC LD1117/A-ADJUSTABLE ELECTRICAL CHARACTERISTICS


(refer to the test circuits, Tj=0 to 125C, Co=10F unless otherwise specified)

PARAMETER

SYMBOL

Reference Voltage
Reference Voltage

Vref
Vref

Line Regulation
Load Regulation
Temperature stability
Long Term Stability
Operating Input Voltage
Adjustment Pin Current
Adjustment Pin Current
Change
Minimum Load Current
Output Current
Output Noise (%Vo)
Supply Voltage
Rejection
Dropout Voltage

Vo
Vo
Vo
Vo
Vin
Iadj
Iadj
Io(min)
Io
eN
SVR
Vd

Thermal Regulation

TEST CONDITIONS
Vin-VO=2V, Io=10mA, Tj=25C
Io=10 to 800/1000mA, Vin-Vo=1.4 to
10V
Vin-Vo=1.5 to 13.75V, Io=10mA
Vin-Vo=3V, Io=10 to 800/1000mA

MIN.

TYP.

MAX.

UNIT

1.238
1.225

1.25

1.262
1.275

V
V

0.035
0.10
0.50
0.3

0.200
0.400

%
%
%
%
V
A
A

1000 hrs, Tj=125C


Vin15V
Vin-Vo=1.4 to 10V,
Io=10 to 800/1000mA
Vin=15V
Vin-Vo=5V, Tj=25C
B=10Hz to 10KHz, Tj=25C
Io=40mA, f=120Hz, Tj=25C,
Vin-Vo=3V, Vripple=1Vpp
Io=100mA
Io=500mA
Io=800mA
Io=1000mA
Ta=25C, 30ms Pulse

60
1

800
60

15
120
5

2
950
0.003
75

5
1200

mA
mA
%
dB

1.00
1.05
1.10
1.15
0.01

1.10
1.15
1.20
1.25
0.10

V
V
V
V
%/W

TYPICAL APPLICATIONS

FIG.1 Negative Supply

UTC

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT

FIG.2 Active Terminator for SCSI-2 BUS

FIG.3 Circuit for Increasing Output Voltage

UTC

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT

FIG.4 Voltage Regulator With Reference

FIG.5 Battery Backed-up Regulated Supply

UTC

UNISONIC TECHNOLOGIES CO., LTD.

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


FEEDBACK PATH

FIG.6 Post-Regulated Dual Supply

UTC

UNISONIC TECHNOLOGIES CO., LTD.

10

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


LD1117/A ADJUSTABLE APPLICATION NOTE
The LD1117/A ADJUSTABLE has a thermal stabilized 1.250.012V reference voltage between the OUT and ADJ
pins. IADJ is 60A typ. (120A max.) and IADJ is 1A typ. (5A max.).
R1 is normally fixed to 120. From figure 7 we obtain:
VOUT=VREF+R2(IADJ + IR1)=VREF + R2(IADJ + VREF / R1)=VREF(1+R2/R1) + R2 x IADJ.
In normal application R2 value is in the range of few Kohm,, so the R2 X IADJ product could not be considered in the
VOUT calculation; then the above expression becomes: VOUT=VREF(1+R2/R1)
In order to have the better load regulation it is important to realize a good Kelvin connection of R1 and R2 resistors.
In particular R1 connection must be realized very close to OUT and ADJ pin, while R2 ground connection must be
placed as near as possible to the negative Load pin. Ripple rejection can be improved by introducing a 10F
electrolytic capacitor placed in parallel to the R2 resistor (See Fig. 8)

FIG.7 Adjustable Output Voltage Application Circuit

FIG.8 Adjustable Output Voltage Application with improved Ripple Rejection.

UTC

UNISONIC TECHNOLOGIES CO., LTD.

11

QW-R102-006,H

UTC LD1117/A LINEAR INTEGRATED CIRCUIT


TYPICAL CHARACTERISTICS
Fig.2 Output Voltage vs.
Temperautre

Fig.1 Reference Voltge vs.


Temperature
3.70

1.245

3.65

1.240

3.60

Output Voltage(V)

reference voltage (V)

1.250

1.235
1.230
1.225
1.220
1.215

3.50
3.45
3.40
3.35
3.30

1.205

3.25

1.200
-75 -50 -25

3.20
0

25

50

75 100 125 150 175

Vout=3.6V

3.55

1.210

Junction Temperature(C)

VOUT SET WITH 1% RESISTORS

-75

Vout=3.3V
Note: LD1117 Only
-50 -25

25

50 75

100 125 150 175

Junction Temperature(C)

Fig.3 Maximum Power Dissipation


10

Power (W)

TO-263 & TO-252


6

SOT-223
2

0
25

45

65

85

105

125

Case Temperature(C)

UTC

UNISONIC TECHNOLOGIES CO., LTD.

12

QW-R102-006,H

NIKO-SEM

L1084

5A Adjustable Low Dropout


Linear Regulator (LDO)

TO-252, 263, 220

GENERAL DESCRIPTION

FEATURES

The L1084 is a positive and low dropout


three-terminal voltage regulator with 5A output current capability. This device is designed for use in low voltage applications that
offers lower dropout voltage and faster transient response.

z Very easy to use, it requires only two


external resistors to set the output voltage
z Low dropout voltage:
1.2V typical at up to 5A
z Low ground current
z Fast transient response
z Current & thermal limiting
z Line regulation: 0.5% typical
z Load regulation: 0.5% typical
z TO-220, TO-263 and TO-252 packages

This device is fully protected against over


current faults, over temperature operation,
reversed input polarity, reversed lead insertion, transient voltage spike etc.
On-Chips trimming the reference voltage to
1% and features the low dropout of maximum 1.45 volts.

APPLICATIONS
z High current microprocessor supplies
z Low voltage logic supply
z Powering VGA & sound card
z Portable instrumentation
z Constant current regulator
z Post regulator for switching power supply

The L1084 Series regulators are available


in the popular industry standard TO-220,
TO-263 and TO-252 packages.

TYPICAL APPLICATION

Vin

Vout

L1084
IN

OUT
ADJ

Cin

Vref

R1

10uF

Cout
10uF

R2

Iadj

Vo = Vref (1+R2/R1) + Iadj x R2


1. Cin needed if device is far from from filter capacitors.
2. Cout required for stability.
- Basic Adjustable Regulator Circuit -

MAY-31-2001

NIKO-SEM

L1084

5A Adjustable Low Dropout


Linear Regulator (LDO)

TO-252, 263, 220

ABSOLUTE MAXIMUM RATINGS


z Maximum Supply Voltage

7V
Internally
Limited

z Power Dissipation
z Thermal Resistance
Junction to Case, JC
z Thermal Resistance
Junction to Ambient, JA
TO-220
TO-263
TO-252

2.5 C/W

z Operating Junction
Temperature Range
z Storage Temperature
Range
z Lead Temperature
(Soldering, 10 Seconds)

0 to 125 C
-40 to 150 C
260 C

50 C/W
60 C/W
70 C/W

ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = 25 C.)


Parameter
Reference Voltage
Dropout Voltage
Line Regulation
Load Regulation
Minimum Load
Current

Symbol
VREF

Test Conditions

Typical

VIN = 5V, IOUT = 10mA

1.25V

VD
VREF = 1%, IOUT = 5A
REG(LINE) (VOUT + 1.5V) VIN 7V, IOUT = 10mA
REG(LOAD) (VIN -VOUT) = 3V, 10mA IOUT 5A

1.2V
0.5%
0.5%

1.5V (VIN -VOUT) 5.75V

10mA

IO

Adjust Pin Current


Current Limit

IADJ
ICL

RMS Output Noise

VN

Ripple Rejection
Ratio

RA

VIN - VOUT = 2V

f = 120Hz, CADJ = 22F for ADJ pin,


VIN = 5V, IOUT = 5A

Limits
1.23VMin
1.27VMax
1.45V
2%
2.5%

55A
7.5A
0.003%
of VOUT

100A
5.0A (Min)

72dB

60dB (Min)

DEVICE SELECTION GUIDE


Device

L1084D

L1084S

L1084S3

L1084T

Package

TO-252

TO-263 (2-Lead)

TO-263 (3-Lead)

TO-220

Marking

L1084D

L1084S

L1084S3

L1084T

MAY-31-2001

NIKO-SEM

5A Adjustable Low Dropout


Linear Regulator (LDO)

L1084
TO-252, 263, 220

Typical Performance Characteristics

Vout=3.3V,Vin=5V,Iout=105mA/5A
Cin=10F,Cout=10F

MAY-31-2001

NIKO-SEM

5A Adjustable Low Dropout


Linear Regulator (LDO)

L1084
TO-252, 263, 220

PIN CONFIGURATIONS

Pin #

Function

Adjust

Output

Input

Note: TAB is Output Pin

MAY-31-2001

NIKO-SEM

5A Adjustable Low Dropout


Linear Regulator (LDO)

L1084
TO-252, 263, 220

TO-263 (D2PAK) MECHANICAL DATA


mm
Dimension

mm

Min.

Typ.

Max.

14.5

15

15.8

4.2

1.20

Dimension

Min.

Typ.

Max.

1.0

1.5

1.8

4.7

9.8

1.35

6.5

1.5

2.8

0.3

-0.102

8.5

0.4
9

0.5

0.7

0.203

4.83

9.5

10.3

1.4
5.08

5.33

MAY-31-2001

NIKO-SEM

L1084

5A Adjustable Low Dropout


Linear Regulator (LDO)

TO-252, 263, 220

TO-263 (D2PAK) MECHANICAL DATA


mm
Dimension

mm

Min.

Typ.

Max.

14.5

15

15.8

4.2

1.20

Dimension

Min.

Typ.

Max.

1.0

1.5

1.8

4.7

9.8

1.35

6.5

1.5

2.8

0.3

-0.102

8.5

0.4
9

0.5

0.7

0.203

4.83

9.5

10.3

1.4
5.08

5.33

MAY-31-2001

NIKO-SEM

L1084

5A Adjustable Low Dropout


Linear Regulator (LDO)

TO-252, 263, 220

TO-220 (3-Lead) MECHANICAL DATA


mm
Dimension

mm

Min.

Typ.

Max.

9.78

10.16

10.54

2.61

2.74

2.87

Dimension

20

Min.

Typ.

Max.

2.4

2.54

2.68

1.19

1.27

1.35

4.4

4.6

4.8

28.5

28.9

29.3

1.14

1.27

1.4

14.6

15.0

15.4

2.3

2.6

2.9

8.4

8.8

9.2

0.26

0.46

0.66

0.72

0.8

0.88

MAY-31-2001

NIKO-SEM

L1084

5A Adjustable Low Dropout


Linear Regulator (LDO)

TO-252, 263, 220

TO-252 (DPAK) MECHANICAL DATA


mm
Dimension

Min.

Typ.

mm
Max.

Dimension

Min.

Typ.

Max.

9.35

10.1

2.2

2.4

6.4

6.6

0.48

0.6

5.2

5.4

0.89

1.5

0.6

0.45

0.6

0.64

0.9

0.03

0.23

4.4

4.6

6.2

0.8

MAY-31-2001

Features
Low-voltage and Standard-voltage Operation

2.7 (VCC = 2.7V to 5.5V)


1.8 (VCC = 1.8V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead
SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Two-wire
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)

Description

16K (2048 x 8)

The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial


electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead Ultra Th in Mini-MAP (MLP 2 x3) , 5-lead SOT23
(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is
accessed via a Two-wire serial interface. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
8-lead TSSOP

Table 1. Pin Configuration


Pin Name

Function

A0 - A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

NC

No Connect

GND

Ground

VCC

Power Supply

A0
A1
A2
GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA

8-ball dBGA2
VCC
WP
SCL
SDA

A0
A1
A2
GND

Bottom View

8-lead SOIC
A0
A1
A2
GND

1
2
3
4

VCC
WP
SCL
SDA

8
7
6
5

8-lead Ultra Thin Mini-MAP


(MLP 2x3)
VCC
WP
SCL
SDA

8
7
6
5

1
2
3
4

AT24C01A
AT24C02(1)
AT24C04
AT24C08A
AT24C16A
Note:

1. Not Recommended for


new design; Please
refer
to
24C02B
datasheet.

A0
A1
A2
GND

Bottom View

8-lead PDIP

5-lead SOT23
A0
A1
A2
GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA

SCL

GND

SDA

WP

VCC

0180YSEEPR2/06

Absolute Maximum Ratings


Operating Temperature..................................55C to +125C
Storage Temperature .....................................65C to +150C
Voltage on Any Pin
with Respect to Ground .................................... 1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V

*NOTICE:

Stresses beyond those listed under Absolute


Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect and can
be connected to ground.
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no connects
and can be connected to ground.
The AT24C16A does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be
connected to ground.
WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal Read/Write
operations when connected to ground (GND). When the Write Protect pin is connected
to VCC, the write protection feature is enabled and operates as shown in Table 2.
Table 2. Write Protect
WP Pin
Status

Memory Organization

Part of the Array Protected


24C01A

24C02

At VCC

Full (1K)
Array

Full (2K)
Array

At GND

Normal Read/Write Operations

24C04
Full (4K)
Array

24C08A
Full (8K)
Array

24C16A
Full (16K)
Array

AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,


the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.
AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.
AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.

3
0180YSEEPR2/06

Table 3. Pin Capacitance(1)


Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V
Symbol

Test Condition

CI/O
CIN
Note:

Max

Units

Conditions

Input/Output Capacitance (SDA)

pF

VI/O = 0V

Input Capacitance (A0, A1, A2, SCL)

pF

VIN = 0V

1. This parameter is characterized and is not 100% tested.

Table 4. DC Characteristics
Applicable over recommended operating range from: TAI = 40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V
(unless otherwise noted)
Symbol

Parameter

VCC1

Supply Voltage

VCC2

Max

Units

1.8

5.5

Supply Voltage

2.7

5.5

VCC3

Supply Voltage

4.5

5.5

ICC

Supply Current VCC = 5.0V

READ at 100 kHz

0.4

1.0

mA

ICC

Supply Current VCC = 5.0V

WRITE at 100 kHz

2.0

3.0

mA

ISB1

Standby Current VCC = 1.8V

VIN = VCC or VSS

0.6

3.0

ISB2

Standby Current VCC = 2.5V

VIN = VCC or VSS

1.4

4.0

ISB3

Standby Current VCC = 2.7V

VIN = VCC or VSS

1.6

4.0

ISB4

Standby Current VCC = 5.0V

VIN = VCC or VSS

8.0

18.0

ILI

Input Leakage Current

VIN = VCC or VSS

0.10

3.0

ILO

Output Leakage Current

VOUT = VCC or VSS

0.05

3.0

VIL

Input Low Level(1)

0.6

VCC x 0.3

VIH

Input High Level(1)

VCC x 0.7

VCC + 0.5

VOL2

Output Low Level VCC = 3.0V

IOL = 2.1 mA

0.4

VOL1

Output Low Level VCC = 1.8V

IOL = 0.15 mA

0.2

Note:

Test Condition

Min

Typ

1. VIL min and VIH max are reference only and are not tested.

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
Table 5. AC Characteristics
Applicable over recommended operating range from TAI = 40C to +85C, VCC = +1.8V to +5.5V, VCC = +2.7V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
1.8-volt
Symbol

Parameter

fSCL

Clock Frequency, SCL

tLOW

Clock Pulse Width Low

tHIGH

Clock Pulse Width High

Min

2.7, 5.0-volt

Max

Min

100

Max

Units

400

kHz

4.7

1.2

4.0

0.6

(1)

tI

Noise Suppression Time

tAA

Clock Low to Data Out Valid

0.1

tBUF

Time the bus must be free before


a new transmission can start(1)

4.7

1.2

tHD.STA

Start Hold Time

4.0

0.6

tSU.STA

Start Setup Time

4.7

0.6

tHD.DAT

Data In Hold Time

tSU.DAT

Data In Setup Time

200

100

ns

tR

Inputs Rise Time(1)

1.0

0.3

tF

Inputs Fall Time(1)

300

300

ns

tSU.STO

Stop Setup Time

4.7

0.6

tDH

Data Out Hold Time

100

50

ns

tWR

Write Cycle Time

Endurance(1)

5.0V, 25C, Byte Mode

Note:

100
4.5

0.1

5
1M

50

ns

0.9

5
1M

ms
Write
Cycles

1. This parameter is characterized.

5
0180YSEEPR2/06

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing


Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA

8th BIT

ACK

WORDn
twr
STOP
CONDITION

Note:

(1)

START
CONDITION

1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

7
0180YSEEPR2/06

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
Device Addressing

The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation (refer to Figure
7).
The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices
should be considered the most significant bits of the data word address which follows.
The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR , to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 11).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K
and 16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (see Figure 9 on page 11).
The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
incremented following the receipt of each data word. The higher data word address bits
are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data
words are transmitted to the EEPROM, the data word address will roll over and previous data will be overwritten.

9
0180YSEEPR2/06

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero allowing the read or write sequence to continue.

Read
Operations

Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address roll
over during read is from the last byte of the last memory page to the first byte of the first page.
The address roll over during write is from the last byte of the current page to the first byte of
the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 12).
RANDOM READ: A random read requires a dummy byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 12 on page 12).

10

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A

Figure 7. Device Address

MSB

8K
16K

Figure 8. Byte Write

Figure 9. Page Write

(* = DONT CARE bit for 1K)

11
0180YSEEPR2/06

Figure 10. Current Address Read

Figure 11. Random Read

(* = DONT CARE bit for 1K)


Figure 12. Sequential Read

12

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
AT24C01A Ordering Information(1)
Ordering Code

Package

AT24C01A-10PU-2.7(2)
AT24C01A-10PU-1.8(2)
AT24C01A-10SU-2.7(2)
AT24C01A-10SU-1.8(2)
AT24C01A-10TU-2.7(2)
AT24C01A-10TU-1.8(2)
AT24C01A-10TSU-1.8(2)
AT24C01AU3-10UU-1.8(2)
AT24C01AY1-10YU-1.8(2) (Not recommended for new design)
AT24C01AY6-10YH-1.8(3)

8P3
8P3
8S1
8S1
8A2
8A2
5TS1
8U31
8Y1
8Y6

AT24C01A-W1.8-11(4)

Die Sale

Notes:

1.
2.
3.
4.

Operation Range

Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)

Industrial Temperature
(40C to 85C)

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
U designates Green Package + RoHS compliant.
H designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.

Package Type
8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2

8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y1

8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

8Y6

8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)

5TS1

5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1

8-ball, die Ball Grid Away Package (dBGA2)


Options

2.7

Low-voltage (2.7V to 5.5V)

1.8

Low-voltage (1.8V to 5.5V)

13
0180YSEEPR2/06

AT24C02 Ordering Information(1)


Ordering Code

Package
(2)

AT24C02-10PU-2.7
AT24C02-10PU-1.8(2)
AT24C02N-10SU-2.7(2)
AT24C02N-10SU-1.8(2)
AT24C02-10TU-2.7(2)
AT24C02-10TU-1.8(2)
AT24C02Y1-10YU-1.8(2)
AT24C02-10TSU-1.8(2)
AT24C02U3-10UU-1.8(2)

8P3
8P3
8S1
8S1
8A2
8A2
8Y1
5TS1
8U3-1

AT24C02-W2.7-11(3)

Die Sale

Notes:

Operation Range

Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)

Industrial Temperature
(40C to 85C)

1. This device is not recommended for new design. Please refer to AT24C02B datasheet. For 2.7V devices used in the 4.5V to
5.5V range, please refer to performance values in the AC and DC characteristics table.
2. U designates Green Package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM Marketing.

Package Type
8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2

8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y1

8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

5TS1

5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1

8-ball, die Ball Grid Away Package (dBGA2)


Options

2.7

Low-voltage (2.7V to 5.5V)

1.8

Low-voltage (1.8V to 5.5V)

14

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
AT24C04 Ordering Information(1)
Ordering Code

Package
(2)

AT24C04-10PU-2.7
AT24C04-10PU-1.8(2)
AT24C04N-10SU-2.7(2)
AT24C04N-10SU-1.8(2)
AT24C04-10TU-2.7(2)
AT24C04-10TU-1.8(2)
AT24C04Y1-10YU-1.8(2) (Not recommended for new design)
AT24C04Y6-10YH-1.8(3)
AT24C04-10TSU-1.8(2)
AT24C04U3-10UU-1.8(2)

8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
5TS1
8U3-1

AT24C04-W1.8-11(4)

Die Sale

Notes:

1.
2.
3.
4.

Operation Range

Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)

Industrial Temperature
(40C to 85C)

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
U designates Green Package + RoHS compliant.
H designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.

Package Type
8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2

8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y1

8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

8Y6

8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)

5TS1

5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1

8-ball, die Ball Grid Away Package (dBGA2)


Options

2.7

Low-voltage (2.7V to 5.5V)

1.8

Low-voltage (1.8V to 5.5V)

15
0180YSEEPR2/06

AT24C08A Ordering Information(1)


Ordering Code
(2)

AT24C08A-10PU-2.7
AT24C08A-10PU-1.8(2)
AT24C08AN-10SU-2.7(2)
AT24C08AN-10SU-1.8(2)
AT24C08A-10TU-2.7(2)
AT24C08A-10TU-1.8(2)
AT24C08AY1-10YU-1.8(2) (Not recommended for new design)
AT24C08AY6-10YH-1.8(3)
AT24C08AU2-10UU-1.8(2
AT24C08A-W1.8-11(4)
Notes:

1.
2.
3.
4.

Package

Operation Range

8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
8U2-1

Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)

Die Sale

Industrial Temperature
(40C to 85C)

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
U designates Green Package + RoHS compliant.
H designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.

Package Type
8P3

8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2

8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y1

8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

8Y6

8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)

8U2-1

8-ball, die Ball Grid Array Package (dBGA2)


Options

2.7

Low Voltage (2.7V to 5.5V)

1.8

Low Voltage (1.8V to 5.5V)

16

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
AT24C16A Ordering Information(1)
Ordering Code
(2)

AT24C16A-10PU-2.7
AT24C16A-10PU-1.8(2)
AT24C16AN-10SU-2.7(2)
AT24C16AN-10SU-1.8(2)
AT24C16A-10TU-2.7(2)
AT24C16A-10TU-1.8(2)
AT24C16AY1-10YU-1.8(2) (Not recommended for new design)
AT24C16AY6-10YH-1.8(3)
AT24C16AU2-10UU-1.8(2)
AT24C16A-W1.8-11(3)
Notes:

1.
2.
3.
4.

Package

Operation Range

8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
8U2-1

Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)

Die Sale

Industrial Temperature
(40C to 85C)

For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
U designates Green Package + RoHS compliant.
H designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.

Package Type
8P3

8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2

8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

8Y1

8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

8Y6

8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)

8U2-1

8-ball, die Ball Grid Array Package (dBGA2)


Options

2.7

Low Voltage (2.7V to 5.5V)

1.8

Low Voltage (1.8V to 5.5V)

17
0180YSEEPR2/06

Packaging Information
8P3 PDIP
E

E1

Top View

c
eA

End View

COMMON DIMENSIONS
(Unit of Measure = inches)

D
e
D1

A2 A

b2

b3
b

4 PLCS

Side View

SYMBOL

NOM

MAX

NOTE

0.210

A2

0.115

0.130

0.195

0.014

0.018

0.022

b2

0.045

0.060

0.070

b3

0.030

0.039

0.045

0.008

0.010

0.014

0.355

0.365

0.400

D1

0.005

0.300

0.310

0.325

E1

0.240

0.250

0.280

0.100 BSC

eA

0.300 BSC

Notes:

MIN

0.115

0.130

4
0.150

1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

18

2325 Orchard Parkway


San Jose, CA 95131

TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

DRAWING NO.

REV.

8P3

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
8S1 JEDEC SOIC
C

E1

Top View
End View
e

B
COMMON DIMENSIONS
(Unit of Measure = mm)

A
SYMBOL

A1

Side View

MIN

NOM

MAX

1.35

1.75

A1

0.10

0.25

0.31

0.51

0.17

0.25

4.80

5.00

E1

3.81

3.99

5.79

6.20

NOTE

1.27 BSC

0.40

1.27

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03

1150 E. Cheyenne Mtn. Blvd.


Colorado Springs, CO 80906

TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)

DRAWING NO.
8S1

REV.
B

19
0180YSEEPR2/06

8A2 TSSOP

2 1

Pin 1 indicator
this corner

E1

L1

N
L

Top View

End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
D

MIN

NOM

MAX

NOTE

2.90

3.00

3.10

2, 5

3, 5

A2

6.40 BSC

E1

4.30

4.40

4.50

1.20

A2

0.80

1.00

1.05

0.19

0.30

Side View

0.65 BSC
0.45

L1

0.60

0.75

1.00 REF

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02

20

2325 Orchard Parkway


San Jose, CA 95131

TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)

DRAWING NO.
8A2

REV.
B

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
8Y1 MAP

PIN 1 INDEX AREA

A
1

PIN 1 INDEX AREA

E1
D1

L
8

Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)

MIN

NOM

MAX

0.90

A1

0.00

0.05

SYMBOL

Side View

5
e

End View

Top View

A1

4.70

4.90

5.10

2.80

3.00

3.20

D1

0.85

1.00

1.15

E1

0.85

1.00

1.15

0.25

0.30

0.35

e
L

NOTE

0.65 TYP
0.50

0.60

0.70

2/28/03

2325 Orchard Parkway


San Jose, CA 95131

TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1

DRAWING NO.

REV.

8Y1

21
0180YSEEPR2/06

8Y6 Mini-MAP (MLP 2x3 mm)


D2

b
(8X)

E2

Pin 1
Index
Area

Pin 1 ID
L (8X)

D
A2

e (6X)

A1

1.50 REF.
A3

COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

MIN

2.00 BSC

3.00 BSC

MAX

D2

1.40

1.50

1.60

E2

1.40

0.60

A1

0.0

0.02

0.05

A2

0.55

A3
L

NOTE

0.20 REF
0.20

Notes:

NOM

0.30

0.40

0.50 BSC
0.20

0.25

0.30

1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.

8/26/05

22

2325 Orchard Parkway


San Jose, CA 95131

DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)

REV.
C

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
5TS1 SOT23
e1
C

E1

C
L

L1
1

End View

Top View

A2

Seating
Plane

A1

D
COMMON DIMENSIONS
(Unit of Measure = mm)

Side View
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-193, Variation AB, for additional information.
2. Dimension D does not include mold flash, protrusions, or gate burrs.
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.
Dimension E1 does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions
D and E1 are determined at the outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. These dimensions apply to the flat section of the lead between 0.08 mm
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the "b" dimension at
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead
shall not be less than 0.07 mm.

SYMBOL

MIN

NOM

MAX

1.10

A1

0.00

0.10

A2

0.70

0.90

1.00

0.08

0.20

NOTE

2.90 BSC

2, 3

2.80 BSC

2, 3

E1

1.60 BSC

2, 3

L1

0.60 REF

0.95 BSC

e1

1.90 BSC

0.30

0.50

4, 5

6/25/03

1150 E. Cheyenne Mtn. Blvd.


Colorado Springs, CO 80906

TITLE
5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
Small Outline Package (SHRINK SOT)

DRAWING NO.
PO5TS1

REV.
A

23
0180YSEEPR2/06

8U2 dBGA2

Pin 1 Mark
this corner

Top View
- Z -

COMMON DIMENSIONS
(Unit of Measure = mm)

b
0

SYMBOL

MIN

NOM

d
D1
e

E1

D1

1.43 TYP

NOTE

5.10

3.25

MAX

A2
A
A1

Bottom View
Side View

E1

1.25 TYP

0.75 TYP

0.75 TYP

0.90 REF

A1

0.49

0.52

0.55

A2

0.35

0.38

0.41

0.47

0.50

0.53

Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information.
2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z.

TITLE
R

24

1150 E. Cheyenne Mtn. Blvd.


Colorado Springs, CO 80906

02/04/02
DRAWING NO.

8U2, 8-ball 0.75 pitch, Die Ball Grid Array


Package (dBGA) AT24C512 (AT19870)

8U2

REV.
A

AT24C01A/02/04/08A/16A
0180YSEEPR2/06

AT24C01A/02/04/08A/16A
8U3-1 dBGA2
E

1.

A1

PIN 1 BALL PAD CORNER

A2

Top View

Side View

PIN 1 BALL PAD CORNER

(d1)

e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)

Bottom View
8 SOLDER BALLS

1. Dimension b is measured at the maximum solder ball diameter.


This drawing is for general information only.

SYMBOL

MIN

NOM

MAX

0.71

0.81

0.91

A1

0.10

0.15

0.20

A2

0.40

0.45

0.50

0.20

0.25

0.30

NOTE

1.50 BSC

2.00 BSC

0.50 BSC

e1

0.25 REF

1.00 BSC

d1

0.25 REF

6/24/03

1150 E. Cheyenne Mtn. Blvd.


Colorado Springs, CO 80906

TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)

DRAWING NO.

REV.

PO8U3-1

25
0180YSEEPR2/06

Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500

Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369

Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581

Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314

RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340

Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

1150 East Cheyenne Mtn. Blvd.


Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80

Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743

Literature Requests
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0180YSEEPR2/06

W9425G6EH
4 M 4 BANKS 16 BITS DDR SDRAM
Table of Contents1.

GENERAL DESCRIPTION............................................................................................................. 4

2.

FEATURES .................................................................................................................................... 4

3.

KEY PARAMETERS ...................................................................................................................... 5

4.

PIN CONFIGURATION .................................................................................................................. 6

5.

PIN DESCRIPTION........................................................................................................................ 7

6.

BLOCK DIAGRAM ......................................................................................................................... 8

7.

FUNCTIONAL DESCRIPTION....................................................................................................... 9
7.1

Power Up Sequence............................................................................................................ 9

7.2

Command Function ........................................................................................................... 10


7.2.1

Bank Activate Command ......................................................................................................10

7.2.2

Bank Precharge Command ..................................................................................................10

7.2.3

Precharge All Command ......................................................................................................10

7.2.4

Write Command ...................................................................................................................10

7.2.5

Write with Auto-precharge Command...................................................................................10

7.2.6

Read Command ...................................................................................................................10

7.2.7

Read with Auto-precharge Command ..................................................................................10

7.2.8

Mode Register Set Command ..............................................................................................11

7.2.9

Extended Mode Register Set Command ..............................................................................11

7.2.10 No-Operation Command ......................................................................................................11


7.2.11 Burst Read Stop Command..................................................................................................11
7.2.12 Device Deselect Command ..................................................................................................11
7.2.13 Auto Refresh Command .......................................................................................................11
7.2.14 Self Refresh Entry Command...............................................................................................12
7.2.15 Self Refresh Exit Command .................................................................................................12
7.2.16 Data Write Enable /Disable Command .................................................................................12

7.3

Read Operation ................................................................................................................. 12

7.4

Write Operation ................................................................................................................. 13

7.5

Precharge .......................................................................................................................... 13

7.6

Burst Termination .............................................................................................................. 13

7.7

Refresh Operation ............................................................................................................. 13

7.8

Power Down Mode ............................................................................................................ 14

7.9

Input Clock Frequency Change during Precharge Power Down Mode ............................ 14

7.10

Mode Register Operation .................................................................................................. 14


7.10.1 Burst Length field (A2 to A0) ................................................................................................14

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7.10.2 Addressing Mode Select (A3)...............................................................................................15
7.10.3 CAS Latency field (A6 to A4)................................................................................................16
7.10.4 DLL Reset bit (A8) ................................................................................................................16
7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) ........................................16
7.10.6 Extended Mode Register field ..............................................................................................16
7.10.7 Reserved field ......................................................................................................................16

8.

9.

10.

OPERATION MODE .................................................................................................................... 17


8.1

Simplified Truth Table........................................................................................................ 17

8.2

Function Truth Table ......................................................................................................... 18

8.3

Function Truth Table for CKE............................................................................................ 21

8.4

Simplified Stated Diagram ................................................................................................. 22

ELECTRICAL CHARACTERISTICS ............................................................................................ 23


9.1

Absolute Maximum Ratings............................................................................................... 23

9.2

Recommended DC Operating Conditions ......................................................................... 23

9.3

Capacitance....................................................................................................................... 24

9.4

Leakage and Output Buffer Characteristics ...................................................................... 24

9.5

DC Characteristics............................................................................................................. 25

9.6

AC Characteristics and Operating Condition..................................................................... 26

9.7

AC Test Conditions............................................................................................................ 28

9.8

AC Overshoot/Undershoot Specification for Address and Control Pins ........................... 30

9.9

Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins ............................ 31

TIMING WAVEFORMS ................................................................................................................ 32


10.1

Command Input Timing ..................................................................................................... 32

10.2

Timing of the CLK Signals ................................................................................................. 32

10.3

Read Timing (Burst Length = 4) ........................................................................................ 33

10.4

Write Timing (Burst Length = 4) ........................................................................................ 34

10.5

DM, DATA MASK (W9425G6EH) ..................................................................................... 35

10.6

Mode Register Set (MRS) Timing ..................................................................................... 36

10.7

Extend Mode Register Set (EMRS) Timing....................................................................... 37

10.8

Auto-precharge Timing (Read Cycle, CL = 2) ................................................................... 38

10.9

Auto-precharge Timing (Read cycle, CL = 2), continued .................................................. 39

10.10 Auto-precharge Timing (Write Cycle) ................................................................................ 40


10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 41
10.12 Burst Read Stop (BL = 8) .................................................................................................. 41
10.13 Read Interrupted by Write & BST (BL = 8)........................................................................ 42
10.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 42
10.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 43

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10.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43
10.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44
10.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44
10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45
10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46
10.23 Auto Refresh Cycle............................................................................................................ 47
10.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47
10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47
10.26 Self Refresh Entry and Exit Timing ................................................................................... 48
11.

PACKAGE SPECIFICATION ....................................................................................................... 49


11.1

12.

TSOP 66 lI 400 mil ......................................................................................................... 49

REVISION HISTORY ................................................................................................................... 50

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W9425G6EH
1. GENERAL DESCRIPTION
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words 4 banks 16 bits. W9425G6EH delivers a data bandwidth
of up to 500M words per second (-4). To fully comply with the personal computer industrial standard,
W9425G6EH is sorted into the following speed grades: -4/-5/-6 and -75. The -4 is compliant to the
DDR500/CL3 specification. The -5 is compliant to the DDR400/CL3 specification. The -6 is compliant
to the DDR333/CL2.5 specification. The -75 is compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9425G6EH is ideal for main memory in
high performance applications.

2. FEATURES

2.5V 0.2V Power Supply for DDR266/333/400

2.6V 0.1V Power Supply for DDR500

Up to 250 MHz Clock Frequency

Double Data Rate architecture; two data transfers per clock cycle

Differential clock inputs (CLK and CLK )

DQS is edge-aligned with data for Read; center-aligned with data for Write

CAS Latency: 2, 2.5 and 3

Burst Length: 2, 4 and 8

Auto Refresh and Self Refresh

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = 1

7.8S refresh interval (8K/64 mS refresh)

Maximum burst refresh cycle: 8

Interface: SSTL_2

Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant

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3. KEY PARAMETERS
SYMBOL

DESCRIPTION
CL = 2

tCK

Clock Cycle Time

CL = 2.5

CL = 3
tRAS

Active
Period

tRC

Active to Ref/Active Command Period

IDD0

IDD1

to

Precharge

Command

Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge

MIN./MAX.

-4

-5

-6

-75

Min.

7.5 nS

7.5 nS

7.5 nS

Max.

12 nS

12 nS

12 nS

Min.

6 nS

6 nS

7.5 nS

Max.

12 nS

12 nS

12 nS

Min.

4 nS

5 nS

6 nS

7.5 nS

Max.

10 nS

12 nS

12 nS

12 nS

Min.

36 nS

40 nS

42 nS

45 nS

Min.

52 nS

55 nS

60 nS

67.5 nS

Max.

110 mA

110 mA

110 mA

110 mA

Max.

150 mA

150 mA

150 mA

150 mA

IDD4R

Burst Operation Read Current

Max.

210 mA

180 mA

170 mA

160 mA

IDD4W

Burst Operation Write Current

Max.

210 mA

180 mA

170 mA

160 mA

IDD5

Auto Refresh Current

Max.

190 mA

190 mA

190 mA

190 mA

IDD6

Self-Refresh Current

Max.

3 mA

3 mA

3 mA

3 mA

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4. PIN CONFIGURATION

VDD

66

VSS

DQ0

65

DQ15

VDDQ

64

VSSQ

DQ1

63

DQ14

DQ2

62

DQ13

VSSQ

61

VDDQ

DQ3

60

DQ12

DQ4

59

DQ11

VDDQ

58

VSSQ

DQ5

10

57

DQ10

DQ6

11

56

DQ9

VSSQ

12

55

VDDQ

DQ7

13

54

DQ8

NC

14

53

NC

VDDQ

15

52

VSSQ

LDQS

16

51

UDQS

NC

17

50

NC

VDD

18

49

VREF

NC

19

48

VSS

LDM

20

47

UDM

WE

21

46

CLK

CAS

22

45

CLK

RAS

23

44

CKE

CS

24

43

NC

NC

25

42

A12

BA0

26

41

A11

BA1

27

40

A9

A10/AP

28

39

A8

A0

29

38

A7

A1

30

37

A6

A2

31

36

A5

A3

32

35

A4

VDD

33

34

VSS

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5. PIN DESCRIPTION
PIN NUMBER

PIN
NAME

FUNCTION

DESCRIPTION
Multiplexed pins for row and column address.

28 32,
35 42

A0 A12

26, 27

BA0, BA1

Bank Select

Select bank to activate during row address latch time, or


bank to read/write during column address latch time.

2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65

DQ0
DQ15

Data Input/ Output

The DQ0 DQ15 input and output data are synchronized


with both edges of DQS.

16,51

LDQS,
UDQS

Data Strobe

DQS is Bi-directional signal. DQS is input signal during write


operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data.

24

CS

Chip Select

Disable or enable the command decoder. When command


decoder is disabled, new command is ignored and previous
operation continues.

23, 22, 21

Address

Row address: A0 A12.


Column address: A0 A8. (A10 is used for Auto-precharge)

RAS ,

Command Inputs

CAS , WE

Command inputs (along with CS ) define the command


being entered.

LDM, UDM

Write Mask

When DM is asserted high in burst write, the input data is


masked. DM is synchronized with both edges of DQS.

CLK,
CLK

Differential Clock
Inputs

All address and control input signals are sampled on the


crossing of the positive edge of CLK and negative edge of
CLK .

44

CKE

Clock Enable

CKE controls the clock activation and deactivation. When


CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.

49

VREF

1, 18, 33

VDD

Power (+2.5V)

Power for logic circuit inside DDR SDRAM.

34, 48, 66

VSS

Ground

Ground for logic circuit inside DDR SDRAM.

3, 9, 15, 55, 61

VDDQ

6, 12, 52, 58, 64

VSSQ

Ground for I/O


Buffer

14, 17, 19, 25,


43, 50, 53

NC

No Connection

20, 47

45, 46

Reference Voltage VREF is reference voltage for inputs.

Power (+2.5V) for Separated power from VDD, used for output buffer, to
improve noise.
I/O Buffer
Separated ground from VSS, used for output buffer, to
improve noise.
No connection (NC pin should be connected to GND or

floating)

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6. BLOCK DIAGRAM

CLK
CLK

DLL
CLOCK
BUFFER

CKE

CONTROL

CS

SIGNAL
GENERATOR

RAS
CAS

COMMAND

DECODER
COLUMN DECODER

COLUMN DECODER

A10

CELL ARRAY
BANK #0

ROW DECODER

ROW DECODER

WE

MODE
REGISTER

A0

SENSE AMPLIFIER

SENSE AMPLIFIER
ADDRESS
BUFFER

PREFETCH REGISTER
DQ
DATA CONTROL

BUFFER

DQ0
DQ15

CIRCUIT
COLUMN

COUNTER

COUNTER

LDQS
UDQS
LDM
UDM

COLUMN DECODER

CELL ARRAY
BANK #2

COLUMN DECODER

ROW DECODER

REFRESH

ROW DECODER

A9
A11
A12
BA0
BA1

CELL ARRAY
BANK #1

SENSE AMPLIFIER

CELL ARRAY
BANK #3

SENSE AMPLIFIER

NOTE: The cell array configuration is 8912 * 512 * 16

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7. FUNCTIONAL DESCRIPTION
7.1

Power Up Sequence
(1)

(2)
(3)
(4)
(5)
(6)

(7)
(8)
(9)

Apply power and attempt to CKE at a low state ( 0.2V), all other inputs may be undefined
1) Apply VDD before or at the same time as VDDQ.
2) Apply VDDQ before or at the same time as VTT and VREF.
Start Clock and maintain stable condition for 200 S (min.).
After stable power and clock, apply NOP and take CKE high.
Issue precharge command for all banks of the device.
Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable
command applied.)
Issue precharge command for all banks of the device.
Issue two or more Auto Refresh commands.
Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.

CLK
CLK

Command

PREA

EMRS
tRP

MRS

2 Clock min.

PREA
2 Clock min.

AREF
tRP

AREF
tRFC

ANY
CMD

MRS
tRFC

2 Clock min.

200 Clock min.

Inputs
maintain stable
for 200 S min.

Enable DLL

Disable DLL reset with A8 = Low

DLL reset with A8 = High

Initialization sequence after power-up

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W9425G6EH
7.2

Command Function

7.2.1

Bank Activate Command

( RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 = Row Address)
The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row
addresses are latched on A0 to A12 when this command is issued and the cell data is read out of
the sense amplifiers. The maximum time that each bank can be held in the active state is specified
as tRAS (max). After this command is issued, Read or Write operation can be executed.

7.2.2

Bank Precharge Command

( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9, A11, A12 = Dont
Care)
The Bank Precharge command percharges the bank designated by BA. The precharged bank is
switched from the active state to the idle state.

7.2.3

Precharge All Command

( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Dont Care, A10 = "H", A0 to A9, A11, A12 =
Dont Care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.

7.2.4

Write Command

( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address)
The write command performs a Write operation to the bank designated by BA. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.

7.2.5

Write with Auto-precharge Command

( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address)
The Write with Auto-precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.

7.2.6

Read Command

( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address)
The Read command performs a Read operation to the bank designated by BA. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the
Mode Register at power-up prior to the Read operation.

7.2.7

Read with Auto-precharge Command

( RAS = "H", CAS = L, WE = H, BA0, BA1 = Bank, A10 = H, A0 to A8 = Column Address)


The Read with Auto-precharge command automatically performs the Precharge operation after the
Read operation.

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1) READA tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.
2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after tRAS (min) has completed.
This command must not be interrupted by any other command.

7.2.8

Mode Register Set Command

( RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data)
The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.

7.2.9

Extended Mode Register Set Command

( RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable,
output drive strength selection. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.

7.2.10 No-Operation Command


( RAS = "H", CAS = "H", WE = "H")
The No-Operation command simply performs no operation (same command as Device Deselect).

7.2.11 Burst Read Stop Command


( RAS = "H", CAS = "H", WE = "L")
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.

7.2.12 Device Deselect Command


( CS = "H")
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE and Address inputs are ignored. This command is similar to the No-Operation command.

7.2.13 Auto Refresh Command


( RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Dont Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS
BEFORERAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits Dont Care during an AUTO REFRESH command. The DDR SDRAM requires AUTO

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REFRESH cycles at an average periodic interval of tREFI (maximum). To allow for improved
efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given
DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 8 * tREFI.

7.2.14 Self Refresh Entry Command


( RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Dont Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are Dont Care during SELF REFRESH. Since CKE is a
SSTL_2 input, VREF must be maintained during SELF REFRESH.

7.2.15 Self Refresh Exit Command


(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR because time is required for the completion of any internal refresh in
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.

7.2.16 Data Write Enable /Disable Command


(DM = "L/H" or LDM, UDM = "L/H")
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.

7.3

Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes
available after CAS Latency from the issuing of the Read command. The CAS Latency must be set
in the Mode Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the
Burst operation is terminated.
When the Read with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Read cycle then the bank is switched to the idle state. This command
cannot be interrupted by any other commands. Refer to the diagrams for Read operation.

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7.4

Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched
sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command
(Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode
must be set in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data
duration.
Refer to the diagrams for Write operation.

7.5

Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and
Precharge All). When the Bank Precharge command is issued to the active bank, the bank is
precharged and then switched to the idle state. The Bank Precharge command can precharge one
bank independently of the other bank and hold the unprecharged bank in the active state. The
maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each
bank must be precharged within tRAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks
are not in the active state, the Precharge All command can still be issued. In this case, the
Precharge operation is performed only for the active bank and the precharge bank is then
switched to the idle state.

7.6

Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is
terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is
disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write
cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at
which the precharge command is issued. In this case, the DM signal must be asserted "high"
during tWR to prevent writing the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst
operation. Refer to the diagrams for Burst termination.

7.7

Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh.
By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh
operation must be performed 8192 times (rows) within 64mS. The period between the Auto
Refresh command and the next command is specified by tRFC.
Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks
are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case
of distributed Auto Refresh commands, distributed auto refresh commands must be issued every
7.8 S and the last distributed Auto Refresh commands must be performed within 7.8 S before
entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation
must be performed within 7.8 S. In Self Refresh mode, all input/output buffers are disabled,

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Revision A04

W9425G6EH
resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh
operation.

7.8

Power Down Mode


Two types of Power Down Mode can be performed on the device: Active Standby Power Down
Mode and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled
resulting in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at
next CLK rising edge. Refer to the diagrams for Power Down Mode.

7.9

Input Clock Frequency Change during Precharge Power Down Mode


DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a
minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency
between minimum and maximum operating frequency specified for the particular speed grade.
During an input clock frequency change, CKE must be held LOW. Once the input clock frequency
is changed, a stable clock must be provided to DRAM before precharge power down mode may be
exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS
command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM
is ready to operate with new clock frequency.

7.10 Mode Register Operation


The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to
A12 and BA0, BA1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set
the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode
Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented
the extended function (DLL enable/Disable mode).
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.

7.10.1 Burst Length field (A2 to A0)


This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, and 8 words.
A2

A1

A0

BURST LENGTH

Reserved

2 words

4 words

8 words

Reserved

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W9425G6EH
7.10.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both
addressing Mode support burst length 2, 4, and 8 words.
A3

ADDRESSING MODE

Sequential

Interleave

7.10.2.1. Addressing Sequence of Sequential Mode


A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

2 words (address bits is A0)

Data 1

n+1

not carried from A0 to A1

Data 2

n+2

4 words (address bit A0, A1)

Data 3

n+3

Not carried from A1 to A2

Data 4

n+4

Data 5

n+5

8 words (address bits A2, A1 and A0)

Data 6

n+6

Not carried from A2 to A3

Data 7

n+7

7.10.2.2. Addressing Sequence for Interleave Mode


A Column access is started from the inputted column address and is performed by interleaving the
address bits in the sequence shown as the following.
Addressing Sequence of Interleave Mode
DATA

ACCESS ADDRESS

Data 0

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 1

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 3

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 4

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 5

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 6

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0

- 15 -

BURST LENGTH

2 words

4 words

8 words

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6

A5

A4

CAS LATENCY

Reserved

Reserved

Reserved

Reserved

2.5

Reserved

7.10.4 DLL Reset bit (A8)


This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1

BA0

A12-A0

0
0
1

0
1
x

Regular MRS Cycle


Extended MRS Cycle
Reserved

7.10.6 Extended Mode Register field


1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0

DLL

0
1

Enable
Disable

2) Output Driver Size Control field (A1)


This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard.
A1

OUTPUT DRIVER

0
1

Full Strength
Half Strength

7.10.7 Reserved field


Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to "0" for normal operation.
Reserved bits (A9, A10, A11, A12)
These bits are reserved for future operations. They must be set to "0" for normal operation.

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8. OPERATION MODE
The following table shows the operation commands.

8.1

Simplified Truth Table

SYM.

COMMAND

ACT

DEVICE
STATE

Bank Active

PRE

Bank Precharge

PREA

Precharge All

Idle

(3)
(3)

Any

(4)

BA0,
BA1

A10

A12,
A11,
A9-A0

CS

RAS

CAS

WE

(3)

(3)

(3)

(3)

Active

Mode Register Set

Idle

L, L

Extended Mode
Register Set

Idle

H, L

Write

Active

WRITA

Write with Autoprecharge

Active

READ

Read

Active

READA

Read with Autoprecharge

EMRS

DM

Any

WRIT

MRS

CKEn-1 CKEn

NOP

No Operation

Any

BST

Burst Read Stop

Active

DSL

Device Deselect

Any

AREF

Auto Refresh

SELF
SELEX

Idle

Self Refresh Entry

Idle

Self Refresh Exit

Idle (Self
Refresh)

Idle/
(5)
Active

Power Down
Mode Entry

PD

PDEX

Power Down
Mode Exit

Any (Power
Down)

WDE

Data Write Enable

Active

WDD

Data Write Disable

Active

Notes:
1. V = Valid

X = Dont Care

L = Low level

H = High level

2. CKEn signal is input level when commands are issued.


CKEn-1 signal is input level one clock cycle before the commands are issued.
3. These are state designated by the BA0, BA1 signals.
4. LDM, UDM (W9425G6EH).
5. Power Down Mode can not entry in the burst cycle.

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
8.2

Function Truth Table

(Note 1)
CURRENT
STATE

Idle

Row Active

Read

Write

CS

RAS

CAS

WE

ADDRESS

COMMAND

ACTION

NOTES

DSL

NOP

NOP/BST

NOP

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

Row activating

BA, A10

PRE/PREA

NOP

AREF/SELF

Refresh or Self refresh

Op-Code

MRS/EMRS

Mode register accessing

DSL

NOP

NOP/BST

NOP

BA, CA, A10

READ/READA

Begin read: Determine AP

BA, CA, A10

WRIT/WRITA

Begin write: Determine AP

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

Precharge

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

BST

Burst stop

BA, CA, A10

READ/READA

Term burst, new read: Determine AP

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

Term burst, precharging

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, A10

READ/READA

Term burst, start read: Determine AP

6, 7

BA, CA, A10

WRIT/WRITA

Term burst, start read: Determine AP

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

Term burst, precharging

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
Function Truth Table, continued

CURRENT
STATE

Read with
Autoprecharge

Write with
Autoprecharge

Precharging

Row
Activating

CS

RAS

CAS

WE

ADDRESS

COMMAND

DSL

ACTION

NOTES

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

ILLEGAL

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

ILLEGAL

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

NOP-> Idle after tRP

NOP

NOP-> Idle after tRP

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

Idle after tRP

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

NOP-> Row active after tRCD

NOP

NOP-> Row active after tRCD

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

ILLEGAL

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
Function Truth Table, continued

CURRENT
STATE

Write
Recovering

Write
Recovering
with Autoprecharge

Refreshing

Mode
Register
Accessing

CS

RAS

CAS

WE

ADDRESS

COMMAND

ACTION

NOTES

DSL

NOP->Row active after tWR

NOP

NOP->Row active after tWR

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

ILLEGAL

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

NOP->Enter precharge after tWR

NOP

NOP->Enter precharge after tWR

BST

ILLEGAL

BA, CA, A10

READ/READA

ILLEGAL

BA, CA, A10

WRIT/WRITA

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A10

PRE/PREA

ILLEGAL

AREF/SELF

ILLEGAL

Op-Code

MRS/EMRS

ILLEGAL

DSL

NOP->Idle after tRC

NOP

NOP->Idle after tRC

BST

ILLEGAL

READ/WRIT

ILLEGAL

ACT/PRE/PREA

ILLEGAL

AREF/SELF/MRS/EMRS

ILLEGAL

DSL

NOP->Row after tMRD

NOP

NOP->Row after tMRD

BST

ILLEGAL

READ/WRIT

ILLEGAL

ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS

ILLEGAL

Notes:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which dont satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Dont care), V = Valid data

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
8.3

Function Truth Table for CKE

CURRENT
STATE

Self Refresh

Power Down

All banks Idle

Row Active

Any State
Other Than
Listed Above

CKE
n-1

CS

RAS CAS

WE

ADDRESS

ACTION

NOTES

INVALID

Exit Self Refresh->Idle after tXSNR

Exit Self Refresh->Idle after tXSNR

ILLEGAL

ILLEGAL

Maintain Self Refresh

INVALID

Exit Power down->Idle after tIS

Maintain power down mode

Refer to Function Truth Table

Enter Power down

Enter Power down

2
1

Self Refresh

ILLEGAL

ILLEGAL

Power down

Refer to Function Truth Table

Enter Power down

Enter Power down

ILLEGAL

ILLEGAL

ILLEGAL

Power down

Refer to Function Truth Table

Notes:
1. Self refresh can enter only from the all banks idle state.
2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down.
3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down.

Remark:

H = High level, L = Low level, X = High or Low level (Dont care), V = Valid data

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
8.4

Simplified Stated Diagram

SELF
REFRESH

SREF
SREFX

MRS/EMRS
MODE
REGISTER
SET

AREF

IDLE

AUTO
REFRESH

PD

PDEX
ACT

POWER
DOWN

ACTIVE
POWERDOWN

PDEX
PD
ROW
ACTIVE

BST
Read

Write

Write

Read

Read
Write

Read

Read A

Write A

Read A

Write A
Read A
PRE
Write A

POWER
APPLIED

POWER
ON

PRE

PRE

PRE

Read A

PRE
CHARGE

Automatic Sequence
Command Sequence

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9. ELECTRICAL CHARACTERISTICS
9.1

Absolute Maximum Ratings


PARAMETER

SYMBOL

RATING

UNIT

Input/Output Voltage

VIN, VOUT

-0.3 ~ VDDQ + 0.3

Power Supply Voltage

VDD, VDDQ

-0.3 ~ 3.6

Operating Temperature

TOPR

0 ~ 70

Storage Temperature

TSTG

-55 ~ 150

TSOLDER

260

PD

IOUT

50

mA

Soldering Temperature (10s)


Power Dissipation
Short Circuit Output Current

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

9.2

Recommended DC Operating Conditions

(TA = 0 to 70C)

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

VDD

Power Supply Voltage (for -5/-6/-75)

PARAMETER

2.3

2.5

2.7

VDD

Power Supply Voltage (for -4)

2.5

2.6

2.7

VDDQ

I/O Buffer Supply Voltage (for -5/-6/-75)

2.3

2.5

2.7

VDDQ

I/O Buffer Supply Voltage (for -4)

2.5

2.6

2.7

VREF

Input reference Voltage

0.49 x VDDQ

0.50 x VDDQ

0.51 x VDDQ

2, 3

VTT

Termination Voltage (System)

VREF - 0.04

VREF

VREF + 0.04

2, 8

VIH (DC)

Input High Voltage (DC)

VREF + 0.15

VDDQ + 0.3

VIL (DC)

Input Low Voltage (DC)

-0.3

VREF - 0.15

Differential Clock DC Input Voltage

-0.3

VDDQ + 0.3

15

0.36

VDDQ + 0.6

13, 15

Input High Voltage (AC)

VREF + 0.31

Input Low Voltage (AC)

VREF - 0.31

0.7

VDDQ + 0.6

13, 15

Differential AC input Cross Point Voltage

VDDQ/2 - 0.2

VDDQ/2 + 0.2

12, 15

Differential Clock AC Middle Point

VDDQ/2 - 0.2

VDDQ/2 + 0.2

14, 15

VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)

Input Differential Voltage.


CLK and CLK inputs (DC)

Input Differential Voltage.


CLK and CLK inputs (AC)

Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.

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Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.3

Capacitance

(VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)

MIN.

MAX.

DELTA
(MAX.)

UNIT

Input Capacitance (except for CLK pins)

2.0

3.0

0.5

pF

CCLK

Input Capacitance (CLK pins)

2.0

3.0

0.25

pF

CI/O

DQ, DQS, DM Capacitance

4.0

5.0

0.5

pF

CNC

NC Pin Capacitance

1.5

pF

SYMBOL
CIN

PARAMETER

Notes: These parameters are periodically sampled and not 100% tested.
The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.

9.4

Leakage and Output Buffer Characteristics

SYMBOL
II (L)

IO (L)
VOH

PARAMETER
Input Leakage Current
(0V < VIN < VDDQ, All other pins not under test = 0V)
Output Leakage Current
(Output disabled, 0V < VOUT < VDDQ)
Output High Voltage
(under AC test load condition)

IOH (DC)

Output Low Voltage


(under AC test load condition)
Output Minimum Source DC Current

IOL (DC)

Output Minimum Sink DC Current

IOH (DC)

Output Minimum Source DC Current

IOL (DC)

Output Minimum Sink DC Current

VOL

Full
Strength

Half
Strength

- 24 -

MIN.

MAX.

UNIT NOTES

-2

-5

VTT +0.76

VTT -0.76

-15.2

mA

4, 6

15.2

mA

4, 6

-10.4

mA

10.4

mA

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.5

DC Characteristics

SYM.

IDD0

IDD1
IDD2P

MAX.

PARAMETER
Operating current: One Bank Active-Precharge; tRC = tRC
min; tCK = tCK min; DQ, DM and DQS inputs changing twice
per clock cycle; Address and control inputs changing once
per clock cycle
Operating current: One Bank Active-Read-Precharge; Burst =
2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address
and control inputs changing once per clock cycle.
Precharge Power Down standby current: All Banks Idle;
Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF
for DQ, DQS and DM

UNIT

NOTES

-4

-5

-6

-75

110

110

110

110

150

150

150

150

7, 9

20

20

20

20

IDD2F

Idle floating standby current: CS > VIH min; All Banks Idle;
CKE > VIH min; Address and other control inputs changing
once per clock cycle; Vin = Vref for DQ, DQS and DM

45

45

45

40

IDD2N

Idle standby current: CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs
changing once per clock cycle; Vin > VIH min or Vin < VIL
max for DQ, DQS and DM

45

45

45

40

40

40

40

35

IDD2Q
IDD3P

IDD3N

IDD4R

IDD4W
IDD5
IDD6
IDD7

Idle quiet standby current: CS > VIH min; All Banks Idle;
CKE > VIH min; tCK = tCK min; Address and other control
inputs stable; Vin > VREF for DQ, DQS and DM
Active Power Down standby current: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min
Active standby current: CS > VIH min; CKE > VIH min; One
Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ,
DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating current: Burst = 2; Reads; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL=3; tCK = tCK min; IOUT = 0mA
Operating current: Burst = 2; Write; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs
changing twice per clock cycle
Auto Refresh current: tRC = tRFC min
Self Refresh current: CKE < 0.2V
Random Read current: 4 Banks Active Read with activate
every 20nS, Auto-precharge Read every 20 nS; Burst = 4;
tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing
twice per clock cycle; Address changing once per clock cycle

- 25 -

7
mA

20

20

20

20

70

70

70

65

210

180

170

160

7, 9

210

180

170

160

190
3

190
3

190
3

190
3

300

300

300

300

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.6

AC Characteristics and Operating Condition

(Notes: 10, 12)

SYM.

-4

PARAMETER
MIN.

tRC
tRFC
tRAS
tRCD
tRAP
tCCD
tRP
tRRD
tWR
tDAL

Active to Ref/Active Command Period


Ref to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Active to Read with Auto-precharge Enable
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
Auto-precharge Write Recovery + Precharge Time
2
CLK Cycle Time
2.5
3

52
60
36
16
16
1
16
8
15
---4

Data Access Time from CLK, CLK

tDQSQ
tCH
tCL

DQS Output Access Time from CLK, CLK


Data Strobe Edge to Output Data Edge Skew
CLk High Level Width
CLK Low Level Width

tHP

CLK Half Period (minimum of actual tCH, tCL)

tQH

DQ Output Data Hold Time from DQS

tCK
tAC
tDQSCK

tRPRE
tRPST
tDS
tDH
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tWPRES
tWPRE
tWPST
tDQSS
tIS
tIH
tIS
tIH
tIPW

MAX.

MIN.

UNIT

--10

-0.7

0.7

-0.7

0.7

-0.6

0.6

-0.6

0.6

70000

NOTES

MAX.

55
70
40
15
15
1
15
10
15
-7.5
6
5

70000

nS

tCK

18
12
12
12

nS

16

DQS Read Preamble Time


DQS Read Postamble Time
DQ and DM Setup Time
DQ and DM Hold Time
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Control & Address Input Pulse Width (for each input)

0.45
0.45
min
(tCL,tCH)
tHP
-0.5
0.9
0.4
0.4
0.4
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.85
0.6
0.6
0.7
0.7
2.2

tHZ

Data-out High-impedance Time from CLK, CLK

-0.7

tLZ

Data-out Low-impedance Time from CLK, CLK


SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Time (8k/64mS)
Mode Register Set Cycle Time

tT(SS)
tWTR
tXSNR
tXSRD
tREFI
tMRD

-5

0.45
0.55
0.55

1.1
0.6

0.6
1.15

0.45
0.45
Min,
(tCL,tCH)
tHP
-0.5
0.9
0.4
0.4
0.4
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.72
0.6
0.6
0.7
0.7
2.2

1.1
0.6

tCK

tCK

11

11

nS
0.6
1.25

tCK

11
19, 21-23
19, 21-23
20-23
20-23

nS

-0.7

0.7

-0.7

0.7

0.5
1
72
200

1.5

0.5
2
75
200

1.5

0.7

7.8
10

11

nS

-0.7

7.8

tCK

nS

0.7

- 26 -

0.4
0.55
0.55

tCK
nS
tCK
S
nS

17

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
Continued

SYM.

-6

PARAMETER
MIN.

tRC
tRFC
tRAS
tRCD
tRAP
tCCD
tRP
tRRD
tWR
tDAL

Active to Ref/Active Command Period


Ref to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Active to Read with Auto-precharge Enable
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
Auto-precharge Write Recovery + Precharge Time
2
CLK Cycle Time
2.5
3

60
72
42
18
15
1
18
12
15
-7.5
6
6

Data Access Time from CLK, CLK

tDQSCK

DQS Output Access Time from CLK, CLK

tDQSQ
tCH
tCL

Data Strobe Edge to Output Data Edge Skew


CLk High Level Width
CLK Low Level Width

tHP

CLK Half Period (minimum of actual tCH, tCL)

tQH

DQ Output Data Hold Time from DQS

tCK
tAC

tRPRE
tRPST
tDS
tDH
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tWPRES
tWPRE
tWPST
tDQSS
tIS
tIH
tIS
tIH
tIPW
tHZ
tLZ
tT(SS)
tWTR
tXSNR
tXSRD
tREFI
tMRD

-75
MAX.

MIN.

UNIT

12
12
12

67.5
75
45
20
15
1
20
15
15
-7.5
7.5
7.5

-0.7

0.7

-0.75

0.75

-0.6

0.6

-0.75

0.75

100000

NOTES

MAX.

100000

nS

tCK

18
12
12
12

nS

16

DQS Read Preamble Time


DQS Read Postamble Time
DQ and DM Setup Time
DQ and DM Hold Time
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Control & Address Input Pulse Width (for each input)

0.45
0.45
min
(tCL,tCH)
tHP
-0.55
0.9
0.4
0.45
0.45
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.75
0.75
0.75
0.8
0.8
2.2

Data-out High-impedance Time from CLK, CLK

-0.7

Data-out Low-impedance Time from CLK, CLK


SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Time (8k/64mS)
Mode Register Set Cycle Time

0.45
0.55
0.55

1.1
0.6

0.6
1.25

0.45
0.45
Min,
(tCL,tCH)
tHP
-0.75
0.9
0.4
0.5
0.5
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.75
0.9
0.9
1.0
1.0
2.2

1.1
0.6

tCK

tCK

11

11

nS
tCK

11

1.25
19, 21-23
19, 21-23
20-23
20-23
nS
0.75

-0.7

0.7

-0.75

0.75

0.5
1
72
200

1.5

0.5
1
75
200

1.5

7.8
15

11

nS

-0.75

7.8

tCK

nS

0.7

12

- 27 -

0.5
0.55
0.55

tCK
nS
tCK
S
nS

17

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.7

AC Test Conditions
PARAMETER

SYMBOL

VALUE

UNIT

Input High Voltage (AC)

VIH

VREF + 0.31

Input Low Voltage (AC)

VIL

VREF - 0.31

Input Reference Voltage

VREF

0.5 x VDDQ

Termination Voltage

VTT

0.5 x VDDQ

Differential Clock Input Reference Voltage

VR

Vx (AC)

VID (AC)

1.5

VOTR

0.5 x VDDQ

Input Difference Voltage. CLK and CLK Inputs (AC)


Output Timing Measurement Reference Voltage

VTT

VDDQ
VIH min (AC)
VREF

V SWING (MAX)

50
VIL max (AC)
VSS
T

Output

Output
V(out)

30pF

SLEW = (VIH min (AC) - VILmax (AC)) / T

Timing Reference Load


Notes:
(1)

Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device.

(2)

All voltages are referenced to VSS, VSSQ.( 2.6V0.1V for DDR500)

(3)

Peak to peak AC noise on VREF may not exceed 2% VREF(DC).

(4)

VOH = 1.95V, VOL = 0.35V

(5)

VOH = 1.9V, VOL = 0.4V

(6)

The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.


The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.

(7)

These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of tCK and tRC.

(8)

VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set
equal to VREF and must track variations in the DC level of VREF.

(9)

These parameters depend on the output loading. Specified values are obtained with the output open.

(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.

- 28 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., TDQSS = 0.75 tCK, tCK = 7.5 nS, 0.75 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.
(15) Refer to the figure below.

CLK
VX

VX

VX

VX

VICK

VICK

VX

VID(AC)

CLK
VICK

VICK

VSS
VID(AC)

0 V Differential

VISO
VISO(min)

VISO(max)

VSS

(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
(18) tDAL = (tWR/tCK) + (tRP/tCK)
(19) For command/address input slew rate 1.0 V/nS.
(20) For command/address input slew rate 0.5 V/nS and <1.0 V/nS.
(21) For CLK & CLK slew rate 1.0 V/nS (single--ended).
(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
(23) Slew Rate is measured between VOH(ac) and VOL(ac).

- 29 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.8

AC Overshoot/Undershoot Specification for Address and Control Pins


SPECIFICATION

PARAMETER
DDR500

DDR400

DDR333

DDR266

Maximum peak amplitude allowed for overshoot

1.5 V

1.5 V

1.5 V

1.5 V

Maximum peak amplitude allowed for undershoot

1.5 V

1.5 V

1.5 V

1.5 V

The area between the overshoot signal and VDD


must be less than or equal to Max. area in Figure 1

3.0 V-nS

3.0 V-nS

3.6 V-nS

4.5 V-nS

The area between the undershoot signal and GND


must be less than or equal to Max. area in Figure 1

3.0 V-nS

3.0 V-nS

3.6 V-nS

4.5 V-nS

VDD
Overshoot
5
Max. amplitude = 1.5V

4
3
2
Max. area
1
0
-1
-2
-3

Max. amplitude = 1.5V

GND

-4
-5
0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0
Time (nS)

Undershoot

Figure 1: Address and Control AC Overshoot and Undershoot Definition

- 30 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
9.9

Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins


SPECIFICATION

PARAMETER
DDR500

DDR400

DDR333

DDR266

Maximum peak amplitude allowed for overshoot

1.2 V

1.2 V

1.2 V

1.2 V

Maximum peak amplitude allowed for undershoot

1.2 V

1.2 V

1.2 V

1.2 V

The area between the overshoot signal and VDD


must be less than or equal to Max. area in Figure 2

1.44 V-nS

1.44 V-nS

2.25 V-nS

2.4 V-nS

The area between the undershoot signal and GND


must be less than or equal to Max. area in Figure 2

1.44 V-nS

1.44 V-nS

2.25 V-nS

2.4 V-nS

VDD
Overshoot
5
Max. amplitude = 1.2V

4
3
2
Max. area
1
0
-1
-2
Max. amplitude = 1.2V

-3

GND

-4
-5
0

0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0
Time (nS)

Undershoot

Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition

- 31 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCK

tCH

tCL

CLK
CLK
tIS

tIH

CS

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

RAS

CAS

WE

A0~A12
BA0,1
Refer to the Command Truth Table

10.2 Timing of the CLK Signals


tCL

tCH
CLK
CLK

tT

tT

VIH
VIH(AC)
VIL(AC)
VIL

tCK
VIH

CLK
CLK

VX

VX

- 32 -

VX

VIL

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.3 Read Timing (Burst Length = 4)

tCH

tCL

tCK

CLK

CLK

tIH

tIS

CMD

READ

tIS

ADD

tIH

Col
tDQSCK

tDQSCK
tRPST

tDQSCK

CAS Latency = 2

tRPRE
Hi-Z

Hi-Z
DQS
tQH

Preamble

Output
(Data)

tDQSQ

tQH

QA0
DA0

QA1
DA1

Postamble

tDQSQ

tDQSQ

QA2
DA2

QA3
DA3

Hi-Z

Hi-Z
tAC

tHZ
tDQSCK

tLZ

tDQSCK

tDQSCK
tRPRE

CAS Latency = 3

tRPST

Hi-Z

Hi-Z

DQS
tQH

Preamble

Output
(Data)

tDQSQ

tQH

QA0
DA0

QA1
DA1

Postamble

tDQSQ

tDQSQ

QA2
DA2

QA3
DA3

Hi-Z

Hi-Z
tAC
tLZ

tHZ

Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6EH)

LDQS

DQ0~7

UDQS

DQ8~15

- 33 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.4 Write Timing (Burst Length = 4)
tCH

tCL

tCK

CLK

CLK

tIS

CMD

tIH

WRIT

tIS

ADD

x4, x8 device

tIH

tDSH

tDSS

tDSH

tDSS

tDQSH

tDQSL

tDQSH

tWPST

Col

tWPRES
tWPRE

DQS
Postamble

Preamble
tDS

tDS

tDS
tDH

Input
(Data)

DA0

DA1

tDQSS
x16 device

tDH

tWPRES

tDH

DA2

DA3

tDSH

tDSS

tDSH

tDSS

tDQSH

tDQSL

tDQSH

tWPST

tWPRE
LDQS
Postamble

Preamble
tDS

tDS

DA0

tDH

tDH

tDH

DQ0~7

tDS

DA1

DA2

DA3

tDQSS

tDSH
tWPRES

tDSS

tDSH

tDQSL

tDQSH

tDSS

tDQSH

tWPST

tWPRE
UDQS
Preamble
tDS

tDH

tDH

DQ8~15

tDS Postamble

tDS

DA0

DA1

DA2

tDH

DA3

tDQSS

Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS
and LDQS must be toggled.

- 34 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH

10.5 DM, DATA MASK (W9425G6EH)


C LK

C LK

CMD

W R IT

LD Q S

tD S

tD S

tD H

tD H

LD M
t D IP W

D Q 0~D Q 7

D0

D1

t D IP W

D3
M asked

UDQS

tD S

tD S

tD H

tD H

UDM
t D IP W

D Q 8~D Q 15

D2

D0
M asked

D3

t D IP W

- 35 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.6 Mode Register Set (MRS) Timing
CLK

CLK

tMRD
CMD

MRS

ADD

Register Set data

NEXT CMD

Burst Length

A0
Burst Length

A1
A2

Addressing Mode

A3
A4

A5

CAS Latency

A2

A1

A0

Sequential

Interleaved

Reserved

Reserved

0
Reserved

Reserved

A6
A7

"0"

A8

A9
A10

Reserved
DLL Reset

"0"
"0"
Reserved

A11

Addressing Mode

A3

"0"

A12

"0"

BA0

"0"

BA1

"0"

Mode Register Set


or
Extended Mode
Register Set

Sequential

Interleaved

A5

A4

Reserved

Reserved

2.5

Reserved
DLL Reset

A8

* "Reserved" should stay "0" during MRS cycle.

- 36 -

CAS Latency

A6

No

Yes

BA1

BA0

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

Reserved

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.7 Extend Mode Register Set (EMRS) Timing

CLK
CLK

tMRD
CMD

EMRS

ADD

Register Set data

Output Driver

A1
A2

"0"

A3

"0"

A4

"0"

A5

"0"

A6

"0"

A7

"0"

A8

"0"

"0"

A11

"0"

A12

"0"

BA0

"0"

BA1

"0"

Enable

Disable

A1

Output Driver Size

Full Strength

Half Strength

Reserved
BA0

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

BA1

"0"

A10

DLL Switch

A0

DLL Switch

A0

A9

NEXT CMD

Mode Register Set


or
Extended Mode
Register Set

* "Reserved" should stay "0" during EMRS cycle.

- 37 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.8 Auto-precharge Timing (Read Cycle, CL = 2)
1) tRCD (READA) tRAS (MIN) (BL/2) tCK

tRAS

tRP

CLK
CLK
BL=2
CMD

ACT

READA

ACT

AP

DQS

DQ

Q0

Q1

BL=4
CMD

ACT

READA

ACT

AP

DQS

DQ

Q0

Q1

Q2

Q3

BL=8
CMD

ACT

AP

READA

ACT

DQS

DQ

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3
In this case, the internal precharge operation begin after BL/2 cycle from READA command.
AP

Represents the start of internal precharging.


The Read with Auto-precharge command cannot be interrupted by any other command.

- 38 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.9 Auto-precharge Timing (Read cycle, CL = 2), continued
2) tRCD/RAP(min) tRCD (READA) < tRAS (min) (BL/2) tCK

tRAS

tRP

CLK
CLK
BL=2
CMD

ACT

READA

AP

ACT

AP

ACT

tRAP
tRCD
DQS

DQ

Q0

Q1

BL=4
CMD

ACT

READA
tRAP
tRCD

DQS

DQ

Q0

Q1

Q2

Q3

BL=8
CMD

ACT

READA

ACT

AP

tRAP
tRCD
DQS

DQ

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3.
In this case, the internal precharge operation does not begin until after tRAS (min) has command.
AP

Represents the start of internal precharging.

The Read with Auto-precharge command cannot be interrupted by any other command.

- 39 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.10 Auto-precharge Timing (Write Cycle)

CLK
CLK
tDAL
BL=2
CMD

AP

WRITA

ACT

DQS

DQ

D0

D1
tDAL

BL=4
CMD

WRITA

ACT

AP

DQS

DQ

D0

D1

D2

D3
tDAL

BL=8
CMD

WRITA

AP

ACT

DQS

DQ

D0

D1

D2

D3

D4

D5

D6

D7

The Write with Auto-precharge command cannot be interrupted by any other command.
AP

Represents the start of internal precharging .

- 40 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)
CLK
CLK

CMD

ACT

READ A

tRCD
ADD

READ B

READ C

tCCD

Row
Address

COl,Add,A

tCCD
Col,Add,B

READ D

tCCD
Col,Add,C

READ E

tCCD
Col,Add,D

Col,Add,E

DQS

DQ

QA0

QA1

QB0

QB1

QC0

10.12 Burst Read Stop (BL = 8)


CLK
CLK

CMD

READ

BST

CAS Latency = 2
DQS

CAS Latency
DQ

Q0

Q1

Q2

Q3

Q4

Q5

CAS Latency = 3
DQS

CAS Latency
DQ

Q0

Q1

Q2

- 41 -

Q3

Q4

Q5

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.13 Read Interrupted by Write & BST (BL = 8)
CLK
CLK
CAS Latency = 2
CMD

READ

BST

WRIT

DQS

DQ

Q0

Q1

Q2

Q3

Q4

Q5

D0

D1

D2

D3

D4

D5

D6

D7

Burst Read cycle must be terminated by BST Command to avoid I/O conflict.

10.14 Read Interrupted by Precharge (BL = 8)


C LK
C LK

CMD

READ

PR E

C AS Latency = 2
DQS

C AS Latency
DQ

Q0

Q1

Q2

Q3

Q4

Q5

C AS Latency = 3
DQS

C AS Latency
DQ

Q0

Q1

Q2

- 42 -

Q3

Q4

Q5

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.15 Write Interrupted by Write (BL = 2, 4, 8)
CLK
CLK

CMD

ACT

WRIT A

tRCD

tCCD

Row
Address

ADD

WRIT B

COl. Add. A

WRIT C

tCCD
Col.Add.B

WRIT D

tCCD

Col. Add. C

WRIT E

tCCD

Col. Add. D

Col. Add. E

DQS

DQ

DA0

DA1

DB0

DB1

DC0

DC1

DD0

DD1

10.16 Write Interrupted by Read (CL = 2, BL = 8)


CLK
CLK

CMD

WRIT

READ

DQS

DM

tWTR
DQ

D0

D1

D2

D3

Data must be
masked by DM

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Data masked by READ


command, DQS input ignored.

- 43 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.17 Write Interrupted by Read (CL = 3, BL = 4)
CLK
CLK

CMD

WRIT

READ

DQS

DM

tWTR
DQ

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Data must be masked by DM

10.18 Write Interrupted by Precharge (BL = 8)


CLK
CLK

CMD

WRIT

PRE

ACT

tWR

tRP

DQS

DM

DQ

D0

D1

D2

D3

D4

D5

Data must be
masked by DM

D6

D7

Data masked by PRE command,


DQS input ignored.

- 44 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)
tCK = 100 MHz
CLK
CLK
tRC(b)
tRC(a)
tRRD
CMD

ACTa

tRRD
ACTb

READAa

READAb

ACTa

ACTb

tRCD(a)
tRAS(a)

tRP(a)
tRCD(b)
tRAS(b)

tRP(b)

DQS
Preamble

Postamble

CL(a)
Q0a

DQ

ACTa/b
: Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b
: Auto Pre. of bank a/b

Preamble

Postamble

CL(b)
Q1a

APa

Q0b

Q1b

APb

10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)


CLK
CLK
tRC(b)
tRC(a)
tRRD

tRRD
CMD

ACTa

ACTb

READAa

READAb

ACTa

ACTb

tRCD(a)
tRAS(a)

tRP(a)
tRCD(b)
tRAS(b)

tRP(b)

DQS
Preamble

Postamble

CL(a)

CL(b)
Q0a

DQ

ACTa/b
: Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b
: Auto Pre. of bank a/b

APa

- 45 -

Q1a

Q2a

Q3a

Q0b

Q1b

Q2b

Q3b

APb

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
t R C(a)
t R RD

CMD

AC Ta

tR R D

AC Tb

tR R D

ACTc

tR R D

R EADAa

ACTd

R EAD Ab

AC Ta

READ Ac

t R C D (a)
t R AS(a)

tR P
t R C D (b)
t R AS(b)
t R C D(c)
t RAS(c)
t R C D (d)
t RAS(d)

DQS
Pream ble

Postam ble

C L(a)
Q 0a

DQ

ACTa/b/c/d
: Bank Act. C M D of bank a/b/c/d
READ Aa/b/c/d : Read w ith Auto Pre.CM D of bank a/b/c/d
APa/b/c/d
: Auto Pre. of bank a/b/c/d

Pream ble

CL(b)
Q 1a

APa

Q0b

Q 1b

APb

10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)


CLK
CLK
t R C (a )
tR R D

tR R D

CMD

ACTa

ACTb

READAa

tR R D

ACTc

tR R D

READAb

ACTd

READAc

ACTa

READAd

t R C D (a )
t R A S (a )

t R P (a )
t R C D (b )
t R A S (b )
t R C D (c )
t R A S (c )
t R C D (d )
t R A S (d )

DQS
P re a m b le
C L (a )

C L (b )
Q 0a

DQ

A C T a /b /c /d
: B a n k A c t. C M D o f b a n k a /b /c /d
R E A D A a /b /c /d : R e a d w ith A u to P re .C M D o f b a n k a /b /c /d
A P a /b /c /d
: A u to P re . o f b a n k a /b /c /d

- 46 -

APa

Q1a

C L (c )

Q 0a

Q 1a

Q2a

APb

Q 3a

Q0b

Q 1b

Q 2b

Q3b

APc

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.23 Auto Refresh Cycle
CLK
CLK

CMD

PREA

NOP

AREF

NOP

tRP

AREF

CMD

NOP

tRFC

tRFC

Note: CKE has to be kept High level for Auto-Refresh cycle.

10.24 Precharged/Active Power Down Mode Entry and Exit Timing


CLK
CLK
tIH

tIS

tCK

tIH

tIS

CKE

Precharge/Activate
Note 1,2
Entry
CMD

CMD

Exit

NOP

NOP

CMD

NOP

Note:
1. If power down occurs when all banks are idle, this mode is referred to as precharge power down.
2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.

10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing
CLK
CLK

NOP

CMD

NOP

NOP

NOP

NOP

CMD

tIS

Frequency Change
Occurs here

CKE

DLL
RESET

200 clocks

tRP

Minmum 2 clocks
required before
changing frequency

Stable new clock


before power down exit

- 47 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
10.26 Self Refresh Entry and Exit Timing

CLK
CLK

tIH

tIS

tIH

tIS

CKE

CMD

PREA

NOP

SELF

SELEX

Entry

Exit

NOP

CMD

tRP

tXSNR
tXSRD

SELF

SELFX

Entry

Exit

NOP

ACT

NOP

READ

NOP

Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.

- 48 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
11. PACKAGE SPECIFICATION
11.1 TSOP 66 lI 400 mil

E1

O1
L
L1

O
O1

- 49 -

Publication Release Date:Apr. 11, 2008


Revision A04

W9425G6EH
12. REVISION HISTORY
VERSION

DATE

PAGE

A01

Dec. 12, 2007

All

A02

Jan. 04, 2008

5, 25

Revise -4 speed grade Max.IDD4R/IDD4W value from


190mA to 210mA

5, 26

Revise -5 speed grade Max. CLK cycle time tCK value


from 10nS to 12nS

A03

DESCRIPTION

Formally data sheet

Feb. 21, 2008


23

Change VDDQ max from VDD to 2.7V


Modify -4 speed grade DC Characteristics IDD6
parameter value from 5mA to 3mA

5, 25

A04

Add figure to illustrate Initialization sequence after


power-up

23

Revise overshoot/undershoot pulse width


Before VIH (max.) = -1.2V with a pulse width < 3 nS
After VIH (max.) = -1.5V with a pulse width < 5 nS
Before VIL (min.) = VDDQ +1.2V with a pulse width < 3 nS
After VIL (min.) = VDDQ +1.5V with a pulse width < 5 nS

Apr. 11, 2008

26, 27, 29

Revise input setup/hold time tIS/tIH parameters with


skew rate dependency of AC characteristics table

Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

- 50 -

Publication Release Date:Apr. 11, 2008


Revision A04

Issued Date: Feb. 4th, 2009


Model No.: V216B1-P01

Approval

: 29
: 2003
: L05
: Approval

TFT LCD Preliminary Specification

MODEL NO.: V216B1 P01

Customer:

__________________________

Approved by:_______________________________
Note:

Approved By

Reviewed By

TV Head Division
LY Chen
QRA Dept.

Product Development Div.

Tomy Chen

WT Lin

LCD TV Marketing and Product Management Div.


Prepared By

WY Li

Steven Tu

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1-P01

Approval

REVISION HISTORY

-------------------------------------------------------

1. GENERAL DESCRIPTION

-------------------------------------------------------

------------------------------------------------------2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V216B1-L01)


2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)

1.1 OVERVIEW
1.2 CHARACTERISTICS
1.3 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

-------------------------------------------------------

-------------------------------------------------------

-------------------------------------------------------

-------------------------------------------------------

12

-------------------------------------------------------

15

----------------------------------------------

19

-------------------------------------------------------

20

-------------------------------------------------------

22

-------------------------------------------------------

23

3.1 TFT LCD OPEN CELL

4. BLOCK DIAGRAM
4.1 TFT LCD OPEN CELL

5. INPUT TERMINAL PIN ASSIGNMENT


5.1 TFT LCD MODULE
5.2 LVDS DATA MAPPING TABLE
5.3 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS

8. DEFINITION OF LABELS
8.1 OPEN CELL LABEL
8.2 CARTON LABEL

9. PACKING
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD

10. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS

11. MECHANICAL DRAWING

: L05
: Approval

- CONTENTS -

3. ELECTRICAL CHARACTERISTICS

: 29
: 2003

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
REVISION HISTORY
Version

Date

Ver 2.0 Aug. 15, 08


Ver 2.1 Feb. 4th, 09

Page
(New)
All
P20

Section

Description

All
Approval Specification was first issued.
Packing Packing specifications
(1) 27 lcd TV Panels / 1 Box
(2) Box dimensions : 640(L) x 490(W) x 320(H) mm
(3) Weight : Approx.24.2Kg

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V216B1- P01 is a 21.6-inch wide TFT LCD cell with driver ICs and a 30-pin 1-ch LVDS interface. The
product supports 1366 x 768 (16.9 wide screen) mode and displays up to 16.7 ( 6-bit+Hi-FRC colors) millions
: The inverter module

colors. The backlight unit is not built in.

for the Backlight Unit is not


built in.

1.2 CHARACTERISTICS
CHARACTERISTICS ITEMS
Screen Diagonal [in]
Pixels [lines]

SPECIFICATIONS
21.6
1366 x R.G.B. x 768

Active Area [mm]


Sub -Pixel Pitch [mm]

477.417 (H) x 268.416 (V) (21.6 diagonal)


0.1165 (H) x 0.3495 (V)

Pixel Arrangement

RGB vertical stripe

Weight

TYP. 606

[g]

Physical Size
Display Mode

[mm]

488.917(W) x 279.916(H) x 2.0(D) Typ.


TN / Normally White

Contrast Ratio

800:1 Typ.
(Typical value measured at CMOs module: V216B1-L01)
0.7 / 0.7
+85/-85(H),+80/-80(V) Typ.
(Typical value measured at CMOs module: V216B1-L01)
R=(0.644, 0.331)
G=(0.273,0.588)
B=(0.151,0.061)
W=(0.285,0.293)
*Please refer to color chromaticity on p.15
(Typical value measured at CMOs module: V216B1-L01)
7.38%Typ.s
(Typical value measured at CMOs module: V216B1-L01)
Anti-glare coating,
484.4(H) x 275.8(w). Hardness: 3H
484.4(H) x 275.8(w)

Glass thickness (Array/CF) [mm]


Viewing Angle (CR>10)
Color Chromaticity

Cell Transparency []
Polarizer (CF side)
Polarizer (TFT side)

1.3 MECHANICAL SPECIFICATIONS


Item
Weight
I/F connector mounting
position

Min.

Typ.
Max.
606
The mounting inclination of the connector makes
the screen center within 0.5mm as the horizontal.

Unit
g

Note
(2)

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position

+/- 0.5mm

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V216B1-L01)
Item

Value

Symbol

Storage Temperature
Operating Ambient Temperature
Altitude Operating
Altitude Storage

Min.
-20
0
0
0

TST
TOP
A OP
A ST

Max.
+60
+50
5000
12000

Unit

Note

C
C
M
M

(1), (3)
(1), (2), (3)
(3)
(3)

Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 C).
(b) Wet-bulb temperature should be 39 C Max. (Ta > 40 C).
(c) No condensation..

Relative Humidity (%RH)


100
90
80

60

Operating Range
40

20

Storage Range

10
-40

-20

20

40

60

80

Temperature (C)

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 C with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in your product design to prevent the surface
temperature of display area from being over 65 C. The range of operating temperature may
degrade in case of improper thermal management in your product design.
Note (3) The rating of environment is base on LCD module. Leave LCD cell alone, this environment condition cant
be guaranteed. Except LCD cell, the customer has to consider the ability of other parts of LCD module
and LCD module process.

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
Storage Condition : With shipping package.
Storage temperature range : 255
Storage humidity range : 5010%RH
Shelf life : a month

2.3 ELECTRICAL ABSOLUTE RATINGS


2.3.1 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
Item
Power Supply Voltage
Input Signal Voltage

Symbol
Vcc
VIN

Value
Min.
-0.3
-0.3

Unit

Max.
6.0
3.6

Note

V
V

3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD OPEN CELL
Parameter
Power Supply Voltage
Power Supply Ripple Voltage
Rush Current
White
Power Supply Current Black
Vertical Stripe
Differential Input High
Threshold Voltage
LVDS
Differential Input Low
Interface
Threshold Voltage
Common Input Voltage
Terminating Resistor
CMOS
Input High Threshold Voltage
interface Input Low Threshold Voltage

Ta = 25 2 C
Min.
4.5
-

Value
Typ.
5.0
0.50
0.85
0.75

Max.
5.5
150
3.0
0.95
-

VLVTH

+100

mV

VLVTL

-100

mV

VLVC
RT
VIH
VIL

1.125
2.7
0

1.25
100
-

1.375
3.3
0.7

V
ohm
V
V

Symbol
VCC
VRP
IRUSH
ICC

Unit

Note

V
mV
A
A
A
A

(1)
(2)
(3)

Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

Vcc rising time is 470us


+5V
0.9Vcc
0.1Vcc

GND
470us

Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 2 C, f v = 60 Hz,
whereas a power dissipation check pattern below is displayed.
b. Black Pattern

a. White Pattern

Active Area

Active Area
7

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

c. Vertical Stripe Pattern

R G B R G B
B R G B R G B R
B R G B R G B R
R G B R G B
Active Area

4. BLOCK DIAGRAM
4.1 TFT LCD OPEN CELL

RX3(+/-)

SELLVDS

Vcc
GND

V/L

RXCLK(+/-)

TIMING
CONTROLLER

SCAN DRIVER IC

RX2(+/-)

INPUT CONNECTOR

RX1(+/-)

(P-TWO,196108-30041)

RX0(+/-)

TFT LCD PANEL


(1366x3x768)

DATA DRIVER IC
DC/DC CONVERTER &
REFERENCE VOLTAGE

Inverter (W/O)

BACKLIGHT UNIT

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin No.
Symbol
Description
1
NC
No Connection
2
NC
No Connection
3
NC
No Connection
4
GND
Ground
5
RX0Negative transmission data of pixel 0
6
RX0+
Positive transmission data of pixel 0
7
GND
Ground
8
RX1Negative transmission data of pixel 1
9
RX1+
Positive transmission data of pixel 1
10
GND
Ground
11
RX2Negative transmission data of pixel 2
12
RX2+
Positive transmission data of pixel 2
13
GND
Ground
14
RXCLKNegative of clock
15
RXCLK+
Positive of clock
16
GND
Ground
17
RX3Negative transmission data of pixel 3
18
RX3+
Positive transmission data of pixel 3
19
GND
Ground
20
NC
No Connection
21
SELLVDS
Select LVDS data format
22
NC
No Connection
23
GND
Ground
24
GND
Ground
25
GND
Ground
26
VCC
Power supply: +5V
27
VCC
Power supply: +5V
28
VCC
Power supply: +5V
29
VCC
Power supply: +5V
30
VCC
Power supply: +5V
Note (1) Connector part no.: P-TWO 196108-30041 (1.0mm FFC) or compatible

Note
(2)
(2)
(2)

(2)
(3)
(2)

Note (2) Reserved for CMO internal use, please leave it open
Note (3) Low: JEIDA data format. High/open: VESA data format.
Note (4) Logic level voltage definition: Low: 0V, High: 3.3V

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
5.2 LVDS DATA MAPPING TABLE
SELLVDS = H or Open (VESA)

SELLVDS = L (JEIDA)

R0~R7: Pixel R Data (7; MSB, 0; LSB)


G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
Notes(1) RSVD(reserved)pins on the transmitter shall be H or L
: Note (2) Specified
values are for lamp (Refer
to 3.2 for further
information).

10

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
5.3 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of color
versus data input.
Data Signal
Color

Red

Green

Blue

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black

0 0 0 0 0

0 0

0 0 0

Red

1 0 0 0 0

0 0

0 0 0

Green

0 1 1 1 1

0 0

0 0 0

Basic Blue

0 0 0 0 0

1 1

1 1 1

Colors Cyan

0 1 1 1 1

1 1

1 1 1

Magenta

1 0 0 0 0

1 1

1 1 1

Yellow

1 1 1 1 1

0 0

0 0 0

Gray

White

1 1 1 1 1

1 1

1 1 1

Red(0) / Dark

0 0 0 0 0

0 0

0 0 0

Red(1)

1 0 0 0 0

0 0

0 0 0

Red(2)

0 0 0 0 0

0 0

0 0 0

Red(253)

1 0 0 0 0

0 0

0 0 0

Red(254)

0 0 0 0 0

0 0

0 0 0

Red(255)

Scale
Of
Red

Gray

1 0 0 0 0

0 0

0 0 0

Green(0) / Dark 0

0 0 0 0 0

0 0

0 0 0

Green(1)

0 0 0 0 0

0 0

0 0 0

Green(2)

0 0 0 0 0

0 0

0 0 0

Green(253)

0 1 1 1 1

0 0

0 0 0

Green(254)

0 1 1 1 1

0 0

0 0 0

Green(255)

0 1 1 1 1

0 0

0 0 0

Blue(0) / Dark

0 0 0 0 0

0 0

0 0 0

Blue(1)

0 0 0 0 0

0 0

0 0 1

Scale
Of
Green

Gray
Scale
Of
Blue

Blue(2)

0 0 0 0 0

0 0

0 1 0

Blue(253)

0 0 0 0 0

1 1

1 0 1

Blue(254)

0 0 0 0 0

1 1

1 1 0

Blue(255)

0 0 0 0 0

1 1

1 1 1

Note (1) 0: Low Level Voltage, 1: High Level Voltage

11

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Item
Symbol Min.
Typ.
Max.
Unit
Frequency
1/Tc
60
76
82
MHZ
Input cycle to
LVDS Receiver Clock
Trcl
200
ps
cycle Jitter
LVDS Receiver Data

Vertical Active Display Term

Horizontal Active Display Term

Setup Time
Hold Time

Tlvsu
Tlvhd

Frame Rate

Fr

Total
Display
Blank
Total
Display
Blank

Tv
Tvd
Tvb
Th
Thd
Thb

600
600
47

50

53

57

60

63

778
768
10
1442
1366
76

806
768
38
1560
1366
194

888
768
120
1936
1366
570

Note

ps
ps
Hz
Th
Th
Th
Tc
Tc
Tc

Tv=Tvd+Tvb
Th=Thd+Thb
-

Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
(2) Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

Tv
Tvd

Tvb

DE
Th

DCLK
Tc
DE

DATA

Thd
Thb

Valid display data (1366 clocks)

12

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

LVDS RECEIVER INTERFACE TIMING DIAGRAM


Tc

RXCLK+/-

RXn+/Tlvsu
Tlvhd

1T
14

3T
14

5T
14

7T
14

9T
14

11T
14

13T
14

13

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the
diagram below.

0.1Vcc

0.1VCC
0V
T1

0.5T110ms
0T250ms
0T350ms
1s T4

T3

T2

T4

VALID
LVDS Signals

0V

Power On

Power Off

0T7T2
0T8T3
T8

T7

Option Signals
(SELLVDS)

Backlight (Recommended)
500msT5
100ms T6

50%

50%

T5

T6

Power ON/OFF Sequence


Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.

14

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Model No.: V216B1 P01

Approval
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Symbol

Value

Ambient Temperature

Item

Ta

252

oC

Ambient Humidity

Ha

5010

%RH

Supply Voltage
Input Signal

Unit

VCC
5.0
V
According to typical value in "3. ELECTRICAL CHARACTERISTICS

Inverter Current

IL

7.0

mA

Inverter Driving Frequency

FL

50

KHz

Dimming Frequency

FB

160 (type)

Hz

Minimum Duty Ratio

DMIN

20

Maximum Duty Ratio

DMAX

100

Inverter

Ampower (27-D024817)

7.2 OPTICAL SPECIFICATIONS


The relative measurement methods of optical characteristics are shown as below. The following items should
be measured under the test conditions described in 7.1 and stable environment shown in Note (5).
Item

Symbol

Contrast Ratio
Response Time

Horizontal
Viewing
Angle
Vertical

Note

(2)

ms

(3)

1.3

(7)

(5)

2.2

CT

Color Gamut

Unit

5.8

Cross Talk

White

Max.

1.3

LC

Blue

800
3.7

Green

Typ.

600

TF

White Variation

Red

Min.

TR

Center Luminance of White

Color
Chromaticity

Condition

CR

Rx
Ry
Gx
Gy
Bx

300

x=0, Y =0
Viewing Angle at
Normal Direction
With CMOs
module:
V216B1-L01

Typ.
-0.03

By

400

(4)

0.644

0.331

0.273

0.588

0.151
0.061

Typ.
+0.03

(0),(6)

Wx

0.285

Wy

0.293

68

72

NTSC
Ratio

75

85

75

85

70

80

Deg.

(1)

70

80

CG
x+
xY+
Y-

CR10
With CMOs
module:
V216B1-L01

15

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
Note (0) Light source is the standard light source C which is defined by CIE and driving voltage are based on
suitable gamma voltages. The calculating method is as following :
1. Measure Modules and BLUs spectrum. White is without signal input and R,G,B are with signal input.
BLU (for V216B1-L01) is supplied by CMO.
2. Calculate cells spectrum.
Calculate cells chromaticity by using the spectrum of standard light source C.
Note (1) Definition of Viewing Angle (x, y):
Viewing angles are measured by EZ-Contrast 160R (Eldim)
Normal
x = y = 0
y-
X- = 90

y
12 oclock direction

x-

y+

y+ = 90

6 oclock

y-

x+

y- = 90

X+ = 90

Note (2) Definition of Contrast Ratio (CR):


The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5),
CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).
Note (3) Definition of Response Time (TR, TF):

Gray Level 255

Gray Level 255

100%
90%

Optical

Gray Level 0

Response
10%
0%

TR

16

TF

Time

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
Note (4) Definition of Luminance of White (LC ):
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5)
L (X) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | YB YA | / YA 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
(0, 0)

Active Area

(0, 0)

Active Area

YA, U (D/2,W/8)

YB, U (D/2,W/8)
(D/4,W/4)

YA, L (D/8,W/2)

Gray 128

YB, L (D/8,W/2)
YA, R (7D/8,W/2)

YB, R (7D/8,W/2)

Gray 0

(3D/4,3W/4)

YA, D (D/2,7W/8)

YB, D (D/2,7W/8)

Gray 128

(D,W )

(D,W )

Note (6) Measurement Setup:


The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be executed
after lighting Backlight for 1 hour in a windless room.

LCD Module
LCD Panel
Center of the Screen

Display Color Analyzer


(Minolta CA210)

Light Shield Room


(Ambient Luminance < 2 lux)

Note (7) Definition of White Variation (W):


Measure the luminance of gray level 255 at 5 points
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

17

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

Horizontal Line
D

Vertical Line

D/4

W/4

D/2

W/2

3D/4

: Test Point
X=1 to 5

3W /4

Active Area

18

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
8. DEFINITION OF LABELS
8.1 OPEN CELL LABEL
The barcode nameplate is pasted on each open cell as illustration for CMO internal control.
V216B1-P01

XXXXXXXXXXXX

8.2 CARTON LABEL


The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation

P.O. NO.
Parts ID.

Carton ID.

Quantities

30

XXXXXXXXXXXXXX
Made in XXXX

(a) Model Name: V216B1-P01


(b) Carton ID: CMO internal control
(c) Quantities: 30
(d) Production Location:XXXX, for example:TAIWAN or CHINA .

19

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
9. packaging
9.1 packing specifications

(4) 27 LCD TV Panels / 1 Box


(5) Box dimensions : 640(L) x 490(W) x 320(H) mm
(6) Weight : Approx.24.2Kg
9.2 packing Method

Figures 9-1 and 9-2 are the packing method

Figure.9-1 packing method

20

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

PE Sheet
PE Sheet

Film

PP Belt

PP Belt

Film

Film

Carton Label

Carton Label

PE Sheet

PP Belt

Film

Carton Label

Figure.9-2 packing method

21

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the product during assembly.
(2) To assemble backlight or install module into users system can be only in clean working areas. The dust
and oil may cause electrical short or worsen the polarizer.
(3) Its not permitted to have pressure or impulse on the module because the LCD panel will be damaged.
(4) Always follow the correct power sequence when the product is connecting and operating. This can
prevent damage to the CMOS LSI chips during latch-up.
(5) Do not pull the I/F connector in or out while the module is operating.
(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the
product when it is operating.
(8) High temperature or humidity may reduce the performance of module. Please store this product within
the specified storage conditions.
(9) When ambient temperature is lower than 10C may reduce the display quality. For example, the
response time will become slowly.

10.2 SAFETY PRECAUTIONS


(1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case

: The startup voltage


of Backlight is

of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

approximately 1000 Volts.

(2) After the products end of life, it is not harmful in case of normal operation and storage.

It may cause electrical


shock while assembling
with inverter. Do not
disassemble the module or
insert anything into the
Backlight unit.

22

Version 2.1

Issued Date: Feb. 4th, 2009


Model No.: V216B1 P01

Approval

11. Mechanical Drawing

23

Version 2.1

SHENZHEN ACT INDUSTRIAL CO., LTD.

SPECIFICATION FOR APPROVAL

CUSTOMER

CLIENT P/N

TBD

DESCRIPTION

TBD

MODEL

A C T

DATE

AIP4904002A-G
2009-4-21

Please return to us one copy of SPECIFICATION FOR APPROVAL


with your approved signatures
APPROVED SIGNATURES
(CUSTOMER APPROVAL)

ENGINEER
CHECKED BY APPROVAL BY

(CHOP&SIGNATURES)
DATE

ACT APPROVAL

ENGINEER
CHECKED BY APPROVAL BY

(CHOP&SIGNATURES)
DATE

SHEN ZHEN ACT INDUSTRIAL CO.,LTD.


5
NO.5 Building, Beishan Industrial Park,
Beishan Road, Yantian District, Shenzhen, Guangdong, China
Tel86-755-25558506 25558255 25552808
Fax86-755-25558229
P.C.518083
E-mail: wonder@public.szptt.net.cn
support@szaction.com
Web: www.szaction.com

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 1 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.


Catalog
...................................................................................................................................................................... 4
1.

Introduction........................................................................................................................................................ 5
1.1 Power Supply Overview........................................................................................................................ 5
1.2 Applicable Documents.......................................................................................................................... 5

2.

Key Components................................................................................................................................... 6

3.

Electrical Specification ................................................................................................................................ 6


3.1 Switching Power Supply Parts....................................................................................................... 6
3.1.1 Input Voltage .......................................................................................................................... 6
3.1.2 Input Frequency...................................................................................................................... 6
3.1.3 Inrush Current ........................................................................................................................ 6
3.1.4 Standby Input Power ................................................................................................................ 6
3.1.5 Input Current Limiting ....................................................................................................... 6
3.1.6 Efficiency ........................................................................................................................................ 7
3.1.7 DC Voltage Regulation ......................................................................................................... 7
3.1.8 DC Output Current ................................................................................................................... 7
3.1.9 Output Ripple and Noise............................................................................................... 7
3.1.10 Output Dynamic Load Response ............................................................................... 8
3.1.11 Overshoot at turn-on/ turn-off .................................................................................................... 8
3.2 Protection Function .............................................................................................................................. 8
3.2.1 Over Voltage Protection............................................................................................................ 8
3.2.2 Short Circuit Protection............................................................................................................. 8
3.2.3 Over Current Protection............................................................................................................ 9
3.3 Timing................................................................................................................................................. 9
3.3.1 Hold up Time ........................................................................................................................... 9
3.3.2 Start up Time........................................................................................................................... 9
3.4 Inverter Parts.................................................................................................................................. 9
3.4.1 Input Characteristic ................................................................................................................. 9
3.4.2 Output Characteristic............................................................................................................. 10

Environment Requirement......................................................................................................................... 10
4.1 Temperature .............................................................................................................................................. 10
4.2 Humidity .................................................................................................................................................... 10
4.3 Altitude ..................................................................................................................................................... 10

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 2 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

Reliability..................................................................................................................................................... 11
5.1 Reliability Test ............................................................................................................................... 11
5.2 MTBF ............................................................................................................................ 11
5.3 Burn-in and Life test ................................................................................................................... 11

Product Safety Requirement.............................................................................................................. 11


6.1 Standard ................................................................................................................................................... 11
6.2 Leakage Current ................................................................................................................................ 11
6.3 Dielectric Strength Testing .................................................................................................................. 12
6.4 Insulation Resistance ........................................................................................................................ 12

Mechanical Dimensions ............................................................................................................................ 12


7.1 Mechanical Dimensions...................................................................................................................... 12
7.2 Mechanical Appendix ............................................................................................................................. 12
7.3 AC AC Connector .............................................................................................................................. 13
7.4 DC DC Connector.............................................................................................................................. 13

Packing ........................................................................................................................................................... 13

Quality Assurance Provision ...................................................................................................................... 15


9.1

Service .......................................................................................................................................... 15

9.2 Component Change ........................................................................................................................... 15


10

Major Test Equipment ...................................................................................................................... 16

11

Inspection Standards ....................................................................................................................... 16

12

Statement....................................................................................................................................................... 16

................................................................................................................................................................ 17
........................................................................................................................................................................ 19

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 3 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

Revision History
Spec.

Spec. Edition

Release Date

Modified content

Product Edition

V0.1

2009-4-21

Initial

V0.1

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 4 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

1. Introduction
1.1 Power Supply Overview
LCD 19 LCD TV
This product is PI power for LCD, and adapts to 19 LCD TV of caixun.

1.2 Applicable Documents

The products choose the standards as following for design verification test (No limited).
GB/T 2423.1-01 A
Basic environmental testing procedures for electric and electronic products Tests A: Cold
GB/T 2423.2-01 B
Basic environmental testing procedures for electric and electronic products Tests B: Dry heat
GB/T 2423.3-93 Ca
Basic environmental testing procedures for electric and electronic products Test Ca: Damp heat, steady state
GB/T 2423.4-93 Db
Basic environmental testing procedures for electric and electronic products Test Db: Damp heat cyclic
GB/T 2423.5-95 2 Ea
Environmental testing for electric and electronic products. Part 2: test methods. Test Ea and guidance: Shock
GB/T 2423.6-95 2 Eb
Environmental testing for electric and electronic products. Part 2: Test methods. Test Eb and guidance: Bump
GB/T 2423.8-95 2 Ed
Environmental testing for electric and electronic products. Part 2: Test methods. Test Ed: Free fall
GB/T 2423.10-95 2 Fc
Environmental testing for electric and electronic products. Part 2: Test methods. Test Fc and guidance:
Vibration(Sinusoidal)
GB/T 2423.11-97 2 Fd

Environmental testing for electric and electronic products. Part 2: Test methods. Test Fd: Random Vibration wide
band_ general requirements.
GB/T 2423.22-87 N
Basic environmental testing procedures for electric and electronic products. Test N: Change of temperature
GB8898-2001
(Audio, video and similar electric apparatus safety requirement)
GB 17625.1-2003 16A
The limits for the harmonic current emissions caused by low-voltage electrical and electronic
equipments(equipment input current16A per phase)
GB/T 17626.2-1998
Electromagnetic compatibility-Testing and measurement techniques-Electrostatic discharge immunity test
GB/T 17626.4-1998
Electromagnetic compatibility-Testing and measurement techniques-Electrical fast transient/ burst immunity test
GB/T 17626.5-1998
Electromagnetic compatibility-Testing and measurement techniques-Surge immunity test
GB/T 17626.11-1998
Electromagnetic compatibility-Testing and measurement techniques-Voltage dips, short interruptions and voltage
variations immunity tests

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

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SHENZHEN ACT INDUSTRIAL CO., LTD.

2. Key Components
.
Refer to appendix of key components information.

3. Electrical Specification
3.1 Switching Power Supply Parts
3.1.1

Input Voltage

2 AC
Table 2: Lists the AC input operating voltage range. The power shall work normally and meet all electrical
requirements throughout this range.
2AC Table 2: AC Input Voltage Limitations

3.1.2

Minimum

Nominal

Maximum

90Vac

100Vac-240Vac

264Vac

Input Frequency

3 AC
Table 3: Lists the AC input operating frequency range. The power shall work normally and meet all electrical
requirements throughout this range.
Table 3: AC Input Frequency Limitations 3AC

3.1.3

Minimum

Nominal

Maximum

47Hz

60Hz/50Hz

63Hz

Inrush Current

25 60A;
2.
Peak inrush current shall be limited to 60A cold start at 25 degrees C, and shall not result in a permanent damage of
the power supply under any conditions of load and input voltage as specified at any input voltage as specified in table 2.

3.1.4

Standby Input Power

230Vac/50Hz +12V 45mA 1W


The standby input power should no more than 1W under the 230Vac/50Hz input12V/45mA.

3.1.5

Input Current Limiting

1.4A
The input current should no more than 1.4A, under minimum input and full load.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

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SHENZHEN ACT INDUSTRIAL CO., LTD.

3.1.6

Efficiency

230Vac/50Hz 80%.
The power supply efficiency shall be greater than 80% under 230Vac/50Hz input. It will be measured at the maximum
load and typical load.

3.1.7

DC Voltage Regulation

4
3.1.10 DC
The DC output voltages will remain within the regulation ranges shown in Table 5 when measured ate the load end of
the output connectors.
The voltage regulation limits do not include the transient DC load changes, which are covered in Section 3.1.10.
4 Table 4: DC Output voltage regulation limits
Parameter

Line Regulation

Load regulation

Cross regulation

V1:12V

1%

5%

3.1.8

DC Output Current
5 Table 5: DC output current limits

3.1.9

Parameter

Min.

Typ.

PEAK

Unit

V1:12V

0.045

4.0

5.0

Output Ripple and Noise


6 3.1.8 3.1.1

20MHz 0.1uF
10uF ESR
The following table 6 is output ripple and noise requirements, it will be met throughout the load ranges specified in
Section 3.1.8 and under all input voltage conditions as specified Section 3.1.1, Measurements will be made with an
oscilloscope set to 20MHz bandwidth limit. The outputs will be bypassed with one 0.1uF multilayer (type X7R) and one
10uF tantalum electrolytic (low ESR) capacitors.
6 Table 6: Output ripples and noise limits
Parameter
V1:12V

Model No.: AIP4904002A-G

Rev.:V0.1

Max.
120mVp-p@25
200mVp-p@0

2009-4-21

Page 7 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

3.1.10 Output Dynamic Load Response


7 0.1Amps/uS, 50Hz~10 KHz

The output voltages will remain within specified regulation limit of the nominal set voltage for changes in load as
specified below under the following load steps defined below table 7. At a slew rate of 0.1Amps/uS between 50Hz to 10
KHz.
7
Table 7: Output dynamic load response limits
Dynamic Load

DC Voltage Regulation

10%~100%~10%

10%

10%~50%~10%

5%

50%~100%~50%

5%

3.1.11 Overshoot at turn-on/ turn-off


10% .
Any overshoot at turn on or turn off shall be less than 10% of rated output voltage.

3.2 Protection Function


3.2.1

Over Voltage Protection

The power supply will provide for over voltage protection as defined below.
8

3.2.2

Table 8: Over Voltage Protection limits

Parameter

Min.

Max

Unit

V1:12V

15

23

VDC

Short Circuit Protection

0.1 3.1

An output short circuit is defined as any output impedance of less than 0.1 ohms. The power supply will protect
without damage to overseers of to the unit (components, connectors, etc) under the input conditions specified in Section
3.1 above.

Model No.: AIP4904002A-G

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2009-4-21

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SHENZHEN ACT INDUSTRIAL CO., LTD.

3.2.3

Over Current Protection

The power supply has OCP function, and without any damage during test, the unit shall recovery and functions

automatically after the protection is removed.


output

Min. current

Max. current

unit

V1(12V)

4.8

7.2

3.3 Timing
3.3.1

Hold up Time
110Vac 8mS 220Vac

20mS
Hold-up time no less than 8mS at 110Vac input and no less than 20mS at 220Vac input, the output loading should
be set up with full load during the test.

3.3.2

Start up Time
110Vac 3 , 220Vac

1.5
Start up time no more than 3 seconds at 110Vac input and no more than 1.5second at 220Vac, the output
loading should be set up with full load during the test.

3.4 Inverter Parts


3.4.1

Input Characteristic

10 Table 10 Input characteristic

Parameter

Symbol

Min.

Typical

Max.

Unit

Remarks

Input Voltage

Vin

10.8

12

13.2

VDC

BKLT-ADJ

2.4

5.0

ON

1.2

OFF

1.8

Brightness Control Voltage

ON/OFF Control Voltage

BKLT-EN

Iin

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Bright(max)=0V
Bright(min)=5V

Page 9 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

3.4.2

Output Characteristic

11 Table 11 Output Characteristic

Parameter

Symbol

Min.

Typical

Max.

Unit

Remarks

Output Current

ADJ=0V
mArms

ADJ=5V

Vs

1000

2300

Vrms

Load: Open 25

Kickoff Voltage

Vs

1300

Vrms

Load: Open 0

Ts

Sec

/Frequency

40

50

60

KHz

/Efficiency

65

N/A

N/A

Start-up Time

6
Io

Environment Requirement
4.1 Temperature
:

0~ 50

Operating Ambient: 0~ 50
: -25~ +80
Non-operating Ambient: -25~ +80

4.2 Humidity
: 10%~90%
Operating: 10%~90% relative humidity (Non- condensing)
10%~90%
Non-operating: 10%~90% relative humidity (Non- condensing)

4.3 Altitude
2000
Operating: 2000 meters
2000
Non-operating: 2000meters

Model No.: AIP4904002A-G

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2009-4-21

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SHENZHEN ACT INDUSTRIAL CO., LTD.

Reliability
5.1 Reliability Test
12

Table 12: Reliability test items

Test Item

Test conditions

Storage at high temperature test

+80

Storage at low temperature

Operating at high temperature test

16Hrs

Test quantity
2 Pcs

-25

16Hrs

2 Pcs

+50

24Hrs

2 Pcs

Operating at low temperature test

24Hrs

2 Pcs

02

Low Temperature turn on test

EUT
EUT should start-up normally after storage at 0 of 2

2 Pcs

hours under minimum input voltage and maximum load.

thermal circle test

0(30min)50(30min)0(30min)
2 Pcs

4
Continually work 4 cycles

/Constant
temperature and humidity test

+50 90%RH 24
+50 90%RH, continually operating 24 hours

2 Pcs

5.2 MTBF
25100K (MIL-HDBK-217F)
MTBF no less than 100K hours (25 degrees C, Full load and rated voltage input, MIL-HDBK-217F)

5.3 Burn-in and Life test


ACT
ACT shall discuss with customer to maker sure the power in house Burn-In and life test procedures.

Product Safety Requirement


6.1 Standard
IEC60065
Meet IEC60065 (Audio, video and similar electric apparatus -safety requirement) standard requirement.

6.2 Leakage Current


3.5mA (230Vac/50Hz)
Leakage current shall not exceed 3.5mA at 230Vac/50Hz.

Model No.: AIP4904002A-G

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2009-4-21

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SHENZHEN ACT INDUSTRIAL CO., LTD.

6.3 Dielectric Strength Testing


100% 3S
Hi-pot test shall be met the table 13 requirements, an item listing this test as a 100% production test must be performed
and be maintained at that level for a minimum of 3 seconds without failure.
13 Table 13: Hi-pot test

Item

Specification

----- Primary to Secondary


-----

Primary to P.G

----- Secondary to P.G

Remark

3.0KVac

<10mA

1.5KVac

<10mA

No arcing
No broken

6.4 Insulation Resistance


50M 500VDC
-Primary to Secondary: 50 Meg. Ohms min. 500VDC
75%.

Mechanical Dimensions
7.1 Mechanical Dimensions
147mm*110mm*23mm (L*W*H)

7.2 Mechanical Appendix

Model No.: AIP4904002A-G

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SHENZHEN ACT INDUSTRIAL CO., LTD.

7.3 AC AC Connector
PIN NO.

L (AC Line,100~240Vac,50/60Hz)

G(GND,0V)

N (AC Line,100~240Vac,50/60Hz)

7.4 DC DC Connector
PIN NO.

12V(11.4-12.6V)

12V(11.4-12.6V)

+5V(NC)

+5V(NC)

GND(0V)

GND(0V)

ON/OFF(0-1.2V INVERTER OFF,2.4-5.0V INVERTER ON)

ADJ(0-5VDC,0V 5V )

Packing

Unless specially requirement of customer, the packing according to ACT company style.
8.1 :
Inner package: static-free bag.
8.2 :
Outer package: paper-box.
8.3 :
Outer package notes include the information: Customer Name, LOT Number, Model No., Date, and so on.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 13 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 14 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

Quality Assurance Provision


9.1

Service

1.
()
30

ACT Company is responsible for the quality control of all the products, and customer should check the products by this
specification. The products (same Lots) could be returned to ACT Company if the products function were not meet customer
requirement (unless any situations of discussion projects). When any failures were found in product line, customer can
require change the products in 30 days to ACT Company, but the problem cause by the customer are not fit to this.
2.
(2)
.
ACT Company promises one-year warranty for the products after service and would afford maintained service or
substitute the fault products in 2 weeks (after received the products) if the failure reason were no by improper operation
without cost. Otherwise if the fault products were over warranty period or caused by improper operation, ACT company also
would afford the service but to take the maintain fee or material fee is requirement.

9.2 Component Change


1.

When the production performance and quality are affected by the design or engineering modification, ACT Company
need supply corresponding files and produce productions after discussion with customer. The modified specifications or
diagrams must be enclosed and marked at new specifications book.
2.

When customer needs to modified the design or the process, to notice ACT Company about the information is
requirement. In order to guarantee the products quality and the process stability, ACT should be performed the modified
contents after discussion together and agreement.
3.
Substitution may be made for parts, but prior to customers approval is requirement for any component change.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 15 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

10 Major Test Equipment


10-1 AC SOURCE: CHROMA 61602
10-2 / POWER METER: PF9800
10-3 / ELECTRONIC LOAD: CHROMA 6312
10-4 / OSCILLOSCOPE: Tektronix TDS 1012
10-5 / MULTIMETER: Fluke 45
10-6 / DC POWER: TPR-3003-2D
10-7 / HI-POT TESTER:GOODWILL GPT-605
10-8 /Multi-routes temperature test instrument: WeiGe DWC2515
10-9 LOW AND HIGH TEMPERATURE ENVIRONMENT ALTERNATION TEST CHAMBER: TERCHY MHU-1000A

11 Inspection Standards
14
NO.
1
2
3

Table 14 Inspection Requirement

Test project

Performance

Size

Shell , Package

Test standard

Sample Level

GB2828-2003

II

Test standard
CR=0
Serious defect: CR=0
AQL=0.65
Main defect: AQL=0.65
AQL=1.0
Petit defect: AQL=1.0

12 Statement
12-1
All rights reserved by Shenzhen ACT Industrial Co., Ltd. for all of this specification for approval.
12-2
This specification for approval has two copies, one for customer, and the other for provider. It comes into effect after approval
this specification by customers.
12-3
If specification for approval needs to update, its made an agreement after discuss between customer and provider.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 16 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

No.

10

Y1

5R/3A

MF72 5D9

5R/3A

MF72 5D9

82UF/400V

82UF 400V

CapXon

CAPXON

82UF/400V

82UF 400V

THICON

82UF/400V

82UF 400V

XUNDA

10UF/50V

10UF 50V

XUNDA

10UF/50V

10UF 50V

10UF/50V

10UF 50V

CapXon

CAPXON

470UF/25V

470UF 25V

CapXon

CAPXON

470UF/25V

470UF 25V

470UF/25V

470UF 25V

680uF/25V

680uF 25V

CapXon

CAPXON

680uF/25V

680uF 25V

680uF/25V

680uF 25V

XUNDA

0.47uF 280V(UL:E246678)

.47k 280V

MPX/MKP

0.47uF 275V(UL:E120045)

.47k 275V

MPX

0.47uF 275V(UL:E320206

.47k 275V

MPX

0.47uF 275V(UL:E183780

.47k 275V

HQX

1000pF 250V (UL:E221839)

102M 250V

STE CD

1000pF 250V (UL:E114280)

102M 250V

SE

1000pF 250V (UL:E208107)

102M 250V

HJ

102K/1KV

102 1KV

102K/1KV

102 1KV

102K/1KV

102K 1KV

2200pF 250V(UL:E221839)

222M 250V

HJ

2200pF 250V(UL:E114280 )

222M 250V

SE

2200pF 250V(UL:E208107 )

222M 250V

STE CD

5PF/6KV

5 6KV

5PF/6KV

5 6KV

5PF/6KV

5 6KV

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

THR101

PCS

C107

PCS

C122

PCS

C206/C206A

PCS

C118/C104A/C104

PCS

CX101

PCS

CY101/CY102

PCS

C101

PCS

CY103

PCS

C213/C214

PCS

Page 17 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

No.

11

12

13

14

15

16

17

18

19

20

21

22

222J/630V

2J222J

222J/630V

2J222J

MBR20100CTG

B20100G

ON

ON

SBR20100

B20100

DIODES

600V/2A

RL205

"Hg"

600V/2A

RL205

"HG"

600V/2A

RL205

PY

FR107

FR107

"HG"

FR107

FR107

"Hg"

1000V/2A

FR207

"Hg"

1000V/2A

FR207

"HG"

1000V/2A

FR207

PY

AZ431AZ

AZ431AZ-AE1

BCD

BCD

TL431A

TL431A

EST

EST

FQPF8N60C

FQPF8N60C

FAIRCHILD

STM STP8NK60ZFP

8NK60

ST

ST

STK0860F

STK0860F

AUK

AUK

EL-817 (UL:E214129)

817

EL

EVERLIGHT

LTV-817 (UL:E113898)

817

LITEON

BPC-817 (UL: E236324)

817

Bright LED

H11A817 (UL: E90700)

817

Fairchild
Semiconductor

K1010 (UL: E169586)

1010

COSMO

250V 3.15A

T3.15A 250V

3K

250V 3.15A

T3.15A 250V

32S

B3942

B3942

BITEK

AP4511GM

4511GM

AO4606

AO4606

SP5005SOP16

SP5005

SP

APEC
ALPHA
OMEGA

BIT3713SSOP16

BIT3713

BITEK

BITEK

R7731

R7731

SD4563

SD4563

OB2263

OB2263

SMD/IC

SMD/IC

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

CX102

PCS

D105

PCS

BD101A/BD101B/BD
PCS
101C/BD101D

D101

PCS

D103

PCS

U103

PCS

Q101

PCS

U102

PCS

F101

PCS

Q204/Q205

PCS

U201

PCS

U101

PCS

Page 18 of 19

SHENZHEN ACT INDUSTRIAL CO., LTD.

Model No.: AIP4904002A-G

Rev.:V0.1

2009-4-21

Page 19 of 19

:CX-MST106-V3.0

1

T15.011060-03R

T06.102402-00R

Date:2009-10-21

PCB

CX-MST106-V3.0
,FR4(234.8*126.3mm) ROHS

PCS

PCB

24C02 SOP-8 ROHS

PCS

U12 HDMI EDID CODE

24C02 SOP-8 ROHS

PCS

U6 VGA DDC

T06.100B32-00R

EN25F32-100HIP

PCS

U24

T06.102404-00R

24C04 SOP-8 ROHS

PCS

U21

T06.100106-CHR

MSD106CHL QFP256 SMD ROHS

PCS

U2

T06.101117-18R

AP1117-18 SOT-223 ROHS

PCS

U11

T06.101117-33R

AP1117-33 SOT-223 ROHS

PCS

U16

T06.107314-00R

IRF7314 SOP-8 ROHS

PCS

U5

T06.101117-00R

PCS

U28

10

T06.109425-00R

W9425G6EH-4,256M,TSOP66,ROHS PCS

U9

11

T06.106353-00R

CE6353

PCS

U14

12

T06.109410-00R

EC9410 SOP-8 ROHS

PCS

U15

13

T06.104558-00R

LM4558 SOP-8 ROHS

PCS

U33

14

T06.107805-00R

LM7805 TO-252 ROHS

PCS

U18

D9650H SAWFB1 ROHS

PCS

U23

15

T06.209650-00R

AMS1117-adj SOT-223 ROHS

QFP64 ROHS

16

T06.203953-00R

K3953D SAWFB1 ROHS

PCS

U29

17

T06.101084-33R

AMS1084-3.3 TO-263 ROHS

PCS

U30

18

T06.101517-00R

TDA1517 DIP18 3W+3W

PCS

U31

19

T06.100407-00R

R2S10407 SOP-24 ROHS

PCS

U26

20

T12.XF1GA0-00R

XF-1GA(DVB-TPALSECAM)
ROHS

PCS 1

U20

21

T04.8099DW-00R

Bav99w SOT-363 ROHS

PCS

DD24,DD25,DD26D62

22

T04.800099-00R

Bav99 SOT-23 ROHS

PCS

DD30,DD32

23

T04.800054-0CR

BAT54C,SOT-23 ROHS

PCS

DD39,DD48

24

T04.805819-00R

1N5819,SMD,DO-214,ROHS

PCS

D3

25

T04.800277-52R

BA277,SMD,SOD523,ROHS

PCS

D66

26

T05.203904-00R

NPN,MMBT3904,SMD,SOT-23,ROHS PCS 18

Q6,Q7,Q9,Q11,Q12,Q14,Q24,Q26,Q27,Q29,Q31,Q42,Q44,Q45,Q54,Q55,Q57
.Q23

27

T05.203906-00R

PNP,MMBT3906,SMD,SOT-23,ROHS PCS

Q22,Q32,Q41

28

T05.207002-00R

MOS

2N7002 SMD,SOT-23,ROHS

PCS

Q56

29

T03.134700-12R

FB DCR=0.7-3A(1206),ROHS

PCS 22

L2,L4,L5,L10,L19,L30,L32,L34,L38,L40,L83L3,L20
L16,L23,L47,L55,F3,L1,D8,L22,L25

30

T03.134700-06R

FB DCR=0.7-1A(0603),ROHS

PCS 17

L6,L7,L9,L17,L18,L31,L74L11,L12,L13,L24,L28,L29,L45,L66,L68,L73

31

T03.504150-10R

15uH/1A DR105-SERIES ROHS

PCS

L8

32

T01.365000-06R

0 0603 1/16W 5% ROHS

PCS 18

R3,R113,R154,R156,R282,R297,R355,R371,R382,R387,R374,R70,R291,R29
5,R285,R298,R322,R325

33

T01.365100-06R

10 0603 5% ROHS

PCS 14

R54,R133,R135,R136,R137,R139,R140,R141,R142,R143,R146,R284,R230,R
417

34

T01.365121-06R

120 0603 5% ROHS

PCS

R63,R40,R42

35

T01.365470-06R

47 0603 5% ROHS

PCS 20

R28,R29,R33,R45,R48,R51,R81,R83,R84,R90,R91,R92,R123,R130,R131,R13
2,R434,R459,R504,R505

36

T01.365750-06R

75 0603 5% ROHS

PCS 18

R30,R31,R35,R46,R50,R53,R62,R86,R87,R88,R110,R128,R129,R235,R236,R
246,R232,R506

1/5

:CX-MST106-V3.0

Date:2009-10-21

37

T01.365101-06R

100 0603 5% ROHS

PCS 30

R21,R103,R105,R111,R114,R165,R166,R167,R249,R274,R278,R294,R305,R
311,R338,R388,R76,R176,R312,R316,R358,R359,R401,R402,R403,R425,R42
6,R428,R476,R715

38

T01.365153-06R

15k 0603 5% ROHS

PCS

R60

39

T01.365560-06R

56 0603 5% ROHS

PCS

R72,R73,R104,R117,R118,R390,R395,R396

40

T01.365471-06R

470 0603 5% ROHS

PCS

R56,R79,R138,R256,R317,R323,

41

T01.365102-06R

1K 0603 5% ROHS

PCS 20

R16,R24,R26,R27,R47,R107,R116,R157,R175,R178,R260,R286,R320,R420,R
452,R658,R427,R429,R321,R367

42

T01.365220-06R

22 0603 5% ROHS

PCS

R74,R75,R97,R102,R394

43

T01.365221-06R

220 0603 5% ROHS

pcs

R435,R436

44

T01.365472-06R

4.7K 0603 5% ROHS

PCS 37

R17,R177,R188,R215,R221,R222,R237,R241,R248,R275,R276,R319,R329,R
334,R339,R340,R347,R349,R373,R376,R384,R391,R392,R393,R397,R453,R4
73,R657,R708,R710,R712,R713,R714,R718,R379,R409,R293

45

T01.365331-06R

330 0603 5% ROHS

PCS

R78

46

T01.365103-06R

10K 0603 5% ROHS

PCS 47

R15,R19,R20,R22,R32,R36,R44,R57,R64,R80,R85,R101,R112,R119,R121,R1
22,R149,R158,R161,R207,R253,R259,R280R306,R307,R335,R336,R353,R38
9,R399,R400,R404,R410,R411,R412,R413,R414,R416,R418,R419,R475,R484
,R709,R71,R254,R5,R711

47

T01.365332-06R

3.3K 0603 5% ROHS

PCS

R292

48

T01.365223-06R

22K 0603 5% ROHS

PCS

R108,R109,R152,R153,R289,R423,R380

49

T01.365123-06R

12K 0603 5% ROHS

PCS

R34,R38,R82,R89,R106,R115

50

T01.365330-06R

33 0603 5% ROHS

PCS 16

R124,R126,R150,R155,R160,R170,R181,R201,R203,R205,R217,R219,R220,
R223,R239,R240

51

T01.365333-06R

33K 0603 5% ROHS

PCS

R58,R224,R495

52

T01.365473-06R

47K 0603 5% ROHS

PCS 22

R145,R192,R195,R196,R210,R211,R216,R225,R226,R227,R228,R234,R252,
R279,R281,R287,R301,R308,R314,R309,R296,R352

53

T01.365822-06R

8.2K 0603 5% ROHS

PCS

R204,R229

54

T01.365226-06R

2.2M 0603 5% ROHS

PCS

R212,R214,R283,R290

55

T01.365152-06R

1.5K 0603 5% ROHS

PCS

R231

56

T01.365202-06R

2K 0603

5% ROHS

PCS

R243,R258

57

T01.365104-06R

100K 0603 5% ROHS

PCS

R251,R262,R272,R482,R503

58

T01.365511-06R

510 0603 5% ROHS

PCS

R255

59

T01.365133-06R

13K 0603

PCS

R302,R304

60

T01.365273-06R

27K 0603

5% ROHS

PCS

R324

61

T01.365513-06R

51K 0603

5% ROHS

PCS

R328

62

T01.365183-06R

18K 0603 5% ROHS

PCS

R348,R356

63

T01.365681-06R

680R 0603

PCS

R406,R407

64

T01.365393-06R

39K 0603

5% ROHS

PCS

R422,R496

65

T01.365272-06R

2.7K 0603 5% ROHS

PCS

R415,R491

66

T01.365303-06R

30K 0603 5% ROHS

PCS

R424

67

T01.365122-06R

1.2K 0603 5% ROHS

PCS

R488

68

T01.365151-06R

150R 0603 5% ROHS

PCS

R502

69

T01.365682-06R

6.8K 0603

PCS

R507,R369

70

T01.385122-08R

1.2K 0805

PCS

R1,R4,R332,R333

71

T01.361901-06R

909 0603 1% ROHS

PCS

R2

5% ROHS

5% ROHS

5% ROHS
5% ROHS

2/5

:CX-MST106-V3.0

Date:2009-10-21

72

T01.361102-06R

1K 0603 1% ROHS

PCS

R8,R9

73

T01.361391-06R

390 0603 1% ROHS

PCS

R10 ,R59,R457

74

T01.361622-06R

6.2K 0603 1% ROHS

PCS

R14

75

T01.361202-06R

2K 0603 1% ROHS

PCS

R18

76

T01.361151-06R

150 0603 1% ROHS

PCS

R120

77

T01.361103-06R

10K 0603 1% ROHS

PCS

R244,R69,

78

T01.361221-06R

220 0603 1% ROHS

PCS

R245

T01.935270-06R

EZJZ1V270RA 0603

T01.935100-06R

ICVL1018100Y500FR

80

T01.205150-00R

81

T01.865220-06R

82

79

PCS 10

DD19,DD20,DD28,DD29,DD52,DD16,DD17,DD41,DD42,DD43,

15R/2W ROHS

PCS

R147

22R 4P 0603 1/16W 5% ROHS

PCS

RP10,RP17,RP34,RP38

T01.865330-06R

33R 4P 0603 1/16W 5% ROHS

PCS

RP12,RP13,RP16

83

T01.865470-06R

47R 4P 0603 1/16W 5% ROHS

PCS

RP14

84

T01.865560-06R

56R 4P 0603 1/16W 5% ROHS

PCS

RP35,RP36,RP37

85

T01.865101-06R

100R 4P 0603 1/16W 5% ROHS PCS

RP41,RP42,RP43,RP44,RP46,RP47,RP48,RP49,RP50

86

T02.336330-06R

33PF 16V +80-20% 0603 ROHS

PCS

C167,C171,C398,C172,C173

87

T02.364103-06R

10NF 50V 10% 0603 ROHS

PCS 10

C3,C230,C277,C317,C318,C347,C177,C275,C345

88

T02.336331-06R

330PF 16V +80-20% 0603 ROHS

PCS

C19,C21,C27,C40,C64,C74

89

T02.336105-06R

1uF 16V +80-20% 0603 ROHS

PCS

C24,C301,C378,C448,C463

90

T02.336473-06R

47NF 16V +80-20% 0603 ROHS

PCS 19

C16,C17,C23,C42,C45,C46,C48,C49,C51,C56,C57,C58,C77,C78,C82,C96,C10
0,C72,C88

91

T02.336104-06R

0.1uF 16V +80-20% 0603 ROHS

PCS 116

C44,C67,C92,C125,C126,C127,C128,C131,C155,C164,C168,C169,C174,C175
,C183,C184,C185,C187,C191,C306,C316,C344,C441,C443,C852,C853,C854,
C13,C14,C41,C69,C98,C99,C103,C106,C108,C109,C110,C111,C118,C119,C1
29,C138,C143,C170,C176,C181,C182,C196,C197,C198,C199,C200,C215,C26
6,C267,C281,C310,C334,C336,C348,C406,C446,C456,C465,C36,C245,C371,
C372,C373,C374,C375,C376,C380,C381,C385,C386,C387,C390,C393,C394,C
395,C399,C400,C401,C402,C403,C407,C408,C409,C410,C411,C412,C415,C4
16,C417,C418,C420,C421,C428,C433,C434,C435,C436,C437,C438,C439,C44
0,C459,C186,C212,C213,C270,C341,C349,C343

92

T02.336225-06R

2.2uF 10V +80-20% 0603 ROHS

PCS 24

C22,C28,C35,C37,C50,C55,C63,C66,C75,C229,C235,C238,C241,C242,C247,C
248,C255,C256,C257,C389,C413,C429,C460,C116

93

T02.336561-06R

560PF16V +80-20% 0603 ROHS

PCS

C26,C33,C34,C38,C47,C65,C68,C254

94

T02.336102-06R

1NF 16V +80-20% 0603 ROHS

PCS

C39,C54,C262,C43,C93,C95,C233,C239,C307

95

T02.336822-06R

8.2NF 16V +80-20% 0603 ROHS

PCS

C97

96

T02.336203-06R

22NF 16V +80-20% 0603 ROHS

PCS

C165

97

T02.336183-06R

18NF 16V +80-20% 0603 ROHS

PCS

C236,C237,C259,C260

98

T02.336100-06R

10PF 16V +80-20% 0603 ROHS

PCS

C210

99

T02.336101-06R

100PF 16V +80-20% 0603 ROHS

PCS

C211,C234,C240,C246,C252,C314,C315

100 T02.336204-06R

220NF 16V +80-20% 0603 ROHS

PCS

C258,C346,C404,C414

101 T02.346106-12R

10UF 10V +80-20% 1206 ROHS

PCS 35

C30,C52,C53,C70,C80,C115,C117,C193,C283,C284,C313,C464,C469,C370,C
377,C379,C383,C384,C388,C391,C396,C405,C422,C425,C426,C454,C249,C2
61,C265,C269,C280,C308,C311,C312,C331,

102 T02.233476-57R

47uF/16V(5*7)ROHS

PCS

CA72,CA73,C243

103 T02.233104-57R

100uF/16V(5*7)ROHS

PCS 10

CA2,CA9,CA39,CA47,CA51,CA52,CA464,CA465,C455,C458

3/5

:CX-MST106-V3.0

Date:2009-10-21

104 T02.233477-8BR

470uF/16V(8*12)ROHS

PCS

CA3,CA6,CA8,CA15,CA50,CA55,CA61,CA62,

105 T02.223477-6QR

470uF/10V,6*12

PCS

C244

106 T07.190021-00R

SCART

Scart 21PIN PCS

P14

107 T07.23001D-00R

HDMI

HDMI-01D ROHS

PCS

CON9

108 T07.160001-0AR

SVIDEO JACK SW-4-10 4PIN

PCS

CON16

109 T07.102017-19R

2*17*2.0mm()ROHS

PCS

CON11

110 T07.102005-19R

5PIN 2.0mm()ROHS

PCS

CN31

111 T07.102006-19R

6PIN 2.0mm(ROHS

PCS

CON2

112 T07.102009-19R

9PIN 2.0mm()ROHS

PCS

CON37

113 T07.102004-19R

4PIN 2.0mm(

PCS

CON31

114 T07.200000-16R

VGA

VGAHDR15SNGDIP

PCS

CON7

115 T07.013505-00R

Phone Jack 5PIN CKX-3.5-20

PCS

CON8

116 T07.013055-00R

Phone Jack 7PIN PJ-3055

PCS

HP1

117 T07.112504-19R

4PIN 2.54mmROHS

PCS

CN21

118 T11.002048-49R

XTAL,
20.48MHZ,33pF,30ppm,U49S,DIP

PCS

X1

119 T11.000012-49R

XTAL, 12MHZ,20pF,30ppm,U49S,DIP PCS

Y5

120 T11.000004-49R

XTAL, 4MHZ,20pF,30ppm,U49S,DIP PCS

Y4

121 T19.209E89-00R

-9E89,28x28x10mm,
,ROHS

PCS

TO MST106

122 T50.190000-10R

0.3

PCS

R398

3.3V

PCS

R386

5V

PCS

R7

12V

TO MST106

T03.134700-12R

2DC

FB DCR=0.7-3A(1206),ROHS

T07.020003-11R DC

DC POWER JACK JS-DC014KA


2.0 mm,ROHS

PCS 1 CON5

T50.000030-05R

30mmx0.5mm ROHS

PCS 1 F2

T06.109483-00R

EC9483

SOP-8 ROHS

PCS

1 U47

T03.504150-12R

SMRH127-150M ROHS

PCS

1 L33

T04.80SK34-00R

SK34,SMD,DO-214,ROHS

PCS

1 D12

T06.107314-00R

IRF7314 SOP-8 ROHS

PCS

1 U13

3
1

T06.109483-00R

EC9483

SOP-8 ROHS

PCS

1 U47

T03.504150-12R

SMRH127-150M ROHS

PCS

1 L33

T04.80SK34-00R

SK34,SMD,DO-214,ROHS

PCS

1 D12

T06.107314-00R

IRF7314 SOP-8 ROHS

PCS

1 U13

426
1

T03.134700-12R

FB DCR=0.7-3A(1206),ROHS

PCS

1 R25

T07.112513-19R

2.54MM,1X13 DIP180,ROHS

PCS

1 CON21

4/5

:CX-MST106-V3.0

Date:2009-10-21

5DVDYPBPR
1

T01.365000-06R

0 0603 1/16W 5% ROHS

PCS

3 R93,R94,R95

6DVD
1

T06.10V330-00R

PI5V330 TSOP16 ROHS

PCS

1 U17

T02.346106-12R

10UF 10V +80-20% 1206 ROHS

PCS

6 C89,C90,C91 C79,C85,C87

T07.102005-19R

5PIN 2.0mm()ROHS

PCS 1 CON4

T07.102006-19R

6PIN 2.0mm(ROHS

PCS 1 CON34

T07.102003-19R

3PIN 2.0mm(ROHS

PCS 1 CON35

T07.102004-19R

4PIN 2.0mm(

PCS 1 CON13

T02.233477-8BR

470uF/16V(8*12)ROHS

PCS

2 CA5,CA10

7AV, YPBPR
1

T07.062562-01R

AV

()ROHS

PCS

1 CON23

YPBPR+AV

T07.062492-00R

AV

(),
ROHS

PCS

1 CON23

AV

pcmica

pcmica CI
NC7SZ32 SOT-23-5

PCS
PCS

1 CONN1
1 U27

CEM4953

PCS 1 U7

8CI
1
2
3

T07.2200CI-00R
T06.17SZ32-00R

T06.104953-00R

SOP-8

T04.804001-00R

1N4001,SMD,SMA,ROHS

PCS 2 D4,D5

5
6

T04.805819-00R
T02.346106-12R

IN5819,SMD,DO-214,ROHS
10UF 10V +80-20% 1206 ROHS

PCS
PCS

1 D6
1 C461

9YPBPR
1

T06.10V330-00R

PI5V330 TSOP16 ROHS

PCS

1 U17

T02.346106-12R

10UF 10V +80-20% 1206 ROHS

PCS

6 C89,C90,C91 C79,C85,C87

10268

1
2
3
4
5
6
7

0 0603 1/16W5% ROHS


0 0603 1/16W5% ROHS

47K 06035% ROHS


0 0603 1/16W5% ROHS

LM4558 SOP-8 ROHS


13K 06035% ROHS
10K 06035% ROHS
47K 06035% ROHS
10K 06035% ROHS
22K 06035% ROHS
470 06035% ROHS

1PCS

2PCS
2PCS
2PCS
2PCS
2PCS
2PCS

U32
R288,R299
R291,R295
R285,R298
R127,R144
R296,R352
R322,R325

5/5

PO NO.:T0908-03 LT-2298(21.6)

STL-02

AO

Date:2009-08-31

T44.1E2298-20R

LT-2298 (21.6").ROHS

SET

T43.2298QK-02R

HIPSLOGO"AXXION"ROHS

PCS

L216S60

T43.2298HK-00R

HIPS
PCS
8ACROHS

L216S

T43.2298ZS-01R

PVCROHS

PCS

L216S60

PCS

L185F

T43.1998AJ-00R

ABS,7
ROHS

T43.1998GZ-00R

PMMAROHS

PCS

L15F6

T43.2298JX-00R

HIPSMSTAR 106SCART+AV)ROHS

PCS

L22S

T43.2298DY-00R

HIPS22ROHS

PCS

L22S

T43.2298DB-00R

HIPSMSTAR 106
SCART+AV)DCROHS

PCS

L22S

T43.1998LZ-01R

HIPSROHS

PCS

L19S

10

T43.1998LD-00R

ROHS

PCS

L19F5

11

T43.3298BG-00R

PCM6

PCS

L32S

12

T43.1998DZ-00R

HIPSROHS

PCS

L19S

13

T43.3298JD-00R

16*6ROHS

PCS

L32S

T43.1998ZZ-00R

SGSST=2MM

PCS

L19S

T43.2298LP-00R

SGSST=1MM

PCS

L216S

T43.2298PY-00R

SGSST=0.8MM

PCS

L22F5

-(3),-(2),-(2),
-(8),-(4),
36 -(4),-2
-4-(4),
-3

T16.213008-00R

BA3*8 ,,ROHS

PCS

T16.243010-01R

BB3*10,,,,ROHS

PCS 18 -(2),AC(2)

T16.244012-01R

BB4*12,,,,ROHS

PCS

-(4)

T16.413010-11R

PWA3*10w=11mm,,ROHS

PCS

-4

T16.234008-01R

BM4*8,,ROHS

PCS

-(3)

T16.233005-00R

BM3*5,,,ROHS

PCS

-(4)

L-2298W21.6")T0908-03ROHS

PCS

-(10),-4-

T34.090803-00R

.!

PCS

T28.138120-30R

380*120()*0.05mm,,PE(),
PCS

T50.010012-00R

12MM ROHS

T32.070015-00R

71.5V,ROHS

PCS

T23.250180-55R

250*180*55MM,ROHS

PCS

T45.500320-00R

22 500*320*0.1mmPVC,ROHS

PCS

T50.010030-10R

3M ROHS

1
.02

.01

T29.090803-03R

PVC7T=0.3mmVOL-,VOL+,CHPCS
,CH+,MENU,SOURCE,POWER"

10

T29.090803-01R

79*59mm,,ROHS

PCS

11

T29.090803-02R

262*14*0.3mm,PVC,3M,MSTAR 106
SCART+AVROHS

PCS

page 1 of 2

PO NO.:T0908-03 LT-2298(21.6)

STL-02

AO

T29.090803-04R

12

T29.TXM000-05R

13

T29.QC0000-04R

14

Date:2009-08-31

PCS

09.09.24

9248034500001--9248034503920

PCS

11

QC

QC PASSED

PCS

T29.ROHS00-14R

ROHS

PCS

15

T28.165600-30R

650*600*0.05mmPE
)

PCS

16

T31.142298-03R

LT-2298W,EPS

17

T39.090803-00R

596*222*460mmROHS

PCS

09.09.17

18

T40.500001-00R

PCS

.!

19

T50.010060-00R

60MMROHS

.02

20

T41.102810-00R

,280*10*0.2mm,ROHS

PCS

21

T41.105010-00R

,500*10*0.2mm,ROHS

PCS

CX-MST106-V3.0

PCS

BOM

,:V216B1-P01

PCS

PCS

PCS

PCS

PCS

PCS

.!!!

T54.MS1063-02R

2
3

T37.090803-01R

T53.07B060-00R

T37.090803-02R

T26.114070-50R

T37.090803-10R

T25.23VDE0-02R

() 2*0.75mm2 L=1.5M

PCS

T07.21F180-00R

AC

RF-180(),ROHS

PCS

10

T37.090803-05R

PCS

11

T40.403000-00R

3*15mm,ROHS

PCS

12

T42.000506-CXR

CX-506

PCS

6*6*5mm),ROHS

PCS

PCS

9E19+98

PCS

IR:5011 9X19+98 ,,
35*18*1.6MMROHS

PCS

PCS

60W,4,ROHS AC
AIP4904002A-G

4/3W,4070,ROHS

:T55.020908-03R
1

T09.812665-01R

T37.090803-07R

T15.022011-00R

PCB

KEY: 2011

T55.030908-03R
1

T15.035011-02R

PCB

T37.090803-08R

T05.408238-00R

LMC 8238(2638) ROHS

PCS

T02.233476-11R

47UF/16V(5*5MM),ROHS

PCS

T04.67W030-25R

LED

3.0 (/),,(),ROHS

PCS

T01.285100-00R

10 1/8W,ROHS

PCS

09.09.19

page 2 of 2

MST Chassis
Program Writer UserGuide

JINPIN ELECTRIAL COMPANY LTD. ZHUHAI S.E.Z


Add:No.15,PingBei 2nd Road, Nan Ping Technology & Industrial Park, Zhuhai,
Guangdong, China.
Tel:(86-756)3837798
3837386

Http://www.jinnpina.com.cn

Software Upgrade
Preparing :
Connect LPT-VGA download tool line, One connector is connected to VGA
connect port of Plasma TV ,while another side is connected to PC Parallel port . PC
CMOS setup the Parallel port is ECPmode.
Store the MST ISP Tool into the PC.

Figure 1.

Figure 2

3
Figure 3.
1) ISP-tool.rar,
Release the zip file ISP tool.rar send shortcut key to the desktop, clicking the
program icon when the icon displays in the Start Menu and the desk. Clicking the icon

Figure 4.

Downloading :
2) ISP
Dblclick ico, Run ISP_TOOL.exe
3) Read
click Read ico, Select the update binary by pressing browse button,Follow setp1,2,3,4

Figure 5.

4).
Turn on the LCD TV power supply.
5).
a.Connect,.
Select the connect ico, display dialog the connect is ok.

EN25F32

6
Figure 6.
b. AutoRUN,
Select the Auto ico, Press Run Upgrade button and start update process.

Figure 7

Figure 8.

c.
The update process is successful as the display End time:xx:xx:xx. After the
update process is ok,

Figure 9.

6errorRun
If display error, repeat click Run.
7)
turn off power and wait indicator light is off. Turn on power and TV can work.
8
Done.

2007-10-19

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