From: Phm Tun Vng , L nh Trung

Group :AP_Course 54
To: ESRC LAB
Weekly Report
Dear,
We have finished first 4 labs and are proceeding lab 5.
Lab 1: Switches, Lights, and Multiplexers
We presented its report at last weekend
Lab 2 : Numbers and Displays
Part 1:
Requirement: Designing a circuit that displays a 2-digit BCD number on 2 7-segment LEDs .
Solution: Deriving 7 logic functions for output of 7 segments. Minimize and write them in
VHDL code in form of Boolean expression
Part 2:
Requirement: Designing a circuit that converts 4-bit binary number into its 2-digit decimal
equivalent.
Solution: From truth table of Circuit A, Circuit B, Comparator ,we derive their logic functions.
Base on the main block circuit, we combine the component using port map statement
Part 3:
Requirement: Designing 4-bit ripple-carry adder circuit
Solution: Writing a VHDL entity for a full adder sub-circuit. Add this to the top-level one
instantiates 4 instances of full adder . After component declaration and port-mapping, we got
the required circuit.
Part 4:
Requirement: Designing a BCD adder . The inputs to the circuit are BCD numbers A and B,
plus a carry-in. The output should be a two-digit BCD sum.
Solution:
Firstly, we need 2 4-bit ripple-carry adders from part 3 to implement operations A+B+cin and
S+ 0110 (S is the 4bit sum output from operation A+B+cin)
Secondly, we need a 4bit multiplexer 2 to 1 using Carry out of operation (A+B+Cin) to select
S if Carry out = 0, select (S+0110) if Carry out= 1.
Thirdly, reconfiguring the circuit in part 2 a little bit to get new sub-circuit that contain one more
input C (C is carry out of operation A+B+cin).we change the part 2 circuit at , before the
output signal z of comparator goes directly to circuit B, it will be ORed with C.
Next, connecting outputs of circuit 4bit mux 2to1 and Carry out to inputs of the circuit in step
3. There we completed a part of main circuit.
Finally, we have to design a comparator circuit that compares A and B with 9, and then sends
result 1 to LEDG7 if one or both of them are larger than 9. We use the component comparator
in part 2 to implement this one.
Part 5:
Requirement: implement the similar circuit as part 4 but using another method. Using condition
statements. Compare RTL view of between part 4 and part 5
Solution: Using if else ,when case statement to implement, basing on pseudo-code.
Compare: RTL structure of 2 parts are not too much different. But time for implementing part 5
is much less than part 4
Part 6:
Requirement: designing a circuit that converts 6-bit binary number into decimal number
displayed on 7- segment LEDs
Solution: Using Double Dabbe (shift-add 3) algorithm and for/loop ,if-else condition statements.

Lab 3: Latches, Flip-ops, and Registers

Lab 4: Counters
Lab 5: Clocks and Timers

Problem:
when I compiled and tested my entity on quartus and kit, it ran well. But when I simulated it on
model-sim, it didnt work. Model sim warned that: in my main circuit my components that are
port mapped are not bounded.
Thanks for reading