I.

INTRODUCTION:
Designing the reliable and robust telecommunication system faces a stiff hurdle from non-ideal
behavior of the intermediate channel between transmitter and receiver. One major challenge is to
keep the communication error-free to combat against the adverse effect of Inter-Symbol
Interference (ISI). Due to this phenomenon, previous samples from transmitted signals interfere
with the current one and thus a corrupted data is received. Moreover, if the speed of
communication has to increase, the effect of ISI increases for obvious reason. One way to
mitigate the effect of ISI is to design a channel equalizer based on the known information about
the communication channel. As described in [Rappaport] the channel equalization problem is
broadly classified into two families, namely non-adaptive channel equalization and adaptive
channel equalization. Equalizing a real-world time varying communication channel requires an
adaptive method because in this method information about ever-changing channel is gathered in
specific time interval and based on that information equalization is done. One approach to design
an adaptive equalizer is to employ an adaptive error-minimization algorithm [Haykin]. A few
popular error-minimization algorithms are Least Mean Square (LMS), Recursive Least Square
(RLS) etc. Among them, LMS algorithm is most popular and widely used due to its simplicity in
implementation and lesser computational complexity.
Implementation and performance analysis of adaptive error-minimization algorithm based
channel equalizers has already been done in simulation platform. As a next step, hardware
implementation of the same design is also done using Field Programming Gate Array (FPGA)
hardware boards using VHSIC Hardware Description Language (VHDL). In this approach
extensive coding in VHDL language is to be done to construct the equalizer and present the
design to the hardware board in an understandable way (bit stream) so that the board can
accommodate the design using the built-in resources. In the current paper, an alternate approach
to implement LMS algorithm based Additive White Gaussian Noise (AWGN) channel equalizer
is presented employing a special technique namely Hardware Cosimulation. The feature that
makes this approach very attractive is that it does not require extensive coding in VHDL to
construct the equalizer in hardware domain. It uses a few built-in programming blocks
performing elementary arithmetic operations to build the whole design. Or in other words, it can
be said that the whole design is being quantized in small operational blocks which eventually
contains codes understandable to hardware boards. This approach makes designing an LMS-
based channel equalizer very convenient.
In the current work, firstly the basic LMS algorithm is briefly described to understand the
operating principle of the designed channel equalizer in section II. Next the basic system model
on hardware FPGA based design platform and working principle of Hardware Cosimulation
method is described is section III. In section IV the simulation model and whole design is shown
along with the hardware board specification and related software environment. Next in section
V, we describe the detailed performance analysis (both from equalization point of view and
hardware resource point of view) of the channel equalizer for various channel signal to noise
ratio (SNR) value, tap length and step size of the equalizer.
II. BASICS OF ADAPTIVE CHANNEL EQUALIZATION AND LMS
ALGORITHM
A typical telecommunication system designed to employ LMS algorithm in the equalizer in
receiver section is shown in the following figure:
[INSERT SYSTEM MODEL of fig: 5.1 of thesis]
The input information in the form of bits is being sent to the channel featuring additive white
Gaussian noise with specific channel SNR value. Obviously the channel output will be affected
heavily by the channel noise and more importantly, the inter symbol interference (ISI) occurred
due to non-ideal behavior of the channel. So, to retrieve the actual information from the
corrupted bit stream, a channel equalizer must be utilized to nullify the effect of the channel. The
channel equalizer employs LMS algorithm to execute supervised learning.
The LMS algorithm is the readymade adaptation of the learning rule described by Widrow and
Hoff [8 of thesis]. The LMS algorithm is an iterative procedure that constantly updates a vector
of equalizer coefficients. The weights are updated based on the mean square criterion, which
means, if 'e' be the error, then the mean-squared error is defined as:
J = [|e|]
2
(1)
The LMS algorithm updates the filter coefficients based on gradient of eqn. (2.13), the gradient
being calculated with respect to the filter weights. Every iteration performed in LMS algorithm is
associated with a vector representing the filter weights and an error corresponding to that vector;
the main objective of LMS algorithm is to find at what value of the filter coefficient vector, the
error is minimized. The functional block diagram of LMS algorithm is shown below:
[INSERT BLOCK DIAGRAM OF LMS, fig: 2.7 of thesis]
A detailed description and statistical treatment of LMS algorithm is found in [HAYKIN] and
[FARHANG]. The basic steps of the algorithm are given here:
(i) Initialize the algorithm:
by specifying step size () of the algorithm.
w(n) = 0(Null vector);
(ii) For every iteration n=1,2,3.
Compute:
y(n) = w
H
(n)u(n);
e(n) = d(n) y(n);
w(n+1) = w(n) + e(n)u(n);
end
III. FPGA BASED DESIGN PLATFORM AND THE HARDWARE COSIMULATION
TECHNIQUE
We have conducted a comprehensive study in Spartan-6 based design platform. The hardware
board is manufactured by Digilent Inc. USA. The model number of the FPGA device is
XC6SLX45. The Spartan-6 FPGA board's salient resource features are summarized in the
following table.
[INSERT Fig. 3.3 & Table 3.1 of THESIS]
A detailed report on resource packaging and I/O distribution with working principle of each
block tabulated above is found in [42, 43 of thesis].
Hardware Cosimulation is a co-operative programming environment working as a bridge
between MATLAB/SIMULINK and Xilinx VHDL compiler. In this method, by employing a
special plug-in (available in official Xilinx website) a handful of special Simulink blocks
representing various arithmetic and/or logical FPGA operations can be availed (obviously, these
special blocks are not available in normal SIMULINK platform). Actually this Hardware
Cosimulation technique offers an environment for multi-domain simulation and model-based
design for dynamic and embedded systems. It is a powerful tool to incorporate hardware into
SIMULINK design [46 of thesis]. A detailed working principle of this method is found in [45 of
thesis].
The LMS channel equalizer is designed block by block using the hardware Cosimulation
blocks found from Xilinx ISE-supported Simulink environment. These blocks generically
contain the necessary VHDL code required to perform the necessary task assigned to the block.
the whole design of the AWGN channel equalizer employing LMS algorithm in Hardware
Cosimulation is shown in the following figure:
[INSERT Fig 5.3 of thesis]
The whole design presented in Fig 5.3 is actually an integrated structure using various
elementary blocks like adder/subtracter, scalar multiplier, memory element like register etc. this
programming structure as a whole is compiled to a bit file which is an understandable version to
the hardware. The bit file is finally executed by the hardware FPGA processor-equipped board
and delivers the equalization error as the output. The equalization error is observed as the output
due to the fact that this entity can be analyzed to check both the convergence nature of the
designed algorithm as well as a measure of channel equalization accuracy.