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Slide 1

Optimization of Patch Antennas


Authored by:
Tony Donisi
Ansoft Corporation
Ansoft 2003 / Global Seminars: Delivering Performance
Presentation #10
Slide 2
Introduction
Overview
Single Patch Element Design
Linear Patch Array
Corporate Fed Patch Array
System and Circuit Integration
Conclusion
Goal: To introduce a more effective and streamlined design flow for
systems with patch antennas that leverage Parameterization, Solver-On-
Demand and Co-Simulation
Slide 3
Designer Capability Overview
Designer can accurately simulate very large structures, quickly!
SVD fastsolve
Low memory requirements
Geometries can be drawn or imported
User friendly GUI
Dxf, iges, and popular geometry imports
Ansoft Links for Allegro and other CAD tools
Full Parameterization
Solver on Demand
The ability of designer that lets the user decide which solver to use on an element by
element basis
Co-Simulation
The capability of designer to seamlessly integrate circuit, system and EM simulations
Slide 4
Single Patch Design
Designer allows easy design of single patches
Patch estimator tool gives a good first approximation
Fully parameterized single patch will be created
Solution for a range of geometries
Patch characteristics will be plotted
Functions of geometry, Frequency
Current and field distributions
Plots can be animated
Real time tuning
Both 2D and 3D plotting available
Slide 5
Patch Estimator Tool
Integral patch estimator tool
Slide 6
Single Patch: Recessed feed
WPatch
LPatch
Wf1
Lfeed
Wfeed
WSlot
LSlot
This Patch can be used as either a full
planar EM model or a Solver on
Demand component
This Patch can be used as either a full
planar EM model or a Solver on
Demand component
Z
in
) L
L
( Cos
) G G ( 2
1
R
slot
Patch
2
12 1
in

=
2
3
0
2
patch 0
1
120
d Sin
Cos
) Cos W k ( Sin
G

d Sin ) Sin L k ( J
Cos
) Cos W k ( Sin
120
1
G
3
patch 0 0
0
2
patch 0
2
12

=
Slide 7
Single Patch Design Procedure
Use Patch Estimator to get starting point
10mil Duroid 5880
Frequency 10GHz
Resulting Width and length 393 mil
Also gives a starting point for Lslot
Nominal patch frequency response
Lslot and Wslot will have minimal effect on
center frequency
Adjust Wpatch if necessary
Vary Lslot and Wslot to get Best VSWR
Assume 100
Lslot from 10mil to 100 mil
Wslot from 30mil to 150mil
Edge meshed to concentrate at Edges
Slide 8
Single Patch Frequency Sweep
Sweep of Frequency
and LSlot. Note
Frequency response is
not centered at 10GHz
Sweep of Frequency
and LSlot. Note
Frequency response is
not centered at 10GHz
Sweep of Frequency and
Wpatch. As the
frequency increases, it
is obvious that LSlot will
need further adjustment
Sweep of Frequency and
Wpatch. As the
frequency increases, it
is obvious that LSlot will
need further adjustment
Slide 9
Single Patch Optimization
Designer allows the user
to optimize with respect to
any variable, Including
field quantities.
Slide 10
Single Patch Parameter Results
Smith plot of input Match Versus Slot
width and length.
Smith plot of input Match Versus Slot
width and length.
Optimal Match
(100) at
Wslot = 50mil
Lslot=127mil
Optimal Match
(100) at
Wslot = 50mil
Lslot=127mil
Slide 11
Single Patch Scalar Return Loss
Parametric sweep of return loss
with respect to Wslot and Lslot
Parametric sweep of return loss
with respect to Wslot and Lslot
Slide 12
Single Patch Real Time Tuning
Slide 13
Single Patch Far Field & Near Field
Slide 14
Patch Arrays
Patches can be arranged various Arrays
Two examples will be shown
Linear array
Both x- and y- patches variable
Corporate Array
Arrays will be built with previous patches
100 impedance
Feed networks will be considered
Feeds have impact on antenna performance
Many, many feed designs
Slide 15
Patch Array Feed Networks
Co-linear feed network
Straightforward Extension to other feed
styles
Vias
Designer has no restrictions on vias
This presentation will not take into effect
vias
Vias and feeds on other layers are
simple to add
Patch
Patch
Matching
Matching
Patch
Patch
Matching
Matching
Input
Patch
(100 )
Patch
(100 )
100 Line
100 Line
Input
Patch
(100 )
Patch
(100 )
/4
Transformer
/4
Transformer
100 Line
100 Line
Patch
(100 )
Patch
(100 )
/4
Transformer
/4
Transformer
Slide 16
Linear Array
Patch antenna with feed
Patch dimensions as previously outlined
Quarter wave transformers
The number of patches can be large
nx Set as number of x-dimension Patches
ny Set as number of x-dimension Patches
Lambda4
W01
Lf1
dx
dy
Lf1
Quarter Wave
transformer sections.
Width and length
parameterized for user
optimization
Slide 17
Analysis Overview
One structure can represent
Circuit
Planar EM
Circuit provides quick analysis
Match and VSWR information
Planar EM provides
Fields
Full match and VSWR information
Near field and far field information
Current Distributions
A sample patch array is built to utilize:
Solver on demand
Equivalent Circuit modeling
Full parameterization
Parameter passing
Slide 18
Component Description
The Patch Array will consist
of:
Component
Represents the overall patch
Contains parameters, circuit
equivalent
Footprint
Contains geometry information
Can be scripted in VB or Java
Full script of patch can be found in
appendix
Symbol
Schematic representation of patch
Circuit equivalent
Slide 19
Design Procedure
1. Determine Geometry and parameters
2. Create parameterized footprint
Standard drawing of polygons or shapes
VBscript or JavaScript
3. Create circuit equivalent
4. Create symbol
5. Generate component
6. Optional: Create circuit equivalent
Once this is done the user has a flexible Solver on
Demand component that can be used as a versatile
stand alone design or as part of a larger scale circuit
or system design.
Once this is done the user has a flexible Solver on
Demand component that can be used as a versatile
stand alone design or as part of a larger scale circuit
or system design.
Slide 20
Patch Array Design
One row, nx = 4 (4 elements) nominal
Same patch as previously designed
10mil, 2.2 RT Duroid
50, 8 mil, 70.7, 17mil, 50, 30mil
Contains parameters, circuit equivalent
/4 = 218 mil
The spacing between elements is important
Orthogonal pattern
Normal to x-y plane
Patch elements must be fed in phase
Feeding the patches
in phase will make the
pattern orthogonal to
the x-y plane. This
will occur when the
separation is an
integral multiple of a
wavelength
Slide 21
Performance Plots
Gain Vs dx
Gain Vs dx
Return Loss
Return Loss
N=4, dx= 600mil
Nominal
N=4, dx= 600mil
Nominal
Slide 22
Swept Plots
Effect of varying dx versus frequency
Effect of varying dx versus frequency
Effect of varying dx on the 3D gain pattern,
from 500mil to 1200mil. The optimal
gain/direction occurs between 800mil and 100mil
Effect of varying dx on the 3D gain pattern,
from 500mil to 1200mil. The optimal
gain/direction occurs between 800mil and 100mil
Slide 23
4-Element Phased Array
Previously designed recessed patch
Array of 4 elements
Fully parameterized
Input Phase and amplitude can be set to
variables
These can be modified to observe field patterns
Designer allows the user
to feed the ports with
different phases and
amplitudes. These can
be set to variables to
allow for any desired feed
pattern
Designer allows the user
to feed the ports with
different phases and
amplitudes. These can
be set to variables to
allow for any desired feed
pattern
Slide 24
Small Phased Array Animation
Variables are set up for the four ports.
In this simple example, the ports toggle
between 0 and 135 in a set pattern,
based on the variable FeedControl.
Slide 25
Corporate Fed Array
A corporate array is a popular configuration
Feed structure can affect performance
Methods of analysis
Infinite array
Finite array without feed
Finite array with feed
Slide 26
Corporate Feed Patch Geometry
Assume 4-Unit Cell
Recessed Slot Patch
Patch dimensions
Calculated previously
Variable number of patches
dx
dy
Wpatch
W100
Lf1
(0,0)
LSlot
WSlot
Slide 27
Corporate Array Dimensions
Fully Parameterized
2
n
Unit Cells
Square Array
Single Feed Point
Patch may be any
dimension
VBScript Generation
Slide 28
Patch Geometry
Quarter Wave transformer
sections. Width and length
parameterized for user
optimization
This patch was created
with a VB script, located
in appendix
Slide 29
Corporate Fed 8X8 Array
Solution Details
21,267 Unknowns
343M Ram
13 Minutes
Slide 30
Corporate Fed 8X8 Array Details
Solution Plots
Slide 31
Corporate Fed 16X16 Array
Solution Details
86,428 Unknowns
121M Ram
2 Hours, 54 Minutes
Slide 32
Corporate Fed 16X16 Solutions
Slide 33
Patch as an Infinite array
Slide 34
System Co-simulation
Slide 35
Circuit, System and EM Cosimulation
Slide 36
Conclusion
An improved design flow for systems with
patch antennas has been presented
Advanced features
Parameterization
Solver On Demand
Co-Simulation
Optimization
Graphics and plotting
Field and geometry plots and animations
Integration with system and circuit tool
Slide 37
Appendix: Patch Arrays
Patches can be arranged various Arrays
Two examples will be shown
Linear array
Both x- and y- patches variable
Corporate Array
Arrays will be built with previous patches
100 impedance
Slide 38
Appendix: Linear Array
Patch antenna with feed
The wide sections are patches, narrow sections are the feeds
The lengths of the patches are equal
The lengths of the feeds are equal
The widths of the patches can vary to form a beam
The number of patches can be large
Up to 16 patches
Lpatch
dx
Wfeed
W01
W03
Wn
Patch n
W02
Slide 39
Appendix: Design Procedure
1. Determine Geometry and parameters
2. Create parameterized footprint
3. Create circuit equivalent
4. Create symbol
5. Generate component
Once this is done the user has a
flexible Solver on Demand
component that can be used as a
versatile stand alone design or as
part of a larger scale circuit or system
design.
Once this is done the user has a
flexible Solver on Demand
component that can be used as a
versatile stand alone design or as
part of a larger scale circuit or system
design.
Slide 40
Appendix: Important Linear Patch Parameters
A component can be set up with
the following parameters:
Lpatch
W1 to W16
WFeed
dx
n
These parameters fully define the
patch element
Slide 41
Appendix: Component Description
The Linear Patch will consist of:
Component
Represents the overall patch
Contains parameters, circuit equivalent
Footprint
Contains geometry information
Can be scripted in VB or Java
Symbol
Schematic representation of patch
Slide 42
Appendix: Determine Footprint Geometry
Variables
Lpatch
Lfeed = dx-Lpatch
Since rectangle objects are determined by
their center, width and height, the centers of
each of the patches/feeds will be determined.
Center x Point Chart
A Reference, (0,0)
B Lfeed/2+Lpatch/2
C Lfeed+Lpatch
D (3/2)*Lfeed+(3/2)*Lpatch
E 2*Lfeed+2*Lpatch
F (5/2)*Lfeed+(5/2)*Lpatch
Y (n-.5)*(Lfeed+Lpatch)
Z n*(Lfeed+Lpatch)
A
B C D E F Y Z
dx
Slide 43
Appendix: Creating a Footprint
dx
Slide 44
Appendix: Create Footprint Script Part 1
The script is broken into two parts for clarity
The first part sets up variables
The second part is the actual code
Note that the code section is only a few lines
One loop
Width(6) = LayoutHost.Pars.Item("W06")
Width(7) = LayoutHost.Pars.Item("W07")
Width(8) = LayoutHost.Pars.Item("W08")
Width(9) = LayoutHost.Pars.Item("W09")
Width(10) = LayoutHost.Pars.Item("W10")
Width(11) = LayoutHost.Pars.Item("W11")
Width(12) = LayoutHost.Pars.Item("W12")
Width(13) = LayoutHost.Pars.Item("W13")
Width(14) = LayoutHost.Pars.Item("W14")
Width(15) = LayoutHost.Pars.Item("W15")
Width(16) = LayoutHost.Pars.Item("W16")
Lfeed = LayoutHost.LayoutPars.Item("Lfeed")
idnum= LayoutHost.GetLayerID("anywhere")
Script Part 1 Defining all Variables
Dim W1, W2, W3, W4, W5, W6, W7, W8
Dim W9, W10, W11, W12, W13, W14, W15, W16
Dim Lpatch, Lfeed, idnum, x, n, pi, pointsvar, width(20)
set Pointsvar = LayoutHost.CreatePointsObject()
pi = 3.1415926535
n = LayoutHost.Pars.Item("n")
Lpatch = LayoutHost.Pars.Item("Lpatch")
Wfeed = LayoutHost.Pars.Item("Wfeed")
dx= LayoutHost.Pars.Item("dx")
Width(1) = LayoutHost.Pars.Item("W01")
Width(2) = LayoutHost.Pars.Item("W02")
Width(3) = LayoutHost.Pars.Item("W03")
Width(4) = LayoutHost.Pars.Item("W04")
Width(5) = LayoutHost.Pars.Item("W05")
Slide 45
Appendix: Create Footprint Script part 2
Main VB Script J ust a for/ Next Loop with incremental Parameters!
Create a Points object to Draw First line
pointsvar.Add (-1*lfeed/2),(width(1))
pointsvar.Add (n*(Lpatch+Lfeed)+lfeed/2),(Width(1))
Draw First line
layouthost.NewRect idnum, 0, 0, Lfeed,Wfeed, 0
Main Loop
for x = 1 to n
Draw Patches
layouthost.NewRect idnum, (x-.5)*(Lpatch+Lfeed),0, Lpatch,width(x),0
Draw Feeds
layouthost.NewRect idnum, (x)*(Lpatch+Lfeed),0, Lfeed,Wfeed,0
next
Manipulat Ports
LayoutHost.MovePort "n1", -1*lfeed/2,0, pi
LayoutHost.MovePort "n2", n*(Lpatch+Lfeed)+lfeed/2,0, 0
Main VB Script J ust a for/ Next Loop with incremental Parameters!
Create a Points object to Draw First line
pointsvar.Add (-1*lfeed/2),(width(1))
pointsvar.Add (n*(Lpatch+Lfeed)+lfeed/2),(Width(1))
Draw First line
layouthost.NewRect idnum, 0, 0, Lfeed,Wfeed, 0
Main Loop
for x = 1 to n
Draw Patches
layouthost.NewRect idnum, (x-.5)*(Lpatch+Lfeed),0, Lpatch,width(x),0
Draw Feeds
layouthost.NewRect idnum, (x)*(Lpatch+Lfeed),0, Lfeed,Wfeed,0
next
Manipulat Ports
LayoutHost.MovePort "n1", -1*lfeed/2,0, pi
LayoutHost.MovePort "n2", n*(Lpatch+Lfeed)+lfeed/2,0, 0
Slide 46
Appendix: Create Circuit Equivalent
A simple circuit equivalent could be made
Electromagnetic simulation is very fast
Largest problems
SVD Fast Solve
Low memory requirements
Geometries may get very large
Circuit equivalent is a good method to speed solution
Gives S-parameter equivalents
Demonstrates Designers flexibility
Slide 47
Appendix: Equivalent Circuit
Purely optional
Some designers prefer electromagnetic analysis only
May consist of any circuit element
Can be as simple as a single resistor
Can be as complex as user can describe
Is formed as a Netist line
Slide 48
Appendix: Netlist Basics
To complete the component, a Netlist line will be added
Circuit simulations run much faster than Planar EM simulations
It is desirable to have a circuit equivalent even if its just an approximation
Designer is a Netlist based program
All simulations run the engine through a netlist
This netlist is Spice compatible where applicable
The circuit geometry is similar to 3 to 33 microstrip
transmission lines
Transmission lines are well characterized within the circuit solver
Between each transmission line, there may be a step
discontinuity
The circuit equivalent would look like:
Slide 49
Appendix: Geometric Variable Setup
The largest structure (n=16) contains
16 patches and 17 Feeds : Total 33 Transmission lines
One step discontinuity between each line
Total 32 Steps
The smallest Structure (n=1) contains:
1 patch, 2 feed lines, and 3 steps
Provisions must be made in the netlist to
remove components that are not used
Accomplished by setting lengths of the unused lines to
Lpatch/1000
Widths of the Unused transmission lines set to Wfeed
Unused transitions take care of themselves
Worst case (n=1)
Total of 30 lines hanging off end of the model
Total length of Lpatch *30/1000
This is an insignificant amount
Slide 50
Appendix: Geometric Variable Setup
Variables We1 through we33 represent widths of each line
The odd numbers represent feeds
They will all have the width wfeed
The even numbers of Wexx represent patch widths
Dependent on the number of sections
16 sections, possibly 16 different width values
Case 1: n = 1
Second line (first patch) set to width We1
Remaining sections set to a width of Wfeed
Lengths are set to Lpatch/1000
Case 2: 1 < n <16
sections after the nth section are set to width Wfeed
Therefore Transmission line 2 (first patch) will always be set to We1
Lengths of the lines will be defined as L1 through L33
Depending on the value of n, these transmission lines will be set to a length
corresponding to the length of the patches & feeds, or set to a small value,
Lpatch/1000 as discussed
If statements will be used to define the lengths and widths
Slide 51
Appendix: Typical Variable Property
We32@id= \{ if \( @n < 16 , @wfeed , @w16 \) \}
The variable We32
The variable We32@id (no
space) is the syntax that tells
designer to assign a unique
identifier to the variable
We32
Open and closed brackets surround an expression in the
netlist. Designer uses brackets for special functions, so In
order to netlist correctly, the backslash character must be put
in front of the bracket or any other special character, such as
parenthesis. This tells designer to netlist this character
directly.
The @ character preceding a
variable name means that the
variable is a passed
parameter directly from the
component
The if statement in the netlist line will have the syntax
If (expression, true, false) or We32= if(n<16, wfeed, w16)
Slide 52
Appendix: Component Setup
Shown are the lines in the component and the netlist line
In the component, carriage returns are for visuals in this presentation, they will not
be in the component. The \n tells Designer to put carriage returns in the netlist
Designer puts the carriage returns in the netlist
MSTRL:@ID %0 %_101 w= @Wfeed p= \{ @dx - @Lpatch \} Sub=@sub \n
MSSTEP:@ID_ca %_101 %_1 W1= @Wfeed W2= @W01 sub=@sub \n
61 more lines
MSSTEP:@ID_bf %_132 %_32 W1= \{ We32@id \} W2= @wfeed sub=@sub \n
MSTRL:@ID_af %_32 %1 w=@Wfeed p= \{ @dx - @Lpatch \} Sub=@sub
The syntax for defined variables is different that that of the
passed parameters. We32 was defined previously, and as
explained, Designer assigned a unique ID to it. To reference
that variable in the netlist line, @id must follow the variable
name
MSTRL:1 Port1 inet_101 w= 10mil p= { 150mil - 50mil } Sub=Alumina
MSSTEP: inet_101 inet_1 W1= 10mil W2= 50mil sub=Alumina
62 more lines
MSSTEP: inet_132 inet_32 W1= { We321 } W2= 10mil sub=Alumina
MSTRL: inet_32 Port2 w=10mil p= { 150mil - 50mil } Sub=Alumina
Component text. Note
that there will be no
carriage returns.
Component text. Note
that there will be no
carriage returns.
Netlist Line. Note that
Designer puts in
carriage returns.
Netlist Line. Note that
Designer puts in
carriage returns.
Since it is a multiple line component, each component must have a unique ID. The
underscore following the @ID tells designer to assign it a unique ID, and each element
must have unique characters following the underscore. These can be alpha-numeric
Slide 53
Appendix Linear Patch Script
Dim Lpatch, Lfeed, idnum, x, n, pi,
pointsvar,feedline1,feedline2,feedline3
Dim width(20)
Set Pointsvar = LayoutHost.CreatePointsObject()
Set Feedline1= LayoutHost.CreatePointsObject()
Set Feedline2= LayoutHost.CreatePointsObject()
Set Feedline3= LayoutHost.CreatePointsObject()
Set PatchOutline=LayoutHost.CreatePointsObject()
pi = 3.1415926535
nx = LayoutHost.Pars.Item("nx")
ny = LayoutHost.Pars.Item("ny")
n = LayoutHost.Pars.Item("n")
Lpatch = LayoutHost.Pars.Item("Lpatch")
Wfeed = LayoutHost.Pars.Item("Wfeed")
dx= LayoutHost.Pars.Item("dx")
dy= LayoutHost.Pars.Item("dy")
lf1= LayoutHost.Pars.Item("lf1")
lf2= LayoutHost.Pars.Item("lf2")
wf1= LayoutHost.Pars.Item("wf1")
wf2= LayoutHost.Pars.Item("wf2")
W100= LayoutHost.Pars.Item("W100")
W50= LayoutHost.Pars.Item("W50")
W70= LayoutHost.Pars.Item("W70")
Lambda4= LayoutHost.Pars.Item("Lambda4")
Wcutout= LayoutHost.Pars.Item("WSlot")
Lcutout= LayoutHost.Pars.Item("LSlot")
WPatch= LayoutHost.Pars.Item("WPatch")
Linput= LayoutHost.Pars.Item("Linput")
Lfeed = LayoutHost.LayoutPars.Item("Lfeed")
idnum = LayoutHost.GetLayerID("anywhere")
, W50
if x=nx-2 then
Feedline2.Add (cx+dx-w100/2-lambda4),(cy-lf1)
Feedline2.Add (cx+dx+w100/2),(cy-lf1)
LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
call clearlines
end if
end Sub 'Draw patch
for y = 0 to ny-1
'*****Draw Vertical Feeds
Feedline2.Add (-1*lambda4-w100),(y*dy-lf1+(w70-w100)/2)
Feedline2.Add (w100/2),(y*dy-lf1+(w70-w100)/2)
LayoutHost.NewLine Qwave, feedline2,W70, "corner", "flat"
Feedline2.Add (-1*lambda4-w100),(y*dy-lf1)
Feedline2.Add (-1*lambda4-w100-lf2),(y*dy-lf1)
LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
if y<>0 then
Feedline2.Add (-1*lambda4-w100-lf2+w70/2),(y*dy-lambda4-lf1-w100/2)
Feedline2.Add (-1*lambda4-w100-lf2+w70/2),(y*dy-lf1-w100/2)
LayoutHost.NewLine Qwave, feedline2,W70, "corner", "flat"
call clearlines
Feedline2.Add (-1*lambda4-w100-lf2+w100/2),(y*dy-lambda4-lf1-w100/2)
Feedline2.Add (-1*lambda4-w100-lf2+w100/2),((y-1)*dy-lf1+w100/2)
LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"
end if
for x = 0 to nx-1
Call drawpatch(dx*x,dy*y)
next nx
Next 'ny
'***Draw input Feed
Feedline2.Add (-1*lambda4-w100-lf2+w100/2)-w100/2,(-lf1-w100/2+w50/2)
Feedline2.Add (-1*lambda4-w100-lf2+w100/2)-linput-w100/2,(-lf1-w100/2+w50/2)
LayoutHost.NewLine idnum, feedline2,W50, "corner", "flat"
call clearlines
' Manipulate Port
LayoutHost.MovePort "n1", (-1*lambda4-w100-lf2+w100/2)-linput-w100/2,(-lf1-
w100/2+w50/2), pi
LayoutHost.SetPortWidth idnum, "n1", W50
Sub ClearLines
'This routine will clear all feedlines and is to be used after each
line build
..
End Sub ' Clearlines
Sub DrawPatch(CenterZX,CenterZY)
Cx =CenterZX
Cy =CenterZy
'Patch Drawing Subroutine, Cx and Cy are the coords
PatchOutline.Add (cx-Wpatch/2),(cy)
PatchOutline.Add (cx-Wpatch/2),(cy+Lpatch)
PatchOutline.Add (cx+Wpatch/2),(cy+Lpatch)
PatchOutline.Add (cx+Wpatch/2),(cy)
PatchOutline.Add (cx+WCutout/2),(cy)
PatchOutline.Add (cx+WCutout/2),(cy+Lcutout)
PatchOutline.Add (cx+W100/2),(cy+Lcutout)
PatchOutline.Add (cx+W100/2),(cy)
PatchOutline.Add (cx-W100/2),(cy)
PatchOutline.Add (cx-W100/2),(cy+Lcutout)
PatchOutline.Add (cx-Wcutout/2),(cy+Lcutout)
PatchOutline.Add (cx-Wcutout/2),(cy)
LayoutHost.Newpoly idnum, Patchoutline
'*** Draw Horiz Feeds
'LayoutHost.NewCircle idnum,cx,cy,(Wpatch/4)
Feedline2.Add (cx),(cy)
Feedline2.Add (cx),(cy-lf1)
if x<>nx-1 then
Feedline2.Add (cx+dx-w100/2-lambda4),(cy-lf1)
end if
LayoutHost.NewLine FeedL, feedline2,W100, "corner", "flat"