S.

NO CODE TITLE DOMAIN YEAR

1 VLSI-01 Area-Delay-Power Efficient Fixed-Point LMS
Adaptive Filter With Low Adaptation-Delay
Area + Power +
Delay Efficient
2014
2 VLSI-02 Fast Sign Detection Algorithm for the RNS
Moduli Set {2
n+1
1, 2n 1, 2n}
Area + Power +
Delay Efficient
2014
3 VLSI-03 Efficient Integer DCT Architectures for HEVC Area + Power
Efficient
2014
4 VLSI-04 AreaDelayPower Efficient Carry-Select Adder Area + Power
Efficient
2014
5 VLSI-05 Design of Efficient Binary Comparators
in Quantum-Dot Cellular Automata
Area + Power
Efficient
2014
6 VLSI-06 Reverse Converter Design via Parallel-Prefix
Adders: Novel Components, Methodology,
and Implementations
Delay + Power
Efficient
2014
7 VLSI-07 Area-Delay Efficient Binary Adders in QCA Area + Delay
Efficient
2014
8 VLSI-08 Low-Complexity Low-Latency Architecture for
Matching of Data Encoded With Hard Systematic
Error-Correcting Codes
Area + Delay
Efficient
2014
9 VLSI-09 Parallel AES Encryption Engines for Many-Core
Processor Arrays
Area + Delay
Efficient
2013
10 VLSI-10 Multifunction Residue Architectures for
Cryptography
Area Efficient 2014
11 VLSI-11 Low-Complexity Multiplier for GF(2
m
) Based on
All-One Polynomials
Area Efficient 2013
12 VLSI-12 Split Radix Algorithm for Length 6
m
DFT Area Efficient 2013
13 VLSI-13 Flexible Integer DCT Architectures for HEVC Area Efficient 2013
14 VLSI-14 Area-Efficient Parallel FIR Digital Filter
Structures for Symmetric Convolutions Based on
Fast FIR Algorithm
Area Efficient 2012
15 VLSI-15 Low-Power, High-Throughput, and Low-Area
Adaptive FIR Filter Based on Distributed
Arithmetic
Power
Consumption
2013
16 VLSI-16 A Novel Modulo Adder for 2
n
-2
k
- 1Residue
Number System
Power
Consumption
2013
17 VLSI-17 Low-Power and Area-Efficient Carry Select Adder Power
Consumption
2012
18 VLSI-18 Measurement and Evaluation of Power Analysis
Attacks on Asynchronous S-Box
Power
Consumption
2012
19 VLSI-19 A Low-Power Single-Phase Clock Multiband
Flexible Divider
Power
Consumption
2012
20 VLSI-20 Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic
High Speed 2014
21 VLSI-21 Critical-Path Analysis and Low-Complexity
Implementation of the LMS Adaptive Algorithm
High Speed 2014
22 VLSI-22 Eliminating Synchronization Latency Using
Sequenced Latching
High Speed 2014
23 VLSI-23 Design of Digit-Serial FIR Filters: Algorithms,
Architectures, and a CAD Tool

High Speed 2013
24 VLSI-24 Design of an Error Detection and Data Recovery
Architecture for Motion Estimation Testing
Applications

High Speed 2012
25 VLSI-25 Gate Mapping Automation for Asynchronous Testing 2014
NULL Convention Logic Circuits
26 VLSI-26 Design of Testable Reversible Sequential Circuits Testing 2013
27 VLSI-27 Test Patterns of Multiple SIC Vectors: Theory
and Application in BIST Schemes
Testing 2013
28 VLSI-28 Period Extension and Randomness Enhancement
Using High-Throughput Reseeding-Mixing PRNG
Testing 2012
29 VLSI-29 High-Throughput Multistandard Transform Core
Supporting MPEG/H.264/VC-1 Using Common
Sharing Distributed Arithmetic
VLSI+
MATLAB
2014
30 VLSI-30 Improved 8-Point Approximate DCT for Image
and Video Compression Requiring Only 14
Additions
VLSI+
MATLAB
2014
31 VLSI-31 Efficient FPGA and ASIC Realizations of DA-
Based Reconfigurable FIR Digital Filter

VLSI+
MATLAB
2014
32 VLSI-32 Multicarrier Systems Based on Multistage Layered
IFFT Structure
VLSI+
MATLAB
2013
33 VLSI-33 Improvement of the Security of ZigBee by a New
Chaotic Algorithm
VLSI+
MATLAB
2013
34 VLSI-34 CORDIC Based Fast Radix-2 DCT Algorithm VLSI+
MATLAB
2013