IC Layout using L-EDIT

L EDIT with
its simulation using T
T-Spice
Spice
Asst.Prof.Dr.Pipat
Asst.Prof.Dr.
Pipat Prommee
TelecommunicationsEngineeringDepartment
Telecommunications Engineering Department
FacultyofEngineering

Why use L-edit?

L edit?
LLEdit
Editisafreewareandisveryusefulfor
is a freeware and is very useful for
academicpurposes
Th
ThoughindustryusesCadence,LEditcan
hi d
C d
L Edi
illustrativethesignificantpointsforlaying
outCMOScircuits.Cadenceisrather
complexincomparison.
p
p
LEditcanbeusedtoextractparasitic
capacitancewhichenablesustopredict
it
hi h
bl
t
di t
thedelayinCMOScircuits.

DOWNLOAD INSTRUCTIONS
The
ThematerialsaboutLEdit(Handout,Spice
materials about L Edit (Handout Spice
models,etc.)canbefoundinDrPipat
Prommees
website.
http://www.kmitl.ac.th/~kppipat
LEditProstudentversion.Youcanalso
download L Edit from
downloadLEditfrom
http://www.tannereda.com/longform

Setup
Thisversionmustrunin256colors.
For Windows XP users, set the display by
ForWindowsXPusers,setthedisplayby
rightclickingtheshortcutcreatedforLedit
and choosing properties
andchoosingproperties.
Thenclickthecompatibilitytab. Under
displaysettingsclick256colors.
OpenLedit
Open Ledit

L-EDIT
L
EDIT Windows

Drawing Layout
CreatenewLayoutfile
Create new Layout file
File>New.
Inthefollowingopenwindow,Browseandchoose
In the following open window Browse and choose
Generic_025.tdbinCopyTDBsetupfromfilearea.It
usuallylocatesin\MyDocuments\TannerEDA\Tanner
Toolsv13.0\LEditandLVS\Tech\Generic0_25um\.

Relationship between Lambda and

Microns

= 0.25m or
Another
way, define
d fi
4 = 1m

To establish GRID
Zoomthewindowtoseegrid
Distancebetweengridpointsis1m
Distance between grid points is 1 m
InordertosetmousesnaptoGrid:
ClickSetup>Design
ClickontheGridtab
SetMousesnapgridto1locatorunit

Now the technology is setup!

Nowthetechnologyissetup!

Grid Setup

Inverter Layout
LayoutSpecifications:
NMOS:
L=0.5m,W=2 m

VDD

PMOS:
W/L

L=0.5m,W=4

Vout

Vin

W/L
VSS

NMOS and PMOS

Topview

Topview

CrossSection(FrontView)
CrossSection(FrontView)

PMOS Design

ChooseNWellintheleftpalette
anddrawabox.
IntheNWellarea,drawPSelect.
Noticethatthesizeandposition
should obey Design Rule which
shouldobeyDesignRule,which
canbefoundat
http://www.mosis.org/Technical/
Layermaps/lmscmos
y
p/
_scnpc.html.
p
WiththehelpofDRCbutton,
theviolationofdesignrulecanbe
shownbyrightclickingtheplace
whichishighlighted.Itisagood
hi h i hi hli h d i
d
ideatorunDRCateachstageof
yourdesignsothatyoucanfix
any error along the way
anyerroralongtheway
DrawActive.
DrawPoly.

Active
Contact

NSelect

NWell
Poly

Metal1

PSelect

NMOS Design
Metal1

D
DonotneedtodrawP
t
dt d
P
Wellbecausethe
p yg
emptygridofLEdit
standsforPWell.
DrawNSelect.
DrawActive.
DrawPoly.

PSelect
Poly

Active
Active
Contact
PSelect

Connects P
P-Substrate
Substrate

For PMOS place a

ForPMOS,placea
smallNSelecton
theNWell,adda
y
smallActivelayer.
Fromthisactive
layerputcontacts
totheMetal1layer
that connects to
thatconnectsto
VDD.

Connects N
N-Substrate
Substrate
FForNMOS,ontheP
NMOS
th P
substrate,placea
smallPSelectand
then Active layer
thenActivelayer.
Fromthisactivelayer
putcontactstothe
Metal1 layer that
Metal1layerthat
connectstoVSS.

Connect Poly and Metal

Connect Poly of PMOS

ConnectPolyofPMOS
andNMOSforinput.
Addaninputconnect
betweenMetal1andPoly.
ConnectspolyandMetal1
byusingPolyContactat
input.
Connect source of PMOS
ConnectsourceofPMOS
toVDDbyMetal1.
ConnectsourceofNMOS
toVSSbyMetal1.
ConnectDrainofPMOS
andNMOSbyMetal1.

Connects port names

UsingSwitch
Using
Switchto
to
DrawingPortbutton
Assignedportnameof
differentports,VDD,
VSS,Output,Input

Design Rule Check (DRC)

Cli
ClickTools>DRC(orthe
k T l > DRC ( th
DRCboxinthetoolbar)
RunDRCforthetotal
l
layout.
t
ClicktheWriteerrorsto
filebox,andgivea
d
descriptivefilename
i ti fil
Fixtheerrorslisted.
OncethereisnoDRC
errorshown,thelayoutis
readytobeextracted.

Extract Data for Simulate

P
PressMenu
M
Tool>ExtractSetup
Uncheck
Uncheck Extract
Extract
StandardRuleSet
Browseandchoose
folderforlocatethe
outputdata.
Setfilename
Set file name
inverter.spc
Check Extract
Extract
Check
StandardRuleSet
andpressOK

MOSIS TSMC 0.25um Level49

(mosis025.md)
*DATE:May21/01
*LOT:T14YWAF:101
* Temperature parameters Default
*Temperature_parameters=Default
.MODELNMOSNMOS (LEVEL=49
+VERSION=3.1TNOM=27TOX=5.8E9
+XJ=1E7NCH=2.3549E17VTH0=0.3877332
+K1=0.4503218K2=7.498548E3K3=1E3
+K3B=2.7511903W0=1E7NLX=2.684962E7
+DVT0W = 0
+DVT0W=0DVT1W=0DVT2W=0
DVT1W = 0
DVT2W = 0
+DVT0=0.4948826DVT1=0.5924031DVT2=0.5
+U0=300.237024UA=1.207596E9UB=2.358208E18
+UC=2.411595E11VSAT=1.423302E5A0=1.4820567
+AGS=0.2493074B0=2.000837E7B1=3.568634E6
+KETA=9.120027E4A1=3.802033E5A2=0.4500971
+RDSW=117.272191PRWG=0.5PRWB=0.2
+WR=1WINT=0LINT=4.377598E9
+XL=3E8XW=4E8DWG=2.290208E8
+DWB=5.476111E9VOFF=0.0948739NFACTOR=1.9975727
+CIT=0CDSC=2.4E4CDSCD=0
+CDSCB=0ETA0=4.108112E3ETAB=8.333134E4
+DSUB=0.0311455PCLM=1.8275359PDIBLC1=0.9990847
+PDIBLC2=4.688174E3PDIBLCB=0.0999829DROUT=0.8506408
+PSCBE1=7.991332E10PSCBE2=5.16406E10PVAG=0.0099971
+DELTA=0.01RSH=4.4MOBMOD=1
+PRT=0UTE=1.5KT1=0.11
+KT1L=0KT2=0.022UA1=4.31E9
+UB1=7.61E18UC1=5.6E11AT=3.3E4
+WL
+WL=0WLN=1WW=0
0
WLN
1
WW
0
+WWN=1WWL=0LL=0
+LLN=1LW=0LWN=1
+LWL=0CAPMOD=2XPART=0.5
+CGDO=6.14E10CGSO=6.14E10CGBO=1E12
+CJ=1.753617E3PB=0.99MJ=0.4591946
+CJSW = 4 328986E10
+CJSW=4.328986E
10PBSW=0.99MJSW=0.3552107
PBSW = 0 99
MJSW = 0 3552107
+CJSWG=3.29E10PBSWG=0.99MJSWG=0.3552107
+CF=0PVTH0=0.01PRDSW=10
+PK2=2.428891E3WKETA=0.0103867LKETA=7.732829E3)

.MODELPMOSPMOS (LEVEL=49
+VERSION=3.1TNOM=27TOX=5.8E9
+XJ=1E7NCH=4.1589E17VTH0=0.5887506
+K1=0.6126803K2=7.885899E3K3=0
+K3B=14.442188W0=1E6NLX=1E9
+DVT0W =0DVT1W
+DVT0W
0
DVT1W =0DVT2W
0
DVT2W =0
0
+DVT0=2.3705962DVT1=0.7414674DVT2=0.1278685
+U0=121.9538647UA=1.62789E9UB=1E21
+UC=1E10VSAT=2E5A0=0.9432943
+AGS=0.1657709B0=1.621073E6B1=5E6
+KETA=0.01749A1=6.582776E4A2=0.3
+RDSW=1.050595E3PRWG=0.1217968PRWB=0.3344162
+WR=1WINT=0LINT=3.148114E8
+XL=3E8XW=4E8DWG=4.599354E8
+DWB=3.248109E8VOFF=0.1241961NFACTOR=1.2000247
+CIT=0CDSC=2.4E4CDSCD=0
+CDSCB=0ETA0=0.4473028ETAB=0.1020914
+DSUB=0.9345426PCLM=0.7700996PDIBLC1=8.653573E4
+PDIBLC2=0.0213771PDIBLCB=1E3DROUT=0.4304851
+PSCBE1=2.607383E10PSCBE2=6.650832E9PVAG=6.011881E3
+DELTA=0.01RSH=3.4MOBMOD=1
+PRT=0UTE=1.5KT1=0.11
+KT1L=0KT2=0.022UA1=4.31E9
+UB1=7.61E18UC1=5.6E11AT=3.3E4
+WL = 0
+WL=0WLN=1WW=0
WLN = 1
WW = 0
+WWN=1WWL=0LL=0
+LLN=1LW=0LWN=1
+LWL=0CAPMOD=2XPART=0.5
+CGDO=6.74E10CGSO=6.74E10CGBO=1E12
+CJ=1.913294E3PB=0.9893175MJ=0.4712889
+CJSW =3.825105E
+CJSW
3.825105E10
10PBSW
PBSW =0.6116479MJSW
0.6116479 MJSW =0.296387
0.296387
+CJSWG=2.5E10PBSWG=0.6116479MJSWG=0.296387
+CF=0PVTH0=6.429985E3PRDSW=12.3017562
+PK2=3.434527E3WKETA=0.0244275LKETA=0.0136271)

Add Model file

Cli
Clickiconpencilon
ki

il
SetupExtractDialog
GotoOutputtab
andtypeusedMOSIS
dt
d MOSIS
model.INCLUDE
mosis025.mdin
SPICE include
SPICEinclude
statementthenpress
OK
Finally,PressMenu
Finally Press Menu
Tool>Extract

T-Spice
T
Spice Simulation
O
OpenTspice
T i
Program
OpenMenu
File>open
Selectfile
Inverter.spcwhich
p
wasprevious
extracted.

Simulations using T
T-Spice
Spice
FileInverter.spcis
open.
TransistorM1and
M2arecreatedwith
thevalues,W,Land
parasiticelements
basedonyour
i di id l d i
individualdesign
Atdrain,sourceof
transistorare
namedasport
d
labels.

Simulations using T
T-Spice
Spice
Add
Addfollowing
f ll i
commandsfor
verifying the
verifyingthe
transient
p
response.
VDDVDD0dc1.5
VSSVSS0dc0
VinInput0PULSE(01.55n.01n.01n5n10n)
.TRAN.01n50n
.printtranV(Input)V(Output)

Press
PressF5orRun
F5 or Run
button.

Verify the results

WEditisautomaticopen.
ThesimulationresultsofVinandVout areshowninthe
same graph
samegraph

Customize the output results

Customizethewaveformbyaddingmoreonechartbyusingnewchart
C
i h
f
b ddi
h b
i
h
button.
Removev(Output)fromupperchartbypressmouseonitsandpressDEL.
Pressmouseonlowerchartandaddtraceinlowerchart

Customize the output results

Load
v(Output)
dataintothe
chart.
PressOK

Transient Results
Th
Theresultsofinputandoutputwaveformare
l fi
d
f
showninupperandlowercharts,respectively.

Simulations using T
T-Spice
Spice
Addfollowing
dd f ll i
commandsfor
verifyingtheDC
analysis.
VDDVDD0dc1.5
VSSVSS0dc0
.DC Vin 0 1.5 0.01
.DCVin01.50.01
.printDCV(Input)V(Output)

Press
PressF5orRun
F5 or Run
button.

DC Analysis Results
Theresultsofoutputwhileinputvariedare
comparedinthesamechart.

Assignment (OTA Layout)

IO
= gm =
Vin

Transistor

W
(m)

L
(m)

Transistor

W
(m)

M1 , M2
All NMOS

5
3

0.5
0.5

All PMOS

5
5

(I B )(OCOX W L )

NMOS
Current
mirror

CMOSOTASchematic

Assignment (OTA Layout)

Tricks
UsingMetal1andMetal2whicharelocatedin
differentlayer.
Biascurrentneedsacurrentmirror.
SubstrateofM1andM2areconnectedtoVSS

L
(m)
0.5
0.5