1

LAB4. 4-Bit Ripple Carry Adder Design

In this lab, you will draw a 4-bit ripple carry adder (RCA) layout using Cadence (Composer). A
schematic hierarchy of this design is shown in Figure 1. You'll design the RCA and extract its
parameter (netlist), and finally simulate the netlist using Hspice.



Figure1. 4-bit RCA schematic and symbol

A
B
Z
S
CO Cl
A B
FA FA FA FA
A
B
Z
A
B
Cl
CO
S
A
B
Z
FA
B0 A1 B1 A2 B2 A0 A3 B3
CO
S3 S2 S1 S0
Cl
C1 C2 C3
CO Cl
S(0:3)
A(0:3) B(0:3)
A B
Z
4RCA
NAND
XOR
Full Adder
4-Bit Ripple Carry Adder
2

Before designing the RCA, design a one-bit full adder (FA). Label the input data as A, B, and CI,
and the output as S and CO. Use Composer cell hierarchy to design the FA. In order to simplify
the layout, use three 2-input nand cells and two 2-input exclusive-or (XOR) cells as sub-cells in
this lab. And XOR can be implemented using 4 nand cells as shown in Figure 1. The top-level
parent cell, FA, will contain five children cells, nand_0, nand_1, nand_2, xor_0, and xor_1.
When using cell hierarchy in Composer, make sure that the labels, A, B, CI, S, and CO, are
placed on a square of paint contained in the top-level parent cell, FA. Then, using four FA cells,
design a 4-bit RCA. Make sure that the labels of this RCA are A0~A3, B0~B3, CI, S0~S3, and
CO.

Step 1.

Download FA_frame.sp, 4RCA_frame.sp from the website of VLSI Lab.


Step 2.


1. Run icfb & under your working directory

2. Make a New Library (named lab4)


Step 3. Design 2-input Nand gate

1. Make a new Cell under the lab4 library. (Cell Name : nand2, Tool : Composer-Schematic)


2. Draw 2-input nand circuit referred to Figure 1.

a) PMOS : W=150~600nm, L=50~100nm
b) NMOS: W=50~200nm, L=50~100nm


3. Save and Check the circuit (Select Design->Save and Check)


4. Create Symbol

a) Select Design->Create Cellview->From Cellview

3



b) Check the input names and output names in the symbol editor window



c) Select Design->Save and Check
d) close the symbol editor window


5. Check if the above symbol exists under nand2 Cell in the Library Manager.


Step 3. Design 2-input Xor gate

1. Make a new Cell under the lab4 library. (Cell Name : xor2, Tool : Composer-Schematic)


2. Draw 2-input Xor circuit referred to Figure 1.

a) Select ADD->Instance
b) Choose lab4 Library in the Component Browser
c) Choose nand2 in the Component Browser
d) Place the cell on your schematic editor.

3. Save and Check the circuit (Select Design->Save and Check)


4. Create Symbol (same as the Step 2)
4

Step 4. Design Full Adder

1. Make a new Cell under the lab4 library. (Cell Name : FA, Tool : Composer-Schematic)


2. Draw Full Adder circuit referred to Figure 1. (same as the Step3)
- nand2 and xor cell are needed.

3. Save and Check the circuit (Select Design->Save and Check)


4. Create Symbol (same as the Step 2)


5. In the schematic editor window, Run Analog Environment.


6. Extract spice netlist of the Full Adder.


7. Save the extracted spice file.


8. Copy only circuit netlists from the extracted spice file (excluding any sources and options)


9. Paste the copied netlists in the FA_frame.sp file.


10. Run Hspice, and Awaves.



Step 5. Design 4-bit Ripple Carry Adder

1. Make a new Cell under the lab4 library. (Cell Name : 4RCA, Tool : Composer-Schematic)


2. Draw 4-bit RCA circuit referred to Figure 1. (same as the Step3)
- FA cell are needed.

3. Save and Check the circuit (Select Design->Save and Check)


4. In the schematic editor window, Run Analog Environment.

5

5. Extract spice netlist of the 4-bit RCA.


6. Save the extracted spice file.


7. Copy only circuit netlists from the extracted spice file (excluding any powers and options)


8. Paste the copied netlists in the 4RCA_frame.sp file.


10. Run Hspice, and Awaves.








Lab report guideline:


1. Write down the truth table of XOR2 gate, NAND2 gate, and NOR2 gate.


2. Explain about ripple-carry adder and carry-lookahead adder.
(Include the advantages and disadvantages over each one.)