EC53 COMPUTER ARCHITECTURE AND ORGANIZATION

AIM
To discuss the basic structure of a digital computer and to study in detail the organization
of the Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit.
OBJECTIVES
To hae a thorough understanding of the basic structure and operation of a digital
computer.
To discuss in detail the operation of the arithmetic unit including the algorithms !
implementation of fi"ed#point and floating#point addition, subtraction, multiplication!
diision.
To study in detail the different types of control and the concept of pipelining.
To study the hierarchical memory system including cache memories and irtual memory.
To study the different $ays of communicating $ith I/O deices and standard I/O
interfaces.
TEXTBOOKS
%. &ohn '.(ayes, )Computer architecture and Organisation*, Tata Mc+ra$#(ill, Third edition,
%,,-.
.. /.Carl(amacher, 0on1o +. /aranesic and 2afat +. 0a1y, 3 Computer Organisation3, /
edition, Mc+ra$#(ill Inc, %,,4.
REFERENCES
%.Morris Mano, 3Computer 2ystem Architecture5, 'rentice#(all of India, .666.
..'araami, 3Computer Architecture5, 78( 966., O"ford 'ress.
:. '.'alChaudhuri, , 3Computer organization and design5, .nd 8d., 'rentice (all of India, .66;.
<. +.=ane!&.(einrich, ) MI'2 9I2C Architecture ), 8ngle$ood cliffs, >e$ &ersey, 'rentice
(all, %,,..
SYLLABUS
UNIT I INTRODUCTION 9
Computing and Computers, 8olution of Computers, /L2I 8ra, 2ystem ?esign# 9egister
Leel, 'rocessor Leel, C'@ Organization, ?ata 9epresentation, Ai"ed B 'oint >umbers,
Aloating 'oint >umbers, Instruction Aormats, Instruction Types, Addressing modes.
UNIT II DATA PATH DESIGN 9
Ai"ed 'oint Arithmetic, Addition, 2ubtraction, Multiplication and ?iision,
Combinational and 2eCuential AL@s, Carry loo1 ahead adder, 9obertson algorithm, booth*s
algorithm, non#restoring diision algorithm, Aloating 'oint Arithmetic, Coprocessor, 'ipeline
'rocessing, 'ipeline ?esign, Modified booth*s Algorithm
UNIT III CONTROL DESIGN 9
(ard$ired Control, Microprogrammed Control, Multiplier Control @nit, C'@ Control
@nit, 'ipeline Control, Instruction 'ipelines, 'ipeline 'erformance, 2uperscalar 'rocessing,
>ano 'rogramming.
UNIT IV MEMORY ORGANIZATION 9
9andom Access Memories, 2erial # Access Memories, 9AM Interfaces, Magnetic
2urface 9ecording, Optical Memories, multileel memories, Cache ! /irtual Memory, Memory
Allocation, Associatie Memory.
UNIT V SYSTEM ORGANIZATION 9
Communication methods, 7uses, 7us Control, 7us Interfacing, 7us arbitration, IO and
system control, IO interface circuits, (andsha1ing, ?MA and interrupts, ectored interrupts, 'CI
interrupts, pipeline interrupts, IO' organization, operation systems, multiprocessors, fault
tolerance, 9I2C and CI2C processors, 2uperscalar and ector processor.
TOTAL: 45 HOURS
TEXTBOOKS
%. &ohn '.(ayes, )Computer architecture and Organisation*, Tata Mc+ra$#(ill, Third edition,
%,,-.
.. /.Carl(amacher, 0on1o +. /aranesic and 2afat +. 0a1y, 3 Computer Organisation3, /
edition, Mc+ra$#(ill Inc, %,,4.
REFERENCES
%.Morris Mano, 3Computer 2ystem Architecture5, 'rentice#(all of India, .666.
..'araami, 3Computer Architecture5, 78( 966., O"ford 'ress.
:. '.'alChaudhuri, , 3Computer organization and design5, .nd 8d., 'rentice (all of India, .66;.
<. +.=ane!&.(einrich, ) MI'2 9I2C Architecture ), 8ngle$ood cliffs, >e$ &ersey, 'rentice
(all, %,,..
UESTION BANK
UNIT I
PART A
1. Dhat are the types of C'@ organizationsE
2. Dhat are the different types of address instructionsE +ie e"amples to each.
:. ?efine priority encoder.
4. Dhat are the factors to be considered in selecting a number representation to be used
in a computerE
F. Dhat are the different types of addressing modesE
4. Drite the add/subtract rule for floating point numbersE
;. Dhen is a problem said to be intractableE
-. Dhat is the significance of /L2I designE
,. ?ifferentiate 9I2C and CI2C architecture.
%6. ?efine multiprocessor.
%%. List the performance measures of a computer.
%.. ?efine program counter. Mention its main function.
%:. List the features of addressing modes used in modern processors.
PART B!
1. 8"plain the architecture of basic computer $ith neat diagram. G%4H
2. ?efine addressing mode. Classify addressing modes and e"plain each.
3. GiH ?ra$ the bloc1 diagram of a < bit register leel magnitude comparator and
e"plain. G-H
GiiH 7riefly e"plain the organization of IA2 computer $ith its instruction set. G-H
4. GiH (o$ does one detect and correct errors during data transmissionE G-H
GiiH ?escribe in detail the different 1inds of addressing mode $ith an e"ample. G-H
F. GiH 7riefly e"plain C'@ organization.
GiiH Drite notes on eolution of computers.
4. ?ra$ the structure of babbage analytical engine and e"plain. G-H
;. GiH Drite short notes on I G-H
a. ?ata transfer Instruction.
b. 'rogram control Instruction
c. Logical Instruction
GiiH ?escribe the processor leel design of computer design hierarchy. G-H
-. Dhat are the basic functional units of computerE ?iscuss each $ith neat diagram.
,. 8"plain about fi"ed point and floating numbers and data representation.
%6. 8"plain GiH Instruction format GiiH Instruction Types
UNIT II
PART A
%. Dhat is a coprocessorE
.. Dhat is a data pathE
:. Drite do$n the eCuation for carry generate and propagate.
<. ?efine coprocessor.
F. Dhat is meant by pipeliningE
4. ?efine seCuential AL@E
;. Aind the Cuotient and remainder of %66%%6 diided by %6%.
-. Dhat is ripple carry adderE
,. 2tate the restoring diision algorithm.
%6. Dhat are the problems found in floating point arithmetic operationsE
%%. Dhat are the adantages of using carry loo1 head adderE
%.. ?efine bit#pair recoding.
%:. 2tate the 9obertson algorithm.
%<. 2tate booth*s algorithm.
%F. Dhat are the t$o types of I888 standards to represent floating point numbersE
PART " B
%. ?ra$ the diagram of a carry loo1 ahead adder and e"plain the carry loo1 ahead
principle. G%4H
.. ?escribe in detail boothJs multiplication algorithms and its hard$are
implementation. G%4H
:. 8"plain .*s complement multiplier $ith a neat bloc1 diagram. G%4H
<. 8"plain floating point adder pipeline $ith neat bloc1 diagram. G%4H
F. GiH 8"plain 9obertson algorithm. G%6H
GiiH 8"plain fi"ed point arithmetic multiplication and diision $ith e"ample. G4H
4. GiH8"plain pipeline processing. G%.H
;. GiiH Dhy $e go for Modified 7ooth Algorithm. G<H
-. GiH 7riefly discuss about the connection bet$een C'@ and coprocessor. G-H
GiiH Multiply %%%%%%6% and %%6%6%6% using booth algorithm. 2ho$ each step. G-H
,. 8"plain the non#restoring diision algorithm for unsigned integers and using the
algorithm calculate the Cuotient and remainder of %%6%6%% diided by %6%6. G%4H
%6. 8"plain fi"ed point arithmetic.
%%. 8"plain Aloating point arithmetic.
UNIT III
PART A
%. Dhat are the design methods for control unitsE
.. Dhat is a pipeline controlE
:. Compare the t$o methods to design the hard$ired controller.
<. Dhat is the use of micro assemblerE
F. Dhat are the problems faced in instruction pipelineE
4. ?efine >ano programmingE
;. ?ifferentiate horizontal and ertical micro instruction.
-. Dhat are the components of 7T7E
,. ?istinguish bet$een hard$ired control and micro#programmed control.
%6. Dhat are the factors to improe the speed of micro programmingE
%%. List out the adantages of micro programming.
%.. ?efine superscalar processing.
PART " B
%. 8"plain the different type of hazards that can occur in a pipeline. G%4H
.. Dhat are superscalar processorsE 8"plain the typical structure of a
typical superscalar processorE G%4H
3. GiH Drite short notes on >ano programming and nano programming control. G-H
GiiH ?escribe the characteristics of supper scalar processing. G-H
4. ?esign a micro programmed control unit of non#pipelined
general purpose computers G%4H
F. 8"plain the design of a gcd processor $ith neat bloc1 diagram. G%4H
4. ?escribe instruction pipelines in detail $ith e"amples. Analyze the pipeline
performance. G%4H
;. 8"plain GiH C'@ control unit GiiH 'ipeline control GiiiH Multiplier control unit
-. GiH Compare hard$ired and micro programming unit. G%.H
GiiH List their adantages and disadantages. G<H
UNIT IV
PART A
%. ?efine 9andom Access Memory.
2. Dhat are the adantages of using irtual memoryE
:. Dhat are ?9O and >?9OE
4. Dhat is temporal localityE
F. Drite the differences bet$een cache and irtual memoryE
4. Dhat is called as locality of referenceE
;. ?ra$ the loo1 aside system organization for cache.
-. Compare static 9AM and ?ynamic 9AM.
,. Dhat is meant by flash memoryE
%6. Dhat is cache memoryE
%%. ?efine optical memories.
%.. Dhat is meant by content addressable memoryE
13.Applications of serial access memories.
PART B
%. ?ra$ the neat s1etch of memory hierarchy and e"plain the need of cache
memory. G%4H
.. 8"plain the organization of magnetic dis1 in detail. G%4H
:. ?escribe in detail magnetic tape memories and dis1 memories. G%4H
<. ?escribe cache memory in detail. G%4H
F. ?escribe the organization of the typical 9AM chip. G%4H
4. Dhat is irtual memoryE Dhy it is necessary to implement irtual memoryE G%4H
;. GiH?escribe the serial access memory structure $ith releant bloc1 diagrams. G-H
GiiH +ie the structure of associatie memory and e"plain. G-H
-. GiH8"plain in detail about the memory allocation techniCues. G-H
GiiH Drite short notes on translation loo1aside buffer. G-H
,. 8"plain GiH 9andom access memories GiiH 2erial access memories.
%6. 8"plain GiH optical memory GiiH multileel memories
%%. 8"plain GiH Memory allocation GiiH Associatie memory.
UNIT " V
PART " A
%. ?efine an interrupt.
.. Dhat are the possible data transfer modes aailable $ith peripherals.
:. Dhat are the limitations of programmed IOE
<. Drite do$n the C'@ steps to determine the status of IO deice.
F. Dhat is the disadantage of busE
4. Dhat is ?MAE
;. ?efine tri#state buffer.
-. >ame some factors influencing fault tolerant systemE
,. ?efine I/O interrupt.
%6. ?efine 'CI interrupt.
%%. Compare 9I2C and CI2C processor.
%.. Compare superscalar and ector processor.
%:. Dhat is the need of 7us interfaceE
%<. Dhat is meant by 7us Arbitration/
%F. Dhat do you mean by handsha1ingE
PART " B
%. 8"plain the difference bet$een CI2C and 9I2C processors. G%4H
.. 8"plain the ?MA mode of data transfer. G%4H
3. GiH Dhat is ?MAE ?ra$ the bloc1 diagram and e"plain it in detail.G-H
GiiH ?escribe ectored interrupt scheme $ith a neat bloc1 diagram.G-H..
4. GiH ?efine fault tolerance. (o$ is it related to redundancyE 8"plain
different approaches for designing fault tolerance systems. G-H
GiiH 8"plain different types of bus arbitration scheme. G-H
F. Dith neat bloc1 diagram e"plain IO' organization. G%4H
4. GiH 8laborate daisy chaining arbitration. G-H
GiiH 7rief about the cache coherence problem. G-H
;. GiH 8"plain ectored interrupt and 'CI interrupt in detail. G%6H
GiiH ?iscuss Alynn*s classification of computers. G4H
8. 8"plain the types of processors based on system organization.
,. 8"plain the types of interrupts based on system organization.
%6. 8"plain IO' organization and operating systems.
%%. 8"plain GiH 7us interfacing GiiH 7us arbitration GiiiH 7us interfacing.
%.. 8"plain GiH IO and system control GiiH IO interface circuits.