IFRSAs International Journal Of Computing|Vol2|issue 3|July 2012 668

FPGA and ASIC Implementation of Vedic Multiplier

1*
Bhaskar G.R,
1
Jagannatha K.B,
1
Lakshmisagar HS,
1
Anil Kumar D,
1*
Shailesh M.L,
1*
Asha C.N
Department of Electronics & Communication Engineering
1
BMS Institute of Technology, Bangalore, Karnataka, India
1*
Acharya Institute of Technology, Bangalore, Karnataka, India

ABSTRACT
The ever increasing demand in enhancing the ability of
processors to handle the complex and challenging
processes has resulted in the integration of a number of
processor cores into one chip. Still the load on the
processor is not less in generic system. This load is
reduced by supplementing the main processor with Co-
Processors, which are designed to work upon specific
type of functions like numeric computation, Signal
Processing, Graphics etc. The speed of ALU depends
greatly on the multiplier. In algorithmic and structural
levels, numerous multiplication techniques have been
developed to enhance the efficiency of the multiplier
which concentrates in reducing the partial products and
the methods of their addition but the principle behind
multiplication remains the same in all cases. Vedic
Mathematics [1] is the ancient system of mathematics
which has a unique technique of calculations based on
16 Sutras. Employing these techniques in the
computation algorithms of the coprocessor will reduce
the complexity, execution time, area, power etc. Our
work has proved the efficiency of Urdhva
Triyagbhyam Vedic method for multiplication which
strikes a difference in the actual process of
multiplication itself. It enables parallel generation of
intermediate products. This sutra is to be used to build a
high speed power efficient multiplier in the MAC unit.
First FPGA realization is achieved and next Standard
cell based ASIC design of the multiplier is realized. In
180nm CMOS technology our speed is 5.2ns , 257uW
and its using 1117 cells.
Keywords: Vedic Mathematics, Urdhva Triyakbhyam
Sutra, Field Programmable Gate Array (FPGA).
1. INTRODUCTION
Vedic mathematics [1] was rediscovered in the early
twentieth century from ancient Indian sculptures
(Vedas). Ancient Indian system of mathematics was
derived from Vedic Sutras. The conventional
mathematical algorithms can be simplified and even
optimized by the use of Vedic mathematics. The Vedic
algorithms can be applied to arithmetic, trigonometry,
plain and
Spherical geometry, calculus. In [2], the work presented
in this thesis [1], makes use of Vedic Mathematics and
goes step by step, by first designing a Vedic Multiplier,
then a Multiply Accumulate Unit. Multiplication,
basically is the mathematical operation of scaling one
number by another. Talking about todays engineering
world, multiplication based operations are some of the
frequently used Functions, currently implemented in
many Digital Signal Processing (DSP) applications such
as Convolution, Fast Fourier Transform, filtering and in
Arithmetic Logic Unit (ALU) of Microprocessors. Since
multiplication is such a frequently used operation, its
necessary for a multiplier to be fast and power efficient
and so, development of a fast and low power multiplier
has been a subject of interest over decades. Multiply
Accumulate or MAC operation is also a commonly used
operation in various Digital Signal Processing
Applications. Now, not only Digital Signal Processors,
but also general-purpose Microprocessors come with a
dedicated Multiply Accumulate Unit or MAC unit.
When talking about the MAC unit, the role of Multiplier
is very significant because it lies in the data path of the
MAC unit and its operation must be fast and efficient.
Two most common multiplication algorithms followed
in the digital hardware are array multiplication
algorithm and Booth multiplication algorithm which has
more propagation delay. But Vedic multiplier has
minimum propagation delay.
The paper is organized as follows. Section 2 presents an
overview of Urdhva tiryakbhyam Sutra. In Section 3
Design and analysis of Vedic Multiplier. Section 4
FPGA results, Section 5 shows standard cell based
ASIC design synthesis report and section 6 results and
discussion and Section 7 concludes the paper.
2. URDHVA TIRYAKBHYAM SUTRA
International journal of Computing
Journal homepage: www.ifrsa.org
Bhaskar G.R, Jagannatha K.B, Lakshmisagar HS, Anil Kumar D, Shailesh M.L, Asha C.N | FPGA and ASIC
Implementation of Vedic Multiplier

IFRSAs International Journal Of Computing|Vol2|issue 3|July 2012 669
The Urdhva tiryakbhyam Sutra[3] or Vertically and
Crosswise Algorithm for multiplication is discussed
and then used to develop digital multiplier architecture.
This looks quite similar to the popular array multiplier
architecture. This Sutra shows how to handle
multiplication of a larger number (N x N, of N bits
each) by breaking it into smaller numbers of size (N/2 =
n, say) and these smaller numbers can again be broken
into smaller numbers (n/2 each) till we reach
multiplicand size of (2 x 2) .Thus, simplifying the whole
multiplication process. The multiplication algorithm is
then illustrated to show its computational efficiency by
taking an example of reducing a NxN bit multiplication
to a 2x2-bit multiplication operation. This work presents
a systematic design methodology for fast and area
efficient digit multiplier based on Vedic Mathematics
and then a MAC unit has been made which uses this
multiplier.


Fig 1: RTL 16X16 MULTIPLY BLOCK
3. DESIGN AND ANALYSIS OF VEDIC
MULTIPLIER
The hardware realization of 2x2 multiplier blocks [8] is
illustrated



Fig 2 : The hardware realization of 2x2 multiplier
blocks

Block diagram of 16x16 Multiply block


Fig 3 : 16X16 Multiplier Block

4. FPGA SIMULATION OUTPUTS

Fig 4 : Simulation waveform for Multiplier

Table 1 : COMPARISON OF TIMING DELAY IN
MULTIPLIERS in FPGA

MULTIPLIER (16X16) TIME DELAY (ns)
ARRAY 37ns
BOOTH 43ns
VEDIC 24ns

Device utilization summary for Multiplier:

Number of Slices : 330 out of 3584 9%
Number of 4 input LUTs : 599 out of 7168 8%
Number of bonded IOBs: 65 out of 97 67%
Device utilization summary for MAC:
Number of Slices: 346 out of 3584 9%
Number of 4 input LUTs: 631 out of 7168 8%
Number of bonded IOBs: 65 out of 97 67%
5. STANDARD CELL BASED ASIC DESIGN
Bhaskar G.R, Jagannatha K.B, Lakshmisagar HS, Anil Kumar D, Shailesh M.L, Asha C.N | FPGA and ASIC
Implementation of Vedic Multiplier

IFRSAs International Journal Of Computing|Vol2|issue 3|July 2012 670

Fig 5 : ASIC Synthesis(RTL) schematic

Fig 6 : Floor planning


Fig 7 : Placement


Fig 8 : Routing

Table.2 ASIC SYNTHESIS RESULT TABLE

6. RESULTS INTERPRETATION
In our design we are built 16*16 bit multiplier block and
verified the functionality in XC3STQ144 Xilinx kit and
compared the delay with array and booth multipliers
Table 1 and same multiplier design has been used to for
MAC unit, using cadence RTL complier synthesis of
Vedic multiplier has been carried out. Standard cell
based ASIC design of the vedic multiplier is realized
and Table 6.1 shows the synthesis result for a specific
constraint file the gate level netlist which generated my
RTL complier, tech files and constraints files are
provided to SOC Encounter tool to get place and routed
design, finally design is converted in to GDSII format.
The Vedic multiplier design which has combined
advantages of less chip area, improved power
dissipation and timing delay can be used as the building
blocks in the design of arithmetic logic unit (ALU),
Digital Signal processing such has DFT and FFT, Image
Processing etc
7. CONCLUSION
In this paper we presented the implementation of
efficient Vedic multiplier which has high speed, less
complexity and consuming less area. The design was
simulated, synthesized using Xilinx tool and RTL
Complier and entire backend design was carried out
using CADENCE SOC Encounter.
The Vedic multiplier offered 20% and 19%
improvement in terms of propagation delay and power
consumption respectively, in comparison with parallel
adder based implementation. Whereas,the
corresponding improvement in terms of delay and
power was found to be 33% and 46% respectively, with
reference to the algebraic transformation based
implementation.
BIBLIOGRAPHY
[1] Thesis by Amandeep Singh Implementation of
16 bit Vedic multiplier Thapur University
JUNE 2010
http://dspace.thapar.edu:8080/dspace/bitstream/1
0266/1109/4/1109.pdf
Parameter Vedic Multiplier(16X16)

Area(cells)


1117

Power(mw)


257

Timing(ns)


5.2
Bhaskar G.R, Jagannatha K.B, Lakshmisagar HS, Anil Kumar D, Shailesh M.L, Asha C.N | FPGA and ASIC
Implementation of Vedic Multiplier

IFRSAs International Journal Of Computing|Vol2|issue 3|July 2012 671
[2] Harpreet Singh Dhillon and Abhijit Mitra, A
Reduced- Bit Multiplication Algorithm for
Digital Arithmetics, International Journal of
Computational and Mathematical Sciences 2;2 ,
Spring 2008.
[3] Himanshu Thapliyal, Saurabh Kotiyal and M. B
Srinivas, Design and Analysis of A Novel
Parallel Square and Cube Architecture Based On
Ancient Indian Vedic Mathematics, Centre for
VLSI and Embedded System Technologies,
International Institute of Information
Technology, Hyderabad, 500019, India, 2005
IEEE
[4] M. Ramalatha, Senior Member, IEEE, K. Deena
Dayalan, IEEE, P. Dharani, IEEE,S. Deborah
Priya, Member, IEEE High Speed Energy
Efficient ALU Design using Vedic
Multiplication Techniques
[5] Abhijeet Kumar, Dilip Kumar, Siddhi,
Hardware Implementation of 16*16 bit
Multiplier and Square using Vedic
Mathematics, Design Engineer, CDAC, Mohali
[6] An Efficient Bit Reduction Binary Multiplication
Algorithm using Vedic Methods Prabir Saha,
Arindam Banerjee , Partha Bhattacharyya ,
Anup Dandapat,2011IEEE
[7] Yun-Nan Chang , Janardhan H.Satyanarayana ,
Keshab K.Parhi, LOW-POWER DIGIT-
SERIAL MULTIPLIER ,1997 IEEE
International Symposium on circuits and
systems, June 9-12,1997, Hong Kong.


Mr. Shailesh M.L., born in Bangalore, Karnataka state, India,
in 1974, received Diploma in Computer Science Engineering
Board of Technical Education, Bangalore, in 1992, from KVT
Polytechnic Chikkaballapur, received Bachelor of Engineering
in Instrumentation & Electronics Engineering from
Siddaganga Institute of Technology, Tumkur, Bangalore
University, in 1997, and received Master of Technology in Bio
Medical Instrumentation from Sri Jaya Chama Rajendra
College of Engineering, Mysore, Vishweshwariah
Technological University, Belgaum, Karnataka, India in 2001.
He is presently working as Assistant Professor in Acharya
Institute of Technology, Bangalore and pursuing his research
in signal processing. His areas of interests are signal
processing, Medical Imaging and Multimedia Communication
systems. He is member of IEEE, ISTE, and Computer society
of India, Instrument Society of India, International Association
of Engineers, and Computing in Europe.


Mrs. Asha C.N., born in Bangalore, Karnataka state, India, in
1979, received Bachelor of Engineering in Electronics &
Communication Engineering from Vivekananda Institute of
Technology, Bangalore, Bangalore University, in 2002, and
received Master of Technology in VLSI Design &Embedded
System from VTU Regional Centre U.T.L. Bangalore,
Visvesvaraya Technological University, Belgaum, Karnataka,
India in 2008. She is presently Assistant Professor in Acharya
Institute of Technology, Bangalore and pursuing her research
in Wireless Mesh Networks (WMN). Her areas of interests
are Wireless Mesh Networks, Cross Layer Design and Routing
Protocols in WMN.